Memory and preparation method thereof

Abstract

The invention provides a memory and a preparation method thereof, the memory comprises a plurality of stacked memory array wafers, two adjacent memory array wafers in the plurality of memory array wafers are bonded, each memory array wafer comprises a memory array and a sense amplifier circuit, the sense amplifier circuit is connected with the memory array, and the sense amplifier circuit is connected with the memory array. A memory array includes a plurality of memory cells, each memory cell including a first vertical channel transistor, the plurality of memory cells including a first memory cell, and a sense amplifier circuit to transfer first data in the first memory cell. The memory provided by the invention can improve the storage density.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, specifically to a memory and a method for fabricating the memory. Background Technology

[0002] The rapid development of technologies such as artificial intelligence (AI) and large language models has spurred massive demands for data processing and storage. This places higher demands on storage density, and how to efficiently store the ever-increasing amount of computational data in AI application scenarios has become a technological challenge. Summary of the Invention

[0003] This application provides a memory and a method for manufacturing the memory, which can improve the storage density of the memory.

[0004] In a first aspect, a memory is provided, comprising: a plurality of memory array wafers stacked together, wherein two adjacent memory array wafers are bonded together, each memory array wafer including a memory array and a sense amplifier circuit, the memory array including a plurality of memory cells, each memory cell including a first vertical channel transistor, the plurality of memory cells including a first memory cell, and the sense amplifier circuit being used to transmit first data in the first memory cell.

[0005] This application embodiment improves storage density by stacking multi-layer memory array wafers. Each memory array wafer includes a memory array and a sense amplifier circuit, and the memory array uses vertical channel transistors. If planar transistors are used in the memory array, the memory array wafer needs to be thicker (typically greater than 1-2 micrometers). However, the channel length of vertical channel transistors is typically less than 300 nanometers, requiring a very thin memory array wafer. Therefore, using vertical channel transistors can further improve storage density. Furthermore, when the memory increases storage density through three-dimensional stacking of memory array wafers, if the sense amplifier circuit is only arranged on the peripheral circuit wafers as in the prior art, it is difficult to ensure that the sense amplifier can correctly read data for memory array wafers that are far from the peripheral circuit wafers. Therefore, this application embodiment arranges a sense amplifier circuit on each memory array wafer, ensuring the accuracy of data reading.

[0006] In conjunction with the first aspect, in some implementations of the first aspect, the memory further includes a peripheral circuit wafer, which is bonded to at least one of the plurality of memory array wafers and is provided with peripheral circuitry. The peripheral circuitry includes a data transmission circuit and an error correction circuit. The data transmission circuitry is used to communicate with the sensing amplifier circuit and devices outside the memory, and the error correction circuitry is used to check whether there is an error in reading or writing the first data.

[0007] Optionally, the peripheral circuitry may also include any one or more of a driver, decoder, buffer, and timing controller. The data transmission circuitry may receive the first data transmitted by the sensing amplifier circuitry and send the first data to a device outside the memory. The data transmission circuitry may also receive the first data sent by a device outside the memory and transmit the first data to the sensing amplifier circuitry.

[0008] Error correction circuits can check for errors in reading or writing data in storage cells, and can also correct erroneous data.

[0009] For example, peripheral circuit wafers can be stacked with multiple memory array wafers in the vertical direction to improve the area utilization of the memory and thus increase the memory density.

[0010] The memory provided in this application can improve the area utilization of the memory and thus increase the storage density by stacking multi-layer memory array wafers and peripheral circuit wafers.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the sensing amplifier circuit includes a second vertical channel transistor and a third vertical channel transistor.

[0012] The second and third vertical channel transistors can be the same type of vertical channel transistor or different types of vertical channel transistors.

[0013] It should be understood that this application does not limit the specific number of the second vertical channel transistor and the third vertical channel transistor included in the sense amplifier circuit, and the second vertical channel transistor and the third vertical channel transistor are not limited to being used as a sense amplifier circuit, but may also have other uses, such as word line drivers, control circuits, etc., and this application does not limit them.

[0014] Existing sensing amplifier circuits typically employ planar transistors, which require thicker memory array wafers, reducing memory density during multi-layer memory array wafer stacking. The memory provided in this application utilizes a second and a third vertical-channel transistor to construct the sensing amplifier circuit. Since the first, second, and third vertical-channel transistors are all vertical-channel transistors, they can be fabricated simultaneously with the first vertical-channel transistor, reducing production costs and improving production efficiency. Furthermore, compared to using planar transistors to construct the sensing amplifier circuit, this method can increase memory density.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the first vertical channel transistor and the second vertical channel transistor are N-type vertical channel transistors, and the third vertical channel transistor is a P-type vertical channel transistor.

[0016] It should be understood that N-type vertical channel transistors have higher current and faster speeds for the same size, so setting the first vertical channel transistor as an N-type vertical channel transistor can improve storage efficiency.

[0017] It should be understood that if the sense amplifier circuit is built solely based on N-type vertical channel transistors, its power consumption will be very high. This application uses both N-type and P-type vertical channel transistors to build the sense amplifier circuit, which can reduce the power consumption of the circuit.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the first channel of the first vertical channel transistor and the second channel of the second vertical channel transistor are formed on a P-type silicon substrate, and the third channel of the third vertical channel transistor is formed on an N-type silicon substrate.

[0019] The N-type channel of an N-type vertical channel transistor can be formed using a P-type silicon substrate. When the N-type vertical channel transistor is turned on, an N-type channel is formed on the surface of the P-type silicon substrate. When the thickness of the P-type silicon substrate is thin, the substrate will be completely depleted, which can suppress the floating body effect. The P-type channel of a P-type vertical channel transistor can be formed using an N-type silicon substrate. When the P-type vertical channel transistor is turned on, a P-type channel is formed on the surface of the N-type silicon substrate. When the thickness of the N-type silicon substrate is thin, the substrate will be completely depleted, which can suppress the floating body effect.

[0020] P-type silicon substrates can be formed by adding trivalent impurity elements (such as boron or gallium) to silicon raw materials, which provide additional free holes; N-type silicon substrates can be formed by adding pentavalent impurity elements (such as phosphorus or arsenic) to silicon raw materials, which provide additional free electrons.

[0021] The gates of N-type vertical channel transistors and P-type vertical channel transistors can be the same or different. When the gates are the same, the channels of the N-type vertical channel transistor and the P-type vertical channel transistor can be formed separately first, and then the gates of the N-type vertical channel transistor and the P-type vertical channel transistor can be formed simultaneously. When the gates are different, the channels of the N-type vertical channel transistor and the P-type vertical channel transistor can be formed separately first, and then the gates of the N-type vertical channel transistor and the P-type vertical channel transistor can be formed separately.

[0022] In the memory provided in this application, the sensing amplifier circuit is constructed by using both N-type vertical channel transistors and P-type vertical channel transistors, which can reduce the power consumption of the circuit.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the first gate of the first vertical channel transistor and the second gate of the second vertical channel transistor are provided with an N-type work function layer, and the third gate of the third vertical channel transistor is provided with a P-type work function layer.

[0024] The gate materials for the first, second, and third gates include, but are not limited to, metallic materials such as tungsten (W) and conductive materials such as titanium nitride (TiN). The N-type work function layer includes, but is not limited to, lanthanum oxide (La2O3), and the P-type work function layer includes, but is not limited to, aluminum oxide (Al2O3).

[0025] The channels of N-type vertical-channel transistors and P-type vertical-channel transistors can be the same or different. When the channels are the same, the channels of both N-type and P-type vertical-channel transistors can be formed simultaneously first, and then the gates of the N-type and P-type vertical-channel transistors can be formed separately. When the channels are different, the channels of both N-type and P-type vertical-channel transistors can be formed separately first, and then the gates of the N-type and P-type vertical-channel transistors can be formed simultaneously or separately.

[0026] In the memory provided in this application, the sensing amplifier circuit is constructed by using both N-type vertical channel transistors and P-type vertical channel transistors, which can reduce the power consumption of the circuit.

[0027] In conjunction with the first aspect, in some implementations of the first aspect, the transistors in each memory array wafer are vertical channel transistors.

[0028] In the memory provided in this application embodiment, the transistors in each memory array wafer are vertical channel transistors. The channel length of a vertical channel transistor is typically less than 300 nanometers, requiring the memory array wafer to be very thin. Therefore, using vertical channel transistors can further improve the memory's storage density.

[0029] In conjunction with the first aspect, in some implementations of the first aspect, the first storage cell further includes a dielectric capacitor connected to the first vertical channel transistor, and the memory is a dynamic random-access memory (DRAM).

[0030] The memory provided in this application can increase the storage density of DRAM by stacking multi-layer memory array wafers, and each memory array wafer is equipped with a sense amplifier circuit, which can reduce the parasitic capacitance of bit lines and ensure the accuracy of data reading.

[0031] In conjunction with the first aspect, in some implementations of the first aspect, the first storage unit further includes a ferroelectric capacitor connected to the first vertical channel transistor, and the memory is a ferroelectric random access memory (FeRAM).

[0032] The memory provided in this application can increase the storage density of FeRAM by stacking multi-layer memory array wafers, and each memory array wafer is equipped with a sense amplifier circuit, which can reduce the parasitic capacitance of the bit lines and ensure the accuracy of data reading.

[0033] In a second aspect, a method for fabricating a memory is provided, the method comprising: forming a plurality of memory array wafers, each memory array wafer including a memory array and a sense amplifier circuit, the memory array including a plurality of memory cells, each memory cell including a first vertical channel transistor, the plurality of memory cells including a first memory cell, the sense amplifier circuit being used to transmit first data in the first memory cell; stacking the plurality of memory array wafers, wherein two adjacent memory array wafers in the plurality of memory array wafers are bonded together.

[0034] This application embodiment improves storage density by stacking multi-layer memory array wafers. Each memory array wafer includes a memory array and a sense amplifier circuit, and the memory array uses vertical channel transistors. If planar transistors are used in the memory array, the memory array wafer needs to be thicker (typically greater than 1-2 micrometers). However, the channel length of vertical channel transistors is typically less than 300 nanometers, requiring a very thin memory array wafer. Therefore, using vertical channel transistors can further improve storage density. Furthermore, when the memory increases storage density through three-dimensional stacking of memory array wafers, if the sense amplifier circuit is only arranged on the peripheral circuit wafers as in the prior art, it is difficult to ensure that the sense amplifier can correctly read data for memory array wafers that are far from the peripheral circuit wafers. Therefore, this application embodiment arranges a sense amplifier circuit on each memory array wafer, ensuring the accuracy of data reading.

[0035] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: forming a peripheral circuit wafer, the peripheral circuit wafer being provided with peripheral circuitry, the peripheral circuitry including a data transmission circuit and an error correction circuit, the data transmission circuit being used to communicate with the sensing amplifier circuit and devices outside the memory, the error correction circuit being used to check whether the reading or writing of the first data has an error; and bonding the peripheral circuit wafer to at least one of the plurality of memory array wafers.

[0036] Optionally, the peripheral circuitry may also include any one or more of a driver, decoder, and buffer. The data transmission circuitry may receive the first data transmitted by the sensing amplifier circuitry and send the first data to a device outside the memory. The data transmission circuitry may also receive the first data sent by a device outside the memory and transmit the first data to the sensing amplifier circuitry.

[0037] Error correction circuits can check for errors in reading or writing data in storage cells, and can also correct erroneous data.

[0038] For example, peripheral circuit wafers can be stacked with multiple memory array wafers in the vertical direction to improve the area utilization of the memory and thus increase the memory density.

[0039] The memory fabrication method provided in this application can improve the area utilization of the memory and thus increase the storage density by stacking multilayer memory array wafers and peripheral circuit wafers.

[0040] In conjunction with the second aspect, in some implementations of the second aspect, the sensing amplifier circuit includes a second vertical channel transistor and a third vertical channel transistor.

[0041] The second and third vertical channel transistors can be the same type of vertical channel transistor or different types of vertical channel transistors.

[0042] It should be understood that this application does not limit the specific number of the second vertical channel transistor and the third vertical channel transistor included in the sense amplifier circuit, and the second vertical channel transistor and the third vertical channel transistor are not limited to being used as a sense amplifier circuit, but may also have other uses, such as word line drivers, control circuits, etc., and this application does not limit them.

[0043] Existing sensing amplifier circuits typically employ planar transistors, which require thicker memory array wafers, reducing memory density during multi-layer memory array wafer stacking. The memory provided in this application utilizes a second and a third vertical-channel transistor to construct the sensing amplifier circuit. Since the first, second, and third vertical-channel transistors are all vertical-channel transistors, they can be fabricated simultaneously with the first vertical-channel transistor, reducing production costs and improving production efficiency. Furthermore, compared to using planar transistors to construct the sensing amplifier circuit, this method can increase memory density.

[0044] In conjunction with the second aspect, in some implementations of the second aspect, the first vertical-channel transistor and the second vertical-channel transistor are N-type vertical-channel transistors, and the third vertical-channel transistor is a P-type vertical-channel transistor.

[0045] It should be understood that N-type vertical channel transistors have higher current and faster speeds for the same size, so setting the first vertical channel transistor as an N-type vertical channel transistor can improve storage efficiency.

[0046] It should be understood that if the sense amplifier circuit is built solely based on N-type vertical channel transistors, its power consumption will be very high. This application uses both N-type and P-type vertical channel transistors to build the sense amplifier circuit, which can reduce the power consumption of the circuit.

[0047] In conjunction with the second aspect, in some implementations of the second aspect, forming a plurality of memory array wafers includes: forming a first channel of the first vertical channel transistor, a second channel of the second vertical channel transistor, and a third channel of the third vertical channel transistor on a first memory array wafer, wherein the first memory array wafer is one of the plurality of memory array wafers; forming a first gate oxide layer on the surface of the first channel, a second gate oxide layer on the surface of the second channel, and a third gate oxide layer on the surface of the third channel; forming a first gate on the surface of the first gate oxide layer, a second gate on the surface of the second gate oxide layer, and a third gate on the surface of the third gate oxide layer; forming the source and drain of the first vertical channel transistor, the second vertical channel transistor, and the third vertical channel transistor; and connecting a capacitor to the source or drain of the first vertical channel transistor.

[0048] In some possible implementations, the N-type vertical channel transistor and the P-type vertical channel transistor have different channels but the same gate. The channel of the N-type vertical channel transistor can be formed on the surface of a P-type silicon substrate, and the channel of the P-type vertical channel transistor can be formed on an N-type silicon substrate. The gate can be made of a metal such as tungsten (W) or a conductive material such as titanium nitride (TiN). In this scenario, the channels of the N-type vertical channel transistor and the P-type vertical channel transistor can be formed separately first, and then the gates of the N-type vertical channel transistor and the P-type vertical channel transistor can be formed simultaneously.

[0049] In some possible implementations, N-type vertical-channel transistors (VDCs) and P-type VDCs have the same channel but different gates. Both the NDC and PDC channels are formed on an undoped silicon substrate. The gate of the NDC can have an N-type work function layer, and the gate of the PDC can have a P-type work function layer. The N-type work function layer includes, but is not limited to, lanthanum oxide (La₂O₃), and the P-type work function layer includes, but is not limited to, aluminum oxide (Al₂O₃). In this scenario, the channels of both the NDC and PDC can be formed simultaneously first, and then the gates of the NDC and PDC can be formed separately.

[0050] In some possible implementations, N-type vertical-channel transistors (VDCs) and P-type VDCs have different channels and gates. The channel of an NDC can be formed using a P-type silicon substrate, and the channel of a PDC can be formed using an N-type silicon substrate. The gate of an NDC can have an N-type work function layer, and the gate of a PDC can have a P-type work function layer. In this scenario, the channels of the NDC and PDC can be formed separately first, and then the gates of the NDC and PDC can be formed separately.

[0051] In some possible implementations, the gate oxide layer may be formed on the surface of the channel by thermal oxidation.

[0052] The memory fabrication method provided in this application can construct memory array wafers in different ways, adapting to various fabrication scenarios and improving the generalizability of the fabrication method.

[0053] In conjunction with the second aspect, in some implementations of the second aspect, forming the first channel of the first vertical channel transistor, the second channel of the second vertical channel transistor, and the third channel of the third vertical channel transistor on the first memory array wafer includes: depositing a dielectric layer on a substrate; etching the dielectric layer to form a first channel setting region, a second channel setting region, and a third channel setting region; growing a P-type silicon substrate on the sidewall of the first channel setting region to form the first channel, growing a P-type silicon substrate on the sidewall of the second channel setting region to form the second channel, and growing an N-type silicon substrate on the sidewall of the third channel setting region to form the third channel.

[0054] The substrate includes, but is not limited to, a silicon substrate, and the dielectric layer can be a single layer or multiple layers, such as silicon oxide, silicon nitride, or other materials.

[0055] The first and second channels are formed using a P-type silicon substrate, which can be formed by adding trivalent impurity elements (such as boron or gallium) to the silicon raw material. These impurities provide additional free holes. The third channel is formed using an N-type silicon substrate, which can be formed by adding pentavalent impurity elements (such as phosphorus or arsenic) to the silicon raw material. These impurities provide additional free electrons.

[0056] In the memory fabrication method provided in this application, a sense amplifier circuit is constructed by simultaneously using N-type vertical channel transistors and P-type vertical channel transistors, which can reduce the power consumption of the circuit.

[0057] In conjunction with the second aspect, in some implementations of the second aspect, forming a first gate on the surface of the first gate oxide layer, forming a second gate on the surface of the second gate oxide layer, and forming a third gate on the surface of the third gate oxide layer includes: forming a first gate by disposing a gate material with an N-type work function layer on the surface of the first gate oxide layer; forming a second gate by disposing a gate material with an N-type work function layer on the surface of the second gate oxide layer; and forming a third gate by disposing a gate material with a P-type work function layer on the surface of the third gate oxide layer.

[0058] The gate materials for the first, second, and third gates include, but are not limited to, metallic materials such as tungsten (W) and conductive materials such as titanium nitride (TiN). The N-type work function layer includes, but is not limited to, lanthanum oxide (La2O3), and the P-type work function layer includes, but is not limited to, aluminum oxide (Al2O3).

[0059] In the memory fabrication method provided in this application, a sense amplifier circuit is constructed by simultaneously using N-type vertical channel transistors and P-type vertical channel transistors, which can reduce the power consumption of the circuit.

[0060] In conjunction with the second aspect, in some implementations of the second aspect, forming the source and drain of the first vertical channel transistor, the second vertical channel transistor, and the third vertical channel transistor includes: performing N-type doping on both ends of the first channel and the second channel to form the source and drain of the first vertical channel transistor and the second vertical channel transistor; and performing P-type doping on both ends of the third channel to form the source and drain of the third vertical channel transistor.

[0061] N-type doping refers to the doping of the channel with elements such as phosphorus (P) and arsenic (As), while P-type doping refers to the doping of the channel with elements such as boron (B).

[0062] In the memory fabrication method provided in this application, a sense amplifier circuit is constructed by simultaneously using N-type vertical channel transistors and P-type vertical channel transistors, which can reduce the power consumption of the circuit.

[0063] In conjunction with the second aspect, in some implementations of the second aspect, the transistors in each memory array wafer are vertical channel transistors.

[0064] In the memory fabrication method provided in this application, the transistors in each memory array wafer are vertical channel transistors. The channel length of a vertical channel transistor is typically less than 300 nanometers, requiring the memory array wafer to be very thin. Therefore, using vertical channel transistors can further improve the memory's storage density.

[0065] In conjunction with the second aspect, in some implementations of the second aspect, the first memory cell further includes a dielectric capacitor connected to the first vertical channel transistor, and the memory is DRAM.

[0066] The memory fabrication method provided in this application can improve the storage density of DRAM by stacking multilayer memory array wafers, and each memory array wafer is equipped with a sensing amplifier circuit, which can reduce the parasitic capacitance of bit lines and ensure the accuracy of data reading.

[0067] In conjunction with the second aspect, in some implementations of the second aspect, the first memory cell further includes a ferroelectric capacitor connected to the first vertical channel transistor, and the memory is FeRAM.

[0068] The method for fabricating the memory provided in this application can increase the storage density of FeRAM by stacking multilayer memory array wafers, and each memory array wafer is equipped with a sensing amplifier circuit, which can reduce the parasitic capacitance of the bit lines and ensure the accuracy of data reading.

[0069] Thirdly, a chip is provided, including a memory controller and the memory described in the first aspect, wherein the memory controller and the memory are electrically connected.

[0070] Fourthly, an electronic device is provided, including a circuit board and the chip described in the third aspect, the chip being disposed on the circuit board and electrically connected to the circuit board. Attached Figure Description

[0071] Figure 1 This is a schematic diagram of the structure of a memory provided in an embodiment of this application.

[0072] Figure 2 This is a schematic diagram of another memory structure provided in an embodiment of this application.

[0073] Figure 3 This is an exemplary flowchart of a method for fabricating a memory according to an embodiment of this application.

[0074] Figure 4 This is a schematic diagram of the structure of a memory array wafer provided in an embodiment of this application.

[0075] Figures 5-8 This is an exemplary flowchart of a method for fabricating a memory array wafer provided in an embodiment of this application.

[0076] Figure 9 This is a schematic diagram of another memory array wafer provided in an embodiment of this application.

[0077] Figures 10-15 This is an exemplary flowchart of another method for preparing a memory provided in this application embodiment.

[0078] Figure 16 This is a schematic diagram of another memory structure provided in an embodiment of this application.

[0079] Figure 17 This is a schematic diagram of another memory structure provided in an embodiment of this application.

[0080] Figure 18 This is a schematic diagram of an electronic device provided in an embodiment of this application.

[0081] Figure 19 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application. Detailed Implementation

[0082] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the scope of protection of this application.

[0083] In the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design that is described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.

[0084] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0085] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0086] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0087] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0088] To facilitate understanding of the embodiments of this application, some definitions involved in this application will be briefly explained first.

[0089] 1. NMOS transistor: A field-effect transistor (FET) based on an N-type metal-oxide-semiconductor (NMOS) structure. An NMOS transistor consists of a P-type substrate and two N-type regions (source and drain). The NMOS transistor operates based on gate voltage control. When a positive voltage is applied to the gate, the P-type substrate inverts to form an N-type channel connecting the source and drain, allowing current to flow through the NMOS transistor. In this state, the NMOS transistor is in the on-state. Conversely, when zero or a negative voltage is applied to the gate, the channel is cut off, current cannot flow, and the NMOS transistor is in the off-state.

[0090] 2. PMOS transistor: A type of FET based on a P-type metal-oxide-semiconductor (PMOS) structure. A PMOS transistor consists of an N-type substrate and two P-type regions (source and drain). The operating principle of a PMOS transistor is also based on gate voltage control. When zero or a negative voltage is applied to the control gate, the surface of the N-type substrate inverts to form a P-type channel connecting the source and drain, allowing current to flow through the PMOS transistor. In this state, the PMOS transistor is in the on-state. Conversely, when a positive voltage is applied to the control gate, the channel is cut off, current cannot flow, and the PMOS transistor is in the off-state.

[0091] 3. Floating body effect: This refers to the phenomenon in transistors implemented using silicon-on-insulator technology where charge accumulates on the capacitor due to the relationship between body potential, bias voltage, and carrier recombination, resulting in adverse effects such as threshold voltage drift.

[0092] 4. Lattice constant (or point constant): refers to the edge length of the unit cell, that is, the edge length of each parallelepiped unit. It is an important basic parameter of crystal structure.

[0093] 5. Metal-induced lateral crystallization (MILC): This technique involves depositing or ion-implanting a metal (such as nickel) onto an amorphous silicon thin film and then crystallizing the amorphous silicon at a low temperature below 550°C.

[0094] 6. Work function: Defined as the minimum energy required for an electron to move from the interior of a solid to the surface of an object; that is, the work that an electron must do to escape the metal's binding force. In semiconductor technology, work function adjustment layers influence the electron transport characteristics within semiconductors by modifying the material's work function, which is crucial for optimizing the performance of semiconductor devices.

[0095] The rapid development of technologies such as artificial intelligence (AI) and large language models has spurred massive demands for data processing and storage. Over the past decade, the scale of large language models, exemplified by generative pre-trained transformers (GPT), has grown exponentially; for instance, the GPT-4 model currently has over 100,000 parameters. 12 The rapid increase in the parameter size of large models has placed higher demands on memory storage density. How to efficiently store the ever-growing amount of computational data in artificial intelligence applications has become a technical challenge.

[0096] Dynamic random-access memory (DRAM) is the main memory in current computing systems. However, as manufacturing processes approach their physical limits, the miniaturization speed of DRAM has gradually slowed, making it difficult to meet the ever-increasing data storage demands. The following description uses DRAM as an example to illustrate the memory and its fabrication method provided in this application. Ferroelectric random access memory (FeRAM) is similar and will not be repeated here.

[0097] Figure 1 This is a schematic diagram of a memory structure provided in an embodiment of this application. DRAM consists of a memory array and peripheral circuitry. This embodiment of the application envisions using wafer bonding in DRAM. On the one hand, the memory array wafers and peripheral circuit wafers can be stacked vertically, thereby improving the area utilization of DRAM and increasing memory density. On the other hand, by vertically stacking n memory array wafers, memory density can be further increased, where n > 1.

[0098] DRAM memory arrays consist of multiple memory cells, each containing a transistor and a capacitor, such as a one-transistor-one-capacitor (1T1C) type memory cell. The transistor is typically an N-channel transistor, meaning that when its channel is on, the majority carriers are negatively charged electrons. 1T1C type DRAM distinguishes different data storage states by the voltage value stored on the capacitor; typically, a high voltage corresponds to data "1," and a low voltage corresponds to data "0." Before reading data stored in the DRAM, the bit line (BL) is pre-charged to an intermediate voltage as a reference voltage. Then, the word line of the memory cell is turned on, allowing the storage capacitor and the bit line capacitor to share charge. If the DRAM stores data "1", meaning the voltage stored on the storage capacitor is high, this voltage is higher than the bit line voltage. After charge sharing, the voltage on the bit line will be higher than the reference voltage. In this case, comparing the bit line voltage with the reference voltage through a sensing amplifier will read the data "1". Conversely, if the DRAM stores data "0", meaning the voltage stored on the storage capacitor is low, this voltage is lower than the bit line voltage. After charge sharing, the voltage on the bit line will be lower than the reference voltage. Similarly, comparing the bit line voltage with the reference voltage through a sensing amplifier will read the data "0". The sensing amplifier consists of multiple transistors. Due to potential differences in threshold voltages between these transistors during manufacturing, the sensing amplifier can only correctly read the data stored in the DRAM if the voltage change on the bit line exceeds a certain amplitude after charge sharing. Fluctuations in transistor threshold voltages cause a certain deviation in the sensing amplifier. When the voltage change on the bit line is lower than this deviation, there is a risk of incorrect data reading.

[0099] When DRAM increases storage density through three-dimensional stacking of memory array wafers, if the sense amplifier circuit is only arranged on the peripheral circuit wafer as in the prior art, the memory array wafer, which is vertically far from the peripheral circuit wafer, will have a longer path from its bit line to the sense amplifier, resulting in larger parasitic capacitance. After charge sharing, the voltage change on the bit line will decrease, making it difficult to ensure that the sense amplifier can correctly read the data, thus leading to an increase in the DRAM data read error rate. Therefore, to avoid the problem of decreased storage density due to the additional bit line load when stacking memory array wafers in three dimensions, this embodiment of the application also arranges the sense amplifier circuit on the memory array wafer to reduce the distance between the bit line and the sense amplifier, thereby reducing the parasitic capacitance of the bit line.

[0100] In this application embodiment, when increasing storage density through the stacking of multilayer memory array wafers, to reduce the impact of parasitic capacitance of bit lines on data reading during multilayer stacking, a sense amplifier circuit needs to be arranged on the memory array wafer. This allows the data to be read from the wafer on the memory array first by the sense amplifier circuit on the memory array wafer, and then transmitted to the peripheral circuit wafer for information interaction with the outside world. Planar transistors typically refer to transistors where the source, gate, and drain are all on the same plane. If planar transistors are used, especially when multiple threshold voltages are required, the memory array wafer needs to be relatively thick (typically greater than 1-2 micrometers). Vertical channel transistors, on the other hand, refer to transistors where the source, drain, and gate are arranged vertically, reducing the projected area, allowing for denser transistors, enabling more advanced processes, and eliminating the need for traditional high-precision photolithography. The channel length of vertical channel transistors is typically less than 300 nanometers, requiring a very thin substrate area on the memory array wafer. Therefore, using vertical channel transistors when increasing storage density through the stacking of multilayer memory array wafers can further improve storage density.

[0101] Figure 2 This is a schematic diagram of another memory structure provided in an embodiment of this application.

[0102] The memory includes n memory array wafers stacked together, with adjacent memory array wafers bonded together. Each memory array wafer includes a memory array and a sense amplifier circuit, where n > 1.

[0103] The memory array includes multiple memory cells, each memory cell including a first vertical channel transistor, the multiple memory cells including a first memory cell, and a sense amplifier circuit for transmitting first data in the first memory cell.

[0104] The sensing amplifier circuit can sense, capture and process the voltage on the bit line, and read the data in the memory cell by comparing the voltage on the bit line with a reference voltage.

[0105] In one possible implementation, the sense amplifier circuit includes a second vertical channel transistor and a third vertical channel transistor.

[0106] In one possible implementation, the first vertical-channel transistor, the second vertical-channel transistor, and the third vertical-channel transistor are vertical-channel transistors of the same type. For example, the first vertical-channel transistor, the second vertical-channel transistor, and the third vertical-channel transistor are all N-type vertical-channel transistors or all P-type vertical-channel transistors.

[0107] In one possible implementation, the first vertical-channel transistor, the second vertical-channel transistor, and the third vertical-channel transistor include at least two types of vertical-channel transistors. For example, the first vertical-channel transistor and the second vertical-channel transistor are N-type vertical-channel transistors, and the third vertical-channel transistor is a P-type vertical-channel transistor; or, the first vertical-channel transistor and the second vertical-channel transistor are P-type vertical-channel transistors, and the third vertical-channel transistor is an N-type vertical-channel transistor.

[0108] A first vertical-channel transistor includes a first channel, a first gate oxide layer, a first gate, a first source, and a first drain. The first source and the first drain are located at opposite ends of the first channel, and the first gate oxide layer is located between the first channel and the first gate to isolate the first channel and the first gate. A second vertical-channel transistor includes a second channel, a second gate oxide layer, a second gate, a second source, and a second drain. The second source and the second drain are located at opposite ends of the second channel, and the second gate oxide layer is located between the second channel and the second gate to isolate the second channel and the second gate. A third vertical-channel transistor includes a third channel, a third gate oxide layer, a third gate, a third source, and a third drain. The third source and the third drain are located at opposite ends of the third channel, and the third gate oxide layer is located between the third channel and the third gate to isolate the third channel and the third gate.

[0109] The first vertical channel transistor in the memory array and the second and third vertical channel transistors in the sensing amplifier circuit are connected by a bit line. The sensing amplifier circuit reads the data in the first memory cell by comparing the voltage of the bit line with a reference voltage and transmits it to the peripheral circuit to interact with the outside world.

[0110] It should be understood that this application does not limit the specific number of the second vertical channel transistor and the third vertical channel transistor included in the sense amplifier circuit.

[0111] It should be understood that the second vertical channel transistor and the third vertical channel transistor are not limited to being used as sense amplifier circuits, but may also have other uses, such as word line drivers, control circuits, etc., and this application does not limit them.

[0112] Figure 3 This is an exemplary flowchart of a method for fabricating a memory according to an embodiment of this application.

[0113] 310, forming multiple memory array wafers.

[0114] Each formed memory array wafer includes a memory array and a sense amplifier circuit. The memory array includes multiple memory cells, each memory cell including a first vertical channel transistor. The multiple memory cells include a first memory cell. The sense amplifier circuit is used to transmit first data in the first memory cell.

[0115] The following embodiments use N-type vertical-channel transistors (VLCTs) for the first and second VLCTs and P-type VLCTs for the third VLCT as examples to describe in detail the fabrication method of the memory array wafer provided in this application. It should be understood that the first, second, and third VLCTs can also be the same type of VLCT, or the first and second VLCTs can be P-type VLCTs and the third VLCT can be N-type VLCTs. The following examples should not be construed as limiting this application.

[0116] In some possible implementations, the N-type vertical-channel transistor and the P-type vertical-channel transistor have different channels but the same gate. The channel of the N-type vertical-channel transistor can be formed on a P-type silicon substrate, and the channel of the P-type vertical-channel transistor can be formed on an N-type silicon substrate. The gate can be made of a metal such as tungsten (W) or a conductive material such as titanium nitride (TiN). In this scenario, the channels of the N-type and P-type vertical-channel transistors can be formed separately first, and then the gates of the N-type and P-type vertical-channel transistors can be formed simultaneously. For details, please refer to [link to relevant documentation]. Figures 4 to 8 The description.

[0117] In some possible implementations, the N-type vertical-channel transistor and the P-type vertical-channel transistor have the same channel but different gates. Both the N-type and P-type vertical-channel transistors have channels formed on an undoped silicon substrate. The gate of the N-type vertical-channel transistor can have an N-type work function layer, and the gate of the P-type vertical-channel transistor can have a P-type work function layer. The N-type work function layer includes, but is not limited to, lanthanum oxide (La₂O₃), and the P-type work function layer includes, but is not limited to, aluminum oxide (Al₂O₃). In this scenario, the channels of both the N-type and P-type vertical-channel transistors can be formed simultaneously first, and then the gates of the N-type and P-type vertical-channel transistors can be formed separately. For details, please refer to [link to relevant documentation]. Figures 9 to 15 The description.

[0118] 320, multiple memory array wafers are stacked.

[0119] Bonding setup for two adjacent memory array wafers in multiple memory array wafers.

[0120] Figure 4This is a schematic diagram of the structure of a memory array wafer provided in an embodiment of this application.

[0121] The memory array wafer 400 includes stacked dielectric layers 420, 480, and 440, in which a first vertical-channel transistor 401, a second vertical-channel transistor 402, and a third vertical-channel transistor 403 are embedded. The constituent materials of dielectric layers 420, 480, and 440 include, but are not limited to, silicon oxide.

[0122] The first vertical-channel transistor 401 and the second vertical-channel transistor 402 are N-type vertical-channel transistors, and the third vertical-channel transistor 403 is a P-type vertical-channel transistor. The first vertical-channel transistor 401 and the second vertical-channel transistor 402 have the same channel and the same gate, while the first vertical-channel transistor 401 and the third vertical-channel transistor 403 have different channels but the same gate.

[0123] The first vertical channel transistor 401 includes a first channel 411, a gate oxide layer 405, a gate 406, a source 407, and a drain 408. The source 407 and the drain 408 are located at both ends of the first channel 411, and the gate oxide layer 405 is located between the first channel 411 and the gate 406 to isolate the first channel 411 and the gate 406.

[0124] The second vertical channel transistor 402 includes a second channel 412, a gate oxide layer 405, a gate 406, a source 407, and a drain 408. The source 407 and the drain 408 are located at both ends of the second channel 412, and the gate oxide layer 405 is located between the second channel 412 and the gate 406 to isolate the second channel 412 and the gate 406.

[0125] The third vertical channel transistor 403 includes a third channel 413, a gate oxide layer 405, a gate 406, a source 407, and a drain 408. The source 407 and the drain 408 are located at both ends of the third channel 413, and the gate oxide layer 405 is located between the third channel 413 and the gate 406 to isolate the third channel 413 and the gate 406.

[0126] It should be understood that Figure 4 The four first vertical-channel transistors 401, two second vertical-channel transistors 402, and two third vertical-channel transistors 403 included are for illustrative purposes only; this application does not limit the number of transistors. A capacitor is also connected to the source 407 or drain 408 of the first vertical-channel transistor 401, but is not shown in the figure. The positions of the source 407 and drain 408 can also be interchanged.

[0127] Figures 5-8This is an exemplary flowchart of a method for fabricating a memory array wafer provided in this application embodiment. This method can be used to fabricate... Figure 4 The memory array wafer 400 is shown. Figure 5 Including steps 501 to 504, Figure 6 Including steps 505 to 508, Figure 7 Including steps 509 to 513, Figure 8 This includes steps 514 to 518.

[0128] 501. Dielectric layer 420, dielectric layer 430 and dielectric layer 440 are sequentially deposited on substrate 410. Wherein, substrate 410 includes but is not limited to single crystal silicon substrate, dielectric layer 420 and dielectric layer 440 include but are not limited to silicon oxide, and dielectric layer 430 includes but is not limited to silicon nitride.

[0129] 502. Etching is performed on the deposited dielectric stack structure to form a first channel region 421 and a second channel region 422. The dielectric stack structure includes stacked dielectric layers 420, 430, and 440. The surface of the substrate 410 serves as a stop layer for etching. The etching method includes, but is not limited to, dry etching. Due to the high etching selectivity during the etching process, a high etching rate is achieved only for the target material (such as the constituent materials of dielectric layers 420, 430, and 440), while other materials are hardly etched. In some possible implementations, a mask layer can be deposited on the top dielectric layer 440 first, and then the pattern to be etched can be formed on the mask layer by photolithography. The mask layer can then be used as a mask to etch the dielectric stack structure.

[0130] 503. A P-type silicon substrate is grown on the sidewalls of the first channel setting region 421 and the second channel setting region 422 formed in the previous etching step to serve as the channel for the N-type vertical channel transistor. The growth method includes, but is not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). The P-type silicon substrate can be formed by adding trivalent impurity elements (such as boron or gallium) to the silicon raw material. These impurities provide additional free holes. A P-type silicon substrate is grown on the sidewalls of the first channel setting region 421 to form the first channel 411, and a P-type silicon substrate is grown on the sidewalls of the second channel setting region 422 to form the second channel 412.

[0131] It should be understood that an N-type silicon substrate can also be grown first, thus forming the channel of a P-type transistor. The above examples should not be construed as limiting this application. After the channel of the N-type vertical channel transistor is grown, a dielectric layer 450 is filled inside the channel of the N-type vertical channel transistor. The dielectric layer 450 includes, but is not limited to, silicon oxide.

[0132] The grown silicon substrate is polycrystalline or amorphous. Due to its numerous grain boundaries, it exhibits significant leakage current when the device is off, and hinders carrier migration when the device is on, resulting in low carrier mobility. Subsequent crystallization processing is required to improve its electrical performance. When the silicon channel is thick, the performance of vertical channel transistors (VSTs) is susceptible to the floating body effect. Holes generated by gate-induced drain leakage (GIDL) accumulate at the floating substrate end of the VST, causing a shift in the threshold voltage and affecting its electrical performance. This application addresses this issue by controlling the silicon substrate growth time or employing a growth-then-etching method to achieve a thinner silicon channel, ensuring the channel is fully depleted by the source and drain, thus avoiding the floating body effect.

[0133] 504. A dielectric layer 460 is grown on the dielectric stack to cover and protect the N-type vertical channel transistor region. This dielectric layer 460 includes, but is not limited to, silicon nitride. Subsequently, the dielectric stack is etched, with the surface of the substrate 410 serving as a stop layer for etching, forming the third channel region 423 of the P-type vertical channel transistor. During the etching process, the N-type vertical channel transistor region is protected by the dielectric layer 460 and is therefore not damaged during the etching stage.

[0134] On existing memory wafers with vertical-channel transistors (VSTs), only N-type VSTs exist as part of the 1T1C memory cell; P-type VSTs are absent. If the sense amplifier circuit is built solely based on N-type VSTs, its power consumption will be very high. The memory array wafer provided in this application embodiment can include different types of VSTs to construct a low-power sense amplifier circuit.

[0135] It should be understood that the formation of the N-type vertical channel transistor region followed by the P-type vertical channel transistor region in steps 503 and 504 is merely an example. Alternatively, the P-type vertical channel transistor region can be formed first, followed by the N-type vertical channel transistor region; this application does not impose any limitation on this. The N-type and P-type vertical channel transistor regions may include one transistor or multiple transistors; this application does not impose any limitation on the number of transistors included in the N-type and P-type vertical channel transistor regions.

[0136] 505. An N-type silicon substrate is grown on the sidewall of the third channel region 423 formed by etching in the previous step to serve as the channel for a P-type vertical channel transistor. The growth methods include, but are not limited to, ALD, CVD, and PVD. The grown silicon substrate is polycrystalline or amorphous. Due to its numerous grain boundaries, it hinders carrier migration and therefore has a low carrier mobility, requiring subsequent crystallization treatment to improve its electrical performance. The N-type silicon substrate can be formed by adding pentavalent impurity elements (such as phosphorus or arsenic) to the silicon raw material; these impurities provide additional free electrons. An N-type silicon substrate is grown on the sidewall of the third channel region 423 to form the third channel 413.

[0137] After the channel growth of the P-type vertical channel transistor is completed, a dielectric layer 470 is filled inside the channel of the P-type vertical channel transistor. The dielectric layer 470 includes, but is not limited to, silicon oxide.

[0138] 506. The wafer surface is smoothed by chemical mechanical polishing (CMP) process, with dielectric layer 440 as the stop layer of CMP, in order to remove the excess channel portion of the P-type vertical channel transistor.

[0139] 507. A layer of metallic material is grown on the surface of the wafer. For example, the metallic material may be nickel (Ni), which has the effect of promoting the crystallization of polycrystalline or amorphous silicon.

[0140] 508. This involves metal-induced crystallization of previously deposited polycrystalline or amorphous silicon channels. In some possible implementations, since Ni can form the NiSi2 phase with Si at relatively low temperatures (e.g., 280°C), and the lattice constant of NiSi2 is very close to that of single-crystal silicon, metal-induced lateral crystallization (MILC) can be used to first form NiSi2 at the Ni-Si interface, and then crystallize the polycrystalline or amorphous silicon through grain boundary growth and diffusion to obtain a morphology close to that of single-crystal silicon, thereby improving the electrical properties of the channel, such as carrier mobility.

[0141] 509. The metal material on the wafer surface is removed by processes such as CMP or wet cleaning to expose the crystallized channel material.

[0142] 510. The dielectric layer structure is etched to form trenches, with the surface of the substrate 410 as the etching stop layer. The etching method includes, but is not limited to, dry etching. The purpose of this step is to open a channel for subsequent etching of the dielectric layer 430 using an etchant.

[0143] 511, Etching is performed on dielectric layer 430. The etching method includes, but is not limited to, wet etching using an etchant. The etchant includes, but is not limited to, thermal phosphoric acid. After etching, the silicon channel of the vertical channel transistor is exposed.

[0144] 512. A gate oxide layer 405 is grown on the exposed channel surface in the previous step. The growth method includes, but is not limited to, oxidizing the exposed silicon on the surface of the silicon channel into silicon oxide as the gate oxide layer 405 by thermal oxidation, thereby forming isolation between the gate and the channel.

[0145] 513. A gate 406 is grown on the surface of the gate oxide layer 405 formed in the previous step to serve as a word line of the memory. The material of the gate 406 includes, but is not limited to, metallic materials such as tungsten (W) and conductive materials such as titanium nitride (TiN).

[0146] N-type vertical-channel transistors and P-type vertical-channel transistors can use the same gate material or different gate materials; this application does not impose any limitation on this. It should be understood that when the gates of N-type and P-type vertical-channel transistors are the same, the gate 406 of both transistors can be grown simultaneously. When the gates of N-type and P-type vertical-channel transistors are different, the gate 406 can be grown separately.

[0147] 514. After the gate 406 is formed, the dielectric layer 480 is backfilled in the trench formed in step 510 and in the original location of the dielectric layer 430. The dielectric layer 480 includes, but is not limited to, silicon oxide.

[0148] 515. One end of the channel of the N-type vertical channel transistor and the P-type vertical channel transistor are doped to form a drain 408. Specifically, one end of the channel (first channel 411 and second channel 412) of the N-type vertical channel transistor is N-type doped, with doping elements including but not limited to phosphorus (P) and arsenic (As). The N-type vertical channel transistor includes a first vertical channel transistor 401 in the memory array region and a second vertical channel transistor 402 in the sense amplifier circuit region. One end of the channel (third channel 413) of the P-type vertical channel transistor is P-type doped, with doping elements including but not limited to boron (B). The P-type vertical channel transistor includes a third vertical channel transistor 403 in the sense amplifier circuit region.

[0149] Alternatively, the source electrode may be doped first and then the drain electrode may be doped. This example should not be construed as a limitation of this application.

[0150] 516. After completing the doping of the drain 408 on the front side of the wafer, the memory array wafer is flipped so that the back side of the substrate 410 faces upward.

[0151] 517. Thin the back side of the memory array wafer until the dielectric layer 420, the channel of the N-type vertical channel transistor, and the channel of the P-type vertical channel transistor are exposed.

[0152] 518. On the back side of the wafer, the other ends of the channels of the N-type vertical channel transistor and the P-type vertical channel transistor are doped to form source 407. Specifically, the other end of the channel (first channel 411 and second channel 412) of the N-type vertical channel transistor is N-type doped, with doping elements including but not limited to P and As. The N-type vertical channel transistor includes a first vertical channel transistor 401 in the memory array region and a second vertical channel transistor 402 in the sense amplifier circuit region. The other end of the channel (third channel 413) of the P-type vertical channel transistor is P-type doped, with doping elements including but not limited to boron (B). The P-type vertical channel transistor includes a third vertical channel transistor 403 in the sense amplifier circuit region.

[0153] After the vertical-channel transistor is formed, dielectric capacitors or ferroelectric capacitors can be formed on the first vertical-channel transistor 401 in the memory array region to form a complete DRAM or ferroelectric random access memory (FeRAM). If a dielectric capacitor is formed on the first vertical-channel transistor 401 in the memory array region, DRAM can be formed; if a ferroelectric capacitor is formed on the first vertical-channel transistor 401 in the memory array region, FeRAM can be formed.

[0154] For the sensing amplifier circuit region, the channel widths of N-type and P-type vertical-channel transistors can be controlled by photolithographic patterns. In some possible implementations, vertical-channel transistors with different equivalent channel lengths can be achieved by connecting multiple vertical-channel transistors in series to meet different transistor size requirements of the circuit design.

[0155] Figure 9 This is a schematic diagram of another memory array wafer provided in an embodiment of this application.

[0156] The memory array wafer 900 includes a first vertical channel transistor 901, a second vertical channel transistor 902, a third vertical channel transistor 903, a dielectric layer 970, and a dielectric layer 980. The dielectric layer 970 is used to isolate adjacent channels, and the dielectric layer 980 is used to isolate adjacent gates.

[0157] The first vertical-channel transistor 901 and the second vertical-channel transistor 902 are N-type vertical-channel transistors, and the third vertical-channel transistor 903 is a P-type vertical-channel transistor. The first vertical-channel transistor 901 and the second vertical-channel transistor 902 have the same channel and the same gate, while the first vertical-channel transistor 901 and the third vertical-channel transistor 903 have the same channel but different gates.

[0158] The first vertical channel transistor 901 includes a first channel 911, a gate oxide layer 905, a first gate 931, a source 907, and a drain 908. The source 907 and the drain 908 are located at both ends of the first channel 911, and the gate oxide layer 905 is located between the first channel 911 and the first gate 931 to isolate the first channel 911 and the first gate 931.

[0159] The second vertical channel transistor 902 includes a second channel 912, a gate oxide layer 905, a second gate 932, a source 907, and a drain 908. The source 907 and the drain 908 are located at both ends of the second channel 912, and the gate oxide layer 905 is located between the second channel 912 and the second gate 932 to isolate the second channel 912 and the second gate 932.

[0160] The third vertical channel transistor 903 includes a third channel 913, a gate oxide layer 905, a third gate 933, a source 907, and a drain 908. The source 907 and the drain 908 are located at both ends of the third channel 913. The gate oxide layer 905 is located between the third channel 913 and the third gate 933 and is used to isolate the third channel 913 and the third gate 933.

[0161] It should be understood that Figure 9 The four first vertical-channel transistors 901, two second vertical-channel transistors 902, and two third vertical-channel transistors 903 included are for illustrative purposes only; this application does not limit the number of transistors. A capacitor is also connected to the source 907 or drain 908 of the first vertical-channel transistor 901, but is not shown in the figure. The positions of the source 907 and drain 908 can also be interchanged.

[0162] Figures 10-15 This is an exemplary flowchart of another method for fabricating a memory provided in this application embodiment. This method can be used to fabricate... Figure 9 The memory array wafer 900 is shown. Figure 10 Including steps 1001 to 1004, Figure 11 Including steps 1005 to 1008, Figure 12 Including steps 1009 to 1012, Figure 13 Including steps 1013 to 1016, Figure 14 Including steps 1017 to 1019, Figure 15This includes steps 1020 to 1022.

[0163] 1001. A mask layer 920 is deposited on a substrate 910, wherein the material of the substrate 910 includes, but is not limited to, monocrystalline silicon, and the mask layer 920 includes, but is not limited to, amorphous carbon.

[0164] 1002, the substrate 910 is etched to form a first transistor setting region 921, a second transistor setting region 922, and a third transistor setting region 923. The etching method includes, but is not limited to, dry etching. In some possible implementations, the pattern to be etched can first be formed on the mask layer 920 by photolithography, and then the mask layer 920 can be used as a mask to etch the substrate 910.

[0165] 1003. A gate oxide layer 905 is grown on the sidewalls of the first transistor setting region 921, the second transistor setting region 922, and the third transistor setting region 923 formed in the previous step. The growth method includes, but is not limited to, thermal oxidation, CVD, PVD, and other deposition methods. In some possible implementations, the exposed silicon on the surfaces of the first transistor setting region 921, the second transistor setting region 922, and the third transistor setting region 923 can be oxidized to silicon oxide as the gate oxide layer 905 by thermal oxidation, thereby forming isolation between the gate and the channel.

[0166] 1004. After the gate oxide layer 905 is grown, the gates of the N-type and P-type vertical channel transistors are grown separately. In this embodiment, the gate of the N-type vertical channel transistor is grown first, followed by the gate of the P-type vertical channel transistor. However, the gate of the P-type vertical channel transistor can also be grown first, followed by the gate of the N-type vertical channel transistor. Before growing the gate of the N-type vertical channel transistor, the gate region of the P-type vertical channel transistor needs to be filled with a dielectric layer 930. The material of the dielectric layer 930 includes, but is not limited to, silicon nitride.

[0167] 1005. A gate material with an N-type work function layer is deposited in the trench of an N-type vertical channel transistor. The N-type work function layer includes, but is not limited to, lanthanum oxide (La₂O₃), and its function is to adjust the work function of the gate material. The gate material of the N-type vertical channel transistor includes, but is not limited to, conductive materials such as TiN, and its function is to form the gate of the N-type vertical channel transistor. A first gate 931 is formed by depositing the gate material with an N-type work function layer in the first transistor setting region 921, and a second gate 932 is formed by depositing the gate material with an N-type work function layer in the second transistor setting region 922. The gates of the N-type vertical channel transistors located in the memory array region are connected to form a word line structure.

[0168] 1006. The gates of the N-type vertical channel transistor are etched back, specifically the first gate 931 and the second gate 932, so that their upper surfaces are lower than the upper surface of the substrate 910. Etching methods include, but are not limited to, dry etching. After the etch back is completed, a dielectric layer 940 is filled into the etch-back grooves, and CMP is performed to smooth it. This dielectric layer 940 includes, but is not limited to, silicon oxide. In some possible implementations, vertical channel transistors with different gate lengths can be achieved by controlling the etch back depth.

[0169] 1007. The dielectric layer 930 filling the trench of the P-type vertical channel transistor is removed by etching. The etching method includes, but is not limited to, wet etching with an etchant. The etchant includes, but is not limited to, reagents such as hot phosphoric acid. This etchant has a high etch selectivity, that is, it has a high etching rate only for the material of the dielectric layer 930 without affecting other materials, so as to expose the gate oxide layer 905 of the P-type vertical channel transistor.

[0170] 1008. A gate material with a P-type work function layer is deposited in the groove of the P-type vertical channel transistor formed by etching in the previous step. The P-type work function layer includes, but is not limited to, aluminum oxide (Al2O3), and its function is to adjust the work function of the gate material. The gate material of the P-type vertical channel transistor includes, but is not limited to, conductive materials such as TiN, and its function is to form the gate of the P-type vertical channel transistor. A gate material with a P-type work function layer is deposited in the third transistor setting region 923 to form the third gate 933.

[0171] 1009. The third gate 933 of the P-type vertical channel transistor is etched back so that its upper surface is lower than the upper surface of the substrate 910. The etching method includes, but is not limited to, dry etching. After the etch back is completed, a dielectric layer 940 is filled in the groove formed by the etch back and then CMP is performed to smooth it. The dielectric layer 940 includes, but is not limited to, silicon oxide. In some possible implementations, vertical channel transistors with different gate lengths can be achieved by controlling the depth of the etch back.

[0172] 1010, Etching to remove mask layer 920, the etching method including but not limited to high temperature processing, to remove mask layer 920 of materials such as amorphous carbon to expose the upper surface of substrate 910.

[0173] 1011. Since the channel structures of N-type vertical channel transistors and P-type vertical channel transistors will be formed by etching later, a mask layer 950 needs to be deposited in the area where etching is not required.

[0174] 1012. A dielectric layer 960 is deposited on the wafer surface. The deposition method includes, but is not limited to, methods with high conformability such as ALD and CVD, which can maintain the original shape of the wafer surface after deposition. The material of the dielectric layer 960 includes, but is not limited to, silicon nitride, which can be used as a mask layer for subsequent etching processes.

[0175] 1013, A dielectric layer 960 of a certain thickness is uniformly etched on the wafer surface to form a mask structure for subsequent channels. The etching method includes, but is not limited to, dry etching.

[0176] 1014. Based on the mask structure formed in the previous step, the substrate 910 is etched to form the channel structures of the N-type vertical channel transistor and the P-type vertical channel transistor, including the first channel 911 of the first vertical channel transistor 901, the second channel 912 of the second vertical channel transistor 902, and the third channel 913 of the third vertical channel transistor 903. This self-aligned etching method allows for control over the thinness of the channels in the N-type and P-type vertical channel transistors, effectively suppressing the floating body effect.

[0177] 1015. A dielectric layer 970 is filled into the trenches formed by etching in step 1014 to isolate adjacent channels. This dielectric layer 970 includes, but is not limited to, silicon oxide. When the trenches between adjacent channels are narrow, the dielectric layer 970 may not be able to completely fill the trenches, resulting in an air gap in the trenches. Since the air gap has a very low dielectric constant, it can effectively avoid capacitive coupling interference between channels. Simultaneously, the dielectric layer 970 also serves as an isolation material between the memory array region and the sense amplifier circuit region, as well as an isolation material for N-type vertical-channel transistors and P-type vertical-channel transistors in the sense amplifier circuit region.

[0178] 1016. The gate and dielectric layer 940 in the first transistor setting region 921, the second transistor setting region 922 and the third transistor setting region 923 are etched to make them the gates of two vertical channel transistors on the left and right sides, respectively, and control the channels on the left and right sides to form two vertical channel transistors.

[0179] Specifically, the first gate 931 and dielectric layer 940 of the first transistor setting region 921 are etched to form the first gate 931 of two N-type vertical channel transistors on the left and right sides, respectively, controlling the first channel 911 of the N-type vertical channel transistors on the left and right sides; the second gate 932 and dielectric layer 940 of the second transistor setting region 922 are etched to form the second gate 932 of two N-type vertical channel transistors on the left and right sides, respectively, controlling the second channel 912 of the N-type vertical channel transistors on the left and right sides; the third gate 933 and dielectric layer 940 of the third transistor setting region 923 are etched to form the third gate 933 of two N-type vertical channel transistors on the left and right sides, respectively, controlling the third channel 913 of the N-type vertical channel transistors on the left and right sides.

[0180] 1017. The trench formed by etching in step 1016 is filled with dielectric layer 980 as an isolation material between two adjacent gates. When the width of the trench is small, dielectric layer 980 may not be able to completely fill the trench, in which case an air gap will be formed in the trench. Since the air gap has a very low dielectric constant, it can effectively avoid capacitive coupling interference between word lines.

[0181] 1018, The wafer surface is smoothed by CMP to expose the upper surface of the wafer substrate 910.

[0182] 1019. On the upper surface of the wafer substrate 910, one end of the channel of the N-type vertical channel transistor and the P-type vertical channel transistor are doped to form the source 907. Specifically, one end of the channel (first channel 911 and second channel 912) of the N-type vertical channel transistor is N-type doped, with doping elements including but not limited to phosphorus (P) and arsenic (As). The N-type vertical channel transistor includes a first vertical channel transistor 901 in the memory array region and a second vertical channel transistor 902 in the sense amplifier circuit region. One end of the channel (third channel 913) of the P-type vertical channel transistor is P-type doped, with doping elements including but not limited to boron (B). The P-type vertical channel transistor includes a third vertical channel transistor 903 in the sense amplifier circuit region.

[0183] 1020. The memory array wafer is flipped so that the lower surface of the wafer substrate 910 faces upward. The substrate 910 of the memory array wafer is thinned until the other end of the channel of the N-type vertical channel transistor and the P-type vertical channel transistor is exposed, that is, the end to be doped to form the drain 908.

[0184] 1021. On the lower surface of the wafer substrate 910, the other ends of the channels of the N-type vertical channel transistor and the P-type vertical channel transistor are doped to form drains 908. Specifically, one end of the channel (first channel 911 and second channel 912) of the N-type vertical channel transistor is N-type doped, with doping elements including but not limited to P and As. The N-type vertical channel transistor includes a first vertical channel transistor 901 in the memory array region and a second vertical channel transistor 902 in the sense amplifier circuit region. One end of the channel (third channel 913) of the P-type vertical channel transistor is P-type doped, with doping elements including but not limited to B. The P-type vertical channel transistor includes a third vertical channel transistor 903 in the sense amplifier circuit region.

[0185] 1022, Flip the memory array wafer so that the upper surface of the wafer substrate 910 faces upward.

[0186] After the vertical channel transistor is formed, dielectric capacitors or ferroelectric capacitors can be formed on the first vertical channel transistor 901 in the memory array region to form a complete DRAM or FeRAM. If a dielectric capacitor is formed on the first vertical channel transistor 901 in the memory array region, DRAM can be formed; if a ferroelectric capacitor is formed on the first vertical channel transistor 901 in the memory array region, FeRAM can be formed.

[0187] For the sensing amplifier circuit region, the channel widths of N-type and P-type vertical-channel transistors can be controlled by photolithographic patterns. In some possible implementations, vertical-channel transistors with different equivalent channel lengths can be achieved by connecting multiple vertical-channel transistors in series to meet different transistor size requirements of the circuit design.

[0188] In this embodiment, the memory array wafer simultaneously includes a memory array and a sense amplifier circuit. Data in the memory array can be read through the read circuit in the sense amplifier circuit on the memory array wafer. Since the corresponding bit line capacitance is small at this time, a large read window is available during reading, thereby effectively reducing the data read error rate. After the read circuit completes the data reading, the read data can be further transmitted to the peripheral circuit wafer for data interaction with the outside world.

[0189] Figure 16 This is a schematic diagram of another memory structure provided in an embodiment of this application.

[0190] The memory includes stacked peripheral circuit wafers and n memory array wafers, with adjacent memory array wafers bonded together, where n > 1. The peripheral circuit wafers are bonded to at least one of the n memory array wafers (e.g., memory array wafer 1) and are equipped with peripheral circuitry.

[0191] Each memory array wafer includes a memory array and a sense amplifier circuit. The memory array includes multiple memory cells, each memory cell including a first vertical-channel transistor and a capacitor, the first vertical-channel transistor being connected to the capacitor. The sense amplifier circuit is used to transmit data in the memory cell. Peripheral circuitry includes a data transmission circuit and an error correction circuit. The data transmission circuit is used to communicate with the sense amplifier circuit and devices outside the memory, and the error correction circuit is used to check for errors in reading or writing data in the memory cell.

[0192] In one possible implementation, the sense amplifier circuit includes a second vertical channel transistor and a third vertical channel transistor.

[0193] In one possible implementation, the first vertical-channel transistor, the second vertical-channel transistor, and the third vertical-channel transistor are vertical-channel transistors of the same type. For example, the first vertical-channel transistor, the second vertical-channel transistor, and the third vertical-channel transistor are all N-type vertical-channel transistors or all P-type vertical-channel transistors.

[0194] In one possible implementation, the first vertical-channel transistor, the second vertical-channel transistor, and the third vertical-channel transistor include at least two types of vertical-channel transistors. For example, the first vertical-channel transistor and the second vertical-channel transistor are N-type vertical-channel transistors, and the third vertical-channel transistor is a P-type vertical-channel transistor; or, the first vertical-channel transistor and the second vertical-channel transistor are P-type vertical-channel transistors, and the third vertical-channel transistor is an N-type vertical-channel transistor.

[0195] The capacitor connected to the first vertical-channel transistor can be a dielectric capacitor or a ferroelectric capacitor, and this capacitor is connected to the source or drain of the first vertical-channel transistor. When the capacitor is a dielectric capacitor, the memory is DRAM; when the capacitor is a ferroelectric capacitor, the memory is FeRAM.

[0196] Figure 17 This is a schematic diagram of another memory structure provided in an embodiment of this application.

[0197] The memory includes stacked peripheral circuit wafers and n memory array wafers. Each memory array wafer includes a memory array 171 and a sense amplifier circuit 172. The memory array 171 includes multiple arrayed memory cells, each of which can store 1 bit or more bits of data. The memory array 171 may also include word lines (WL), bit lines (BL), source lines (SL), and precharge lines (CL). Each memory cell is electrically connected to a corresponding word line WL, bit line BL, source line SL, and precharge line CL. Different memory cells can be electrically connected via WL, BL, SL, or CL. For convenience, the above-mentioned WL, BL, SL, and CL are collectively referred to as signal lines in this embodiment.

[0198] The peripheral circuit wafer includes a data transmission circuit 173 and an error correction circuit 174. Optionally, it may also include one or more of a buffer 175, a timing controller 176, a driver 177, and a decoder 178. The sense amplifier circuit 172 of each memory array wafer is connected to the data transmission circuit 173, and can transmit data from the memory cell to the data transmission circuit 173.

[0199] Buffer 175 is used to buffer read data, for example, using a first-in-first-out (FIFO) buffering method. Error correction circuit 174 is used to check for errors in reading or writing data in the memory cell and can also correct erroneous data. Data transmission circuit 173 is used to communicate with sense amplifier circuit 172 and external devices. Decoder 178 is used to decode the memory cell address and command. Decoder 178 decodes the received address to determine the memory cell to be accessed. Driver 177 controls the level of signal lines based on the decoding result generated by decoder 178, thereby enabling access to the specified memory cell. Timing controller 176 controls the timing of buffer 175 and controls driver 177 to drive the signal lines in memory array 171.

[0200] Figure 18This is a schematic diagram of an electronic device provided in an embodiment of this application. The electronic device 1800 includes a chip 1810 and a circuit board 1820, with the chip 1810 disposed on the circuit board 1820. An electronic device 1830 may also be disposed on the circuit board 1820. The electronic device 1830 can be electrically or communicatively connected to the chip 1810. For example, the electronic device 1830 can be a camera module, a radio frequency module, an audio module, etc. The electronic device 1800 provided in this embodiment can be, but is not limited to, terminal devices (e.g., mobile terminals, wearable terminals, etc.), communication devices (e.g., servers, network products, etc.), home appliances, vehicle-mounted devices, energy storage devices, etc.

[0201] In some possible implementations, chip 1810 includes memory 1811, memory controller 1812, and substrate 1813. The memory 1811 can be... Figure 1 , Figure 2 , Figure 16 The memory 1811 and memory controller 1812 are disposed on substrate 1813, with memory controller 1812 used to control the memory 1811. Exemplarily, the memory 1811 can be connected to the surface of substrate 1813 via connectors (e.g., solder balls, pads, or wire bonding). Other devices, including but not limited to passive devices (capacitors, inductors, etc.), can also be disposed on the surface of substrate 1813. Substrate 1813 connects the memory 1811 and circuit board 1820 to facilitate the transmission of current and other signals between the memory 1811 and circuit board 1820.

[0202] In some possible implementations, chip 1810 can be fixed to circuit board 1820 by solder balls, or chip 1810 can be assembled on the surface of circuit board 1820 using surface mounted technology (SMT). Chip 1810 and other circuits or electronic components on circuit board 1820 can be electrically connected. For example, chip 1810 can be electrically connected to other circuits or electronic components on circuit board 1820 by gold wire bonding, or chip 1810 can be electrically connected to other circuits or electronic components on circuit board 1820 through structures such as solder pads.

[0203] Figure 19 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application.

[0204] The electronic device 1900 can be a terminal device, such as a mobile phone, tablet computer, or smart bracelet, or a personal computer (PC), server, workstation, etc. The electronic device 1900 includes a bus 1905 and a system-on-chip (SoC) 1910 connected to the bus 1905. The SoC 1910 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one possible implementation, the SoC 1910 may include an application processor (AP) 1911 for processing applications, a graphics processing unit (GPU) 1912 for processing image data, and a first RAM 1913 for caching high-speed data. The first RAM 1913 can be static random-access memory (SRAM) or embedded flash memory (EFlash), etc. The AP 1911, GPU 1912, and first RAM 1913 can be integrated into a single die or disposed in multiple dies. The electronic device 1900 may further include a second RAM 1920 connected to the SoC 1910 via a bus 1905. This second RAM 1920 may be the DRAM provided in the embodiments of this application. The second RAM 1920 may be used to store volatile data, such as temporary data generated by the SoC 1910. The storage capacity of the second RAM 1920 is typically larger than that of the first RAM 1913, but its read speed is typically slower. Furthermore, the electronic device 1900 may also include a communication chip 1930 and / or a power management chip 1940 connected to the SoC 1910 via a bus 1905. The communication chip 1930 may be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 1940 may be used to supply power to other chips. In one embodiment, the SoC 1910 and the second RAM 1920 may be packaged in a single package structure, such as using 2.5D (dimension) or 3D packaging, to achieve a faster inter-chip data transfer rate.

[0205] It should be noted that, in the embodiments of this application, when one device is "connected" to another device, it can be a direct connection to the other device, or there can be an intermediate device between them. "Connection" can be "electrical connection," "coupling," etc., and this application does not limit the terminology.

[0206] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the scope of this application. It should be understood that the above are illustrative examples, and the examples above are merely to help those skilled in the art understand the embodiments of this application, and are not intended to limit the embodiments of the application to the specific numerical values ​​or specific scenarios exemplified. Those skilled in the art can obviously make various equivalent modifications or variations based on the examples given above, and such modifications and variations also fall within the scope of the embodiments of this application.

[0207] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: Multiple memory array wafers are stacked together, with adjacent memory array wafers bonded together. Each memory array wafer includes a memory array and a sense amplifier circuit. The memory array includes multiple memory cells, each memory cell includes a first vertical channel transistor, and the multiple memory cells include a first memory cell. The sense amplifier circuit is used to transmit first data in the first memory cell.

2. The memory according to claim 1, characterized in that, It also includes a peripheral circuit wafer, which is bonded to at least one of the plurality of memory array wafers and is provided with peripheral circuits. The peripheral circuits include a data transmission circuit and an error correction circuit. The data transmission circuit is used to communicate with the sensing amplifier circuit and devices outside the memory. The error correction circuit is used to check whether there is an error in reading or writing the first data.

3. The memory according to claim 1 or 2, characterized in that, The sensing amplifier circuit includes a second vertical channel transistor and a third vertical channel transistor.

4. The memory according to claim 3, characterized in that, The first vertical channel transistor and the second vertical channel transistor are N-type vertical channel transistors, and the third vertical channel transistor is a P-type vertical channel transistor.

5. The memory according to claim 4, characterized in that, The first channel of the first vertical channel transistor and the second channel of the second vertical channel transistor are formed on a P-type silicon substrate, and the third channel of the third vertical channel transistor is formed on an N-type silicon substrate.

6. The memory according to claim 4 or 5, characterized in that, The first gate of the first vertical channel transistor and the second gate of the second vertical channel transistor are provided with an N-type work function layer, and the third gate of the third vertical channel transistor is provided with a P-type work function layer.

7. The memory according to any one of claims 1 to 6, characterized in that, The transistors in each memory array wafer are vertical channel transistors.

8. The memory according to any one of claims 1 to 7, characterized in that, The first storage unit further includes a dielectric capacitor connected to the first vertical channel transistor, and the memory is a dynamic random access memory (DRAM).

9. The memory according to any one of claims 1 to 7, characterized in that, The first storage unit further includes a ferroelectric capacitor connected to the first vertical channel transistor, and the memory is a ferroelectric random access memory (FeRAM).

10. A method for fabricating a memory, characterized in that, include: Multiple memory array wafers are formed, each memory array wafer including a memory array and a sense amplifier circuit. The memory array includes multiple memory cells, each memory cell including a first vertical channel transistor. The multiple memory cells include a first memory cell. The sense amplifier circuit is used to transmit first data in the first memory cell. The plurality of memory array wafers are stacked, and two adjacent memory array wafers are bonded together.

11. The method according to claim 10, characterized in that, The method further includes: A peripheral circuit wafer is formed, the peripheral circuit wafer is provided with peripheral circuits, the peripheral circuits include a data transmission circuit and an error correction circuit, the data transmission circuit is used to communicate with the sensing amplifier circuit and devices outside the memory, and the error correction circuit is used to check whether the reading or writing of the first data is incorrect; The peripheral circuit wafer is bonded to at least one of the plurality of memory array wafers.

12. The method according to claim 10 or 11, characterized in that, The sensing amplifier circuit includes a second vertical channel transistor and a third vertical channel transistor.

13. The method according to claim 12, characterized in that, The first vertical channel transistor and the second vertical channel transistor are N-type vertical channel transistors, and the third vertical channel transistor is a P-type vertical channel transistor.

14. The method according to claim 12 or 13, characterized in that, The process of forming multiple memory array wafers includes: A first channel of the first vertical channel transistor, a second channel of the second vertical channel transistor, and a third channel of the third vertical channel transistor are formed on a first memory array wafer, wherein the first memory array wafer is one of the plurality of memory array wafers; A first gate oxide layer is formed on the surface of the first channel, a second gate oxide layer is formed on the surface of the second channel, and a third gate oxide layer is formed on the surface of the third channel; A first gate is formed on the surface of the first gate oxide layer, a second gate is formed on the surface of the second gate oxide layer, and a third gate is formed on the surface of the third gate oxide layer; The source and drain of the first vertical channel transistor, the second vertical channel transistor, and the third vertical channel transistor are formed; Connect the capacitor to the source or drain of the first vertical channel transistor.

15. The method according to claim 14, characterized in that, The process of forming a first channel of the first vertical channel transistor, a second channel of the second vertical channel transistor, and a third channel of the third vertical channel transistor on the first memory array wafer includes: Deposit a dielectric layer on the substrate; The dielectric layer is etched to form a first trench region, a second trench region, and a third trench region; A P-type silicon substrate is grown on the sidewall of the first channel setting region to form the first channel, a P-type silicon substrate is grown on the sidewall of the second channel setting region to form the second channel, and an N-type silicon substrate is grown on the sidewall of the third channel setting region to form the third channel.

16. The method according to claim 14 or 15, characterized in that, The step of forming a first gate on the surface of the first gate oxide layer, forming a second gate on the surface of the second gate oxide layer, and forming a third gate on the surface of the third gate oxide layer includes: A gate material with an N-type work function layer is disposed on the surface of the first gate oxide layer to form a first gate; A gate material with an N-type work function layer is disposed on the surface of the second gate oxide layer to form a second gate; A gate material with a P-type work function layer is disposed on the surface of the third gate oxide layer to form the third gate.

17. The method according to any one of claims 14 to 16, characterized in that, The source and drain of the first vertical channel transistor, the second vertical channel transistor, and the third vertical channel transistor include: The two ends of the first channel and the second channel are N-type doped to form the source and drain of the first vertical channel transistor and the second vertical channel transistor. P-type doping is performed at both ends of the third channel to form the source and drain of the third vertical channel transistor.

18. The method according to any one of claims 10 to 17, characterized in that, The transistors in each memory array wafer are vertical channel transistors.

19. The method according to any one of claims 10 to 18, characterized in that, The first storage unit further includes a dielectric capacitor connected to the first vertical channel transistor, and the memory is a dynamic random access memory (DRAM).

20. The method according to any one of claims 10 to 18, characterized in that, The first storage unit further includes a ferroelectric capacitor connected to the first vertical channel transistor, and the memory is a ferroelectric random access memory (FeRAM).

21. A chip, characterized in that, It includes a storage controller and a memory as described in any one of claims 1 to 9, wherein the storage controller and the memory are electrically connected.

22. An electronic device, characterized in that, It includes a circuit board and the chip of claim 21, wherein the chip is disposed on the circuit board and electrically connected to the circuit board.

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