Semiconductor memory device

Abstract

The semiconductor memory device includes: a substrate including an active region; a bit line structure on the substrate, the bit line structure including a unit conductive line and a unit line cover film; a memory contact disposed on an opposite side of the bit line structure and connected to the active region; a memory pad on one of the memory contacts and connected to the one of the memory contacts; and a data storage pattern on an upper surface of the cell line cover film and connected to the storage pads, in which the storage pads include an upper storage pad and a lower storage pad disposed between the upper storage pad and the storage contact, wherein a width of the upper memory pad disposed on top of an upper surface of the unit line cover film increases as a distance from the upper surface of the unit line cover film increases.

Description

Semiconductor memory devices Technical Field

[0001] This disclosure relates to semiconductor memory devices, and more specifically, to semiconductor memory devices having multiple intersecting wiring lines and buried contacts. Background Technology

[0002] As semiconductor devices become increasingly integrated, circuit patterns are becoming smaller and smaller in order to implement a larger number of semiconductor devices within the same area. In other words, as the integration level of semiconductor devices increases, the design rules for the individual components of semiconductor devices decrease.

[0003] In highly miniaturized semiconductor devices, the process of forming multiple wiring lines and inserting multiple buried contacts (BCs) can become increasingly complex and sophisticated. Summary of the Invention

[0004] The various aspects of this disclosure provide semiconductor memory devices with improved reliability and performance.

[0005] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0006] According to embodiments of the present disclosure, a semiconductor memory device is provided, comprising: a substrate including an active region demarcated by an element isolation film; a bit line structure on the substrate, the bit line structure including a cell conductive line and a cell line capping film, wherein the cell line capping film extends thereon along an upper surface of the cell conductive line; a memory contact on an opposite side of the bit line structure and connected to the active region; a memory pad on and connected to one of the memory contacts; and a data storage pattern on an upper surface of the cell line capping film and connected to the memory pad, wherein the memory pad includes an upper memory pad and a lower memory pad between the upper memory pad and the memory contact, wherein the width of the upper memory pad on the top of the upper surface of the cell line capping film increases with increasing distance from the upper surface of the cell line capping film.

[0007] According to embodiments of the present disclosure, a semiconductor memory device is provided, comprising: a substrate including an active region demarcated by an element isolation film; a bit line structure on the substrate including cell conductive lines and a cell line capping film stacked in a first direction, wherein the cell line capping film extends thereon along an upper surface of the cell conductive lines; a memory contact on an opposite side of the bit line structure and connected to the active region; a memory pad on and connected to one of the memory contacts; and a data storage pattern on an upper surface of the cell line capping film and connected to the memory pad, wherein the memory pad includes an upper memory pad and a lower memory pad between the upper memory pad and the memory contact, wherein the upper memory pad includes an upper surface connected to the data storage pattern, a bottom surface in contact with the lower memory pad and the bit line structure, and a sidewall connecting the upper surface and the bottom surface of the upper memory pad to each other, wherein the upper memory pad includes an upper pad filler film and an upper pad silicide film, wherein the upper pad silicide film includes the sidewall of the upper memory pad.

[0008] According to embodiments of the present disclosure, a semiconductor memory device is provided, comprising: a substrate including a cell region and a peripheral region surrounding the cell region, the cell region including a cell active region demarcated by a cell element isolation film; a bit line structure on the cell region of the substrate and including cell conductive lines and a cell line capping film, wherein the cell line capping film extends thereon along an upper surface of the cell conductive lines; a peripheral gate structure on the peripheral region of the substrate and including a peripheral gate conductive film; peripheral wiring lines on the peripheral gate structure; a memory contact connected to the cell active region; a memory pad connected to the memory contact; a pad isolation pattern isolating adjacent memory pads in the memory pads from each other; and a data storage pattern on the upper surface of the cell line capping film and connected to the memory pads, wherein the memory pads include an upper memory pad and a lower memory pad disposed between the upper memory pad and the memory contact, wherein the upper memory pad includes a first portion disposed on the upper surface of the cell line capping film and a second portion between the first portion of the upper memory pad and the lower memory pad, wherein the width of the first portion of the upper memory pad increases with increasing distance from the upper surface of the cell line capping film.

[0009] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be apparent from the following description. Attached Figure Description

[0010] The above and other features of this disclosure will become more apparent from a detailed description of some embodiments thereof with reference to the accompanying drawings listed below.

[0011] Figure 1 is a schematic layout diagram of a semiconductor memory device according to some embodiments.

[0012] Figure 2 is a layout diagram of region R, which is part of the unit area in Figure 1.

[0013] Figure 3 is a layout diagram showing only the word lines and active areas of Figure 2.

[0014] Figure 4 is a cross-sectional view taken along line AA in Figure 1.

[0015] Figures 5 and 6 are cross-sectional views taken along lines BB and CC in Figure 2, respectively.

[0016] Figure 7 is an enlarged view of part P in Figure 4.

[0017] Figure 8 is an enlarged view of part Q in Figure 5.

[0018] Figures 9 and 10 are diagrams illustrating a semiconductor memory device according to some embodiments.

[0019] Figures 11 and 12 are diagrams illustrating a semiconductor memory device according to some embodiments.

[0020] Figures 13 to 15 are diagrams illustrating semiconductor memory devices according to some embodiments.

[0021] Figures 16 and 17 are diagrams illustrating a semiconductor memory device according to some embodiments.

[0022] Figures 18 to 20 are diagrams illustrating semiconductor memory devices according to some embodiments.

[0023] Figures 21 and 22 are diagrams illustrating a semiconductor memory device according to some embodiments.

[0024] Figures 23 and 24 are diagrams illustrating a semiconductor memory device according to some embodiments.

[0025] Figure 25 is a diagram illustrating a semiconductor memory device according to some embodiments.

[0026] Figures 26 to 31 are diagrams of intermediate structures corresponding to intermediate steps in a method for manufacturing a semiconductor memory device, according to some embodiments.

[0027] Figures 32 to 36 are diagrams of intermediate structures corresponding to intermediate steps in a method for manufacturing a semiconductor memory device, according to some embodiments. Detailed Implementation

[0028] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0029] When used herein, the terms “comprising,” “including,” “including,” and / or “including” specify the presence of the stated element but do not exclude the presence of additional elements. The term “and / or” includes any and all combinations of one or more of the associated listed items. The term “connected” may be used herein to refer to a physical connection and / or an electrical connection. When a component or layer is referred to herein as “directly on,” “in direct contact with,” or “directly connected,” there are no intermediate components or layers. Similarly, when components are “immediately adjacent” to each other, there may be no intermediate components.

[0030] When viewed along a line extending in a particular direction or in a plane perpendicular to that direction, components or layers described as “overlapping” in that particular direction may at least partially obscure each other. The terms “around,” “cover,” or “fill,” as may be used herein, do not necessarily require completely surrounding, covering, or filling the described element or layer, but may, for example, refer to partially surrounding, covering, or filling the described element or layer, even when it has gaps, spaces, or other discontinuities overall. The term “exposed” may be used to describe relationships between elements and / or certain intermediate processes in the fabrication of a complete semiconductor device, but in the context of a complete device, exposure of a particular region, layer, structure, or other element may not necessarily be required.

[0031] It will be understood that spatial relation terms, such as “above,” “upper,” “upper part,” “upper surface,” “below,” “lower,” “lower part,” “lower surface,” “side surface,” etc., may be indicated by reference numerals and refer to the figures, unless otherwise stated. It will be understood that, in addition to the orientation depicted in the figures, these spatial relation terms are intended to also cover other different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements or features will be oriented as “above” other elements or features. Thus, the term “below” can cover both upper and lower orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein may be interpreted accordingly.

[0032] Figure 1 is a schematic layout diagram of a semiconductor memory device according to some embodiments. Figure 2 is a layout diagram of region R, which is part of the cell region in Figure 1. Figure 3 is a layout diagram showing only the word lines and active regions of Figure 2. Figure 4 is a cross-sectional view taken along line AA in Figure 1. Figures 5 and 6 are cross-sectional views taken along lines BB and CC in Figure 2, respectively. Figure 7 is an enlarged view of portion P in Figure 4. Figure 8 is an enlarged view of portion Q in Figure 5.

[0033] For reference, Figure 4 may be a schematic cross-sectional view of the transistor formation region in the peripheral region. In Figure 1, the cut line AA is shown extending along a first direction DR1. However, embodiments of the present disclosure are not limited thereto. Unlike what is shown, the cut line AA may extend along a second direction DR2.

[0034] The figures of a semiconductor memory device according to some embodiments show a dynamic random access memory (DRAM) by way of example. However, the embodiments of this disclosure are not limited thereto.

[0035] Referring to Figures 1 to 3, a semiconductor memory device according to some embodiments may include a cell region 20, a cell region isolation film 22, and a peripheral region 24.

[0036] A cell region isolation membrane 22 can be disposed around the cell region 20. The cell region isolation membrane 22 can isolate the cell region 20 and the peripheral region 24 from each other. The peripheral region 24 can be confined around the cell region 20.

[0037] Cell region 20 may include multiple cell active regions ACT. The cell active regions ACT may be defined by a cell element isolation film (105) formed in a substrate (100 in FIG. 5). As design rules for semiconductor memory devices decrease, the cell active regions ACT may extend in a strip shape along a diagonal or oblique line. For example, the cell active regions ACT may extend on a third-direction DR3.

[0038] Multiple gate electrodes may extend along the first direction DR1 and across the cell active region ACT. The multiple gate electrodes may extend parallel to each other. The multiple gate electrodes may be, for example, multiple word lines WL. The word lines WL may be arranged to be spaced apart from each other at equal intervals. The width of the word lines WL or the spacing between the word lines WL may be determined based on design rules.

[0039] Two word lines WL extending along the first direction DR1 divide each cell active region ACT into three parts. The cell active region ACT may include a bit line connection area 103a and a memory connection area 103b. The bit line connection area 103a may be located in the middle part of the cell active region ACT, and the memory connection area 103b may be located at the end of the cell active region ACT.

[0040] Multiple bit lines BL extending in the second direction DR2 and orthogonal to the word line WL can be disposed on the word line WL. In other embodiments, the multiple bit lines BL may intersect the word line WL and are not necessarily orthogonal. The multiple bit lines BL may extend in a parallel manner to each other. The bit lines BL may be arranged to be spaced apart from each other at equal intervals or at variable intervals. The width of the bit lines BL or the spacing between the bit lines BL may be determined based on design rules.

[0041] Semiconductor memory devices according to some embodiments may include various contact arrays formed on the cell active region ACT. Various contact arrangements may include, for example, direct contacts (DC), buried contacts (BC), and landing pads (LP).

[0042] In this regard, direct contact DC can refer to the contact that electrically connects the cell active region ACT to the bit line BL. Buried contact BC can refer to the contact that connects the cell active region ACT to the lower electrode (191 in Figure 5) of the data storage pattern. Due to the layout structure, the contact area between the buried contact BC and the cell active region ACT can be small. Therefore, to increase the contact area between the buried contact BC and the cell active region ACT, and between the buried contact BC and the lower electrode (191 in Figure 5) of the data storage pattern, conductive drop pads LP can be introduced.

[0043] The landing pad LP can be disposed between the buried contact BC and the lower electrode of the data storage pattern (191 in FIG. 5), and can also be disposed between the cell active region ACT and the buried contact BC. In a semiconductor memory device according to some embodiments, the landing pad LP can be disposed between the buried contact BC and the lower electrode of the data storage pattern (191 in FIG. 5). The contact area can be increased due to the introduction of the landing pad LP, thereby reducing the contact resistance between the cell active region ACT and the lower electrode of the data storage pattern (191 in FIG. 5).

[0044] Direct contact DC can be connected to bit line connection area 103a. Buried contact BC can be connected to memory connection area 103b. Since buried contact BC is located at each of the two opposite ends of cell active area ACT, the landing pad LP can be configured to be adjacent to each of the two opposite ends of cell active area ACT so as to partially overlap with buried contact BC. In other words, buried contact BC can be formed to partially overlap with the arrangement of each of cell active area ACT and cell element isolation film (105 in FIG. 5) between adjacent word lines WL and adjacent bit lines BL.

[0045] Word lines WL can be formed as structures buried in substrate 100. Word lines WL can extend across the portion of the cell active region ACT located between the direct contact DC or the buried contact BC. As shown, two word lines WL can intersect a single cell active region ACT. When the cell active region ACT extends along the third direction DR3, the word line WL can define an angle of less than 90 degrees relative to the cell active region ACT.

[0046] The direct contact DCs can be arranged symmetrically. The buried contact BCs can be arranged symmetrically. Therefore, the direct contact DCs can be arranged in a straight line along each of the first direction DR1 and the second direction DR2. The buried contact BCs can be arranged in a straight line along each of the first direction DR1 and the second direction DR2.

[0047] Unlike the direct contact DC and buried contact BC, the landing pads LP associated with each cell's active region ACT can be arranged in a zigzag pattern along the second direction DR2 extending from the bit line BL. Furthermore, the landing pads LP arranged on the first direction DR1 extending from the word line WL can overlap with the same side surface of the bit line BL, respectively.

[0048] For example, the landing pad LP of the first line can overlap with the left surface of the corresponding bit line BL, while the landing pad LP of the second line can overlap with the right surface of the corresponding bit line BL.

[0049] Referring to Figures 1 to 8, a semiconductor memory device according to some embodiments may include a plurality of cell gate structures 110, a plurality of bit line structures 140ST, a plurality of memory contacts 120, a plurality of memory pads 160, a data storage pattern 190, a peripheral gate structure 240ST, and a peripheral wiring line 265.

[0050] The substrate 100 may include a cell region 20, a cell region isolation film 22, and a peripheral region 24. The substrate 100 may be a silicon substrate or an SOI (silicon-on-insulator) substrate. Optionally, the substrate 100 may include, but is not limited to, silicon germanium, SGOI (silicon-on-insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0051] Multiple cell gate structures 110, multiple bit line structures 140ST, multiple memory contacts 120, multiple memory pads 160, and data storage patterns 190 can be disposed in cell region 20. Peripheral gate structures 240ST and peripheral wiring lines 265 can be disposed in peripheral region 24.

[0052] A cell element isolation film 105 can be formed in the cell region 20 within the substrate 100. The cell element isolation film 105 can have an STI (shallow trench isolation) structure with excellent element isolation capabilities. The cell element isolation film 105 can define a cell active region ACT within the cell region 20. As shown in Figures 2 and 3, the cell active region ACT defined by the cell element isolation film 105 can have an elongated island shape including a short side and a long side. The cell active region ACT can extend diagonally to define an angle of less than 90 degrees relative to the word line WL formed in the cell element isolation film 105. Furthermore, the cell active region ACT can extend diagonally to define an angle of less than 90 degrees relative to the bit line BL disposed on the cell element isolation film 105.

[0053] The cell region isolation membrane 22 may have a cell boundary isolation membrane having an STI structure. The cell region 20 may be defined by the cell region isolation membrane 22.

[0054] Each of the unit element isolation film 105 and the unit region isolation film 22 may comprise, for example, one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. However, embodiments of the present disclosure are not limited thereto. In Figures 5 and 6, the unit element isolation film 105 is shown as an insulating film. However, this is only intended for illustrative purposes, and embodiments of the present disclosure are not limited thereto. Depending on the width of each of the unit element isolation film 105 and the unit region isolation film 22, each of the unit element isolation film 105 and the unit region isolation film 22 may be formed as a single insulating film, or may be formed as a stack of multiple insulating films.

[0055] Figure 5 shows that the upper surface of the unit element isolation film 105 and the upper surface of the substrate 100 are coplanar. However, this is only for illustration purposes, and the embodiments of this disclosure are not limited thereto.

[0056] As shown in FIG. 6, a cell gate structure 110 may be disposed in the substrate 100 and the cell element isolation film 105. The cell gate structure 110 may extend across the cell element isolation film 105 and the cell active region ACT defined by the cell element isolation film 105. The cell gate structure 110 may include a cell gate trench 115, a cell gate insulating film 111, a cell gate electrode 112, a cell gate cap pattern 113, and a cell gate cap conductive film 114 formed in the substrate 100 and the cell element isolation film 105. In this respect, the cell gate electrode 112 may correspond to the word line WL in FIG. 2. Unlike that shown, for the word line WL, the cell gate structure 110 may not include the cell gate cap conductive film 114.

[0057] The cell gate trench 115 can be relatively deep within the cell element isolation film 105 and relatively shallow within the cell active region ACT. That is, the depth of the cell gate trench 115 in the cell element isolation film 105 can be greater than the depth of the cell gate trench 115 in the cell active region ACT. The bottom surface of the cell gate electrode 112 can be curved.

[0058] The cell gate insulating film 111 may extend along the sidewalls and bottom surface of the cell gate trench 115. The cell gate insulating film 111 may extend along the contour of at least a portion of the cell gate trench 115. The cell gate insulating film 111 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. However, embodiments of this disclosure are not limited thereto.

[0059] The unit gate electrode 112 may be disposed on the unit gate insulating film 111. The unit gate electrode 112 may fill a portion of the unit gate trench 115. The unit gate cap conductive film 114 may extend along the upper surface of the unit gate electrode 112.

[0060] The unit gate electrode 112 may include at least one of the following: metal, conductive metal nitride, conductive metal carbonitride, conductive metal carbide, metal silicide, doped semiconductor material, conductive metal oxynitride, or conductive metal oxide. The unit gate electrode 112 may include, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrO. x RuO x Or a combination thereof. However, embodiments of the present disclosure are not limited thereto. The cell gate cap conductive film 114 may include, for example, polycrystalline silicon or polycrystalline silicon germanium. However, embodiments of the present disclosure are not limited thereto.

[0061] A cell gate cap pattern 113 may be disposed on the cell gate electrode 112 and the cell gate cap conductive film 114. The cell gate cap pattern 113 may fill the remaining portion of the cell gate trench 115 after the cell gate electrode 112 and the cell gate cap conductive film 114 have been formed in the cell gate trench 115. Although the cell gate insulating film 111 is shown extending along the sidewall of the cell gate cap pattern 113, embodiments of the present disclosure are not limited thereto.

[0062] The cell gate cover pattern 113 may include, for example, one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon oxy carbon nitride (SiOCN), or a combination thereof.

[0063] Although not shown, an impurity-doped region may be formed on at least one side of the cell gate structure 110. The impurity-doped region may be the source / drain region of a transistor.

[0064] Bit line structure 140ST may include cell conductive lines 140 and cell line cover films 144. Cell conductive lines 140 may be disposed on portions of each of the substrate 100 and cell element isolation films 105 on which cell gate structures 110 are disposed.

[0065] The unit conductive line 140 may extend in the second direction DR2. The unit conductive line 140 may intersect with the unit element isolation film 105 and the unit active region ACT defined by the unit element isolation film 105. The unit conductive line 140 may be formed to intersect with the unit gate structure 110. In this respect, the unit conductive line 140 may correspond to the bit line BL in FIG2.

[0066] The unit conductive line 140 can be a stack of multiple films. The unit conductive line 140 may include, for example, a first unit conductive film 141, a second unit conductive film 142, and a third unit conductive film 143. The first to third unit conductive films 141, 142, and 143 may be sequentially stacked on the substrate 100 and the unit element isolation film 105 in the fourth direction DR4. Although the unit conductive line 140 is shown as a stack of three films, embodiments of this disclosure are not limited thereto.

[0067] Each of the first to third unit conductive films 141, 142, and 143 may include at least one of, for example, a semiconductor material doped with impurities, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a conductive metal oxynitride, a conductive metal oxide, a two-dimensional (2D) material, or a metal. In a semiconductor memory device according to some embodiments, the two-dimensional material may be a metallic material and / or a semiconductor material. The two-dimensional material (2D material) may include a two-dimensional allotrope or a two-dimensional compound. For example, the 2D material may include at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2). However, this disclosure is not limited thereto. In other words, the above-described two-dimensional materials are listed by way of example only. The two-dimensional materials that may be included in the semiconductor memory device of this disclosure are not limited to the materials described above.

[0068] For example, the first conductive film 141 may include a doped semiconductor material, the second conductive film 142 may include at least one of a conductive silicide compound, a conductive metal nitride, or a two-dimensional material, and the third conductive film 143 may include a metal. However, the embodiments of this disclosure are not limited thereto.

[0069] Bit line contact 146 can be disposed between unit conductive line 140 and substrate 100. That is, unit conductive line 140 can be disposed on bit line contact 146. For example, bit line contact 146 can be disposed at the point where unit conductive line 140 intersects with the middle portion of unit active region ACT having an elongated island shape. Bit line contact 146 can be disposed between bit line connection region 103a and unit conductive line 140.

[0070] Bit line contact 146 can electrically connect unit conductive line 140 and substrate 100 to each other. In this respect, bit line contact 146 can correspond to direct contact DC in FIG2. Bit line contact 146 can include at least one of, for example, a semiconductor material doped with impurities, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a conductive metal oxynitride, a conductive metal oxide, or a metal.

[0071] In Figure 5, in the region overlapping the upper surface of the bit line contact 146, the unit conductive line 140 may include a second unit conductive film 142 and a third unit conductive film 143. In the region not overlapping the upper surface of the bit line contact 146, the unit conductive line 140 may include first to third unit conductive films 141, 142, and 143. The thickness of the portion of the unit conductive line 140 in the region overlapping the upper surface of the bit line contact 146 may differ from the thickness of the portion of the unit conductive line 140 in the region not overlapping the upper surface of the bit line contact 146.

[0072] A cell line cover film 144 may be disposed on the cell conductive line 140. The cell line cover film 144 may extend along the upper surface of the cell conductive line 140 in the second direction DR2. In this respect, the cell line cover film 144 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon carbon nitride, or silicon oxy carbon nitride. In semiconductor memory devices according to some embodiments, the cell line cover film 144 may include, for example, silicon nitride. Although the cell line cover film 144 is shown as a single film, embodiments of the present disclosure are not limited thereto. In other words, the cell line cover film 144 may be a stack of multiple films. However, when the films constituting the stack are made of the same material, the cell line cover film 144 may be considered a single film.

[0073] The unit insulating film 130 can be disposed on the substrate 100 and the unit element isolation film 105. More specifically, the unit insulating film 130 can be formed on the portion of each of the substrate 100 and the unit element isolation film 105 where the bit line contact 146 is not disposed. The unit insulating film 130 can be disposed between the substrate 100 and the unit conductive line 140 and between the unit element isolation film 105 and the unit conductive line 140.

[0074] The unit insulating film 130 is shown to be a stack of a first unit insulating film 131 and a second unit insulating film 132. However, the unit insulating film 130 may be a single film. For example, the first unit insulating film 131 may comprise silicon oxide, while the second unit insulating film 132 may comprise silicon nitride. However, embodiments of this disclosure are not limited thereto. In another example, unlike what is shown, the unit insulating film 130 may comprise three or more insulating films. When the unit insulating film 130 includes a third unit insulating film, the third unit insulating film may be a silicon oxide film.

[0075] In the cross-sectional view of Figure 5, the upper surface 100US of the substrate can be defined at the boundary between the unit insulating film 130 and the substrate 100.

[0076] Unit line spacers 150 may be disposed on the sidewalls of each of the unit conductive lines 140 and the unit line capping film 144. Unit line spacers 150 may be formed on the substrate 100 and the unit element isolation film 105, in the region surrounding the area where the unit conductive lines 140 are disposed on the bit line contacts 146. Unit line spacers 150 may be disposed on the sidewalls of each of the unit conductive lines 140, the unit line capping film 144, and the bit line contacts 146.

[0077] In the region surrounding the area where the unit conductive line 140 is formed and the bit line contact 146 is not present, a unit line spacer 150 may be disposed on the unit insulating film 130. The unit line spacer 150 may be disposed on the sidewall of each of the unit conductive line 140 and the unit line cover film 144.

[0078] The unit line spacer 150 can be disposed on the main sidewall that extends in an elongated manner in the second direction DR2 within the sidewall of the bit line structure 140ST.

[0079] The cell line spacer 150 is shown as a stack of multiple films including first to fourth cell line spacers 151, 152, 153, and 154. However, the cell line spacer 150 may be a single film. For example, each of the first to fourth cell line spacers 151, 152, 153, and 154 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride (SiON) film, a silicon oxycarbonitride (SiOCN) film, air, or a combination thereof. However, embodiments of this disclosure are not limited thereto. For example, the second cell line spacer 152 may not be disposed on the cell conductive film 130, but may be disposed on the sidewall of the bit line contact 146.

[0080] A gate pattern 170 may be disposed on the substrate 100 and the cell element isolation film 105. The gate pattern 170 may be formed to overlap with the cell gate structure 110 formed in the substrate 100 and the cell element isolation film 105. The gate pattern 170 may be disposed between bit line structures 140ST extending along the second direction DR2. The gate pattern 170 may include, for example, one of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0081] Storage contacts 120 may be disposed between adjacent unit conductive lines 140 in the first direction DR1. Storage contacts 120 may be disposed on two opposite sides of the bit line structure 140ST. Storage contacts 120 may be disposed between adjacent fence patterns 170 in the second direction DR2. Storage contacts 120 may overlap with portions of each of the substrate 100 and the unit element isolation film 105 disposed between adjacent unit conductive lines 140.

[0082] Storage contact 120 can be connected to storage connection area 103b of the active area ACT of the cell. In this respect, storage contact 120 can correspond to the burial contact BC of Figure 2.

[0083] Storage contact 120 may include at least one of, for example, an impurity-doped semiconductor material, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a conductive metal oxynitride, a conductive metal oxide, or a metal. In a semiconductor memory device according to some embodiments, storage contact 120 may include an impurity-doped semiconductor material.

[0084] Storage pad 160 can be disposed on storage contact 120. Storage pad 160 can be electrically connected to storage contact 120. In this respect, storage pad 160 can correspond to the landing pad LP of FIG2.

[0085] The memory pad 160 may overlap with a portion of the upper surface of the bit line structure 140ST. For example, the memory pad 160 may overlap with the upper surface 144US of the cell line cap film in the fourth direction DR4. The fourth direction DR4 may be the thickness direction of the substrate 100. Each of the first direction DR1, the second direction DR2, and the third direction DR3 may be perpendicular to the fourth direction DR4.

[0086] The storage pad 160 may include a lower storage pad 160B and an upper storage pad 160U. The lower storage pad 160B and the upper storage pad 160U may be sequentially stacked on the corresponding storage contact 120 in the fourth direction DR4.

[0087] The lower storage pad 160B can be disposed on the storage contact 120. The lower storage pad 160B can be connected to the storage contact 120. For example, the lower storage pad 160B can contact the storage contact 120.

[0088] The lower memory pad 160B can be disposed between adjacent bit line structures 140ST in the first direction DR1 and between adjacent gate patterns 170 in the second direction DR2. Based on the upper surface 100US of the substrate, the lower memory pad 160B can be disposed below the upper surface 144US of the cell line capping film. In other words, based on the upper surface 100US of the substrate, the vertical level of the uppermost position of the lower memory pad 160B can be lower than the vertical level of the upper surface 144US of the cell line capping film.

[0089] The lower storage pad 160B may include a lower pad silicide film 161 and a lower pad filler film 162. The lower pad silicide film 161 may be disposed between the storage contact 120 and the lower pad filler film 162.

[0090] The lower storage pad 160B may include a metal or a metal-containing compound. The metal-containing compound may include, for example, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a conductive metal oxynitride, or a conductive metal oxide. The lower pad silicide film 161 may include a metal silicide. The lower pad filler film 162 may include, but is not limited to, at least one of a metal or a metal nitride.

[0091] The upper storage pad 160U can be disposed on the lower storage pad 160B. The upper storage pad 160U can contact the lower storage pad 160B. For example, the upper storage pad 160U can contact the lower pad filler film 162.

[0092] The upper storage pad 160U may overlap with the upper surface 144US of the cell line cover film in the fourth direction DR4. At least a portion of the upper storage pad 160U may be disposed on the upper surface 144US of the cell line cover film.

[0093] The upper storage pad 160U may include an upper surface 160U_US and a bottom surface 160U_BS that are opposite to each other in the fourth direction DR4. The upper storage pad 160U may include a sidewall 160U_SW that connects the upper surface 160U_US and the bottom surface 160U_BS of the upper storage pad to each other.

[0094] The upper surface 160U_US of the upper storage pad can be the upper surface 160US of the storage pad. In the cross-sectional view shown in Figure 5, the bottom surface 160U_BS of the upper storage pad can contact the lower storage pad 160B, the cell line spacer 150, and the bit line structure 140ST. The sidewalls of the upper storage pad 160U_SW can be covered by the pad isolation pattern 180, which will be described later.

[0095] In a semiconductor memory device according to some embodiments, the upper memory pad 160U may include a first portion 160U_P1 and a second portion 160U_P2. The first portion 160U_P1 of the upper memory pad is disposed on the second portion 160U_P2 of the upper memory pad. The second portion 160U_P2 of the upper memory pad is disposed between the first portion 160U_P1 of the upper memory pad and the lower memory pad 160B.

[0096] Based on the upper surface 144US of the cell line cover film, the first portion 160U_P1 and the second portion 160U_P2 of the upper storage pad can be distinguished from each other. The first portion 160U_P1 of the upper storage pad is disposed on or above the upper surface 144US of the cell line cover film.

[0097] The width of the upper storage pad 160U disposed on the top of the upper surface 144US of the cell line cover film can increase as the upper storage pad 160U moves away from the upper surface 144US of the cell line cover film (i.e., with distance). For example, the width W21 of the upper surface 160U_US of the upper storage pad can be greater than the width W22 of the upper storage pad 160U at the vertical level corresponding to the vertical level of the upper surface 144US of the cell line cover film (e.g., along direction DR4).

[0098] The width of the first portion 160U_P1 of the upper storage pad can increase as the first portion 160U_P1 of the upper storage pad moves away from the bit line structure 140ST. That is, the width of the first portion 160U_P1 of the upper storage pad can increase as the first portion 160U_P1 of the upper storage pad moves away from the upper surface 144US of the cell line cover film.

[0099] The upper surface 144US of the cell line cover film may include a first portion that contacts the upper memory pad 160U and a second portion that does not contact the upper memory pad 160U. For example, based on the upper surface 100US of the substrate, the vertical level of the first portion of the upper surface 144US of the cell line cover film may be lower than the vertical level of the second portion of the upper surface 144US of the cell line cover film. During the formation of the upper memory pad 160U, a portion of the cell line cover film 144 may be etched such that the vertical level of the second portion of the upper surface 144US of the cell line cover film may be lower than the vertical level of the second portion of the upper surface 144US of the cell line cover film.

[0100] The upper storage pad 160U may include a metal or a metal-containing compound. For example, the upper storage pad 160U may include at least one of a metal or a metal nitride. However, embodiments of this disclosure are not limited thereto.

[0101] Pad isolation pattern 180 can be formed on memory pad 160 and bit line structure 140ST. For example, pad isolation pattern 180 can be provided on cell line cover film 144 and lower memory pad 160B.

[0102] The pad isolation pattern 180 can define an area for each of the storage pads 160, which serves as a plurality of isolation regions. The pad isolation pattern 180 can isolate adjacent storage pads 160 from each other. The pad isolation pattern 180 can surround the sidewalls 160U_SW of the upper storage pads.

[0103] The pad isolation pattern 180 does not cover the upper surface 160US of the storage pad. The upper surface 180US of the pad isolation pattern may be coplanar with the upper surface 160US of the storage pad. However, embodiments of this disclosure are not limited thereto.

[0104] The pad isolation pattern 180 includes an insulating material. The pad isolation pattern 180 can electrically isolate the storage pads 160 from each other. For example, the pad isolation pattern 180 can electrically isolate the upper storage pads 160U from each other. The pad isolation pattern 180 can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride.

[0105] In Figures 5 and 8, the height H31 from the lowest position of the pad isolation pattern 180 to the upper surface 180US of the pad isolation pattern can be greater than the height H32 from the lowest position of the upper storage pad 160U to the upper surface 180US of the pad isolation pattern.

[0106] An upper etch stop film 292 may be disposed on the pad isolation pattern 180 and the storage pad 160. The upper etch stop film 292 may extend along the upper surface 180US of the pad isolation pattern and the upper surface 160US of the storage pad.

[0107] The upper etch stop film 292 may extend across the cell region 20 and into the peripheral region 24. The upper etch stop film 292 may include at least one of silicon nitride, silicon carbon nitride, silicon boron nitride, silicon oxynitride, and silicon oxycarbide. However, embodiments of this disclosure are not limited thereto.

[0108] Data storage pattern 190 can be disposed on storage pad 160. Data storage pattern 190 can be disposed on the upper surface 144µs of the cell line cover film.

[0109] Data storage pattern 190 can be electrically connected to storage pad 160. Data storage pattern 190 can be connected to the upper surface 160U_US of the upper storage pad.

[0110] A portion of the data storage pattern 190 may be disposed within the upper etch stop film 292. The data storage pattern 190 may include, for example, a capacitor. However, embodiments of this disclosure are not limited thereto. The data storage pattern 190 includes a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193.

[0111] The lower electrode 191 may be disposed on the storage pad 160. The lower electrode 191 may contact the upper surface 160US of the storage pad 160. The lower electrode 191 is shown to have a cylindrical shape. However, embodiments of the present disclosure are not limited thereto. In another example, the lower electrode 191 may have a cylindrical shape.

[0112] A capacitor dielectric film 192 is disposed on the lower electrode 191. The capacitor dielectric film 192 may be formed along the contour of the lower electrode 191. An upper electrode 193 is disposed on the capacitor dielectric film 192. The upper electrode 193 may surround the outer wall of the lower electrode 191.

[0113] For example, the capacitor dielectric film 192 may be configured to overlap with the upper electrode 193 in the fourth direction DR4. The capacitor dielectric film 192 may not extend into the peripheral region 24.

[0114] Each of the lower electrode 191 and the upper electrode 193 may include, for example, a doped semiconductor material, a conductive metal nitride (such as titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (such as ruthenium, iridium, titanium, or tantalum), or a conductive metal oxide (such as iridium oxide or niobium oxide). However, embodiments of this disclosure are not limited thereto.

[0115] For example, the capacitor dielectric film 192 may include at least one of ferroelectric material, antiferroelectric material, and paraelectric material. For example, the capacitor dielectric film 192 may include at least one of the following: ferroelectric material, antiferroelectric material, paraelectric material, a combination of ferroelectric material and antiferroelectric material, a combination of ferroelectric material and paraelectric material, a combination of paraelectric material and antiferroelectric material, or a combination of ferroelectric material, antiferroelectric material, and paraelectric material.

[0116] In one example, the capacitor dielectric film 192 may include a stacked film structure in which a zirconium oxide film, an aluminum oxide film, and a zirconium oxide film are sequentially stacked. In another example, the capacitor dielectric film 192 may include a dielectric film containing hafnium (Hf). The suggestions regarding the materials of the capacitor dielectric film 192 described above are merely examples, and the technical ideas of this disclosure are not limited thereto.

[0117] Unlike the above, the data storage pattern 190 can be a variable resistance pattern that can switch between two resistance states under an electrical pulse applied to the memory element. For example, the data storage pattern 190 can include a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material, or antiferromagnetic material whose crystal state changes according to the amount of current.

[0118] A peripheral element isolation film 26 may be disposed within a peripheral region 24 of the substrate 100. The peripheral element isolation film 26 may define a peripheral active region within the peripheral region 24. The upper surface of the peripheral element isolation film 26 is shown as coplanar with the upper surface 100US of the substrate. However, embodiments of this disclosure are not limited thereto. The peripheral element isolation film 26 may include, but is not limited to, at least one of, for example, silicon oxide films, silicon nitride films, and silicon oxynitride films.

[0119] The peripheral gate structure 240ST can be disposed on the substrate 100 in the peripheral region 24. The peripheral gate structure 240ST can be disposed on the peripheral active region defined by the peripheral element isolation film 26.

[0120] The peripheral gate structure 240ST may include a peripheral gate insulating film 230, a peripheral gate conductive film 240, and a peripheral capping film 244 sequentially stacked on the substrate 100. The peripheral gate structure 240ST may include peripheral spacers 245 disposed on the sidewalls of the peripheral gate conductive film 240 and the sidewalls of the peripheral capping film 244.

[0121] The peripheral gate conductive film 240 may include first to third peripheral conductive films 241, 242, and 243 sequentially stacked on the peripheral gate insulating film 230. For example, an additional conductive film may not be disposed between the peripheral gate conductive film 240 and the peripheral gate insulating film 230. In another example, unlike the one shown, an additional conductive film (such as a work function conductive film) may be disposed between the peripheral gate conductive film 240 and the peripheral gate insulating film 230.

[0122] Although the two peripheral gate structures 240ST are shown disposed between adjacent peripheral element isolation films 26, this is merely for illustration purposes and the embodiments of this disclosure are not limited thereto.

[0123] For example, the peripheral gate conductive film 240 may have the same stacking structure as the stacking structure of the unit conductive lines 140. However, embodiments of this disclosure are not limited thereto. Each of the first to third peripheral conductive films 241, 242, and 243 may include at least one of, for example, a semiconductor material doped with impurities, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a conductive metal oxynitride, a conductive metal oxide, a two-dimensional material, or a metal.

[0124] The peripheral gate insulating film 230 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide.

[0125] For example, the peripheral spacer 245 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, silicon oxycarbon nitride, and combinations thereof. Although the peripheral spacer 245 is shown as formed as a single film, this is only for illustration purposes, and embodiments of this disclosure are not limited thereto. In another example, the peripheral spacer 245 may be a stack of multiple films. For example, the peripheral cover film 244 may include at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0126] A down-etch stop film 250 may be disposed on the substrate 100. The down-etch stop film 250 may be formed along the contour of the peripheral gate structure 240ST. For example, the down-etch stop film 250 may include at least one of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon oxycarbon nitride.

[0127] The first peripheral interlayer insulating film 290 may be disposed on the lower etch stop film 250. The first peripheral interlayer insulating film 290 may be disposed around the peripheral gate structure 240ST. For example, the first peripheral interlayer insulating film 290 may include a silicon oxide-based insulating material. The first peripheral interlayer insulating film 290 may include, but is not limited to, silicon oxide.

[0128] Based on the upper surface 100US of the substrate, the vertical level of the upper surface 290US of the first peripheral interlayer insulating film can be lower than the vertical level of the upper surface 244US of the peripheral cover film. For example, the height H1 from the upper surface 100US of the substrate to the upper surface 290US of the first peripheral interlayer insulating film can be less than the height H21 from the upper surface 100US of the substrate to the upper surface 244US of the peripheral cover film.

[0129] The height H1 from the upper surface 100µs of the substrate to the upper surface 290µs of the first peripheral interlayer insulating film can be measured near the center between adjacent peripheral gate structures 240ST. The height H21 from the upper surface 100µs of the substrate to the upper surface 244µs of the peripheral capping film can be measured near the center of the width of the peripheral capping film 244.

[0130] The height H1 from the upper surface 100US of the substrate to the upper surface 290US of the first peripheral interlayer insulating film can be less than the height H22 from the upper surface 100US of the substrate to the top horizontal level of the peripheral spacer 245.

[0131] For example, the height H21 from the upper surface 100US of the substrate to the upper surface 244US of the outer cover film can be equal to the height H22 from the upper surface 100US of the substrate to the top horizontal level of the outer spacer 245.

[0132] Unlike the example shown, in another example, due to the etching process during manufacturing, the vertical level of the upper surface of the peripheral spacer 245 may be lower than the vertical level of the upper surface 244US of the peripheral cover film. In this case, the height H21 from the upper surface 100US of the substrate to the upper surface 244US of the peripheral cover film may be greater than or equal to the height H22 from the upper surface 100US of the substrate to the top level of the peripheral spacer 245.

[0133] An inserted interlayer insulating film 291 is disposed on the peripheral gate structure 240ST and the first peripheral interlayer insulating film 290. The inserted interlayer insulating film 291 may cover the peripheral gate structure 240ST and the first peripheral interlayer insulating film 290. The inserted interlayer insulating film 291 may cover the portion of the lower etch stop film 250 that protrudes upward beyond the upper surface 290US of the first peripheral interlayer insulating film.

[0134] The upper surface 290US of the first peripheral interlayer insulating film is shown as flat. However, embodiments of the present disclosure are not limited thereto. The upper surface 290US of the first peripheral interlayer insulating film may be a curved surface convex toward the substrate 100.

[0135] The inserted interlayer insulating film 291 may include a material different from that of the first peripheral interlayer insulating film 290. The inserted interlayer insulating film 291 may include, for example, a silicon nitride-based insulating material. For instance, the inserted interlayer insulating film 291 may include a silicon nitride.

[0136] A portion of the inserted interlayer insulating film 291 extends downward into the space between adjacent peripheral gate structures 240ST. In other words, based on the upper surface 100µs of the substrate, the vertical level of the lower surface of the inserted interlayer insulating film 291 can be lower than the vertical level of the upper surface 244µs of the peripheral capping film.

[0137] Therefore, the inserted interlayer insulating film 291 can protect the first peripheral interlayer insulating film 290 during the etching process included in the process of manufacturing the data storage pattern 190. During the etching process included in the process of manufacturing the data storage pattern 190, the inserted interlayer insulating film 291 can prevent defects caused by etching the first peripheral interlayer insulating film 290.

[0138] The peripheral contact plugs 260 can be disposed on two opposite sides of the peripheral gate structure 240ST. The peripheral contact plugs 260 can extend through the inserted interlayer insulating film 291 and the first peripheral interlayer insulating film 290 to the portion of the substrate 100 in the peripheral region 24.

[0139] The peripheral contact plug 260 may include a peripheral plug blocking membrane 261 and a peripheral plug filling membrane 262. The peripheral plug filling membrane 262 may be disposed on the peripheral plug blocking membrane 261.

[0140] Peripheral wiring 265 can be disposed on the inserted interlayer insulating film 291. Peripheral wiring 265 can be disposed on the peripheral gate structure 240ST. Peripheral wiring 265 can be connected to the peripheral contact plug 260. In the cross-sectional view, when peripheral wiring 265 is connected to the peripheral contact plug 260, peripheral wiring 265 can be a portion disposed on the upper surface 291US of the inserted interlayer insulating film. Peripheral wiring 265 can be disposed on the upper surface 291US of the inserted interlayer insulating film.

[0141] The peripheral wiring line 265 may include a peripheral wiring barrier film 266 and a peripheral wiring extension line 267. The peripheral wiring extension line 267 may be disposed on the peripheral wiring barrier film 266.

[0142] The peripheral wiring 265 may include an upper surface 265US and a bottom surface 265BS opposite to each other in the fourth direction DR4. The bottom surface 265BS of the peripheral wiring may face the inserted interlayer insulating film 291. The peripheral wiring 265 may include a sidewall 265SW connecting the bottom surface 265BS and the upper surface 265US of the peripheral wiring to each other.

[0143] The peripheral wiring extension line 267 may include the upper surface 265US of the peripheral wiring line. The sidewalls 265SW of the peripheral wiring line may be defined by the peripheral wiring barrier film 266 and the peripheral wiring extension line 267.

[0144] In a semiconductor memory device according to some embodiments, peripheral wiring extension 267 can be directly connected to peripheral plug filler film 262. Peripheral wiring barrier film 266 can be directly connected to peripheral plug barrier film 261. Peripheral contact plug 260 and peripheral wiring line 265 can be formed in the same manufacturing process.

[0145] The peripheral wiring barrier 266 may include the same material as the peripheral plug barrier 261. The peripheral wiring barrier 266 may include, for example, one of a metal silicide compound, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal oxynitride, or a conductive metal carbonitride.

[0146] The peripheral wiring extension line 267 may include the same material as the peripheral plug filler film 262. The peripheral wiring extension line 267 may include metal. For example, the peripheral wiring extension line 267 may be made of metal.

[0147] Unlike the example shown, in another example, the peripheral contact plug 260 may include a peripheral plug blocking membrane 261 and may not have a peripheral plug filling membrane 262. In yet another example, the peripheral contact plug 260 may include a peripheral plug filling membrane 262 made of metal and may not have a peripheral plug blocking membrane 261. The peripheral wiring line 265 may include a peripheral wiring extension line 267 made of metal and may not have a peripheral wiring blocking membrane 266.

[0148] For example, the width W12 of the bottom surface 265BS of the peripheral cabling line can be greater than or equal to the width W11 of the top surface 265US of the peripheral cabling line.

[0149] The peripheral cabling isolation pattern 280 can isolate adjacent peripheral cabling lines 265 from each other. The peripheral cabling lines 265 include a first peripheral cabling line 265_1 and a second peripheral cabling line 265_2 that are adjacent to each other, and the peripheral cabling isolation pattern 280 isolates the first peripheral cabling line 265_1 and the second peripheral cabling line 265_2 from each other.

[0150] The peripheral wiring isolation pattern 280 may cover the sidewall 265SW of the peripheral wiring line. The upper surface 280US of the peripheral wiring isolation pattern may be coplanar with the upper surface 265US of the peripheral wiring line. However, the embodiments of this disclosure are not limited thereto.

[0151] The peripheral wiring isolation pattern 280 includes an insulating material. The peripheral wiring isolation pattern 280 can electrically isolate adjacent peripheral wiring lines 265 from each other. For example, the peripheral wiring isolation pattern 280 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and silicon carbonitride.

[0152] The upper etch stop film 292 can be disposed on the peripheral wiring isolation pattern 280 and the peripheral wiring line 265. For example, the upper etch stop film 292 can extend along the upper surface 265US of the peripheral wiring line and the upper surface 280US of the peripheral wiring isolation pattern.

[0153] The second peripheral interlayer insulating film 293 may be disposed on the upper etch stop film 292. Although not shown, the second peripheral interlayer insulating film 293 may cover the sidewall of the upper electrode 193. The second peripheral interlayer insulating film 293 may include an insulating material.

[0154] Figures 9 and 10 are diagrams illustrating semiconductor memory devices according to some embodiments. Figures 11 and 12 are diagrams illustrating semiconductor memory devices according to some embodiments. For ease of description, the following description is primarily based on the differences between these descriptions and those presented above with reference to Figures 1 to 8.

[0155] For reference, Figures 10 and 12 are enlarged versions of parts Q in Figures 9 and 11, respectively.

[0156] Referring to Figures 9 and 10, in a semiconductor memory device according to some embodiments, the upper surface 144US of the cell line cover film can be flat in a cross-sectional view.

[0157] Based on the upper surface 100US of the substrate, the vertical horizontal of the portion of the upper surface 144US of the cell line cover film that contacts the upper storage pad 160U can be equal to the vertical horizontal of the portion of the upper surface 144US of the cell line cover film that does not contact the upper storage pad 160U.

[0158] Referring to Figures 11 and 12, in a semiconductor memory device according to some embodiments, the upper storage pad 160U can be disposed entirely on the upper surface 144US of the cell line cover film and the lower pad filler film 162.

[0159] Based on the upper surface 100US of the substrate, the vertical level of the entire upper memory pad 160U can be higher than the vertical level of the upper surface 144US of the cell line cover film. For example, the boundary surface of the lower pad fill film 162 that contacts the upper memory pad 160U can be coplanar with the upper surface 144US of the cell line cover film.

[0160] Figures 13 to 15 are diagrams illustrating semiconductor memory devices according to some embodiments. For ease of description, the following description is primarily based on the differences between these and the descriptions presented above using Figures 1 to 8.

[0161] For reference, Figure 14 is a magnified view of part Q in Figure 13. Figure 15 is a diagram showing an example of the three-dimensional shape of the silicide film on the upper pad of Figure 13.

[0162] Referring to Figures 13 to 15, in a semiconductor memory device according to some embodiments, the upper storage pad 160U may include an upper pad silicide film 166 and an upper pad filler film 167.

[0163] The upper pad silicide film 166 may include the sidewall 160U_SW of the upper storage pad. At least a portion of the sidewall 160U_SW of the upper storage pad may be defined by the upper pad silicide film 166.

[0164] The upper pad silicide film 166 can be disposed along the boundary surface between the upper pad filler film 167 and the pad isolation pattern 180. In FIG. 15, the upper pad silicide film 166 can have a cylindrical shape.

[0165] The upper pad silicide film 166 and the upper pad filler film 167 may include the upper surface 160U_US of the upper storage pad. In a plan view, the upper surface 160U_US of the upper storage pad defined by the upper pad silicide film 166 may surround the periphery of the upper surface 160U_US of the upper storage pad defined by the upper pad filler film 167.

[0166] The upper pad filler film 167 may contact the lower pad filler film 162. The upper pad silicide film 166 may not be disposed between the upper pad filler film 167 and the lower pad filler film 162. More specifically, the upper pad silicide film 166 does not extend along the boundary surface between the upper pad filler film 167 and the lower pad filler film 162.

[0167] The upper pad silicide film 166 is not directly connected to the lower pad silicide film 161. The lower pad filler film 162 is positioned between the upper pad silicide film 166 and the lower pad silicide film 161. The upper pad silicide film 166 and the lower pad silicide film 161 can be isolated from each other via the lower pad filler film 162.

[0168] In the cross-sectional views of Figures 13 and 14, the upper pad silicide film 166 may include a first upper pad silicide film 166_1 and a second upper pad silicide film 166_2 spaced apart from each other, with an upper pad filler film 167 inserted therebetween. The first upper pad silicide film 166_1 and the second upper pad silicide film 166_2 may be spaced apart from each other in the first direction DR1. In a semiconductor memory device according to some embodiments, the height H41 of the first upper pad silicide film 166_1 in the fourth direction DR4 may be equal to the height H42 of the second upper pad silicide film 166_2 in the fourth direction DR4.

[0169] The upper pad silicide film 166 may include a metal silicide. The upper pad filler film 167 may include at least one of a metal or a metal nitride. However, embodiments of this disclosure are not limited thereto.

[0170] The upper pad silicide film 166 may include a silicide of the metal included in the upper pad filler film 167. For example, when the upper pad filler film 167 includes tungsten (W), the upper pad silicide film 166 may include a tungsten silicide.

[0171] Figures 16 and 17 are diagrams illustrating semiconductor memory devices according to some embodiments. For ease of description, the following description is primarily based on the differences between these and the descriptions presented above using Figures 1 through 8.

[0172] Referring to Figures 16 and 17, in a semiconductor memory device according to some embodiments, the height H31 from the lowest position of the pad isolation pattern 180 to the upper surface 180US of the pad isolation pattern can be less than the height H32 from the lowest position of the upper storage pad 160U to the upper surface 180US of the pad isolation pattern.

[0173] Based on the upper surface 100US of the substrate, the vertical level of the lowest position of the pad isolation pattern 180 can be higher than the vertical level of the lowest position of the upper storage pad 160U.

[0174] Figures 18 to 20 are diagrams illustrating semiconductor memory devices according to some embodiments. For ease of description, the following description is primarily based on the differences between these and the descriptions presented above with reference to Figures 13 to 17.

[0175] For reference, Figure 19 is a magnified view of part Q in Figure 18. Figure 20 is a diagram showing an example of the three-dimensional shape of the silicide film on the upper pad of Figure 18.

[0176] Referring to Figures 18 to 20, in a semiconductor memory device according to some embodiments, the sidewall 160U_SW of the upper storage pad may be defined by an upper pad silicide film 166.

[0177] For example, the upper pad filler 167 may not contact the pad isolation pattern 180.

[0178] In Figures 18 and 20, the upper pad silicide film 166 may have a cylindrical shape, the height of which decreases as the upper pad silicide film 166 moves away from the lower storage pad 160B in the first direction DR1.

[0179] In the cross-sectional views of Figures 18 and 19, the upper pad silicide film 166 may include a first upper pad silicide film 166_1 and a second upper pad silicide film 166_2 spaced apart from each other in the first direction DR1. The first upper pad silicide film 166_1 may contact the lower storage pad 160B. For example, the first upper pad silicide film 166_1 may contact the lower pad filler film 162. The second upper pad silicide film 166_2 may contact the bit line structure 140ST. For example, the second upper pad silicide film 166_2 may contact the cell line cover film 144.

[0180] For example, the height H41 of the first upper pad silicide film 166_1 in the fourth direction DR4 is greater than the height H42 of the second upper pad silicide film 166_2 in the fourth direction DR4.

[0181] Figures 21 and 22 are diagrams illustrating a semiconductor memory device according to some embodiments. For ease of description, the following description is primarily based on the differences between these and the descriptions presented above with reference to Figures 1 through 8.

[0182] For reference, Figure 22 is an enlarged view of part P of Figure 21.

[0183] Referring to Figures 21 and 22, in a semiconductor memory device according to some embodiments, the width of the peripheral wiring line 265 may increase as the peripheral wiring line 265 moves away from the peripheral gate conductive film 240.

[0184] The width W12 of the bottom surface 265BS of the peripheral cabling line is smaller than the width W11 of the top surface 265US of the peripheral cabling line.

[0185] In the cross-sectional view, the width of the peripheral wiring isolation pattern 280 disposed between adjacent peripheral wiring lines 265 can increase and then decrease as the peripheral wiring isolation pattern 280 moves away from the peripheral gate conductive film 240.

[0186] The peripheral wiring line 265 may include the same conductive material as the upper storage pad 160U in FIG5.

[0187] Figures 23 and 24 are diagrams illustrating a semiconductor memory device according to some embodiments. For ease of description, the following description is primarily based on the differences between these and the descriptions presented above using Figures 21 and 22. For reference, Figure 24 is an enlarged view of portion P of Figure 23.

[0188] Referring to Figures 23 and 24, in a semiconductor memory device according to some embodiments, peripheral wiring lines 265 may include a peripheral wiring silicide film 268 and a peripheral wiring filler film 269.

[0189] The peripheral wiring silicide film 268 may include sidewalls 265SW of the peripheral wiring lines. The sidewalls 265SW of the peripheral wiring lines may be defined by the peripheral wiring silicide film 268.

[0190] The peripheral wiring silicide film 268 can be disposed along the boundary surface between the peripheral wiring fill film 269 and the peripheral wiring isolation pattern 280.

[0191] The peripheral wiring silicide film 268 and the peripheral wiring filler film 269 may include the upper surface 265US of the peripheral wiring lines. The peripheral wiring silicide film 268 and the peripheral wiring filler film 269 may include the bottom surface 265BS of the peripheral wiring lines.

[0192] The peripheral wiring filler film 269 may contact the peripheral contact plug 260. The peripheral wiring filler film 269 may contact the inserted interlayer insulating film 291. The peripheral wiring silicide film 268 does not extend along the boundary surface between the peripheral contact plug 260 and the peripheral wiring filler film 269. The peripheral wiring silicide film 268 does not extend along the boundary surface between the inserted interlayer insulating film 291 and the peripheral wiring filler film 269.

[0193] The peripheral wiring silicide film 268 may include a metal silicide. The peripheral wiring silicide film 268 may include a metal silicide included in the peripheral wiring fill film 269. The peripheral wiring fill film 269 may include the same conductive material as the conductive material of the upper pad fill film 167 of FIG. 13 or FIG. 18.

[0194] Figure 25 is a diagram illustrating a semiconductor memory device according to some embodiments.

[0195] Referring to FIG25, a semiconductor memory device according to some embodiments may have a COP (Cell on Periphery) structure, wherein the cell array region CA is disposed on the peripheral structure region PA.

[0196] The peripheral structure region PA can correspond to the peripheral region 24 in Figures 1 and 4. The cell array region CA can correspond to the cell region 20 in Figures 1 to 3.

[0197] Figures 26 to 31 are diagrams of intermediate structures corresponding to intermediate steps in a method for manufacturing a semiconductor memory device according to some embodiments. In the description of the method for manufacturing the device, content that is repeated above using Figures 1 to 8 is briefly described or its description is omitted.

[0198] Referring to Figure 26, a bit line structure 140ST can be formed on the substrate 100.

[0199] Bitline structure 140ST may include unit conductive lines 140 and unit line capping films 144 stacked on the fourth direction DR4.

[0200] Cell line spacers 150 can be formed on the sidewalls of the bit line structure 140ST. After forming the cell line spacers 150, memory contacts 120 can be formed between adjacent bit line structures 140ST in the first direction DR1.

[0201] A lower storage pad 160B can be formed on the storage contact 120. For example, the upper surface of the lower storage pad 160B can be coplanar with the upper surface 144US of the cell line cover film.

[0202] After forming a lower pad silicide film 161 on the storage contact 120, a lower pad filler film 162 can be formed.

[0203] Referring to Figure 27, a pad mask pattern 50 can be formed on the lower storage pad 160B and the bit line structure 140ST.

[0204] The pad mask pattern 50 may include a storage pad hole 160U_H that exposes the lower storage pad 160B. The storage pad hole 160U_H may expose the lower pad fill film 162.

[0205] More specifically, a polysilicon film can be formed on the lower memory pad 160B and the bit line structure 140ST. A memory pad hole 160U_H that exposes the lower memory pad 160B can be formed in the polysilicon film. Thus, a pad mask pattern 50 can be formed. The width of the memory pad hole 160U_H can increase as the memory pad hole 160U_H moves away from the lower memory pad 160B.

[0206] While forming the storage pad hole 160U_H, a portion of the cell line cover film 144 and a portion of the lower pad fill film 162 may be etched. However, this disclosure is not limited thereto.

[0207] The pad mask pattern 50 may include, for example, polysilicon. The polysilicon may have high etch selectivity relative to each of the materials included in the cell line capping film 144 and the materials included in the lower pad fill film 162. Due to this high etch selectivity, the amount of etching of each of the cell line capping film 144 and the lower pad fill film 162 can be reduced while forming the memory pad via 160U_H. That is, the lowermost position of the memory pad via 160U_H can be spaced sufficiently from the cell conductor 140, for example, sufficient to reduce the possibility of an electrical short circuit between the cell conductor 140 and the memory pad 160. Furthermore, the memory pad via 160U_H can be spaced sufficiently from another adjacent lower memory pad 160B.

[0208] Referring to Figures 27 and 28, the upper storage pad 160U can be formed on the lower storage pad 160B.

[0209] The upper storage pad 160U can be formed within the storage pad hole 160U_H. The upper storage pad 160U can fill the storage pad hole 160U_H. Therefore, a storage pad 160 including the lower storage pad 160B and the upper storage pad 160U can be formed.

[0210] The upper storage pad 160U can be formed, for example, using a chemical vapor deposition (CVD) method. However, embodiments of this disclosure are not limited thereto. Although not shown, an upper pad silicide film (166 in FIG. 13) can be formed on the sidewall of the storage pad hole 160U_H simultaneously with the formation of the upper storage pad 160U. The upper pad silicide film 166 can be formed by converting the portion of polysilicon exposed through the storage pad hole 160U_H into silicide.

[0211] Referring to Figures 28 and 29, the pad mask pattern 50 can be removed.

[0212] The pad mask pattern 50 can be removed so that at least a portion of the upper storage pad 160U can protrude upward beyond the upper surface 144US of the cell line cover film.

[0213] Referring to Figures 29 and 30, the upper storage pad 160U can be used as a mask to remove another part of the lower storage pad 160B.

[0214] Therefore, a pad isolation groove 180R can be formed around the upper storage pad 160U.

[0215] Referring to Figures 30 and 31, a pad isolation pattern 180 can be formed on the lower storage pad 160B and the bit line structure 140ST.

[0216] The pad isolation pattern 180 can fill the pad isolation recess 180R. The pad isolation pattern 180 can be formed using a deposition process. The pad isolation pattern 180 can cover the sidewall of the upper storage pad 160U. The pad isolation pattern 180 can be formed around the upper storage pad 160U.

[0217] Although not shown, an air gap or seam pattern can be formed within the pad isolation pattern 180 between adjacent upper storage pads 160U.

[0218] Next, referring to Figure 5, a data storage pattern 190 can be formed on the storage pad 160.

[0219] Figures 32 to 36 are diagrams of intermediate structures corresponding to intermediate steps in a method for manufacturing a semiconductor memory device according to some embodiments. Figure 32 may represent a manufacturing process performed after Figure 26.

[0220] Briefly describe or omit the content that is repeated in the description of the manufacturing method described in Figures 26 to 31, or omit the description of it.

[0221] Referring to Figure 32, a portion of the lower storage pad 160B can be etched so that the vertical level of the upper surface of the lower storage pad 160B can be lower than the vertical level of the upper surface 144US of the cell line cover film.

[0222] For example, a portion of the lower pad filler film 162 can be removed, so that the vertical level of the upper surface of the lower storage pad 160B can be lowered.

[0223] Referring to Figure 33, a pad mask pattern 50 can be formed on the lower storage pad 160B and the bit line structure 140ST.

[0224] Pad mask pattern 50 can be formed on lower storage pad 160B, the upper surface of lower storage pad 160B having a reduced vertical level.

[0225] The pad mask pattern 50 may include a storage pad hole 160U_H exposing the lower storage pad 160B. A portion of the storage pad hole 160U_H may extend into or be recessed into the lower pad fill film 162. While forming the storage pad hole 160U_H, another portion of the lower pad fill film 162 may be removed. However, embodiments of this disclosure are not limited thereto.

[0226] Referring to Figures 33 and 34, the upper storage pad 160U can be formed on the lower storage pad 160B.

[0227] Therefore, storage pad 160 can be formed.

[0228] Although not shown, while forming the upper storage pad 160U, an upper pad silicide film (166 in Figure 18) can be formed on the sidewall of the storage pad hole 160U_H.

[0229] Referring to Figures 34 and 35, the pad mask pattern 50 can be removed.

[0230] The pad mask pattern 50 can be removed so that at least a portion of the upper storage pad 160U can protrude upward beyond the upper surface 144US of the cell line cover film.

[0231] Referring to Figures 35 and 36, a pad isolation pattern 180 can be formed on the lower storage pad 160B and the bit line structure 140ST.

[0232] Pad isolation pattern 180 can be formed around the upper storage pad 160U.

[0233] Next, referring to Figure 18, a data storage pattern 190 can be formed on the storage pad 160.

[0234] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of this disclosure. Therefore, the preferred embodiments of this disclosure are used only in a general and descriptive sense and not for limiting purposes.

[0235] Cross-reference to related applications

[0236] This application claims priority to Korean Patent Application No. 10-2024-0152538, filed with the Korean Intellectual Property Office on October 31, 2024.

Claims

1. A semiconductor memory device, comprising: A substrate, including an active region demarcated by a component isolation film; a bit line structure on the substrate, the bit line structure including a unit conductive line and a unit line capping film, wherein the unit line capping film extends thereon along the upper surface of the unit conductive line; Storage contact, on the opposite side of the bit line structure and connected to the active region; storage pad, on one of the storage contacts and connected to the one of the storage contacts. and data storage pattern, on the upper surface of the cell line cover film and connected to the storage pad, wherein the storage pad includes an upper storage pad and a lower storage pad between the upper storage pad and the storage contact, and wherein the width of the upper storage pad on the upper surface of the cell line cover film increases with the distance from the upper surface of the cell line cover film.

2. The semiconductor memory device of claim 1, wherein the upper memory pad comprises a first portion and a second portion, wherein the first portion of the upper memory pad is on the upper surface of the cell line cover film, and wherein the second portion of the upper memory pad is between the first portion of the upper memory pad and the lower memory pad.

3. The semiconductor memory device of claim 1, wherein the upper storage pad is integrally located on the upper surface of the cell line cover film and the lower storage pad.

4. The semiconductor memory device of claim 1, wherein the memory contact comprises a semiconductor material, and each of the upper memory pad and the lower memory pad comprises a metal or a metal-containing compound.

5. The semiconductor memory device of claim 1, further comprising a pad isolation pattern on the sidewall of the upper storage pad, wherein the upper storage pad includes an upper pad fill film and an upper pad silicide film, and wherein the upper pad silicide film extends along a boundary surface between the upper pad fill film and the pad isolation pattern.

6. The semiconductor memory device of claim 5, wherein the lower memory pad comprises a lower memory pad filler film and a lower memory pad silicide film between the lower memory pad filler film and the memory contact.

7. The semiconductor memory device of claim 6, wherein the lower pad silicide film and the upper pad silicide film are spaced apart from each other by the lower pad filler film.

8. The semiconductor memory device of claim 5, wherein the upper memory pad contacts the lower memory pad, and wherein the upper pad silicide film does not extend along the boundary surface between the upper pad filler film and the lower memory pad.

9. The semiconductor memory device of claim 5, wherein the upper pad silicide film comprises a silicide of the metal included in the upper pad filling film.

10. A semiconductor memory device, comprising: The substrate includes the active region demarcated by the device isolation film; Bitline structure, on the substrate and including unit conductive lines and unit line capping film stacked in a first direction, wherein the unit line capping film extends thereon along the upper surface of the unit conductive lines; Storage contact, on the opposite side of the bit line structure and connected to the active region; storage pad, on one of the storage contacts and connected to the one of the storage contacts. and a data storage pattern, on the upper surface of the cell line cover film and connected to the storage pad, wherein the storage pad includes an upper storage pad and a lower storage pad between the upper storage pad and the storage contact, wherein the upper storage pad includes an upper surface connected to the data storage pattern, a bottom surface in contact with the lower storage pad and the bit line structure, and a sidewall connecting the upper surface of the upper storage pad and the bottom surface of the upper storage pad to each other, wherein the upper storage pad includes an upper pad filler film and an upper pad silicide film, and wherein the upper pad silicide film includes the sidewall of the upper storage pad.

11. The semiconductor memory device of claim 10, wherein the upper pad silicide film does not extend along the boundary between the upper pad filler film and the lower memory pad.

12. The semiconductor memory device of claim 10, wherein in a cross-sectional view of the semiconductor memory device, the upper pad silicide film includes a first upper pad silicide film and a second upper pad silicide film spaced apart from each other in a second direction perpendicular to the first direction, wherein the cross-sectional view is a plane including the first direction and the second direction, and wherein the height of the first upper pad silicide film in the first direction is equal to the height of the second upper pad silicide film in the first direction.

13. The semiconductor memory device of claim 10, wherein in a cross-sectional view of the semiconductor memory device, the upper pad silicide film includes a first upper pad silicide film and a second upper pad silicide film spaced apart from each other in a second direction perpendicular to the first direction, wherein the cross-sectional view is a plane including the first direction and the second direction, wherein the first upper pad silicide film contacts the lower memory pad, wherein the second upper pad silicide film contacts the bit line structure, and wherein the height of the first upper pad silicide film in the first direction is greater than the height of the second upper pad silicide film in the first direction.

14. The semiconductor memory device of claim 10, wherein the width of the upper storage pad on the upper surface of the cell line cover film increases with increasing distance from the upper surface of the cell line cover film.

15. The semiconductor memory device of claim 10, wherein the lower memory pad includes a lower pad filler film and a lower pad silicide film between the lower pad filler film and the memory contact, and wherein the lower pad silicide film is not directly connected to the upper pad silicide film.

16. The semiconductor memory device of claim 10, wherein the memory contact comprises a semiconductor material, and wherein the lower memory pad comprises a metal or a metal-containing compound.

17. The semiconductor memory device of claim 10, wherein the upper memory pad comprises a first portion and a second portion, wherein the first portion of the upper memory pad is on the upper surface of the cell line cover film, and wherein the second portion of the upper memory pad is between the first portion of the upper memory pad and the lower memory pad.

18. A semiconductor memory device, comprising: The substrate includes a cell region and a peripheral region surrounding the cell region, the cell region including a cell active region demarcated by a cell element isolation film; Bitline structure, on the cell region of the substrate and including cell conductive lines and cell line capping film, wherein the cell line capping film extends thereon along the upper surface of the cell conductive lines; A peripheral gate structure is provided on the peripheral region of the substrate and includes a peripheral gate conductive film. Peripheral wiring lines are provided on the peripheral gate structure. Storage contacts are connected to the active area of ​​the unit; Storage pads are connected to the storage contacts; Pad isolation patterns isolate adjacent storage pads from each other in the storage pads; and a data storage pattern, on the upper surface of the cell line cover film and connected to the storage pad, wherein the storage pad includes an upper storage pad and a lower storage pad between the upper storage pad and the storage contact, wherein the upper storage pad includes a first portion on the upper surface of the cell line cover film and a second portion between the first portion of the upper storage pad and the lower storage pad, and wherein the width of the first portion of the upper storage pad increases with increasing distance from the upper surface of the cell line cover film.

19. The semiconductor memory device of claim 18, wherein the upper memory pad comprises an upper pad fill film and an upper pad silicide film, and wherein the upper pad silicide film extends along a boundary surface between the upper pad fill film and the pad isolation pattern.

20. The semiconductor memory device of claim 18, wherein, The width of the peripheral wiring increases with the distance from the peripheral gate conductive film, wherein the peripheral wiring includes a peripheral wiring filler film and a peripheral wiring silicide film, and wherein the peripheral wiring silicide film includes the sidewalls of the peripheral wiring.

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