DRAM (Dynamic Random Access Memory) storage unit structure and preparation method thereof

Abstract

The invention provides a DRAM (Dynamic Random Access Memory) storage unit structure and a preparation method thereof. The DRAM storage unit structure comprises a substrate, a word line, a bit line, a plurality of vertical channel transistors and capacitor units positioned below the vertical channel transistors, the capacitor unit is located on the substrate and vertically extends into the substrate; a source region, a gate region and a drain region of the vertical channel transistor are sequentially arranged from top to bottom, and the capacitor unit is connected below the drain region; the word line is connected with the gate regions of the at least two vertical channel transistors, and the bit line is connected with the source regions of the at least two vertical channel transistors. According to the invention, the fringe effect is reduced to the greatest extent, subsequent integration with peripheral circuits is facilitated, and the overall performance of the device is improved.

Description

A DRAM memory cell structure and its fabrication method Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a DRAM memory cell structure and its fabrication method. Background Technology

[0002] The 4F²DRAM (Dynamic Random Access Memory) memory cell structure currently in use is typically a vertical channel transistor 4F²DRAM. Based on 6F²DRAM, the cell area is significantly reduced by vertically stacking the source, gate, and drain of the transistors.

[0003] In the relevant 4F² DRAM memory cell structure, the cell capacitor is located at the top, the bit line (BL) at the bottom, and the word line (WL) in the middle layer. Because the cell capacitor is at the top, there is a height difference between it and the surrounding circuitry, making subsequent integration with the surrounding circuitry difficult and failing to resolve the edge effect between the cell capacitor and the surrounding circuitry, thus affecting device performance. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a DRAM memory cell structure and its fabrication method, which minimizes edge effects, is more conducive to subsequent integration with peripheral circuits, and is also compatible with future bonding process requirements, thereby improving the overall performance of the device.

[0005] To achieve the above objectives, the technical solution adopted in the embodiments of the present invention is as follows: In a first aspect, the embodiments of the present invention provide a DRAM memory cell structure, including: a substrate, word lines, bit lines, a plurality of vertical channel transistors, and capacitor cells located below the vertical channel transistors; the capacitor cells are located on the substrate and extend vertically into the interior of the substrate; the source region, gate region, and drain region of the vertical channel transistors are arranged sequentially from top to bottom, and the capacitor cells are connected below the drain region; the word lines are connected to the gate regions of at least two of the vertical channel transistors, and the bit lines are connected to the source regions of at least two of the vertical channel transistors.

[0006] Furthermore, the material of the channel between the gate region and the source region and the drain region is a metal oxide.

[0007] Furthermore, the metal oxide includes indium gallium zinc oxide.

[0008] Furthermore, the DRAM memory cell structure further includes: a dielectric layer, the dielectric layer being located above the capacitor cell, the source region and the bit line being located above the dielectric layer, the gate region and the drain region being embedded in the dielectric layer, and the vertical connection structure formed by the gate region, the channel and the drain region penetrating the dielectric layer.

[0009] Secondly, embodiments of the present invention also provide a method for fabricating a DRAM memory cell structure, comprising: providing a substrate; forming a plurality of uniformly distributed capacitor cells extending vertically into the substrate on the substrate; forming word lines, bit lines, and vertical channel transistors above the capacitor cells, such that the drain region of the vertical channel transistor is connected to the capacitor cell; wherein the source region, gate region, and drain region of the vertical channel transistor are arranged sequentially from top to bottom, the word lines are connected to the gate regions of at least two of the vertical channel transistors, and the bit lines are connected to the source regions of at least two of the vertical channel transistors.

[0010] Furthermore, forming a plurality of uniformly distributed capacitor cells that extend vertically into the interior of the substrate on the substrate includes: etching the substrate to form a plurality of uniformly distributed capacitor holes that extend vertically into the interior of the substrate on the substrate; wherein the depth of the capacitor holes is less than the thickness of the substrate; and sequentially depositing a first conductive layer, a high-k dielectric layer, and a second conductive layer until the capacitor holes are filled to form the capacitor cells.

[0011] Further, forming a word line, a bit line, and a vertical channel transistor above the capacitor cell includes: forming a drain region connecting the capacitor cell above the capacitor cell; depositing a first dielectric layer, forming the gate region and the word line connecting the gate region above the first dielectric layer; depositing a second dielectric layer, etching the first dielectric layer and the second dielectric layer, and filling them with a metal oxide layer to form a channel connecting the drain region and the gate region; depositing a third conductive layer, etching the third conductive layer to form the source region and the bit line connecting the source region; wherein the word line extends along a first direction, the bit line extends along a second direction, and the first direction is perpendicular to the second direction.

[0012] Furthermore, the step of etching and filling the first dielectric layer and the second dielectric layer with a metal oxide layer to form a channel connecting the drain region and the gate region includes: etching a channel hole in the first dielectric layer and the second dielectric layer until the drain region is exposed; wherein the channel hole penetrates the gate region; growing a metal oxide in the channel hole to form a channel connecting the drain region and the gate region; wherein the surface of the channel is flush with the surface of the second dielectric layer.

[0013] Furthermore, the metal oxide is indium gallium zinc oxide.

[0014] Furthermore, the conductive layer is a titanium nitride layer.

[0015] This invention provides a DRAM memory cell structure and its fabrication method. The DRAM memory cell structure includes: a substrate, word lines, bit lines, multiple vertical channel transistors (VCTs), and capacitor cells located below the VCTs. The capacitor cells are located on the substrate and extend vertically into the substrate. The source, gate, and drain regions of the VCTs are arranged sequentially from top to bottom, and the capacitor cells are connected below the drain regions. The word lines are connected to the gate regions of at least two VCTs, and the bit lines are connected to the source regions of at least two VCTs. This invention, by employing an inverted DRAM memory cell structure, places capacitor cells with high depth and width bit points within the substrate, allowing the capacitor cells to be on the same plane as the peripheral circuitry. This minimizes edge effects, facilitates subsequent integration with peripheral circuitry, and is compatible with future bonding process requirements, thus improving the overall performance of the device.

[0016] Other features and advantages of the embodiments of the present invention will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above in the embodiments of the present invention.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1a shows a front view of the relevant 4F² DRAM memory cell structure; Figure 1b shows a top view of the relevant 4F² DRAM memory cell structure; Figure 2 shows a flowchart of a method for fabricating a DRAM memory cell structure according to an embodiment of the present invention; Figure 3a shows a cross-sectional view of a memory cell structure after forming a capacitor cell on a substrate according to an embodiment of the present invention; Figure 3b shows a schematic cross-sectional view of a fabricated DRAM memory cell structure according to an embodiment of the present invention; Figure 4a shows a schematic diagram of substrate etching according to an embodiment of the present invention; Figure 4b shows a schematic diagram of first conductive layer deposition according to an embodiment of the present invention; Figure 4c shows a schematic diagram of high-k dielectric layer deposition according to an embodiment of the present invention; Figure 4d shows a schematic diagram of second conductive layer deposition according to an embodiment of the present invention; Figure 5a shows a schematic diagram of gate region and drain region fabrication according to an embodiment of the present invention; Figure 5b shows a schematic diagram of channel formation according to an embodiment of the present invention; Figure 6 shows a top view of a fabricated DRAM memory cell structure according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be described below in conjunction with the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0021] Currently, referring to the front view of the relevant 4F²DRAM memory cell structure shown in Figure 1a and the top view of the relevant 4F²DRAM memory cell structure shown in Figure 1b, the bit line (BL) of the relevant 4F²DRAM memory cell structure is located at the bottom, the word line (WL) is located in the middle layer of the structure, and the capacitor cell (Cell Capacitor) is located at the top of the DRAM memory cell structure.

[0022] Traditional silicon channels typically use silicon materials that can only be epitaxially grown. Due to the limitations of traditional silicon channel epitaxial processes, it is difficult to fabricate the ring gate word lines of DRAM memory cell structures. Furthermore, since the capacitor cells are located at the top of the structure, there is a height difference between the capacitor cells and the peripheral circuits, which makes it impossible to resolve the edge effect between the capacitor cells and the peripheral circuits, resulting in greater difficulty in subsequent interconnection processes.

[0023] To address the aforementioned issues, this invention provides a DRAM memory cell structure and its fabrication method, which will be described in detail below.

[0024] This embodiment provides a method for fabricating a DRAM memory cell structure. This method can be applied to semiconductor process equipment. Referring to the flowchart of the DRAM memory cell structure fabrication method shown in Figure 2, the method mainly includes the following steps: Step S202, providing a substrate; the substrate can be a silicon substrate. The DRAM memory cell structure can be a 4F² DRAM structure, where "F" is the minimum lithographic feature size for manufacturing this array structure.

[0025] Step S204: Multiple capacitor cells are formed on the substrate, uniformly distributed and vertically extending into the substrate. Inverted high aspect ratio capacitor cells are fabricated on the substrate using high-precision photolithography and deep silicon etching processes. Hole etching and filling are performed on the substrate to form multiple vertically extending high aspect ratio capacitor cells into the substrate, thus placing the high aspect ratio capacitor cells within the substrate. See Figure 3a for a cross-sectional view of the memory cell structure after forming the capacitor cells on the substrate. The depth of the capacitor cell 20 extending into the substrate 10 is less than the thickness of the substrate 10.

[0026] The distribution of the capacitor units can be shown as circles in the top view of Figure 1b, with the same spacing between each capacitor unit and its horizontal and vertical adjacent units.

[0027] In step S206, word lines, bit lines, and vertical channel transistors are formed above the capacitor cell, such that the drain region of the vertical channel transistor is connected to the capacitor cell. The source, gate, and drain regions of the vertical channel transistors are arranged sequentially from top to bottom. The word lines are connected to the gate regions of at least two vertical channel transistors, and the bit lines are connected to the source regions of at least two vertical channel transistors. The word lines extend along a first direction, and the bit lines extend along a second direction, with the first and second directions perpendicular to each other.

[0028] After the capacitor cell is formed, a multilayer dielectric layer and a conductive layer are deposited on the substrate and etched to form a vertical channel transistor. See the schematic cross-sectional view of the fabricated DRAM memory cell structure shown in Figure 3b. The drain region 31 of the vertical channel transistor is connected to the capacitor cell 20, and the gate region 33 is connected to the drain region 31 and the source region 35 through the channel 32.

[0029] As shown in Figure 3b, the above DRAM memory cell structure is placed in a three-dimensional coordinate system XYZ. The DRAM memory cell structure includes multiple bit lines 36 and multiple word lines (not shown in the figure). The bit lines 36 are connected in series with each source region 35 in the X-axis direction, and the word lines are connected with each gate region 33 in the Z-axis direction.

[0030] After the memory cell structure is prepared, it can be interconnected with the peripheral circuit, or the memory cell wafer and logic cell can be integrated through hybrid bonding technology to form a complete 4F² DRAM chip.

[0031] After the complete 4F²DRAM chip is formed, performance tests can be performed on the prepared 4F²DRAM chip to verify its storage density, power consumption and data retention capabilities.

[0032] The method for fabricating the DRAM memory cell structure provided in this embodiment uses an inverted DRAM memory cell structure to place capacitor cells with high depth and width bit points in the substrate, so that the capacitor cells can be on the same plane as the peripheral circuits, minimizing edge effects and making it more conducive to subsequent integration with peripheral circuits. At the same time, it can also be compatible with future bonding process requirements, thereby improving the overall performance of the device.

[0033] In one embodiment, this embodiment provides a specific implementation of forming a plurality of uniformly distributed capacitor cells that extend vertically into the interior of the substrate: etching the substrate to form a plurality of uniformly distributed capacitor holes that extend vertically into the interior of the substrate; wherein the depth of the capacitor holes is less than the thickness of the substrate; and sequentially depositing a first conductive layer, a high-k dielectric layer, and a second conductive layer until the capacitor holes are filled to form a capacitor cell.

[0034] Referring to the substrate etching schematic diagram shown in Figure 4a, capacitor hole etching is performed on the substrate 10 to form a plurality of uniformly distributed capacitor holes 41 that extend vertically into the substrate. The top view of the distribution of capacitor holes 41 on the substrate can be the same as the circular distribution shown in Figure 1b, and the spacing between any two adjacent capacitor holes is the same.

[0035] Referring to the schematic diagram of the first conductive layer deposition shown in Figure 4b, a first conductive layer 42 is deposited on the substrate 10 after etching high aspect ratio capacitor holes and on the bottom and sidewalls of capacitor holes 41. The first conductive layer 42 is a metal conductive layer, such as a titanium nitride layer. The first conductive layer 42 is the lower electrode of the capacitor unit.

[0036] Referring to the schematic diagram of high-K dielectric layer deposition shown in Figure 4c, a high-K dielectric layer 43 is deposited above the first conductive layer 42.

[0037] Referring to the schematic diagram of the deposition of the second conductive layer shown in Figure 4d, a second conductive layer 44 is deposited above the high-k dielectric layer 43. The second conductive layer 44 is a metal conductive layer, such as a titanium nitride layer. The second conductive layer 44 is the upper electrode of the capacitor unit, resulting in a cross-sectional view of the structure after the capacitor unit 20 is formed on the substrate 10.

[0038] In one embodiment, this embodiment provides an implementation method for forming word lines, bit lines, and vertical channel transistors above capacitor cells. Specifically, the following steps can be performed: Step 1, forming a drain region connecting the capacitor cells above the capacitor cells; using a photoresist layer covering each capacitor hole as a mask, etching away the second conductive layer on the structure after forming the capacitor cell 20 on the substrate 10 as shown in FIG. 3a until the high-k dielectric layer 43 is exposed, and removing the photoresist layer to form the drain region 31 of the vertical channel transistor. Referring to the schematic diagram of gate region and drain region fabrication shown in FIG. 5a, after removing the second conductive layer, the protruding conductive layer portion above the high-k dielectric layer 43 is the drain region 31, so that the drain region 31 is connected to the upper electrode of the capacitor cell.

[0039] Step 2: Deposit the first dielectric layer, and form the gate region and word lines connecting the gate region above the first dielectric layer; as shown in Figure 5a, deposit the first dielectric layer 51 above the high-K dielectric layer 43, deposit the metal conductive layer above the first dielectric layer 51, and etch the metal conductive layer using the patterned photoresist layer as a mask until the first dielectric layer 51 is exposed, forming the gate region 33 and the word lines connecting the gate region 33 (Figure 5a is a cross-sectional view and the structure of the word lines is not shown. The word lines are linear structures that extend along the Z-axis direction and are connected in series with each gate region 33 in the Z-axis direction). The gate region 33 is located directly above the gate region 33.

[0040] Step 3: Deposit the second dielectric layer, etch the first dielectric layer and the second dielectric layer and fill them with a metal oxide layer to form a channel connecting the drain region and the gate region; remove the photoresist layer above the word line, see the channel formation schematic diagram shown in Figure 5b, and deposit the second dielectric layer 52.

[0041] The materials of the first dielectric layer 51 and the second dielectric layer 52 can be insulating materials that serve as isolation to prevent signal interference between the transistor and the capacitor unit, such as silicon oxide or silicon nitride.

[0042] In one specific embodiment, a channel hole is etched on the first dielectric layer 51 and the second dielectric layer 52 until the drain region 31 is exposed; wherein the channel hole penetrates the gate region; a metal oxide is grown in the channel hole to form a channel connecting the drain region 31 and the gate region 33; wherein the surface of the channel is flush with the surface of the second dielectric layer.

[0043] As shown in Figure 5b, a metal oxide layer is grown in the channel hole to form the channel 32 by ALD (atomic layer deposition) or CVD (chemical vapor deposition). The second dielectric layer 52 is etched back so that the surface of the channel 32 is flush with the surface of the second dielectric layer 52.

[0044] The inventors discovered that the fabrication process of related memory cell structures typically uses silicon channels. However, silicon channels can usually only be fabricated using epitaxial processes, which makes it difficult to fabricate the ring gate word line structure and makes the process quite challenging.

[0045] In this embodiment, when fabricating the vertical channel transistor, the metal oxide material used for the channel can be a novel channel material that is easy to integrate in the back-end, such as channel IGZO (indium gallium zinc oxide). This novel indium gallium zinc oxide material can be grown using ALD or CVD methods. This embodiment simplifies the fabrication process of the ring gate word line structure and reduces the process complexity by first fabricating the ring gate word line structure, then etching the channel holes and growing indium gallium zinc oxide material in the channel holes.

[0046] Step 4: Deposit the third conductive layer and etch the third conductive layer to form the source region and the bit line connecting the source region; wherein, the word line extends along the first direction and the bit line extends along the second direction, and the first direction is perpendicular to the second direction.

[0047] As shown in Figure 3b, after forming the channel 32, a third conductive layer is deposited above the second dielectric layer 52. The material of the third conductive layer is a metallic conductive material, such as titanium nitride. The third conductive layer is etched using a patterned photoresist layer as a mask to form the source region 35 and the bit line 36 connecting the source region 35.

[0048] Referring to the top view of the fabricated DRAM memory cell structure shown in Figure 6, bit lines 36 are connected in series with multiple source regions in the X-axis direction, word lines 61 are connected in series with multiple gate regions in the Z-axis direction, bit lines 36 are located at the top of the DRAM memory cell structure, word lines 61 are located in the middle layer, capacitor cells 20 are located below word lines 61, the gate region connected to word lines 61 is connected to the drain region below, the drain region is connected to the capacitor cell 20 below, and the extension direction of bit lines 36 is perpendicular to the extension direction of word lines 61.

[0049] The fabrication method of the DRAM memory cell structure provided in this embodiment improves the capacitor density and significantly reduces the chip area by setting an inverted 4F² DRAM memory cell structure and integrating inverted high aspect ratio capacitors. This improves the memory density. The vertical channel transistor (VCT) optimizes transistor performance and leakage current control, thereby reducing power consumption. The inverted high aspect ratio capacitor cell places the capacitor cell area and the peripheral circuit on the same plane, minimizing edge effects and facilitating integration with the peripheral circuit. It is also compatible with future bonding process requirements. The hybrid bonding technology achieves efficient integration of memory cells and logic cells, improving overall performance.

[0050] Corresponding to the fabrication method of the DRAM memory cell structure provided in the above embodiments, this embodiment of the invention provides a DRAM memory cell structure, as shown in FIG3b. The DRAM memory cell structure includes: a substrate 10, word lines (not shown in the figure), bit lines 36, a plurality of vertical channel transistors, and capacitor cells 20 located below the vertical channel transistors; the capacitor cells 20 are located on the substrate 10 and extend vertically into the substrate; the source region 35, gate region 33, and drain region 31 of the vertical channel transistors are arranged sequentially from top to bottom, and the capacitor cells 20 are connected below the drain region 31; the word lines are connected to the gate regions 33 of at least two vertical channel transistors, and the bit lines 36 are connected to the source regions 35 of at least two vertical channel transistors.

[0051] As shown in Figure 3b, the above DRAM memory cell structure is placed in a three-dimensional coordinate system. The DRAM memory cell structure includes multiple bit lines 36 and multiple word lines (not shown in the figure). The bit lines 36 are connected in series with each source region 35 in the X-axis direction, and the word lines are connected with each gate region 33 in the Z-axis direction.

[0052] After the memory cell structure is prepared, it can be interconnected with the peripheral circuit, or the memory cell wafer and logic cell can be integrated through hybrid bonding technology to form a complete 4F² DRAM chip.

[0053] After the complete 4F²DRAM chip is formed, performance tests can be performed on the prepared 4F²DRAM chip to verify its storage density, power consumption and data retention capabilities.

[0054] The DRAM memory cell structure provided in this embodiment adopts an inverted DRAM memory cell structure, placing the capacitor cell with high depth and width bit points in the substrate, so that the capacitor cell can be on the same plane as the peripheral circuit, minimizing edge effects, which is more conducive to subsequent integration with the peripheral circuit, and is also compatible with future bonding process requirements, thus improving the overall performance of the device.

[0055] In one embodiment, the material of the channel between the gate region and the source and drain regions provided in this embodiment is a metal oxide.

[0056] In one embodiment, the metal oxide provided in this embodiment includes indium gallium zinc oxide.

[0057] In one embodiment, the DRAM memory cell structure provided in this embodiment further includes: a dielectric layer, the dielectric layer being located above the capacitor cell, the source region and the bit line being located above the dielectric layer, the gate region and the drain region being embedded in the dielectric layer, and the vertical connection structure formed by the gate region, the channel and the drain region penetrating the dielectric layer.

[0058] As shown in Figure 3b, the dielectric layer may include a first dielectric layer 51 and a second dielectric layer 52. The first dielectric layer 51 is located above the capacitor cell 20, the source region 35 and the bit line 36 are located above the second dielectric layer 52, the gate region 33 and the drain region 31 are embedded in the dielectric layer (including the first dielectric layer 51 and the second dielectric layer 52), and the vertical connection structure formed by the gate region 33, the channel 32 and the drain region 31 penetrates the dielectric layer (including the first dielectric layer 51 and the second dielectric layer 52).

[0059] The DRAM memory cell structure provided in this embodiment achieves a compact 4F² structure by using word lines to connect the gate, bit lines to connect the source, and drain to connect the capacitor cell below. It integrates inverted high aspect ratio capacitors, which increases capacitance density while minimizing edge effects, making it more conducive to integration with peripheral circuits, and also compatible with future bonding process requirements.

[0060] The structure provided in this embodiment has the same implementation principle and technical effect as the aforementioned embodiments. For the sake of brevity, any parts not mentioned in the structural embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0061] Corresponding to the DRAM memory cell structure fabrication method provided in the above embodiments, this embodiment of the invention provides a semiconductor process apparatus, which includes a reaction chamber and a controller. The controller includes a processor and a memory. The memory stores a computer program that can run on the processor. When the processor executes the computer program, it implements the steps of the method provided in the above embodiments.

[0062] This invention provides a computer-readable medium storing computer-executable instructions. When these computer-executable instructions are invoked and executed by a processor, they cause the processor to implement the methods described in the above embodiments.

[0063] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the system described above can be referred to the corresponding process in the foregoing embodiments, and will not be repeated here.

[0064] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0065] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0066] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A DRAM memory cell structure, characterized in that, include: Substrate, word line, bit line, multiple vertical channel transistors and capacitor cells located below the vertical channel transistors; The capacitor unit is located on the substrate and extends vertically into the interior of the substrate; The source, gate, and drain regions of the vertical channel transistor are arranged sequentially from top to bottom, and the capacitor cell is connected below the drain region; the word line is connected to the gate regions of at least two of the vertical channel transistors, and the bit line is connected to the source regions of at least two of the vertical channel transistors.

2. The DRAM memory cell structure according to claim 1, characterized in that, The channel between the gate region and the source and drain regions is made of metal oxide.

3. The DRAM memory cell structure according to claim 2, characterized in that, The metal oxide includes indium gallium zinc oxide.

4. The DRAM memory cell structure according to claim 2, characterized in that, Also includes: A dielectric layer is located above the capacitor cell. The source region and the bit line are located above the dielectric layer. The gate region and the drain region are embedded in the dielectric layer, and the vertical connection structure formed by the gate region, the channel, and the drain region extends through the dielectric layer.

5. A method for fabricating a DRAM memory cell structure, characterized in that, include: Provide a substrate; form a plurality of capacitor cells that are uniformly distributed and extend vertically into the interior of the substrate on the substrate; A word line, a bit line, and a vertical channel transistor are formed above the capacitor cell, such that the drain region of the vertical channel transistor is connected to the capacitor cell; wherein the source region, gate region, and drain region of the vertical channel transistor are arranged sequentially from top to bottom, the word line is connected to the gate region of at least two of the vertical channel transistors, and the bit line is connected to the source region of at least two of the vertical channel transistors.

6. The preparation method according to claim 5, characterized in that, The method of forming a plurality of uniformly distributed capacitor cells that extend vertically into the interior of the substrate includes: etching the substrate to form a plurality of uniformly distributed capacitor holes that extend vertically into the interior of the substrate; wherein the depth of the capacitor holes is less than the thickness of the substrate; and sequentially depositing a first conductive layer, a high-k dielectric layer, and a second conductive layer until the capacitor holes are filled to form the capacitor cells.

7. The preparation method according to claim 5, characterized in that, The method of forming a word line, a bit line, and a vertical channel transistor above the capacitor cell includes: forming a drain region connected to the capacitor cell above the capacitor cell; depositing a first dielectric layer, forming a gate region and a word line connected to the gate region above the first dielectric layer; depositing a second dielectric layer, etching the first dielectric layer and the second dielectric layer, and filling them with a metal oxide layer to form a channel connecting the drain region and the gate region; depositing a third conductive layer, etching the third conductive layer, and forming the source region and the bit line connected to the source region; wherein the word line extends along a first direction, the bit line extends along a second direction, and the first direction is perpendicular to the second direction.

8. The preparation method according to claim 7, characterized in that, The step of etching the first dielectric layer and the second dielectric layer and filling them with a metal oxide layer to form a channel connecting the drain region and the gate region includes: etching a channel hole in the first dielectric layer and the second dielectric layer until the drain region is exposed; wherein the channel hole penetrates the gate region; growing a metal oxide in the channel hole to form a channel connecting the drain region and the gate region; wherein the surface of the channel is flush with the surface of the second dielectric layer.

9. The preparation method according to claim 8, characterized in that, The metal oxide is indium gallium zinc oxide.

10. The preparation method according to claim 6 or 7, characterized in that, The conductive layer is a titanium nitride layer.

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