Embedded flash memory structure and manufacturing method
By forming right-angled floating gates and ONO layer sidewalls in the embedded flash memory structure, the inefficiency caused by improper floating gate tip height is solved, and the erasing and programming efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-01-27
- Publication Date
- 2026-05-01
AI Technical Summary
In existing embedded flash memory structures, improper floating gate tip height leads to low programming and erasing efficiency. If the floating gate tip is too high, it is prone to breakage, or if it is too flat, it affects efficiency.
A right-angled floating gate is formed by forming grooves and etching on the floating gate material layer, using an ONO layer as a sidewall, and forming a tunneling oxide layer and word lines on the surface of the floating gate. The word lines extend towards the source line polysilicon direction to isolate the floating gate and word lines.
It improves erasing efficiency, reduces the chance of the floating gate tip breaking off, improves programming efficiency, and reduces the difficulty of opening the channel.
Smart Images
Figure CN121968584A_ABST
Abstract
Description
Embedded flash memory structure and manufacturing method Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to an embedded flash memory structure and manufacturing method. Background Technology
[0002] Embedded flash memory is a type of non-volatile memory. Because it has the advantages of not losing data after power failure and being able to be repeatedly erased, read, and written, it is widely used in electronic devices such as mobile phones, digital cameras, and tablet computers.
[0003] Referring to Figure 1, the prior art embedded flash memory structure includes a substrate 101, a gate oxide layer 102, a floating gate 103, and a floating gate sidewall 104 sequentially located on the surface of the substrate 101. An opening is formed between the floating gates 103, within which an active line polysilicon 105 is formed. The active line polysilicon 105 is separated from the gate oxide layer 102, the floating gate 103, and the floating gate sidewall 104 by a source line sidewall 106. A word line 107 is also formed on the substrate 101 outside the floating gate 103 relative to the source line polysilicon 105. The word line 107 is separated from the floating gate 103 and the floating gate sidewall 104 by a tunneling oxide layer 108.
[0004] However, in existing embedded flash memory structures, the floating gate 103 has a floating gate tip 109 at the end facing the word line 107. If the height of the floating gate tip 109 is too large, it is prone to breakage. If the height of the floating gate tip 109 is too small, the end of the floating gate is too flat. Therefore, the height of the floating gate tip and the shape of the floating gate have a significant impact on programming and erasing efficiency, potentially reducing the efficiency of programming and erasing. Summary of the Invention
[0005] The purpose of this invention is to provide an embedded flash memory structure and manufacturing method that can improve the efficiency of programming and erasing.
[0006] To achieve the above objectives, the present invention provides a method for manufacturing an embedded flash memory structure, comprising:
[0007] A substrate is provided, on the surface of which a gate oxide layer, a floating gate material layer and a hard mask layer with grooves are sequentially formed, wherein the sidewalls and bottom walls of the grooves are both the hard mask layer;
[0008] A first sidewall is formed within the groove, the first sidewall covering the sidewall and part of the bottom wall of the groove, and the first sidewall is an ONO layer;
[0009] Using the first sidewall as a mask, a portion of the floating gate material layer is etched downwards to expose the surface of the gate oxide layer;
[0010] A second sidewall is formed on the sidewall of the floating grid material. One end of the second sidewall is connected to the first sidewall, and the other end is connected to the grid oxide layer. A first opening is formed on the inner side of the first sidewall and the inner side of the second sidewall.
[0011] A source line polysilicon is formed within the first opening;
[0012] The hard mask layer and part of the floating grid material layer are removed to form a floating grid with right angles and a second opening, the floating grid being located below the first sidewall and the second opening being located between the first sidewall and the floating grid;
[0013] A tunneling oxide layer is formed on the surface of the floating gate;
[0014] A word line is formed on the substrate surface outside the first sidewall, and the word line extends toward the source polysilicon to fill the second opening.
[0015] Optionally, in the manufacturing method of the embedded flash memory structure, an in-situ water vapor generation process is used to form a tunneling oxide layer on the surface of the floating gate.
[0016] Optionally, in the method for manufacturing the embedded flash memory structure, the method for forming the hard mask layer with grooves includes:
[0017] A hard mask layer is formed on the surface of the floating grid material layer;
[0018] The hard mask layer is etched to form a hard mask layer with grooves.
[0019] Optionally, in the manufacturing method of the embedded flash memory structure, the thickness of the hard mask layer located on the bottom wall of the groove is 150 angstroms to 250 angstroms.
[0020] Optionally, in the method for manufacturing the embedded flash memory structure, forming a first sidewall within the groove, the first sidewall covering the sidewall and part of the bottom wall of the groove, includes the following method:
[0021] A first oxide layer, a nitride layer, and a second oxide layer are sequentially formed on the sidewalls and bottom wall of the groove and on the surface of the hard mask layer to form an ONO layer;
[0022] The ONO layer is etched to form the first sidewall.
[0023] Optionally, in the manufacturing method of the embedded flash memory structure, the thickness of both the first oxide layer and the second oxide layer is 200 angstroms to 300 angstroms.
[0024] Optionally, in the manufacturing method of the embedded flash memory structure, the thickness of the nitride layer is 2500 angstroms to 2700 angstroms.
[0025] Optionally, in the method for manufacturing the embedded flash memory structure, the hard mask layer comprises silicon nitride.
[0026] Optionally, in the manufacturing method of the embedded flash memory structure, the floating gate material layer, the source line polysilicon, and the word line all include polysilicon material.
[0027] The present invention also provides an embedded flash memory structure, comprising:
[0028] Substrate;
[0029] A gate oxide layer, a floating gate, a tunneling oxide layer, and a first sidewall are sequentially located on the surface of the substrate, wherein the first sidewall is an ONO layer;
[0030] The source polysilicon, word line, and second sidewall are located on the surface of the gate oxide layer;
[0031] The source polysilicon is located inside the first sidewall and the second sidewall;
[0032] The floating gate is located below the first side wall, and a second opening is formed between the floating gate and the second opening;
[0033] The tunneling oxide layer is located on the surface of the floating gate;
[0034] The word line is located outside the first sidewall and outside the second sidewall. The word line extends toward the source polysilicon and fills the second opening. The word line is isolated from the floating gate through the tunneling oxide layer. The word line is isolated from the word line polysilicon through the first sidewall and the second sidewall.
[0035] In the embedded flash memory structure and manufacturing method provided by this invention, a right-angled floating gate is formed. During erasure, the floating gate tip will not break due to being too high, thus reducing the probability of erasure failure and improving erasure efficiency. During programming, since the source polysilicon and word line are separated by the second sidewall, a coupling voltage is formed between the source polysilicon and word line, increasing the turn-on voltage of the source polysilicon and reducing the difficulty of channel turn-on, thus further improving programming efficiency. Attached Figure Description
[0036] Figure 1 is a schematic diagram of the embedded flash memory structure in the prior art;
[0037] Figure 2 is a flowchart of a method for manufacturing an embedded flash memory structure according to an embodiment of the present invention;
[0038] Figures 3 to 9 are schematic diagrams of the formation process of the embedded flash memory structure according to an embodiment of the present invention;
[0039] In the diagram: 101-substrate, 102-gate oxide layer, 103-floating gate, 104-floating gate sidewall, 105-source line polysilicon, 106-source line sidewall, 107-word line, 108-tunneling oxide layer, 109-floating gate tip, 201-substrate, 202-gate oxide layer, 203-floating gate material layer, 204-hard mask layer, 205-groove, 206-first ONO layer, 206A-first oxide layer, 206B-nitride layer, 206C-second oxide layer, 207-first sidewall, 208-second sidewall, 209-first opening, 210-source line polysilicon, 211-floating gate, 212-second opening, 213-tunneling oxide layer, 214-word line. Detailed Implementation
[0040] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0041] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0042] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.
[0043] Referring to Figure 2, this invention provides a method for manufacturing an embedded flash memory structure, including:
[0044] S11: Provide a substrate, on which a gate oxide layer, a floating gate material layer and a hard mask layer with grooves are sequentially formed, wherein the sidewalls and bottomwalls of the grooves are both hard mask layers;
[0045] S12: A first sidewall is formed in the groove, the first sidewall covering the sidewall and part of the bottom wall of the groove, the first sidewall being an ONO layer;
[0046] S13: Using the first sidewall as a mask, etch a portion of the floating gate material layer downwards to expose the surface of the gate oxide layer;
[0047] S14: A second sidewall is formed on the sidewall of the floating grid material. One end of the second sidewall is connected to the first sidewall, and the other end is connected to the grid oxide layer. A first opening is formed on the inner side of the first sidewall and the inner side of the second sidewall.
[0048] S15: Form source line polysilicon within the first opening;
[0049] S16: Remove the hard mask layer and part of the floating grid material layer to form a floating grid with right angles and a second opening. The floating grid is located below the first sidewall, and the second opening is located between the first sidewall and the floating grid.
[0050] S17: Form a tunneling oxide layer on the surface of the floating gate;
[0051] S18: A word line is formed on the substrate surface outside the first sidewall, and the word line extends toward the source polysilicon to fill the second opening.
[0052] Specifically, referring to Figures 3 and 4, a substrate 201 is preferably provided, which can be a wafer. A gate oxide layer 202, a floating gate material layer 203, and a hard mask layer 204 are sequentially formed on the surface of the substrate 201. A portion of the thickness of the hard mask layer 204 is etched, forming a groove 205 within the hard mask layer 204. The sidewalls of the groove 205 are perpendicular to the bottom wall. The remaining thickness of the hard mask layer 204 on the bottom wall of the groove 205 is 150 angstroms to 250 angstroms.
[0053] Referring to Figure 5, a first ONO layer 206 is formed on the inner wall of the groove 205 and the surface of the hard mask layer 204. The first ONO layer 206 follows the shape of the inner wall of the groove 205. The first ONO layer 206 covering the sidewalls of the groove 205 is perpendicular to the first ONO layer 206 covering the bottom wall of the groove 205. The first ONO layer 206 includes a first oxide layer 206A, a nitride layer 206B, and a second oxide layer 206C covering the hard mask layer 204. The thickness of the first oxide layer 206A is 200 angstroms to 300 angstroms, the thickness of the nitride layer 206B is 2500 angstroms to 2700 angstroms, and the thickness of the second oxide layer 206C is 200 angstroms to 300 angstroms. The method for forming the first oxide layer and the second oxide layer is LPTEOS DEP (low-pressure tetraethyl orthosilicate deposition).
[0054] Referring to Figures 5 and 6, the first ONO layer 206 located at the bottom of the groove 205 and on the surface of the hard mask layer 204, as well as the hard mask layer 204 at the bottom of the first groove 206, are etched to expose the surface of the floating gate material layer 203. The remaining first ONO layer 206 forms the first sidewall 207. The first oxide layer follows the shape of the hard mask layer 204 in an L-shape, the nitride layer is sloped, and the second oxide layer covers the surface of the nitride layer, with one end connected to the top of the first oxide layer and the other end connected to the bottom of the first oxide layer.
[0055] Next, referring to Figure 7, the floating gate material layer 203 is etched downwards along the first sidewall 207, forming a second sidewall 208 on the sidewall of the floating gate material layer 203. A first opening 209 is formed on the inner side of the second sidewall 208 and the first sidewall 207. The second sidewall 208 is formed by depositing and etching a nitride layer material.
[0056] Next, referring to Figure 8, polysilicon material is filled into the first opening 209 and then ground to form the source line polysilicon 210. The hard mask layer 204 is removed using hot phosphoric acid, leaving the first sidewall 207 suspended. The floating gate material layer 203 not located below the first sidewall 207 is then etched away to form a right-angled floating gate 211. Thus, a second opening 212 is formed between the first sidewall 207 and the floating gate 211. Since the first sidewall 207 is an ONO layer, the removal of the hard mask layer 204 protects the nitride within the first sidewall.
[0057] Next, referring to Figure 8, a tunneling oxide layer 213 is formed on the surface of the floating gate 211. In this embodiment of the invention, the tunneling oxide layer 213 is formed using an in-situ steam generation (ISSG) process. Therefore, the oxide in the formed tunneling oxide layer 213 is denser, the interface uniformity is higher, the isolation is improved, and thus the reliability is improved.
[0058] Next, referring to Figure 9, polysilicon material is deposited on the outer side of the first sidewall 207 to form word lines 214, which fill the second opening 212. The first sidewall 207 is an ONO layer, improving the reliability of the connection between the word lines 214 and the first sidewall 207. Furthermore, the word lines 214 are located within the second opening 212, forming a right-angle contact between the word lines and the floating gate, preventing breakage due to excessively high floating gate tips, reducing the probability of erase failure, and thus improving programming efficiency. During programming, since the word lines extend towards the source polysilicon, and are separated from the word lines by the second sidewall, a coupling voltage is formed between the source polysilicon and the word lines, increasing the turn-on voltage of the source polysilicon, reducing the difficulty of channel turn-on, and improving programming efficiency.
[0059] Finally, a third sidewall is formed outside word line 214; this third sidewall is the ONO layer. Then, the source and drain regions are formed using conventional techniques, which will not be elaborated upon here.
[0060] Accordingly, the present invention also provides an embedded flash memory structure, comprising: a substrate; a gate oxide layer, a floating gate, a tunneling oxide layer, and a first sidewall sequentially located on the surface of the substrate, the first sidewall being an ONO layer; a source line polysilicon, a word line, and a second sidewall located on the surface of the gate oxide layer; the source line polysilicon being located inside the first sidewall and the second sidewall; the floating gate being located below the first sidewall and forming a second opening between it and the floating gate; the tunneling oxide layer being located on the surface of the floating gate; the word line being located outside the first sidewall and outside the second sidewall, the word line extending toward the source line polysilicon and filling the second opening, the word line being isolated from the floating gate by the tunneling oxide layer, and the word line being isolated from the word line polysilicon by the first sidewall and the second sidewall.
[0061] In summary, the embedded flash memory structure and manufacturing method provided in this invention form a right-angled floating gate. During erasure, the floating gate tip will not break due to being too high, thus reducing the probability of erasure failure and improving erasure efficiency. During programming, since the source polysilicon and word line are separated by the second sidewall, a coupling voltage is formed between the source polysilicon and word line, increasing the turn-on voltage of the source polysilicon and reducing the difficulty of channel turn-on, thus further improving programming efficiency.
[0062] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for manufacturing an embedded flash memory structure, characterized in that, include: A substrate is provided, on the surface of which a gate oxide layer, a floating gate material layer and a hard mask layer with grooves are sequentially formed, wherein the sidewalls and bottom walls of the grooves are both the hard mask layer; A first sidewall is formed within the groove, covering the sidewall and part of the bottom wall of the groove. The first sidewall is an ONO layer. Using the first sidewall as a mask, part of the floating gate material layer is etched downwards to expose the surface of the gate oxide layer. A second sidewall is formed on the sidewall of the floating gate material. One end of the second sidewall is connected to the first sidewall, and the other end is connected to the gate oxide layer. A first opening is formed on the inner side of the first sidewall and the inner side of the second sidewall. A source line polysilicon is formed in the first opening. The hard mask layer and part of the floating grid material layer are removed to form a floating grid with right angles and a second opening, the floating grid being located below the first sidewall and the second opening being located between the first sidewall and the floating grid; A tunneling oxide layer is formed on the surface of the floating gate; A word line is formed on the substrate surface outside the first sidewall, and the word line extends toward the source polysilicon to fill the second opening.
2. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, An in-situ water vapor generation process is used to form a tunneling oxide layer on the surface of the floating grid.
3. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, A method for forming a hard mask layer with grooves includes: forming a hard mask layer on the surface of the floating gate material layer; and etching portions of the hard mask layer to form a hard mask layer with grooves.
4. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, The thickness of the hard mask layer located on the bottom wall of the groove is 150 angstroms to 250 angstroms.
5. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, The method of forming a first sidewall in the groove, the first sidewall covering the sidewall and part of the bottom wall of the groove, includes: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on the sidewall, bottom wall and the surface of the hard mask layer of the groove to form an ONO layer; etching the ONO layer to form the first sidewall.
6. The method for manufacturing the embedded flash memory structure as described in claim 5, characterized in that, The thickness of both the first oxide layer and the second oxide layer is 200 angstroms to 300 angstroms.
7. The method for manufacturing the embedded flash memory structure as described in claim 5, characterized in that, The thickness of the nitrided layer is 2500 angstroms to 2700 angstroms.
8. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, The hard mask layer comprises silicon nitride.
9. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, The floating gate material layer, source polysilicon, and word line all include polysilicon material.
10. An embedded flash memory structure formed using the manufacturing method of the embedded flash memory structure according to any one of claims 1 to 9, characterized in that, include: Substrate; The substrate comprises, in sequence, a gate oxide layer, a floating gate, a tunneling oxide layer, and a first sidewall, wherein the first sidewall is an ONO layer; a source polysilicon layer, a word line, and a second sidewall are located on the surface of the gate oxide layer; the source polysilicon layer is located inside the first sidewall and the second sidewall; the floating gate is located below the first sidewall and forms a second opening between it and the floating gate; the tunneling oxide layer is located on the surface of the floating gate; the word line is located outside the first sidewall and outside the second sidewall, the word line extends toward the source polysilicon layer and fills the second opening, the word line is isolated from the floating gate by the tunneling oxide layer, and the word line is isolated from the word line polysilicon by the first sidewall and the second sidewall.