Embedded flash memory structure and manufacturing method
By forming right-angled floating gates and isolation structures in the embedded flash memory structure, the problem of low programming and erasing efficiency caused by improper floating gate tip height is solved, achieving higher erasing and programming efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-01-27
- Publication Date
- 2026-05-01
AI Technical Summary
In existing embedded flash memory structures, improper floating gate tip height can lead to low programming and erasing efficiency. If the floating gate tip is too high, it is prone to breakage, or if it is too flat, it will affect programming and erasing efficiency.
By forming right-angled floating gates and isolation structures during the embedded flash memory structure manufacturing process, including the design of ONO layer sidewalls, tunneling oxide layers and word lines, it is ensured that the tip of the floating gate is not easily broken, and the second sidewall isolates the source polysilicon and word lines to form a coupling voltage to improve the turn-on voltage.
It improves erase efficiency, reduces the probability of erase failure, and reduces the difficulty of channel turn-on by increasing the turn-on voltage of the source polysilicon, thereby improving programming efficiency.
Smart Images
Figure CN121968585A_ABST
Abstract
Description
Embedded flash memory structure and manufacturing method Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to an embedded flash memory structure and manufacturing method. Background Technology
[0002] Embedded flash memory is a type of non-volatile memory. Because it has the advantages of not losing data after power failure and being able to be repeatedly erased, read, and written, it is widely used in electronic devices such as mobile phones, digital cameras, and tablet computers.
[0003] Referring to Figure 1, the prior art embedded flash memory structure includes a substrate 101, a gate oxide layer 102, a floating gate 103, and a floating gate sidewall 104 sequentially located on the surface of the substrate 101. An opening is formed between the floating gates 103, within which an active line polysilicon 105 is formed. The active line polysilicon 105 is separated from the gate oxide layer 102, the floating gate 103, and the floating gate sidewall 104 by a source line sidewall 106. A word line 107 is also formed on the substrate 101 outside the floating gate 103 relative to the source line polysilicon 105. The word line 107 is separated from the floating gate 103 and the floating gate sidewall 104 by a tunneling oxide layer 108.
[0004] However, in existing embedded flash memory structures, the floating gate 103 has a floating gate tip 109 at the end facing the word line 107. If the height of the floating gate tip 109 is too large, it is prone to breakage. If the height of the floating gate tip 109 is too small, the end of the floating gate is too flat. Therefore, the height of the floating gate tip and the shape of the floating gate have a significant impact on programming and erasing efficiency, potentially reducing the efficiency of programming and erasing. Summary of the Invention
[0005] The purpose of this invention is to provide an embedded flash memory structure and manufacturing method that can improve the efficiency of programming and erasing.
[0006] To achieve the above objectives, the present invention provides a method for manufacturing an embedded flash memory structure, comprising:
[0007] A substrate is provided, on the surface of which a gate oxide layer, a floating gate material layer, a first nitride layer, a barrier oxide layer and a hard mask layer having a first opening are sequentially formed, wherein a portion of the surface of the barrier oxide layer is exposed in the first opening;
[0008] An ONO layer is formed within the first opening, the ONO layer covering the sidewall and inner wall of the first opening;
[0009] A portion of the ONO layer, the barrier oxide layer, and the first nitride layer are etched onto the bottom wall of the first opening. The remaining ONO layer forms the first sidewall, which covers the sidewall of the first opening and the surface of the portion of the barrier oxide layer.
[0010] Continue etching a portion of the floating gate material layer to expose the surface of the gate oxide layer;
[0011] A second sidewall is formed on the sidewall of the floating gate material. One end of the second sidewall is connected to the first sidewall, and the other end is connected to the gate oxide layer. A second opening is formed on the inner side of the first sidewall and the inner side of the second sidewall, and a source line polysilicon is formed in the second opening.
[0012] Remove the hard mask layer to expose the surface of the barrier oxide layer;
[0013] The blocking oxide layer, the first nitride layer and part of the floating grid material layer are removed, and the remaining floating grid material layer forms a floating grid with right angles. The floating grid is located below the first sidewall, and a third opening is also provided between the first sidewall and the floating grid.
[0014] A tunneling oxide layer is formed on the surface of the floating gate;
[0015] A word line is formed on the substrate surface outside the first sidewall, and the word line extends toward the source polysilicon to fill the third opening.
[0016] Optionally, in the manufacturing method of the embedded flash memory structure, an in-situ water vapor generation process is used to form a tunneling oxide layer on the surface of the floating gate.
[0017] Optionally, in the method for manufacturing the embedded flash memory structure, the method for forming the hard mask layer having the first opening includes:
[0018] A hard mask layer is formed on the surface of the floating grid material layer;
[0019] The hard mask layer is etched to form a hard mask layer with a first opening.
[0020] Optionally, in the manufacturing method of the embedded flash memory structure, an anisotropic etching method is used to etch and remove the barrier oxide layer, the first nitride layer, and part of the floating gate material layer.
[0021] Optionally, in the manufacturing method of the embedded flash memory structure, the ONO layer includes a bottom oxide layer, a second nitride layer and a top oxide layer stacked sequentially from bottom to top.
[0022] Optionally, in the manufacturing method of the embedded flash memory structure, the thickness of both the bottom oxide layer and the top oxide layer is 200 angstroms to 300 angstroms.
[0023] Optionally, in the manufacturing method of the embedded flash memory structure, the thickness of the second nitride layer is 2500 angstroms to 2700 angstroms.
[0024] Optionally, in the method for manufacturing the embedded flash memory structure, the hard mask layer comprises silicon nitride.
[0025] Optionally, in the manufacturing method of the embedded flash memory structure, the floating gate material layer, the source line polysilicon, and the word line all include polysilicon material.
[0026] The present invention also provides an embedded flash memory structure, comprising:
[0027] Substrate;
[0028] A gate oxide layer, a floating gate, a tunneling oxide layer, and a first sidewall are sequentially located on the surface of the substrate, wherein the first sidewall is an ONO layer;
[0029] The source polysilicon, word line, and second sidewall are located on the surface of the gate oxide layer;
[0030] The source polysilicon is located inside the first sidewall and the second sidewall;
[0031] The floating gate is located below the first side wall, and a third opening is formed between the floating gate and the third opening;
[0032] The tunneling oxide layer is located on the surface of the floating gate;
[0033] The word line is located outside the first sidewall and outside the second sidewall. The word line extends toward the source polysilicon and fills the third opening. The word line is isolated from the floating gate through the tunneling oxide layer. The word line is isolated from the word line polysilicon through the first sidewall and the second sidewall.
[0034] In the embedded flash memory structure and manufacturing method provided by this invention, a right-angled floating gate is formed. During erasure, the floating gate tip will not break due to being too high, thus reducing the probability of erasure failure and improving erasure efficiency. During programming, since the source polysilicon and word line are separated by the second sidewall, a coupling voltage is formed between the source polysilicon and word line, increasing the turn-on voltage of the source polysilicon and reducing the difficulty of channel turn-on, thus further improving programming efficiency. Attached Figure Description
[0035] Figure 1 is a schematic diagram of the embedded flash memory structure in the prior art;
[0036] Figure 2 is a flowchart of a method for manufacturing an embedded flash memory structure according to an embodiment of the present invention;
[0037] Figures 3 to 9 are schematic diagrams of the formation process of the embedded flash memory structure according to an embodiment of the present invention;
[0038] In the diagram: 101-substrate, 102-gate oxide layer, 103-floating gate, 104-floating gate sidewall, 105-source polysilicon, 106-source sidewall, 107-word line, 108-tunneling oxide layer, 109-floating gate tip, 201-substrate, 202-gate oxide layer, 203-floating gate material layer, 204-first nitride layer, 205-barrier oxide layer, 206-hard mask layer, 207-first opening, 208-first sidewall, 209-second sidewall, 210-second opening, 211-source polysilicon, 212-floating gate, 213-third opening, 214-tunneling oxide layer, 215-word line. Detailed Implementation
[0039] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0040] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0041] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.
[0042] Referring to Figure 2, this invention provides a method for manufacturing an embedded flash memory structure, including:
[0043] S11: Provide a substrate, and sequentially form a gate oxide layer, a floating gate material layer, a first nitride layer, a barrier oxide layer and a hard mask layer with a first opening on the surface of the substrate, wherein a portion of the surface of the barrier oxide layer is exposed in the first opening.
[0044] S12: An ONO layer is formed inside the first opening, and the ONO layer covers the sidewall and inner wall of the first opening;
[0045] S13: Etch part of the ONO layer, the barrier oxide layer and the first nitride layer on the bottom wall of the first opening. The remaining ONO layer forms the first sidewall, which covers the sidewall of the first opening and the surface of part of the barrier oxide layer.
[0046] S14: Continue etching part of the floating gate material layer to expose the surface of the gate oxide layer;
[0047] S15: A second sidewall is formed on the sidewall of the floating gate material. One end of the second sidewall is connected to the first sidewall, and the other end is connected to the gate oxide layer. A second opening is formed on the inner side of the first sidewall and the inner side of the second sidewall, and a source line polysilicon is formed in the second opening.
[0048] S16: Remove the hard mask layer to expose the surface that blocks the oxide layer;
[0049] S17: Remove the blocking oxide layer, the first nitride layer and part of the floating gate material layer. The remaining floating gate material layer forms a floating gate with right angles. The floating gate is located below the first sidewall. There is also a third opening between the first sidewall and the floating gate.
[0050] S18: Form a tunneling oxide layer on the surface of the floating gate;
[0051] S19: A word line is formed on the substrate surface outside the first sidewall, and the word line extends toward the source polysilicon to fill the third opening.
[0052] Specifically, referring to Figures 3 and 4, a substrate 201 is preferably provided, which can be a wafer. A gate oxide layer 202, a floating gate material layer 203, a first nitride layer 204, a barrier oxide layer 205, and a hard mask layer 206 are sequentially formed on the surface of the substrate 201. The thickness of the first nitride layer 204 can be 250 angstroms to 350 angstroms, for example, 300 angstroms. The thickness of the barrier oxide layer 205 can be 80 angstroms to 100 angstroms, for example, 90 angstroms. A portion of the hard mask layer 206 is etched to form a first opening 207, exposing a portion of the surface of the barrier oxide layer 205 within the first opening 207. The sidewalls of the first opening 207 are perpendicular to the bottom wall.
[0053] Referring to Figure 5, an ONO layer is formed on the inner wall of the first opening 207 and the surface of the hard mask layer 206. The ONO layer follows the shape of the inner wall of the first opening 207, and the ONO layer covering the sidewall of the first opening 207 is perpendicular to the ONO layer covering the bottom wall of the first opening 207. The ONO layer includes a bottom oxide layer, a second nitride layer, and a top oxide layer covering the hard mask layer 206. The thickness of the bottom oxide layer is 200 angstroms to 300 angstroms, the thickness of the second nitride layer is 2500 angstroms to 2700 angstroms, and the thickness of the top oxide layer is 200 angstroms to 300 angstroms. The bottom oxide layer and the top oxide layer are formed by low-pressure tetraethyl orthosilicate deposition (LPTEOS DEP). The ONO layer 206 on the surface of the barrier oxide layer 205 on the bottom wall of the first opening 207, as well as the barrier oxide layer 205 and the first nitride layer 204 on the bottom wall of the first opening 206, are etched to expose the surface of the floating gate material layer 203. The remaining ONO layer 206 becomes the first sidewall 208. The bottom oxide layer follows the shape of the hard mask layer 206 in an L-shape. The second nitride layer is in a sloping shape. The top oxide layer covers the surface of the second nitride layer, with one end connected to the top of the bottom oxide layer and the other end connected to the bottom of the bottom oxide layer.
[0054] Next, referring to Figure 6, continue etching downwards the floating gate material layer 203. A second sidewall 209 is formed on the sidewall of the floating gate material layer 203, and a second opening 210 is formed inside the first sidewall 208 and the second sidewall 209. The second sidewall 209 is formed by depositing a second nitride layer material and etching the second nitride layer material.
[0055] Next, referring to Figure 7, fill the second opening 210 with polysilicon material and grind the polysilicon material to form the source line polysilicon 211. Then, remove the hard mask layer 206. At this time, the barrier oxide layer 205 can serve as a stop layer.
[0056] Next, referring to Figure 8, an anisotropic self-aligned etching barrier oxide layer 205, a first nitride layer 204, and a portion of the floating gate material layer 203 are etched to suspend the first sidewall 208. The remaining floating gate material layer 203 located below the first sidewall 208 forms a right-angled floating gate 212, thus forming a third opening 213 between the first sidewall 208 and the floating gate 212. When etching the portion of the floating gate material layer 203 to form the floating gate 212, the first nitride layer 204 on the surface of the floating gate material layer 203 improves the stability during self-aligned etching. A tunneling oxide layer 214 is formed on the surface of the floating gate 212. In this embodiment of the invention, the tunneling oxide layer 214 is formed using an in-situ steam generation (ISSG) process. Therefore, the oxide of the formed tunneling oxide layer 214 is denser, the interface uniformity is higher, and the isolation is improved, thereby improving reliability.
[0057] Next, referring to Figure 9, polysilicon material is deposited on the outer side of the first sidewall 208 to form word lines 215, which fill the third opening 213. The first sidewall 208 is an ONO layer, improving the reliability of the connection between the word lines 215 and the first sidewall 208. Furthermore, the word lines 215 are located within the third opening 213, forming a right-angle contact between the word lines and the floating gate, preventing breakage due to excessively high floating gate tips, reducing the probability of erase failure, and thus improving programming efficiency. During programming, since the word lines extend towards the source polysilicon, and are separated from the word lines by the second sidewall, a coupling voltage is formed between the source polysilicon and the word lines, increasing the turn-on voltage of the source polysilicon, reducing the difficulty of channel turn-on, and improving programming efficiency.
[0058] Finally, a third sidewall is formed outside word line 215; this third sidewall is the ONO layer. Then, the source and drain regions are formed using conventional techniques, which will not be elaborated upon here.
[0059] Accordingly, the present invention also provides an embedded flash memory structure, comprising: a substrate; a gate oxide layer, a floating gate, a tunneling oxide layer, and a first sidewall sequentially located on the surface of the substrate, the first sidewall being an ONO layer; a source line polysilicon, a word line, and a second sidewall located on the surface of the gate oxide layer; the source line polysilicon being located inside the first sidewall and the second sidewall; the floating gate being located below the first sidewall and forming a third opening between it and the floating gate; the tunneling oxide layer being located on the surface of the floating gate; the word line being located outside the first sidewall and outside the second sidewall, the word line extending toward the source line polysilicon and filling the third opening, the word line being isolated from the floating gate by the tunneling oxide layer, and the word line being isolated from the word line polysilicon by the first sidewall and the second sidewall.
[0060] In summary, the embedded flash memory structure and manufacturing method provided in this invention form a right-angled floating gate. During erasure, the floating gate tip will not break due to being too high, thus reducing the probability of erasure failure and improving erasure efficiency. During programming, since the source polysilicon and word line are separated by the second sidewall, a coupling voltage is formed between the source polysilicon and word line, increasing the turn-on voltage of the source polysilicon and reducing the difficulty of channel turn-on, thus further improving programming efficiency.
[0061] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for manufacturing an embedded flash memory structure, characterized in that, include: A substrate is provided, on the surface of which a gate oxide layer, a floating gate material layer, a first nitride layer, a barrier oxide layer and a hard mask layer having a first opening are sequentially formed, wherein a portion of the surface of the barrier oxide layer is exposed within the first opening; an ONO layer is formed within the first opening, wherein the ONO layer covers the sidewall and inner wall of the first opening; A portion of the ONO layer, the barrier oxide layer, and the first nitride layer are etched onto the bottom wall of the first opening. The remaining ONO layer forms the first sidewall, which covers the sidewall of the first opening and the surface of the portion of the barrier oxide layer. Continue etching a portion of the floating gate material layer to expose the surface of the gate oxide layer; A second sidewall is formed on the sidewall of the floating gate material. One end of the second sidewall is connected to the first sidewall, and the other end is connected to the gate oxide layer. A second opening is formed on the inner side of the first sidewall and the inner side of the second sidewall, and a source line polysilicon is formed in the second opening. Remove the hard mask layer to expose the surface of the barrier oxide layer; The blocking oxide layer, the first nitride layer, and part of the floating grid material layer are removed, and the remaining floating grid material layer forms a floating grid with right angles. The floating grid is located below the first sidewall, and a third opening is also provided between the first sidewall and the floating grid. A tunneling oxide layer is formed on the surface of the floating grid. A word line is formed on the substrate surface outside the first sidewall, and the word line extends toward the source polysilicon to fill the third opening.
2. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, An in-situ water vapor generation process is used to form a tunneling oxide layer on the surface of the floating grid.
3. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, A method for forming a hard mask layer having a first opening includes: forming a hard mask layer on the surface of the floating gate material layer; and etching a portion of the hard mask layer to form a hard mask layer having a first opening.
4. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, An anisotropic etching method is used to etch and remove the barrier oxide layer, the first nitride layer, and part of the floating gate material layer.
5. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, The ONO layer comprises a bottom oxide layer, a second nitride layer, and a top oxide layer stacked sequentially from bottom to top.
6. The method for manufacturing the embedded flash memory structure as described in claim 5, characterized in that, The thickness of both the bottom oxide layer and the top oxide layer is 200 angstroms to 300 angstroms.
7. The method for manufacturing the embedded flash memory structure as described in claim 5, characterized in that, The thickness of the second nitrided layer is 2500 angstroms to 2700 angstroms.
8. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, The hard mask layer comprises silicon nitride.
9. The method for manufacturing the embedded flash memory structure as described in claim 1, characterized in that, The floating gate material layer, source polysilicon, and word line all include polysilicon material.
10. An embedded flash memory structure formed using the manufacturing method of the embedded flash memory structure according to any one of claims 1 to 9, characterized in that, include: Substrate; The substrate comprises, in sequence, a gate oxide layer, a floating gate, a tunneling oxide layer, and a first sidewall, wherein the first sidewall is an ONO layer; a source polysilicon layer, a word line, and a second sidewall located on the surface of the gate oxide layer; the source polysilicon layer being located inside the first and second sidewalls; the floating gate being located below the first sidewall and forming a third opening between it and the floating gate; the tunneling oxide layer being located on the surface of the floating gate; the word line being located outside the first and second sidewalls, extending towards the source polysilicon layer and filling the third opening; the word line being isolated from the floating gate by the tunneling oxide layer; and the word line being isolated from the word line polysilicon by the first and second sidewalls.