Semiconductor structure

Abstract

The invention discloses a semiconductor structure. The semiconductor structure comprises a substrate; an electronic device disposed on the substrate, wherein the electronic device includes a first gate structure; and an interconnect structure including a first interconnect layer conductive trace directly over the electronic device, where the first interconnect layer conductive trace has a first opening for exposing at least one of the first gate structures. In this manner, during manufacturing, light can be irradiated from above the semiconductor structure, and the light can pass through the first opening to irradiate or diffract to the first gate structure of the electronic device, thereby eliminating excess charge in the gate oxide of the first gate structure. In this way, redundant charges can be removed with high efficiency and low cost, increase of the plane area of the semiconductor structure is avoided, and large-scale production and manufacturing and miniaturization design of the semiconductor structure are facilitated.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to the layout of conductive traces in the interconnect layer of a semiconductor structure. Background Technology

[0002] During the manufacturing of semiconductor devices such as transistors and memory, unwanted charges may become trapped in the gate oxide layer. These trapped charges can negatively impact the transistor's threshold voltage, the memory's programming and erasing thresholds, the transistor's switching speed, and the memory's programming and erasing speed.

[0003] Therefore, a novel semiconductor structure is needed. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor structure that effectively eliminates excess charge in the gate oxide of the transistor caused by the manufacturing process, and can avoid increasing the planar area of ​​the semiconductor structure.

[0005] One embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a substrate, an electronic device, and an interconnect structure. The electronic device is disposed on the substrate. The electronic device includes a first gate structure. The interconnect structure includes a first interconnect layer conductive trace located directly above the electronic device. The first interconnect layer conductive trace has a first opening for exposing at least one of the first gate structures.

[0006] Furthermore, in the first direction, the first interval between two adjacent first openings satisfies equation (1):

[0007] Equation (1) is S1=mλ(D1 / A1).

[0008] Where S1 is the first interval between two adjacent first openings.

[0009] D1 is the first distance between the first interconnect layer conductive trace and the electronic device in the second direction.

[0010] A1 is the first dimension of the first opening in the first direction.

[0011] λ is the wavelength of light, and m is greater than 1 and less than 3. This controls the light to pass smoothly through the conductive traces of the first interconnect layer and illuminate or diffract onto the gate structure.

[0012] Furthermore, A1 is greater than or equal to λ. This allows light to pass smoothly through the conductive traces of the first interconnect layer and illuminate or diffract onto the gate structure.

[0013] Furthermore, the first interconnect layer conductive trace is the topmost interconnect layer conductive trace. As the topmost interconnect layer conductive trace, it is generally the widest trace layer in the interconnect structure (or the widest interconnect layer in the interconnect structure), and it blocks light the most. Therefore, an opening can generally be provided in the first interconnect layer conductive trace to allow light to pass through. The line widths of other trace layers (interconnect layers) below in the interconnect structure are generally smaller (smaller than the line width of the first interconnect layer conductive trace). Therefore, openings are not required in these other trace layers (interconnect layers), which simplifies manufacturing and eliminates the need for complex manufacturing processes. Of course, if necessary, openings can be provided in one or more of the other trace layers (interconnect layers) below.

[0014] Furthermore, the electronic device is located within the projection range of the outer edge of the conductive trace of the first interconnect layer on the top surface of the substrate. This allows the gate structure within the electronic device to be illuminated or diffracted by light as much as possible.

[0015] Furthermore, in the first direction, the electronic device is arranged with a unit spacing, and the ratio of the first spacing to the unit spacing is between 1 and 2. This allows the gate structure within the electronic device to be illuminated or diffracted by light as much as possible.

[0016] Furthermore, in the first direction, the electronic device is arranged with a unit pitch, the first opening is arranged with a first interval, and the ratio of the first interval to the unit pitch is between 1 and 2. This allows the gate structure within the electronic device to be illuminated or diffracted by light as much as possible.

[0017] Furthermore, the first gate structure has a second dimension along a first direction, and the first dimension is greater than or equal to the second dimension. This allows the gate structure within the electronic device to be illuminated or diffracted by light as much as possible.

[0018] Furthermore, each of these electronic devices includes:

[0019] A floating gate transistor disposed on a first well region in the substrate, wherein the floating gate transistor includes: one of the first gate structures; and a first source / drain doped region and a second source / drain doped region disposed on the first well region and located on both sides of the first gate structure;

[0020] A selection transistor is disposed on the first well region, wherein the selection transistor includes: a second gate structure located next to the first gate structure of the floating gate transistor; and a third source / drain doped region and the first source / drain doped region disposed on the first well region and located on both sides of the second gate structure. This allows for the configuration of transistors with different functions or types to meet design requirements.

[0021] Furthermore, at least one of the second gate structures of the electronic device is exposed from the first opening. This allows the gate structure within the electronic device to be illuminated or diffracted by light as much as possible.

[0022] Furthermore, the first opening extends along the extension direction of the corresponding first gate structure.

[0023] Furthermore, the first openings are arranged in rows along the extension direction of the corresponding first gate structure. This allows the gate structure within the electronic device to be illuminated or diffracted by light as much as possible.

[0024] Furthermore, the first openings in the adjacent rows are alternately arranged along the extension direction of the corresponding first gate structure.

[0025] Furthermore, the first openings in the adjacent rows are aligned with each other along the first direction. This controls the smooth passage of light through the conductive traces of the interconnect layer, illuminating or diffracting it onto the gate structure.

[0026] Furthermore, in the top view, the first opening and the first gate structure exposed from the corresponding first opening have a one-to-many or one-to-one relationship. This allows the gate structure within the electronic device to be illuminated or diffracted by light as much as possible.

[0027] Furthermore, the first opening can be strip-shaped, square, circular, elliptical, or polygonal to meet different design and manufacturing requirements.

[0028] Furthermore, the interconnect structure further includes:

[0029] A second interconnect layer conductive trace overlaps the first interconnect layer conductive trace, wherein the second interconnect layer conductive trace has a second opening aligned with the corresponding first opening in the second direction. This controls the smooth passage of light through the interconnect layer conductive trace to illuminate or diffract onto the gate structure.

[0030] Furthermore, in the first direction, the second interval between two adjacent second openings satisfies equation (2):

[0031] Equation (2) is S2=pλ(D2 / A2).

[0032] Where S2 is the second interval between two adjacent second openings.

[0033] D2 represents the second distance between the conductive trace of the second interconnect layer and the electronic device in the second direction.

[0034] A2 is the third dimension of the second opening in the first direction.

[0035] λ is the wavelength of light, and p is greater than 1 and less than 3. This controls how light can pass smoothly through the conductive traces of the interconnect layer and illuminate or diffract onto the gate structure.

[0036] Furthermore, the second interconnect layer conductive trace is located directly above or directly below the first interconnect layer conductive trace.

[0037] The semiconductor structure of this invention includes a substrate, an electronic device, and an interconnect structure. The electronic device is disposed on the substrate. The electronic device includes a first gate structure. The interconnect structure includes a first interconnect layer conductive trace located directly above the electronic device. The first interconnect layer conductive trace has a first opening for exposing at least one of the first gate structures. In this way, during manufacturing, light can be irradiated from above the semiconductor structure, passing through the first opening to irradiate or diffract onto the first gate structure of the electronic device, thereby eliminating excess charge in the gate oxide of the first gate structure. This allows for highly efficient and low-cost removal of excess charge, avoids increasing the planar area of ​​the semiconductor structure, and is beneficial for large-scale manufacturing and miniaturized semiconductor structure design. Attached Figure Description

[0038] Figure 1 This is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention;

[0039] Figure 2 This is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention;

[0040] Figure 3 According to some embodiments of the present invention Figure 1 or Figure 2 A schematic top view of a semiconductor structure, showing the arrangement of openings in the interconnect layer conductive traces within the interconnect structure, and the relative positions of these openings to the gate electrode of the electronic device; and

[0041] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 According to some embodiments of the present invention Figure 1 or Figure 2 A schematic top view of the interconnect layer conductive traces in a semiconductor structure, showing various shapes of the openings of the interconnect layer conductive traces in the interconnect structure. Detailed Implementation

[0042] In the following detailed description of one embodiment of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the invention is defined only by the appended claims. The described drawings are illustrative only and not limiting. In the drawings, for illustrative purposes, the dimensions of some elements may be enlarged rather than drawn to scale. In practice of the invention, dimensions and relative dimensions do not correspond to actual dimensions.

[0043] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one component, part, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary component, part, region, layer, or portion discussed below may be referred to as a second or secondary component, part, region, layer, or portion.

[0044] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of a component or feature to it. Another component or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0045] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” “the,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0046] What will be understood is that when a “component” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another component or layer, it can be directly on, connected to, coupled to, or adjacent to the other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another component or layer, there are no intermediate components or layers.

[0047] Note: (i) the same features will be indicated by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0048] The following description is for illustrative purposes only and should not be construed as limiting. The scope of the invention is best determined by referring to the appended claims.

[0049] To remove unwanted charges trapped in (or captured by) the gate oxide layer of a semiconductor device, transistors and memory are typically irradiated with ultraviolet light after semiconductor device fabrication. However, the metal wiring conventionally located above semiconductor devices with gate oxide (GOX) sensitive regions needs to be rearranged to avoid blocking ultraviolet light. This rearrangement can lead to an increase in semiconductor device area, hindering miniaturization.

[0050] Figure 1 This is a schematic cross-sectional view of a semiconductor structure 500A according to some embodiments of the present invention. Figure 3 According to some embodiments of the present invention, Figure 1 A schematic top view of the semiconductor structure 500A shows the arrangement of the openings 250 of the first interconnect layer conductive trace Mtop in the interconnect structure 260 and the relative positions of the openings 250 of the first interconnect layer conductive trace Mtop and the gate structure 210-1 of the electronic device 220. Figure 3 Only some features are shown for illustrative purposes; the remaining features may be shown in [the diagram]. Figure 1 In the cross-sectional view. Figure 1 In the following figures, direction 100 can be referred to as the channel length direction, direction 110 as the channel width direction, and direction 120 as the device height direction. Directions 100 and 110 are approximately parallel to the top surface 200T of the substrate 200 of the semiconductor structure 500A. Direction 120 is approximately perpendicular to the top surface 200T of the substrate 200.

[0051] In some embodiments, the semiconductor structure 500A is applied to a logic device, memory device, or other suitable active or passive device. In such cases... Figure 1 In some of the embodiments shown, the semiconductor structure 500A is applied to a memory device, such as a one-time programmable (OTP) memory device. In some embodiments, the semiconductor structure 500A includes a substrate 200, an electronic device 220, and an interconnect structure 260.

[0052] like Figure 1 As shown, substrate 200 has an active region 300 surrounded by isolation features 204. In some embodiments, substrate 200 includes a semiconductor wafer or a silicon-on-insulator (SOI) wafer. Substrate 200 may be doped with p-type or n-type dopants according to predetermined design rules.

[0053] The semiconductor structure 500A may further include a well region 206 formed within an active region 300 in the substrate 200. In some embodiments, the well region 206 may be doped with a dopant having a first conductivity type. In some embodiments, wherein the semiconductor structure 500A includes an OTP memory device based on the P-type oxide-semiconductor field effect (PMOS), the well region 206 is, for example, an N-type well region.

[0054] Electronic device 220 is disposed on the active region 300 of substrate 200. For example... Figure 1 As shown, two adjacent electronic devices 220 form a unit cell with mirror symmetry. The unit cells of electronic devices 220 can be arranged in an array along directions 100 and 110. Furthermore, the unit cells of electronic devices 220 can be arranged along direction 100 with a cell pitch P1.

[0055] In some embodiments, the electronic device 220 includes an one-time programmable (OTP) memory device, and the electronic device 220 includes a floating gate transistor 220T1 and a select transistor 220T2 connected in series (or otherwise connected) in the same active region 300.

[0056] like Figure 1 In some embodiments shown, a floating gate transistor 220T1 is disposed on a well region 206. The floating gate transistor 220T1 includes a gate structure 210-1, source / drain doped regions 208DS and 208D. The gate structure 210-1 is disposed within an active region 300 on a substrate 200 and extends along direction 110. Direction 110 can be the extension direction of the gate structure 210-1. In some embodiments, the gate structure 210-1 includes a gate insulating layer (not shown) and a gate electrode layer (not shown). The gate insulating layer is formed on the substrate 200. The gate electrode layer is formed on the gate insulating layer. Furthermore, gate spacers (not shown) are formed on opposite sides of the gate electrode layer. Since the erase and programming performance of the OTP memory is sensitive to the trapped charge in the gate insulating layer of the gate structure 210-1, the gate structure 210-1 is located within a gate oxide (GOX) sensitive region.

[0057] Source / drain doped regions 208DS and 208D are located within the same active region 300 in substrate 200. Source / drain doped regions 208DS and 208D are disposed on well region 206 and along direction 100 on opposite sides of gate structure 210-1. In some embodiments, source / drain doped regions 208DS and 208D can be doped with a dopant of a second conductivity type opposite to the first conductivity type. For example, when well region 206 is N-type, source / drain doped regions 208DS and 208D are P-type.

[0058] Selector transistor 220T2 is disposed on well region 206, including gate structure 210-2, source / drain doped regions 208S and 208DS. Gate structure 210-2 is disposed within active region 300 on substrate 200. Furthermore, gate structure 210-2 is located adjacent to first gate structure 210-1 of floating gate transistor 220T1 along direction 100. In some embodiments, gate structures 210-1 and 210-2 may have the same or similar structures and be formed in the same process.

[0059] Source / drain doped regions 208S and 208DS are located within the same active region 300 in substrate 200. Source / drain doped regions 208S and 208DS are disposed on well region 206 and are located opposite gate structure 210-2 along direction 100. Furthermore, the source / drain doped region 208DS of floating gate transistor 220T1 collectively serves as the source / drain doped region of select transistor 220T2, which is opposite to source / drain doped region 208S. In some embodiments, source / drain doped region 208S can be doped with a dopant of a second conductivity type opposite to the first conductivity type. For example, when well region 206 is N-type, source / drain doped region 208S is P-type.

[0060] Interconnect structure 260 is formed on substrate 200. Furthermore, interconnect structure 260 covers electronic device 220. Interconnect structure 260 is configured to be electrically connected to various terminals of electronic device 220. In some embodiments, interconnect structure 260 includes dielectric layer structure 230, interconnect layers or interconnect layer conductive traces (including a first interconnect layer conductive trace Mtop), and conductive vias (not shown). In some embodiments, each interconnect layer conductive trace (interconnect layer) may include one or more conductive traces. For example, the topmost conductive trace may include the first interconnect layer conductive trace Mtop and other conductive traces. The first interconnect layer conductive trace Mtop may be the widest conductive trace in interconnect structure 260, or the first interconnect layer conductive trace Mtop may be located in the interconnect layer with the widest conductive trace (i.e., the topmost layer). Adjacent interconnect layers in interconnect structure 260 may be spaced apart by portions of dielectric layer structure 230, and adjacent interconnect layers may be electrically connected vias (electroplated or metallized) through-holes, etc.

[0061] The dielectric layer structure 230 is vertically stacked on the substrate 200 and the electronic device 220. The dielectric layer structure 230 can be a single-layer structure or a multi-layer structure. In some embodiments, the dielectric layer structure 230 includes silicon dioxide, silicon oxynitride, undoped silicate glass (USG), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), carbon-doped oxide, porous carbon-doped silicon dioxide, polymers such as polyimide or silicon oxycarbide polymer (SiOC), or combinations thereof. In some embodiments, the dielectric layer structure 230 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0062] Interconnect layer conductive traces may be formed laterally (e.g., along direction 100) in the dielectric layer structure 230. In some embodiments, the interconnect layer conductive traces may include the bottommost interconnect layer conductive trace to the topmost interconnect layer conductive trace. In this embodiment, the first interconnect layer conductive trace Mtop is the topmost interconnect layer conductive trace; the first interconnect layer conductive trace Mtop may belong to the topmost interconnect layer in the interconnect structure.

[0063] Conductive vias (not shown) are formed vertically (e.g., along direction 120) in the dielectric layer structure 230 and connect the first interconnect layer conductive trace Mtop to an adjacent interconnect layer conductive trace (not shown). In some embodiments, the interconnect layer conductive traces and conductive vias comprise conductive materials such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or alloys thereof.

[0064] According to design rules, the first interconnect layer conductive trace Mtop, such as the topmost interconnect layer conductive trace, can have a larger trace width than the conductive traces of the lower interconnect layers. For example... Figure 1 and Figure 3As shown, the first interconnect layer conductive trace Mtop can be located directly above and cover the electronic device 220. It is understood that other materials, such as dielectric layers, conductive trace layers, etc., can exist between the first interconnect layer conductive trace Mtop and the electronic device 220. The electronic device 220 can be located within the projection range of the outer edge E1 of the topmost interconnect layer conductive trace on the top surface 200T of the substrate 200. In some embodiments, the first interconnect layer conductive trace Mtop has a dimension L1 in direction 100. In some embodiments, the dimension L1 is greater than 10 μm. In some embodiments, the ratio of dimension L1 to cell spacing P1 is greater than or equal to 3 (i.e., L1 / P1 ≥ 3).

[0065] In some embodiments, the first interconnect layer conductive trace Mtop has an opening 250 extending through the first interconnect layer conductive trace Mtop. The opening 250 allows light 400 to penetrate and illuminate the electronic device 220. The openings 250 are periodically arranged along directions 100 and 110 to exposed portions of the electronic device 220, particularly to gate electrodes located in the gate oxide (GOX) charge sensitive region. For example, at least some gate structures 210-1 of the floating gate transistor 220T1 may be exposed through the opening 250. Other gate structures 210-1 may be located between the exposed gate structures 210-1 and 210-2 and completely covered by the first interconnect layer conductive trace Mtop. Furthermore, gate electrodes not located in the gate oxide (GOX) charge sensitive region may be exposed through the opening 250. For example, some gate structures 210-2 of the selective transistor 220T2 may be exposed through the opening 250. Other gate structures 210-2 may be located between the exposed gate structures 210-1 and 210-2 and covered by the first interconnect layer conductive trace Mtop.

[0066] In some embodiments, in direction 100, the space S1 between two adjacent openings 250 (or the minimum space S1 between the opening 250 and the outer edge E1 of the first interconnect layer conductive trace Mtop) can satisfy equation (1):

[0067] Equation (1) is S1=mλ(D1 / A1).

[0068] Where S1 is the interval between two adjacent openings 250 (or the minimum interval between opening 250 and the outer edge E1 of the first interconnect layer conductive trace Mtop), D1 is the distance between the first interconnect layer conductive trace Mtop and the electronic device 220 in direction 120, A1 is the dimension of opening 250 in direction 100 (or the interval between two adjacent topmost interconnect layer conductive traces Mtop), λ is the wavelength of light 400, and m is greater than 1 and less than 3 (i.e., 1 <m<3)。

[0069] In some embodiments, D1 is the distance in direction 120 between the first interconnect layer conductive trace Mtop and the floating gate transistor 220T1 in the electronic device 220. Furthermore, the distance D1 between the first interconnect layer conductive trace Mtop and the floating gate transistor 220T1 in direction 120 is much larger than the dimension A1 of the opening 250. In some embodiments, the light 400 is ultraviolet (UV) light. In other words, the wavelength λ of the light 400 can be between 10 nm and 400 nm. In some embodiments, the dimension A1 of the opening 250 is proportional to the dimension L2 of the gate structure 210-1 of the floating gate transistor 220T1 in direction 100. In some embodiments, the dimension A1 of the opening 250 is greater than or equal to the dimension L2 of the gate structure 210-1 of the floating gate transistor 220T1. Furthermore, the dimension A1 of the opening 250 is greater than or equal to the wavelength λ of the light 400. For example, when the light 400 is ultraviolet (UV) light, the size A1 of the opening 250 can be between 0.1 μm and 5 μm. Therefore, the light 400 can pass directly through the opening 250 or form a diffraction pattern.

[0070] In some embodiments, when m is greater than 1 and less than 3, the density of the openings 250 is sufficient to maintain a low barrier to the first interconnect layer conductive trace Mtop, thereby preventing electromigration (EM). Furthermore, this range allows sufficient light 400 to penetrate the first interconnect layer conductive trace Mtop and illuminate the electronic device 220, thereby supporting light transmission capability (e.g., UV erasure capability).

[0071] When the size A1 of the opening 250 is approximately equal to (comparable to) the wavelength λ of the light ray 400, the light ray 400 passing through the opening 250 forms a diffraction pattern. In some embodiments, the interval S1 between two adjacent openings 250 (or the minimum interval S1 between the opening 250 and the outer edge E1 of the first interconnect layer conductive trace Mtop) may be located in direction 100 directly above the dark fringe position in the diffraction pattern (e.g., the second dark fringe position when m equals 2). The openings 250 of the first interconnect layer conductive trace Mtop may be arranged at intervals S1 to ensure that all floating gate transistors 220T1 of the electronic device 220 are exposed to the incident light ray 400 or the diffraction of the light ray 400.

[0072] In some embodiments, the openings 250 are arranged along direction 100 at a spacing P2. The spacing P2 of the openings 250 is slightly larger than the interval S1 between two adjacent openings 250. In some embodiments, the ratio of the spacing P2 (or interval S1) to the unit spacing P1 is between 1 and 2 (i.e., 1 ≤ P2 / P1 (or S1 / P1 ≤ 2)). When the ratio of the spacing P2 (or interval S1) to the unit spacing P1 is between 1 and 2, this arrangement helps ensure that the electronic device 220 is not located at a dark fringe position in the diffraction pattern of the light 400 passing through the respective openings 250. This configuration supports effective light transmission capability (e.g., UV erasing capability).

[0073] Figure 2 This is a schematic cross-sectional view of a semiconductor structure 500B according to some embodiments of the present invention. Figure 3 Also according to some embodiments of the present invention Figure 2 A schematic top view of the semiconductor structure 500B shows the arrangement of the openings 240 of the conductive traces Mn in the second interconnect layer in the interconnect structure 260 and the relative positions of the openings 240 and the gate structure 210-1 of the electronic device 220. Figure 3 Only some features are shown for illustration purposes; the remaining features can be displayed in the main text. Figure 1 The cross-sectional view. Elements in subsequent embodiments, as in the previous reference. Figure 1Identical or similar elements will not be repeated for brevity. In this embodiment, the second interconnect layer conductive trace Mn includes any layer from the first interconnect layer conductive trace (M1) (or the base interconnect layer conductive trace (M1)), the second interconnect layer conductive trace (M2), to the layer below the topmost interconnect layer conductive trace (Mtop). In some embodiments, the interconnect structure 260 includes multiple trace layers (or interconnect layers), such as the first interconnect layer conductive trace Mtop, the first interconnect layer conductive trace (M1) closest to the electronic device 220, and other trace layers (or interconnect layers) located between the first interconnect layer conductive trace Mtop and the first interconnect layer conductive trace (M1). In some embodiments, multiple openings (e.g., opening 250) are provided only in the first interconnect layer conductive trace Mtop (as the topmost trace layer (or interconnect layer)). This allows light 400 to pass smoothly through the relatively wide first interconnect layer conductive trace Mtop and reach the gate structure 210-1. In this embodiment, the first interconnect layer conductive trace Mtop (the layer containing the topmost trace layer (or interconnect layer)) can be the trace layer (or interconnect layer) with the widest trace width among all trace layers in the interconnect structure 260. In this embodiment, the first interconnect layer conductive trace (M1) and other trace layers (other trace layers besides the first interconnect layer conductive trace Mtop) may not necessarily have such openings (e.g., opening 250 or similar openings). In some embodiments, in addition to providing multiple openings on the first interconnect layer conductive trace Mtop, these openings may also be provided on the first interconnect layer conductive trace (M1) and / or other trace layers (e.g., when the traces of the first interconnect layer conductive trace (M1) and / or other trace layers (or interconnect layers) are relatively wide), thereby allowing light 400 to smoothly reach the gate structure 210-1. Therefore, in some embodiments, an opening may be provided at least on the first interconnect layer conductive trace Mtop of the interconnect structure 260. Of course, openings may also be provided in traces of other different layers as needed. That is, an opening (e.g., opening 250) can be provided in the topmost trace layer (interconnect layer) of the interconnect structure 260, and additional openings can also be provided in other trace layers (interconnect layers) of the interconnect structure 260; these can be provided as needed. Of course, in one embodiment of the present invention, at least an opening (e.g., opening 250) is provided in the topmost trace layer (interconnect layer) of the interconnect structure 260. In some embodiments, since the trace with the opening is located directly above the gate structure 210-1, it is not necessary to offset (or stagger) the trace with respect to the gate structure 210-1, thereby avoiding increasing the area occupied by the semiconductor structure and reducing the complexity of wiring. In addition, in this embodiment, after the interconnect structure 260 is formed, it can be irradiated with light 400 to eliminate excess charge in the gate oxide, thereby facilitating manufacturing and simplifying the manufacturing process.In some embodiments, the trace layer with an opening (e.g., the topmost trace layer) is located directly above the gate structure 210-1, meaning that light can be irradiated and / or diffracted onto the gate structure 210-1 below through the opening, thereby eliminating excess charge. This eliminates the need for biasing the trace layer and the gate structure 210-1, saving area and facilitating miniaturization of the semiconductor structure. The phrase "directly above" in "the trace layer with an opening (e.g., the topmost trace layer) is located directly above the gate structure 210-1" can mean that when the trace layer with the opening (e.g., the topmost trace layer) is projected onto the gate structure 210-1, at least one gate structure 210-1 is located within the projection of the opening, allowing light to smoothly irradiate and / or diffract onto the gate structure. Similarly, "directly below" has a similar meaning (the projection above completely covers the projection below, and the projection below is within the projection above), which will not be elaborated further here. Furthermore, the semiconductor structure may also have other electronic devices or gate structures beyond the projection of the trace layer with openings (e.g., the topmost trace layer), and the semiconductor structure may also have trace layers (interconnect layers) without openings, etc. For example, these electronic devices or gate structures may not require illumination to eliminate charge, etc., all of which can be configured as needed. In the embodiments of the present invention, at least a portion of the semiconductor structure has the structure described above in the embodiments of the present invention to achieve the above-mentioned intended purpose. In the embodiments of the present invention, the first interconnect layer conductive trace Mtop can be understood as at least one conductive portion in the topmost interconnect layer of the interconnect structure 260, or of course, it can be the collective term for all conductive portions of the topmost interconnect layer. When the first interconnect layer conductive trace Mtop is understood as one or more conductive portions (i.e., partial conductive portions) in the topmost interconnect layer of the interconnect structure 260, the first interconnect layer conductive trace Mtop can be the conductive trace with the widest trace width among all conductive traces in the interconnect structure 260. When the first interconnect layer conductive trace Mtop is interpreted as all conductive portions in the topmost interconnect layer of interconnect structure 260, the first interconnect layer conductive trace Mtop can represent the conductive trace with the widest trace width among all interconnect layers in interconnect structure 260. Of course, regardless of the interpretation, the first interconnect layer conductive trace Mtop can always be the conductive trace with the widest trace width among all conductive traces in interconnect structure 260. The trace widths of other traces in the topmost interconnect layer can be less than or equal to its width, and the trace widths of conductive traces in other interconnect layers can be less than its width. Therefore, the first interconnect layer conductive trace Mtop can represent the topmost interconnect layer or a portion of the topmost interconnect layer.

[0074] like Figure 2As shown, the difference between semiconductor structure 500A and semiconductor structure 500B is that semiconductor structure 500B further includes a second interconnect layer conductive trace Mn that overlaps the first interconnect layer conductive trace Mtop in direction 120. In this embodiment, the second interconnect layer conductive trace Mn is disposed directly below the first interconnect layer conductive trace Mtop. Figure 2 and Figure 3 As shown, the second interconnect layer conductive trace Mn can be located directly above and cover the electronic device 220. In some embodiments, the second interconnect layer conductive trace Mn has a dimension L3 in direction 100. In some embodiments, the ratio of dimension L3 to cell spacing P1 is between 1 and 3 (i.e., 1 ≤ L3 / P1 ≤ 3). The electronic device 220 can be partially or completely located within the projection range of the outer edge E2 of the second interconnect layer conductive trace Mn on the top surface 200T of the substrate. In some embodiments, the number of electronic devices 220 completely located within the projection range of the outer edge E2 can be less than the number of electronic devices 220 located within the projection range of the outer edge E1.

[0075] like Figure 2 and Figure 3 As shown, the second interconnect layer conductive trace Mn has an opening 240 extending through the second interconnect layer conductive trace Mn. In some embodiments, the opening 240 of the second interconnect layer conductive trace Mn is aligned in direction 120 with a corresponding opening 250 of the first interconnect layer conductive trace Mtop. The openings 240 are periodically arranged along directions 100 and 110 to expose portions of the electronic device 220, particularly the gate electrodes disposed in the gate oxide (GOX) charge sensitive region. For example, some gate structures 210-1 of the floating gate transistor 220T1 of the electronic device 220 may be exposed from the openings 240. Other gate structures 210-1 may be located between the exposed gate structures 210-1 and completely covered by the second interconnect layer conductive trace Mn. Furthermore, gate electrodes not disposed in the gate oxide (GOX) charge sensitive region may be exposed from the openings 240. For example, some gate structures 210-2 of the select transistor 220T2 may be exposed from the openings 240. Other gate structures 210-2 may be located between the exposed gate structures 210-1 and 210-2 and covered by the second interconnect layer conductive traces Mn. Furthermore, in some embodiments, the number of gate structures (gate structures 210-1 or 210-2) exposed from the opening 240 may be one.

[0076] In some embodiments, the interval S2 between two adjacent openings 240 in direction 100 (or the minimum interval S2 between the opening 240 and the outer edge E2 of the second interconnect layer conductive trace Mn) can satisfy equation (2):

[0077] Equation (2) is S2=pλ(D2 / A2).

[0078] Where S2 is the interval between two adjacent openings 240 (or the minimum interval between opening 240 and the outer edge E2 of the second interconnect layer conductive trace Mn), D2 is the distance between the second interconnect layer conductive trace Mn and the electronic device 220 in direction 120, A2 is the size of opening 240 (or the interval between two adjacent second interconnect layer conductive traces Mn in direction 100), λ is the wavelength of light 400, and p is greater than 1 and less than 3 (i.e., 1 <p<3)。

[0079] In some embodiments, D2 is the distance between the second interconnect layer conductive trace Mn and the floating gate transistor 220T1 in the electronic device 220 in direction 120. Furthermore, the distance D2 between the second interconnect layer conductive trace Mn and the floating gate transistor 220T1 in direction 120 is much larger than the size A2 of the opening 240. Further, the distance D2 can be smaller than the distance D1. In some embodiments, when the light 400 is ultraviolet (UV) light, the wavelength λ of the light 400 can be between 10 nm and 400 nm. In some embodiments, the size A2 of the opening 240 is proportional to the size L2 of the gate structure 210-1 of the floating gate transistor 220T1 in the electronic device 220 in direction 100. In some embodiments, the size A2 of the opening 240 is greater than or equal to the size L2 of the gate structure 210-1 of the floating gate transistor 220T1 in the electronic device 220. Furthermore, the size A2 of the opening 240 is greater than or equal to the wavelength λ of the light 400. For example, when the light 400 is ultraviolet (UV) light, the size A2 of the opening 240 can be between 0.1 micrometers and 5 micrometers. Therefore, the light 400 can pass through the opening 240 and form a diffraction pattern or not.

[0080] In some embodiments, when p is greater than 1 and less than 3, the density of the openings 240 is sufficient to maintain the first interconnect layer conductive trace Mtop at a low blocking level, thereby preventing electromigration (EM). Furthermore, this range allows a sufficient amount of light 400 to penetrate the first interconnect layer conductive trace Mtop and illuminate the electronic device 220, thereby supporting light transmission capability (e.g., ultraviolet erasure capability).

[0081] When the size A2 of the opening 240 is approximately equal to (or comparable to) the wavelength λ of the light ray 400, the light ray 400 passing through the opening 240 forms a diffraction pattern. In some embodiments, in direction 100, the interval S2 between two adjacent openings 240 (or the minimum interval S2 between the opening 240 and the outer edge E2 of the second interconnect layer conductive trace Mn) can be located directly above the dark fringe position in the diffraction pattern of the light ray 400 passing through the adjacent openings 240 (e.g., the second dark fringe position when p equals 2). The openings 240 of the second interconnect layer conductive trace Mn can be arranged at intervals S2 to ensure that all floating gate transistors 220T1 of the electronic device 220 are exposed to the incident light ray 400 or the diffraction of the light ray 400.

[0082] In some embodiments, the openings 240 are arranged along direction 100 at a spacing P3. The spacing P3 of the openings 240 is slightly smaller than the interval S2 between two adjacent openings 240. In some embodiments, the spacing P3 may be the same as the spacing P2. In some embodiments, the spacing P2 may be an integer multiple of the spacing P3, or vice versa, depending on the dimensions A1, A2 and the distances D1, D2. In some embodiments, the ratio of the spacing P3 (or interval S2) to the unit spacing P1 is between 1 and 2 (i.e., 1 ≤ P3 / P1 (or S2 / P1) ≤ 2). When the ratio of the spacing P3 (or interval S2) to the unit spacing P1 is between 1 and 2, this arrangement helps ensure that the electronic device 220 is not located at a dark fringe position in the diffraction pattern of the light 400 passing through the respective openings 250. This configuration supports effective light transmission capability (e.g., ultraviolet erasure capability).

[0083] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 This is shown according to some embodiments of the present invention. Figure 1 (or Figure 2 A schematic top view of various shapes of the opening 250 (or opening 240) of the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) in the interconnect structure 260 of the semiconductor structure 500A (or semiconductor structure 500B).

[0084] In some embodiments, the first interconnect layer conductive trace Mtop is in the dimension L1 of direction 100. Figure 3The size of the opening 250 is greater than 10 micrometers, which is much larger than the size A1 of the opening 250 in direction 100 (e.g., between 0.1 micrometers and 5 micrometers) (or the size A2 of the opening 240 (e.g., between 0.1 micrometers and 5 micrometers)). In some embodiments, the opening 250 of the first interconnect layer conductive trace Mtop (or the opening 240 of the second interconnect layer conductive trace Mn) in the interconnect structure 260 may be separated from each other and have various shapes in a top view.

[0085] like Figure 4 As shown, the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) may have strip-shaped openings 250A (or openings 240A) arranged along direction 100 and extending along direction 110. Therefore, direction 110 may also be the direction in which the corresponding gate structure 210-1 extends. In some embodiments, the strip-shaped openings 250A (or openings 240A) and the gate structures 210-1 exposed from the corresponding strip-shaped openings 250A (or openings 240A) may have a one-to-many relationship or a one-to-one relationship. In some embodiments, the openings 250A (or openings 240A) and the gate structures 210-1 located in the vertical projection region of the openings 250A (or openings 240A) may have a one-to-many relationship or a one-to-one relationship. Figure 3 The relative positions of the opening 250A of the first interconnect layer conductive trace Mtop (or the opening 240A of the second interconnect layer conductive trace Mn) and the floating gate transistor 220T1 in the electronic device 220 are also shown. For example, in such Figure 3 In the top view shown, when the size W1 of the gate structure 210-1 of the floating gate transistor 220T1 in the electronic device 220 is smaller than the size W2A of the strip opening 250A (or opening 240A) in direction 110, each strip opening 250A (or opening 240A) and the gate structure 210-1 exposed from the corresponding strip opening 250A (or opening 240A) can have a one-to-many relationship. If the size W1 of the gate structure 210-1 is comparable to the size W2A of the strip opening 250A (or opening 240A) in direction 110, then each strip opening 250A (or opening 240A) and the gate structure 210-1 exposed from the corresponding strip opening 250A (or opening 240A) can have a one-to-one relationship. In some embodiments, viewed from the top view, each opening 250A (or opening 240A) can expose at least one gate structure (gate structure 210-1 or 210-2). Alternatively, from a top view, at least one gate structure (gate structure 210-1 or 210-2) can be exposed from each opening 250A (or opening 240A).

[0086] like Figure 5As shown, the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) may have square openings 250B (or openings 240B) periodically arranged in an array along directions 100 and 110. In some embodiments, the square openings 250B (or openings 240B) in adjacent rows are aligned with each other along direction 100. Furthermore, the square openings 250B (or openings 240B) may be arranged in multiple rows along the extension direction (e.g., direction 110) of the respective gate structure 210-1. In some embodiments, the interval S3 (or the interval S4) between two adjacent openings 250B in direction 110 may be the same as or different from the interval S1 (or interval S2) in direction 100.

[0087] In some embodiments, such as Figure 2 and Figure 5 In the top view shown, when the gate structure 210-1 of the floating gate transistor 220T1 in the electronic device 220 is sized W1 ( Figure 2 When the size W2B of the square opening 250B (or opening 240B) in direction 110 is greater than the size of the square opening 250B (or opening 240B), each square opening 250B (or opening 240B) and the gate structure 210-1 exposed from the corresponding strip opening 250B (or opening 240B) may have a one-to-one relationship. In some embodiments, viewed from a top view, each opening 250B (or opening 240B) may expose at least one gate structure (gate structure 210-1 or 210-2).

[0088] like Figure 6 As shown, the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) may have square openings 250B (or openings 240B) arranged periodically along directions 100 and 110. Figure 5 and Figure 6 The difference between the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) and the second interconnect layer conductive trace Mn is that the square openings 250B (or openings 240B) in adjacent rows are alternately arranged along the extension direction of the gate structure 210-1 (e.g., direction 110). Figure 5 Similar to the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) in the process, in Figure 6 In this context, each square opening 250B of the first interconnect layer conductive trace Mtop (or each square opening 240B of the second interconnect layer conductive trace Mn) and the gate structure 210-1 exposed from the corresponding square opening 250B (or square opening 240B) can have a one-to-one relationship. For example... Figure 5 and Figure 6As shown, openings 250B (or openings 240B) are distributed in different rows (or columns), and openings 250B (or openings 240B) in different rows or columns can be arranged side by side or staggered. In some embodiments, openings 250B (or openings 240B) can also be arranged in other ways to form a desired array or pattern.

[0089] like Figure 7 As shown, the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) may have circular openings 250C (or openings 240C) arranged in an array periodically along directions 100 and 110. In some embodiments, the circular openings 250C (or openings 240C) in adjacent rows are aligned with each other along direction 100. Figure 5 and Figure 7 The difference between the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) is that the opening 250C (or opening 240C) is circular.

[0090] In some embodiments, the circular openings 250C (or openings 240C) in adjacent rows are aligned with each other along direction 100. Furthermore, the square openings 250C (or openings 240C) may be arranged in multiple rows along the extension direction of the respective gate structure 210-1 (e.g., direction 110). In some embodiments, the interval S5 (or the interval S6) between two adjacent openings 250C in direction 110 may be the same as or different from the interval S1 (or interval S2) in direction 100.

[0091] In some embodiments, such as Figure 7 In the top view shown, when the gate structure 210-1 of the floating gate transistor 220T1 in the electronic device 220 is sized W1 (see... Figure 2 When the size W2C of the circular opening 250C (or opening 240C) in direction 110 is greater than the size of the circular opening 250C (or opening 240C), each circular opening 250C (or opening 240C) and the gate structure 210-1 exposed from the corresponding circular opening 250C (or opening 240C) may have a one-to-one relationship. In some embodiments, in the top view, each opening 250C (or opening 240C) may expose at least one gate structure (gate structure 210-1 or 210-2).

[0092] like Figure 8 As shown, the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) may have circular openings 250C (or openings 240C) arranged periodically along directions 100 and 110. Figure 7 and Figure 8The difference between the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) and the second interconnect layer conductive trace Mn is that the circular openings 250C (or openings 240C) in adjacent rows are alternately arranged along the extension direction of the gate structure 210-1 (e.g., direction 110). Figure 7 Similar to the first interconnect layer conductive trace Mtop (or the second interconnect layer conductive trace Mn) in the process, in Figure 8 In this context, each circular opening 250C of the first interconnect layer conductive trace Mtop (or each opening 240C of the second interconnect layer conductive trace Mn) and the gate structure 210-1 exposed from the corresponding circular opening 250C (or opening 240C) can be in a one-to-one relationship.

[0093] In some embodiments, when the openings 250 (or 240) are arranged in multiple rows along the extending direction (e.g., direction 110) of the respective gate structure 210-1 (similar to...), Figure 5 or Figure 6 When the arrangement is as described above, the opening 250 (or opening 240) can be elliptical, polygonal, or other suitable shape. It should be noted that the shape of the opening 250 (or opening 240) is not limited to the disclosed embodiments.

[0094] In some embodiments, the opening 250 of the adjacent first interconnect layer conductive trace Mtop (or the opening 240 of the second interconnect layer conductive trace Mn) in direction 100 may have different shapes or different sizes along direction 110.

[0095] For example, such as Figure 4 As shown, one or more strip openings 250A (or openings 240A) can be displayed in one or more rows. Figures 5 to 8 The opening 250B (or opening 240B) or opening 250C (or opening 240C) may be replaced. Alternatively, one or more strip openings 250A (or opening 240A) may be replaced by one or more rows of openings 250 (or opening 240) having an elliptical, polygonal or other suitable shape.

[0096] For example, such as Figure 4 As shown, one or more strip openings 250A (or openings 240A) having size W2A along direction 110 can be replaced with single or multiple rows of openings 250B (or openings 240B) or openings 250C (or openings 240C) having size W2B (or size W2C) smaller than size W2A along direction 110.

[0097] For example, such as Figure 5 and Figure 6As shown, a single or multiple rows of square openings 250B (or opening 240B) can be replaced with a single or multiple rows of circular openings 250C (or opening 240C). Alternatively, a single or multiple rows of square openings 250B (or opening 240B) can be replaced with a single or multiple rows of oval, polygonal, or other suitable shapes of openings 250 (or opening 240).

[0098] In some embodiments, the openings 250 (or openings 240) in the same row may have different shapes.

[0099] For example, an opening 250 (or opening 240) in the same row can consist of a square opening 250B (or opening 240B) and a circular opening 250C (or opening 240C), as well as any combination of openings 250 (or opening 240) having an elliptical, polygonal or other suitable shape.

[0100] In some embodiments, the opening 250 of the first interconnect layer conductive trace Mtop and the opening 240 of the second interconnect layer conductive trace Mn may have different shapes or different sizes along direction 110.

[0101] For example, the opening 250 of the first interconnect layer conductive trace Mtop can be strip-shaped (e.g., strip opening 250A), while the opening 240 of the second interconnect layer conductive trace Mn can be circular, elliptical, polygonal, or other suitable shapes (e.g., square opening 240B or circular opening 240C).

[0102] For example, the opening 250 of the first interconnect layer conductive trace Mtop can be square (e.g., square opening 240B), while the opening 240 of the second interconnect layer conductive trace Mn can be strip-shaped, circular, elliptical, polygonal, or other suitable shapes (e.g., strip-shaped opening 250A or circular opening 240C).

[0103] For example, the first interconnect layer conductive trace Mtop may have an opening 250A with a size of W2A along the direction 110, and the second interconnect layer conductive trace Mn may have an opening 240B with a size of W2B along the direction 110 corresponding to the strip opening 250A (or an opening 240C with a size of W2C).

[0104] This invention provides a semiconductor structure that allows metal wiring to be arranged above the gate oxide (GOX) sensitive region of a semiconductor device. The semiconductor structure includes a substrate, an electronic device, and an interconnect structure. The electronic device is disposed on the substrate. The electronic device includes a first gate structure. The interconnect structure includes a first interconnect layer conductive trace located directly above the electronic device. The first interconnect layer conductive trace has a first opening (e.g., a trench or via) for exposing at least one first gate structure.

[0105] In some embodiments, the first interval S1 between two adjacent first openings in the first direction satisfies equation (1):

[0106] Equation (1) is S1=mλ(D1 / A1).

[0107] Where S1 is the first interval between two adjacent first openings, D1 is the first distance between the first interconnect layer conductive trace and the electronic device in the second direction, A1 is the size of the first opening in the first direction, λ is the wavelength of light, and m is greater than 1 and less than 3.

[0108] In some embodiments, the first interconnect layer conductive trace is the topmost interconnect layer conductive trace, and the light is ultraviolet light. Furthermore, the first size A1 of the first opening is greater than or equal to the wavelength λ of the ultraviolet light.

[0109] In some embodiments, the electronic devices are located within the projection range of the outer edge of the conductive trace of the first interconnect layer on the top surface of the substrate. In some embodiments, the electronic devices are arranged with a cell pitch in a first direction, and the ratio of the first spacing to the cell pitch is between 1 and 2. In some embodiments, the electronic devices are arranged with a cell pitch in a first direction, the first opening is arranged with a first spacing, and the ratio of the first spacing to the cell pitch is between 1 and 2. In some embodiments, the electronic devices include a first gate structure having a third size along a first direction, and the first size is greater than or equal to the third size.

[0110] In some embodiments, each electronic device includes a floating gate transistor and a floating gate transistor. The floating gate transistor is disposed on a first well region in a substrate. The floating gate transistor includes a first gate structure and a first source / drain doped region and a second source / drain doped region disposed on the first well region and located on both sides of the first gate structure. A selection transistor is disposed on the first well region. The selection transistor includes a second gate structure, a second source / drain doped region, and a third source / drain doped region. The second gate structure is located next to the first gate structure of the floating gate transistor. The second source / drain doped region and the third source / drain doped region are disposed on the first well region and located on both sides of the second gate structure.

[0111] In some embodiments, second gate structures of a plurality of electronic devices are exposed from a first opening. In some embodiments, the number of second gate structures of an electronic device exposed from the first opening may be one. In some embodiments, the first opening extends along the extension direction of a corresponding first gate structure. In some embodiments, the first openings are arranged in rows along the extension direction of a corresponding first gate structure. In some embodiments, the first openings in adjacent rows are alternately arranged along the extension direction of a corresponding first gate structure. In some embodiments, the first openings in adjacent rows are aligned with each other along a first direction. In some embodiments, in a top view, the first openings and the first gate structures exposed from the corresponding first openings have a one-to-many or one-to-one relationship. In some embodiments, in a top view, each first opening may expose at least one gate structure. In some embodiments, the first opening is strip-shaped, square, circular, elliptical, or polygonal.

[0112] In some embodiments, the interconnect structure of the semiconductor structure further includes a second interconnect metal layer overlapping the first interconnect metal layer. The second interconnect metal layer may have a second opening aligned in a second direction with a corresponding first opening. In some embodiments, the second interconnect metal layer is located directly above or below the first interconnect conductive trace. For example, when the first interconnect conductive trace is the topmost interconnect conductive trace, the second interconnect conductive trace is a lower interconnect conductive trace. Alternatively, when the first interconnect conductive trace is a lower interconnect conductive trace, the second interconnect conductive trace is the topmost interconnect conductive trace.

[0113] In some embodiments, the second interval S2 between two adjacent second openings in the first direction satisfies equation (2):

[0114] Equation (2) is S2=pλ(D2 / A2).

[0115] Where S2 is the second interval between two adjacent second openings in the first direction, D2 is the second distance between the lower interconnect layer conductive trace and the electronic device in the second direction, A2 is the size of the second opening in the first direction, λ is the wavelength of light, and p is greater than 1 and less than 3.

[0116] Similar to the first interconnect layer conductive trace, the size A2 of the second opening is greater than or equal to the wavelength λ of ultraviolet (UV) light. In some embodiments, the first opening of the first interconnect layer conductive trace and the second opening of the second interconnect layer conductive trace may have different shapes. Furthermore, the size A1 of the first opening may be different from the size A2 of the second opening.

[0117] Based on the arrangement of openings in the conductive traces of the interconnect layers, particularly the openings in the topmost conductive trace, even if the topmost conductive trace is directly above and completely covers the electronic device, ultraviolet (UV) light or UV light diffraction through the openings can remove trapped (or captured) charges in the gate oxide layer of the electronic device. By utilizing the properties of light diffraction, the size of the openings can be minimized (e.g., comparable to the wavelength λ of ultraviolet (UV) light) to reduce the impact on the blocking and electromigration penalties of the conductive traces of the interconnect layers. In the manner described above in this embodiment of the invention, during manufacturing (e.g., after the interconnect structure above the electronic device is formed during manufacturing), light can be used to irradiate from above the semiconductor structure. The light can pass through the first opening and irradiate or diffract to the first gate structure of the electronic device, thereby eliminating excess charges in the gate oxide of the first gate structure. This allows for highly efficient and low-cost removal of excess charges and avoids increasing the planar area of ​​the semiconductor structure, which is beneficial for large-scale manufacturing and miniaturized design of semiconductor structures. In this embodiment of the invention, it is not possible to illuminate the electronic device immediately after its formation, making the manufacturing process difficult. Furthermore, excess charge may enter the gate oxide during the subsequent interconnect structure formation process. After the interconnect structure and wiring processes are completed, subsequent processes are less likely to introduce excess charge, so light can be used to eliminate excess charge.

[0118] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor structure, characterized in that, include: substrate; An electronic device disposed on the substrate, wherein the electronic device includes a first gate structure; as well as An interconnect structure includes a first interconnect layer conductive trace located directly above the electronic device, wherein the first interconnect layer conductive trace has a first opening for exposing at least one of the first gate structures.

2. The semiconductor structure as described in claim 1, characterized in that, In the first direction, the first interval between two adjacent first openings satisfies equation (1): Equation (1) is S1=mλ(D1 / A1). Where S1 is the first interval between two adjacent first openings. D1 is the first distance between the first interconnect layer conductive trace and the electronic device in the second direction. A1 is the first dimension of the first opening in the first direction. λ is the wavelength of light, and m is greater than 1 and less than 3.

3. The semiconductor structure as described in claim 2, characterized in that, A1 is greater than or equal to λ.

4. The semiconductor structure as described in claim 1, characterized in that, The first interconnect layer conductive trace is the topmost interconnect layer conductive trace.

5. The semiconductor structure as described in claim 1, characterized in that, The electronic device is located within the projection range of the outer edge of the conductive trace of the first interconnect layer on the top surface of the substrate.

6. The semiconductor structure as described in claim 2, characterized in that, In a first direction, the electronic device is arranged with a unit spacing, and the ratio of the first spacing to the unit spacing is between 1 and 2.

7. The semiconductor structure as described in claim 1, characterized in that, In a first direction, the electronic device is arranged with a unit pitch, the first opening is arranged with a first interval, and the ratio of the first interval to the unit pitch is between 1 and 2.

8. The semiconductor structure as described in claim 2, characterized in that, The first gate structure has a second dimension along a first direction, and the first dimension is greater than or equal to the second dimension.

9. The semiconductor structure as described in claim 1, characterized in that, Each of these electronic devices includes: A floating gate transistor disposed on a first well region in the substrate, wherein the floating gate transistor includes: one of the first gate structures; and a first source / drain doped region and a second source / drain doped region disposed on the first well region and located on both sides of the first gate structure; The selection transistor disposed on the first well region includes: a second gate structure located next to the first gate structure of the floating gate transistor; and a third source / drain doped region and the first source / drain doped region disposed on the first well region and located on both sides of the second gate structure.

10. The semiconductor structure as described in claim 9, characterized in that, At least one of the second gate structures of the electronic device is exposed from the first opening.

11. The semiconductor structure as claimed in claim 1, characterized in that, The first opening extends along the extension direction of the corresponding first gate structure.

12. The semiconductor structure as claimed in claim 1, characterized in that, The first openings are arranged in rows along the extension direction of the corresponding first gate structure.

13. The semiconductor structure as described in claim 12, characterized in that, The first openings in the adjacent rows are arranged alternately along the extension direction of the corresponding first gate structure.

14. The semiconductor structure as described in claim 2, characterized in that, The first opening in the adjacent row is aligned with each other along the first direction.

15. The semiconductor structure as described in claim 12, characterized in that, In the top view, the first opening and the first gate structure exposed from the corresponding first opening have a one-to-many or one-to-one relationship.

16. The semiconductor structure as claimed in claim 1, characterized in that, The first opening can be strip-shaped, square, circular, elliptical, or polygonal.

17. The semiconductor structure as claimed in claim 2, characterized in that, The interconnect structure further includes: A second interconnect layer conductive trace overlaps the first interconnect layer conductive trace, wherein the second interconnect layer conductive trace has a second opening aligned with the corresponding first opening in the second direction.

18. The semiconductor structure as claimed in claim 17, characterized in that, In the first direction, the second interval between two adjacent second openings satisfies equation (2): Equation (2) is S2=pλ(D2 / A2). Where S2 is the second interval between two adjacent second openings. D2 represents the second distance between the conductive trace of the second interconnect layer and the electronic device in the second direction. A2 is the third dimension of the second opening in the first direction. λ is the wavelength of light, and p is greater than 1 and less than 3.

19. The semiconductor structure as claimed in claim 17, characterized in that, The second interconnect layer conductive trace is located directly above or directly below the first interconnect layer conductive trace.

Images