Gate all-around field effect transistor

Abstract

The invention provides a gate all-around field effect transistor. The gate all-around field effect transistor comprises a semiconductor substrate, a source region, a drain region, a gate structure and a plurality of nano structures, the gate structure comprises a plurality of spaced through holes, the penetrating direction of the through holes is parallel to the upper surface of the semiconductor substrate, the through holes are filled with the nanostructures respectively, and the source region and the drain region are arranged at the two ends of the nanostructures respectively; each nanostructure comprises an inner core region and a shell region wrapping the inner core region, the inner core region is a doped region with the same doping type as the source region, and the shell region and the inner core region are semiconductor structures with different doping types; and under the condition that the gate all-around field effect transistor is in a turn-off state, the inner core region and the shell region are all depleted regions. The effective area of the device can be greatly increased under the condition that the size of the original device is not changed, so that the effective current of the device is increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more particularly to a gate-all-around field-effect transistor. Background Technology

[0002] With the continuous development of integrated circuits, traditional MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices have undergone constant changes in order to continuously reduce device size. From the initial planar structure (such as Planar MOSFET), to the introduction of HKMG (High-K Metal Gate), then to FinFET (Fin Field-Effect Transistor) structure, and now to GAAFET (Gate-All-Around Field-Effect Transistor) structure, Moore's Law continues to firmly guide the development of the entire integrated circuit field. FinFET has a three-sided gate-all-around structure, and GAAFET has a four-sided gate-all-around structure. The principle of device improvement revolves around increasing the channel width to enhance the gate's electrostatic control capability over the channel, thereby suppressing short-channel effects and reducing leakage current. Schematic diagrams of Planar MOSFET, FinFET, and GAAFET are shown below. Figure 1 As shown.

[0003] Ideally, transistor development boils down to four things: ① manufacturing more transistors in the same area (i.e., increasing device integration); ② allowing as much current as possible to flow when turned on (i.e., increasing effective current); ③ allowing as little current as possible to flow when turned off (i.e., reducing leakage current); and ④ switching between on and off states as quickly as possible (i.e., improving device switching performance). However, in actual transistor manufacturing, GAAFETs, due to reasons such as excessively low on-state current, do not perform significantly differently from FinFETs.

[0004] Therefore, based on existing research on GAAFETs, there is an urgent need for a new type of GAAFET device to further increase the effective current allowed to pass through when the device is turned on. Summary of the Invention

[0005] Therefore, embodiments of this application provide a gate-all-around field-effect transistor that can significantly increase the effective current allowed to pass through the device when it is turned on, based on a conventional GAAFET.

[0006] One aspect of this application provides a gate-all-around field-effect transistor, which includes a semiconductor substrate and a source region, a drain region, a gate structure, and a plurality of nanostructures located above the semiconductor substrate; the gate structure includes a plurality of spaced through holes, the through holes having a penetration direction parallel to the upper surface of the semiconductor substrate, each nanostructure filling the through hole, and the source region and drain region being located at opposite ends of the nanostructure. Each nanostructure includes an inner core region and a shell region that surrounds the inner core region. The inner core region is a doped region with the same doping type as the source region, while the shell region is a semiconductor structure with a different doping type than the inner core region. Furthermore, when the gate-all-around field-effect transistor is in the off state, both the inner core region and the shell region are fully depleted regions.

[0007] In some embodiments of this application, when the gate-all-around field-effect transistor is in the on state, the nanostructure is used to form an electronic channel to connect the source region and the drain region.

[0008] In some embodiments of this application, the gate-all-around field-effect transistor further includes a source terminal, a drain terminal, and a gate terminal; One end of the source terminal is connected to the source region, and the other end is connected to the external circuit; one end of the drain terminal is connected to the drain region, and the other end is connected to the external circuit; one end of the gate terminal is connected to the gate structure, and the other end is connected to the external circuit.

[0009] In some embodiments of this application, the gate-all-around field-effect transistor further includes a substrate, with a semiconductor substrate located on the substrate.

[0010] In some embodiments of this application, the gate-all-around field-effect transistor further includes a gate dielectric layer located between the nanostructure and the gate structure.

[0011] In some embodiments of this application, the gate dielectric layer is a thin film layer prepared from a high dielectric constant material.

[0012] In some embodiments of this application, the gate-all-around field-effect transistor further includes a gate oxide structure located between the gate structure and the semiconductor substrate.

[0013] In some embodiments of this application, the gate oxide structure is a silicon dioxide layer.

[0014] In some embodiments of this application, the semiconductor substrate is a semiconductor silicon-based substrate, the gate structure is a structure made of metal material or polycrystalline silicon, and the source region and drain region are doped regions of the same doping type. The outer shell region is a P-type semiconductor silicon structure, and the inner core region is an N-type semiconductor silicon structure; or the outer shell region is an N-type semiconductor silicon structure, and the inner core region is a P-type semiconductor silicon structure.

[0015] In some embodiments of this application, the nanostructure is a nanowire or a nanosheet.

[0016] The gate-all-around field-effect transistor proposed in this application, through the sandwich structure formed by the inner core region and the outer shell region, can make the entire nanostructure wrapped by the gate structure serve as an electron channel when the device is in the on state, which greatly increases the effective area of ​​the device and thus greatly increases the effective current allowed to pass through when the device is turned on.

[0017] Additional advantages, objectives, and features of this application will be set forth in part in the description which follows, and will in part become apparent to those skilled in the art upon review of the following description, or may be learned by practice of the application. The objectives and other advantages of this application can be realized and obtained by means of the structures specifically pointed out in the specification and drawings.

[0018] Those skilled in the art will understand that the purposes and advantages that can be achieved with this application are not limited to those specifically described above, and that the above and other purposes that this application can achieve will be more clearly understood from the following detailed description. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, do not constitute a limitation thereof. The components in the drawings are not drawn to scale but are merely for illustrating the principles of this application. For ease of illustration and description of certain parts of this application, corresponding portions in the drawings may be enlarged, i.e., may appear larger relative to other components in an exemplary device actually manufactured according to this application. In the drawings: Figure 1 This is a schematic diagram of the structure of Planar MOSFET, FinFET, and GAAFET.

[0020] Figure 2 This is a schematic diagram of the gate-all-around field-effect transistor in one embodiment of this application.

[0021] Figure 3 This is a schematic diagram of the GAAFET in the off state according to one embodiment of this application.

[0022] Figure 4 This is a schematic diagram of the GAAFET in a weakly enabled state according to one embodiment of this application.

[0023] Figure 5 This is a schematic diagram of the GAAFET in the ON state according to one embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the embodiments and accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain this application, but are not intended to limit it.

[0025] It should also be noted that, in order to avoid obscuring this application with unnecessary details, only the structures and / or processing steps closely related to the solution according to this application are shown in the accompanying drawings, while other details that are not closely related to this application are omitted.

[0026] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, element, step, or component, but does not exclude the presence or addition of one or more other features, elements, steps, or components.

[0027] It should also be noted that, unless otherwise specified, the term "connection" in this article can refer not only to a direct connection, but also to an indirect connection involving an intermediary.

[0028] In the following description, embodiments of the present application will be illustrated with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar parts, or the same or similar steps.

[0029] Gate all-around field-effect transistors (GAAFETs) are based on a four-sided gate-all-around structure, which improves the gate's electrostatic control over the electron channel. However, in actual transistor manufacturing, the efficiency of GAAFETs is significantly reduced due to factors such as excessively low on-state current. Increasing the effective current and reducing the current during device integration and application are ongoing research topics. Based on this, this application proposes a novel gate all-around field-effect transistor structure by designing a sandwich structure formed by an inner core region and a outer shell region, building upon existing GAAFETs. This structure can not only be improved through a simple doping process but also significantly increase the device's effective current.

[0030] Figure 2 This is a schematic diagram of the gate-all-around field-effect transistor proposed in this application. Figure 2 (a) is a schematic diagram of the overall GAAFET proposed in this application. Figure 2 (b) is a partial cross-sectional view of the GAAFET proposed in this application along the X section. Figure 2 (c) in the diagram is a partial cross-sectional view of the GAAFET proposed in this application along the Y section. Figure 2 As shown, the gate-all-around field-effect transistor includes a semiconductor substrate 100 and a gate structure 310, a source region 330, a drain region 350, and a plurality of nanostructures 200 located above the semiconductor substrate 100.

[0031] As an example, the semiconductor substrate 100 and the nanostructure 200 are fabricated from semiconductor materials (such as semiconductor silicon-based materials). For example, the semiconductor substrate 100 can be fabricated using one or more of silicon, silicon germanium, or silicon carbide. The gate structure 310 can be a structure fabricated using metallic materials or polycrystalline silicon (such as silicon dioxide). The above are merely examples, and this application does not specifically limit the materials used to fabricate the semiconductor substrate 100, the nanostructure 200, and the gate structure 310. Each nanostructure 200 can be a nanowire or a nanosheet, etc., and this application does not specifically limit the shape of the nanostructure 200.

[0032] More specifically, the gate structure 310 includes a plurality of spaced through-holes, the penetration direction of which (the penetration direction of a through-hole refers to the direction in which the through-hole penetrates from one surface to another) is parallel to the upper surface of the semiconductor substrate 100. Therefore, the plurality of through-holes in the gate structure 310 are not spatially connected or intersecting. Considering that each nanostructure 200 is filled in a through-hole (only one nanostructure is filled in a through-hole), the number of through-holes in the gate structure 310 is not less than the number of nanostructures 200 in the GAAFET. Moreover, the nanostructures 200 can be considered to be stacked in a parallel and spaced manner, and the gate structure 310 can be considered to be arranged around the nanostructures 200. In addition, the source region 330 and the drain region 350 are respectively located at both ends of the nanostructure 200 (e.g., the first end of the nanostructure 200 corresponds to the source region 330 of the GAAFET, and the second end of the nanostructure 200 corresponds to the drain region 350 of the GAAFET), and the two ends of the nanostructure 200 are not enclosed by the gate structure 310. The source region 330 and the drain region 350 are doped regions of the same doping type (N-type or P-type).

[0033] In some embodiments of this application, the gate-all-around field-effect transistor further includes a gate dielectric layer 370 located between the nanostructure 200 and the gate structure 310, a gate oxide structure 390 located between the gate structure 310 and the semiconductor substrate 100, and a substrate. For example, the gate dielectric layer 370 may be a thin film layer prepared from a high dielectric constant material (such as hafnium oxide and titanium oxide), and disposed on the inner surface of the through-hole of the gate structure 310 (it can be understood that the gate dielectric layer 370 covers a plurality of spaced nanostructures 200, and the gate structure 310 covers the gate dielectric layer 370). As another example, the gate oxide structure 390 may be a silicon dioxide layer. The substrate includes a region for forming the gate-all-around field-effect transistor, therefore the semiconductor substrate 100 is located on the substrate, and the substrate is insulated from the semiconductor substrate 100.

[0034] Furthermore, such as Figure 2As shown in (b) and (c) of the diagram, in a GAAFET, each nanostructure 200 can be divided into an inner core region 210 and a shell region 230 enclosing the inner core region 210. In this application, the shell region 230 is designed to completely enclose the inner core region 210, preventing it from contacting the outside environment. At this time, the shell region 230 is in contact with and connected to the source region 330 (and the drain region 350). The inner core region 210 is a doped region with the same doping type as the source region 330 (or drain region 350), while the shell region 230 and the inner core region 210 are semiconductor structures with different doping types. Therefore, a first PN junction can be formed at the boundary between the shell region 230 and the inner core region 210. Furthermore, since the source region 330 and the drain region 350 are located at both ends of the nanostructure 200, a second PN junction and a third PN junction can be formed at the boundary with the shell region 230, respectively. For example, as... Figure 2 As shown, if the inner core region 210 is cuboid, all six sides of the inner core region 210 can form PN junctions with the outer shell region 230. Therefore, the PN junctions corresponding to these six sides can be collectively referred to as the first PN junction.

[0035] As an example, if the nanostructure is a structure fabricated using a semiconductor silicon-based material, the outer shell region 230 can be a P-type semiconductor silicon structure, and the inner core region 210 can be an N-type semiconductor silicon structure; or the outer shell region 230 can be an N-type semiconductor silicon structure, and the inner core region 210 can be a P-type semiconductor silicon structure. Furthermore, each nanostructure 200 can extend along the same direction.

[0036] The outer casing region 230 may include a channel region. In this design, when a prior art GAAFET device is in the ON state, the location of the electron channel formed between the source region 330 and the drain region 350 by gate voltage is the location of the channel region in the device proposed in this application. Furthermore, the inner core region 210 is non-contact with the source region 330, the drain region 350, and the channel region, respectively (if the inner core region 210 is in contact with the channel region, the device cannot be turned off).

[0037] In some embodiments of this application, to enable the device to operate in operating modes (including off state, weak on state, and on state), the gate-all-around field-effect transistor may further include a source terminal, a drain terminal, and a gate terminal; wherein, one end of the source terminal is connected to the source region 330, and the other end is connected to an external circuit; one end of the drain terminal is connected to the drain region 350, and the other end is connected to an external circuit; one end of the gate terminal is connected to the gate structure 310, and the other end is connected to an external circuit. The source terminal, drain terminal, and gate terminal may be electrical connectors such as metal wires or pins, and the external circuit is used to provide an applied voltage.

[0038] When the voltage difference applied between the gate terminal and the source terminal is less than the threshold voltage, no current will flow between the source region 330 and the drain region 350 even if a voltage exceeding the threshold voltage is applied between the source and drain. At this time, the device is in the off state. When the voltage applied between the source and the gate is slightly greater than the threshold voltage, but not enough to make the charge density of the inversion layer (i.e., the channel region) on the surface of the nanostructure 200 reach the turn-on state, the device is in the weak turn-on state. When the voltage applied between the source and the gate is large enough to make the charge density of the inversion layer reach a certain level, the device is in the turn-on state.

[0039] The following is a detailed description of the device principle of the novel GAAFET proposed in this application under different operating modes: Figure 3 Images (a) and (c) are schematic diagrams of the existing GAAFET in the off state. Figure 3 Figures (b) and (d) show the schematic diagrams of the GAAFET proposed in this application in the off state. When the device is off, the inner core region 210 and the surrounding outer shell region 230 form a transverse electric field, blocking charge flow between the source and drain. The second PN junction corresponding to the source region 330 and the third PN junction corresponding to the drain region 350 are in a blocked state, while the first PN junction corresponding to the inner core region 210 is in an insulating depletion state. Furthermore, this application does not specifically limit the position and shape of the outer shell region 230 and the inner core region 210. This application designs that, when the GAAFET is off, carrier diffusion causes both the inner core region 210 and the outer shell region 230 to be fully depleted regions (since the inner core region 210 and the outer shell region 230 have different doping types, a fully depleted region can be formed precisely when the number of majority carriers in the inner core region 210 and the outer shell region 230 is equal).

[0040] Figure 4 Images (a) and (c) are schematic diagrams of the existing GAAFET in a weak-on state. Figure 4 Figures (b) and (d) are schematic diagrams of the GAAFET proposed in this application under the weak turn-on state. When the GAAFET is in the weak turn-on state, the charge accumulation at the silicon-gate oxide interface (i.e., the interface formed by the coated nanostructure 200 and the gate structure 310 / gate dielectric layer 370) begins to invert (the electric field between the source and the gate begins to repel the majority carriers of the semiconductor substrate near the gate structure, forming a depletion layer). Current begins to flow from the drain region to the source region and begins to inject carriers into the fully depleted region formed by the inner core region 210 and the outer shell region 230, thereby disrupting and rearranging the carrier distribution in the fully depleted region to conduct the fully depleted region in subsequent processes.

[0041] Figure 5 Images (a) and (c) are schematic diagrams of the existing GAAFET in the on state. Figure 5 Figures (b) and (d) are schematic diagrams illustrating the device principle of the GAAFET proposed in this application in the on-state. In the prior art, when the GAAFET is in the on-state, a first electron channel can be formed in the channel region between the source region 330 and the drain region 350 through gate voltage induction (e.g., ...). Figure 5 (as shown in (c)). In the GAAFET proposed in this application, when in the ON state, due to the carrier rearrangement in the fully depleted region, besides... Figure 5 As shown in (c), the first electronic channel, with its inner core region 210 and a portion of the outer shell region 230 (excluding the channel region), can form a second electronic channel with a contact interface with the first electronic channel between the source region 330 and the drain region 350. That is, carriers in the first electronic channel are injected into the completely depleted outer shell region or even the inner core region, expanding to form the second electronic channel. At this time, a portion of the first electronic channel and the second electronic channel can overlap to form an integrated channel, thereby significantly increasing the effective current between the source and drain.

[0042] The sandwich structure proposed in this application enables electron gas to be formed at all positions within the nanostructure enclosed by the gate structure. That is, when the gate-encircling field-effect transistor is in the on state, the entire nanostructure is used to form an electron channel to connect the source region and the drain region, thereby increasing the effective current between the source region and the drain region.

[0043] From the off state, weak on state to on state, as the electron channel gradually forms, the range of the fully depleted region gradually decreases.

[0044] Currently, the common approach for practical applications is to increase device integration (using multiple GAAFETs in parallel). However, the sandwich structure proposed in this application can significantly increase the effective current of a single GAAFET, eliminating the need for multiple GAAFETs in parallel during actual operation. Even if some chip manufacturers lack sufficient process capabilities, the number of GAAFETs in parallel can be significantly reduced.

[0045] The gate-all-around field-effect transistor (GAAFET) proposed in this application has several significant advantages: ① In terms of process, this application can increase the core region by doping the nanostructure in existing GAAFETs through methods such as ion implantation, simplifying the process; ② Compared to the current electron channels formed on the surface of nanostructures, the device proposed in this application can use the entire nanostructure as an electron channel when turned on, thus significantly expanding the current path during device conduction and thereby greatly increasing the effective current of the device; ③ Because the device in this application has an expanded current path, the effective area of ​​the device can be significantly increased without changing the original device size, thereby... ④ Based on the existing mature GAAFET structure, this application proposes a sandwich structure formed by the inner core region and the outer shell region, which can guarantee a significant increase in current density under Moore's Law; ⑤ The source region and drain region can form PN junctions with the outer shell region respectively, and a PN junction can also be formed between the inner core region and the outer shell region. When the device is in the off state, the PN junction formed by the source and drain is in the blocking state, and the PN junction formed by the inner core region and the non-outer shell region is in the depletion insulation state. Therefore, the GAAFET structure proposed in this application can reduce the leakage current between the source region and the drain region.

[0046] This application does not specifically limit the fabrication method of the proposed novel GAAFET structure. Based on existing fabrication methods, the device structure proposed in this application can be obtained by fabricating doped regions at specific locations in the nanostructure through methods such as ion implantation or impurity atom diffusion. Due to the simplicity of the improved process, the novel device proposed in this application is applicable to any existing GAAFET structure.

[0047] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0048] In this application, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with or in place of features of other embodiments.

[0049] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to the embodiments of this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A gate-all-around field-effect transistor, the gate-all-around field-effect transistor comprising a semiconductor substrate (100) and a source region (330), a drain region (350), a gate structure (310), and a plurality of nanostructures (200) located above the semiconductor substrate (100); the gate structure (310) comprising a plurality of spaced through-holes, the through-holes having a penetration direction parallel to the upper surface of the semiconductor substrate (100), each nanostructure (200) filling the through-hole, and the source region (330) and the drain region (350) being disposed at opposite ends of the nanostructure (200); characterized in that, Each nanostructure (200) includes an inner core region (210) and an outer shell region (230) enclosing the inner core region (210). The inner core region (210) is a doped region with the same doping type as the source region (330), and the outer shell region (230) is a semiconductor structure with a different doping type than the inner core region (210). Furthermore, when the gate-all-around field-effect transistor is in the off state, both the inner core region (210) and the outer shell region (230) are fully depleted regions.

2. The gate-all-around field-effect transistor according to claim 1, characterized in that, When the gate-all-around field-effect transistor is in the ON state, the nanostructure is used to form an electron channel to connect the source region and the drain region.

3. The gate-all-around field-effect transistor according to claim 1, characterized in that, The gate-all-around field-effect transistor further includes a source terminal, a drain terminal, and a gate terminal; One end of the source terminal is connected to the source region (330), and the other end is connected to an external circuit. One end of the drain terminal is connected to the drain region (350), and the other end is connected to the external circuit. One end of the gate terminal is connected to the gate structure (310), and the other end is connected to the external circuit.

4. The gate-all-around field-effect transistor according to claim 1, characterized in that, The gate-all-around field-effect transistor further includes a substrate, wherein the semiconductor substrate (100) is located on the substrate.

5. The gate-all-around field-effect transistor according to claim 1, characterized in that, The gate-all-around field-effect transistor further includes a gate dielectric layer (370) located between the nanostructure (200) and the gate structure (310).

6. The gate-all-around field-effect transistor according to claim 5, characterized in that, The gate dielectric layer (370) is a thin film layer prepared from a high dielectric constant material.

7. The gate-all-around field-effect transistor according to claim 1, characterized in that, The gate-all-around field-effect transistor further includes a gate oxide structure (390) located between the gate structure (310) and the semiconductor substrate (100).

8. The gate-all-around field-effect transistor according to claim 1, characterized in that, The gate oxide structure (390) is a silicon dioxide layer.

9. The gate-all-around field-effect transistor according to claim 1, characterized in that, The semiconductor substrate (100) is a semiconductor silicon substrate, the gate structure (310) is a structure made of metal material or polysilicon, and the source region (330) and the drain region (350) are doped regions of the same doping type. The outer shell region (230) is a P-type semiconductor silicon structure, and the inner core region (210) is an N-type semiconductor silicon structure; or the outer shell region (230) is an N-type semiconductor silicon structure, and the inner core region (210) is a P-type semiconductor silicon structure.

10. The gate-all-around field-effect transistor according to claim 1, characterized in that, The nanostructure (200) is a nanowire or nanosheet.

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