Solar cell and photovoltaic module
By setting an insulating layer and a partition structure between the TCO layers on the side of the solar cell, the problems of leakage and insufficient coverage of the TCO layer are solved, thereby improving the photoelectric conversion efficiency of the cell.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- RISEN ENERGY CO LTD
- Filing Date
- 2025-01-20
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies, the TCO layer on the back of solar cells is prone to leakage during the coating process, and the effective coverage area is insufficient, which affects the cell conversion efficiency.
An insulating layer is placed between the TCO layers on the side of the solar cell, and the insulation is achieved by a second intrinsic amorphous silicon layer and/or a second doped layer to avoid short circuits and ensure that the TCO layer completely covers the silicon wafer surface.
This effectively avoids leakage problems, increases the coverage area of the TCO layer, and improves the photoelectric conversion efficiency of the solar cell.
Smart Images
Figure CN224250102U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of solar cell technology, and in particular to solar cells and photovoltaic modules. Background Technology
[0002] The total organic carbon (TCO) layer in solar cells is typically fabricated using physical vapor deposition (PVD). In existing technologies, the semiconductor substrate is usually placed on a stepped carrier for front and back TCO layer deposition. While the front side is unobstructed and fully covered, the steps on the back side, although preventing the TCO layer from wrapping around to the sides and front of the cell and causing leakage, result in a loss of the back TCO film, leading to a decrease in cell efficiency. Therefore, how to increase the effective TCO layer deposition area to improve cell conversion efficiency without leakage is a pressing problem to be solved. Utility Model Content
[0003] Therefore, it is necessary to provide a solar cell and photovoltaic module to address the aforementioned problems. This solar cell can increase the effective coverage area of the TCO layer on the surface of the solar cell while avoiding leakage, thereby improving the photoelectric conversion efficiency of the solar cell.
[0004] A solar cell, the solar cell comprising:
[0005] A silicon wafer having a first surface, a second surface, and a side surface connecting the first surface and the second surface, which are disposed opposite to each other;
[0006] A first intrinsic amorphous silicon layer, a first doped layer, a first TCO layer, and a first metal electrode are sequentially stacked on the first surface of the silicon wafer;
[0007] A second intrinsic amorphous silicon layer, a second doped layer, a second TCO layer, and a second metal electrode are sequentially stacked on the second surface of the silicon wafer.
[0008] Wherein, the edge of the first TCO layer extends to cover the side of the silicon wafer to form a first side TCO layer, the edge of the second TCO layer extends to cover the side of the silicon wafer to form a second side TCO layer, an insulating layer is provided between the first side TCO layer and the second side TCO layer, and the end of the first side TCO layer and the second TCO layer are mutually separated by the second intrinsic amorphous silicon layer and / or the second doped layer.
[0009] In one embodiment, the end of the first side TCO layer near the second TCO layer is located on the surface of the second intrinsic amorphous silicon layer or the surface of the second doped layer.
[0010] In one embodiment, the end of the insulating layer near the second TCO layer is located on the surface of the second intrinsic amorphous silicon layer.
[0011] In one embodiment, the end of the insulating layer near the second TCO layer is located on the surface of the second doped layer.
[0012] In one embodiment, the end of the insulating layer near the second TCO layer is located on the surface of the second TCO layer, and the insulating layer is connected to the edge of the second doped layer.
[0013] In one embodiment, the thickness of the insulating layer is 50nm-500nm.
[0014] In one embodiment, the first doped layer is a P-type doped layer and the second doped layer is an N-type doped layer;
[0015] Alternatively, the first doped layer may be an N-type doped layer, and the second doped layer may be a P-type doped layer.
[0016] In one embodiment, the insulating layer is made of an inorganic insulating material or an organic insulating material, wherein the inorganic insulating material is selected from at least one of silicon oxide, silicon nitride, or silicon oxynitride.
[0017] In one embodiment, the silicon wafer is selected from P-type monocrystalline silicon wafers or N-type monocrystalline silicon wafers.
[0018] A photovoltaic module comprising a solar cell as described above.
[0019] The solar cell of this invention, by setting an insulating layer between the first and second side TCO layers, and separating the ends of the first and second side TCO layers through a second intrinsic amorphous silicon layer and / or a second doped layer, not only achieves complete isolation between the first and second TCO layers, completely eliminating leakage problems caused by short circuits between the first and second TCO layers, but also ensures that both the first and second TCO layers can completely cover the entire main surface of the solar cell, effectively increasing the effective area and photoelectric conversion efficiency of the solar cell. Therefore, the solar cell of this invention can increase the effective coverage area of the TCO layer on the solar cell surface and improve the photoelectric conversion efficiency of the solar cell while avoiding leakage. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a schematic diagram of the structure of the solar cell according to the first embodiment of the present invention;
[0022] Figure 2 This is a schematic diagram of the structure of the solar cell according to the second embodiment of the present invention;
[0023] Figure 3 This is a schematic diagram of the structure of the solar cell according to the third embodiment of the present invention;
[0024] Figure 4 This is a schematic diagram of the structure of the solar cell according to the fourth embodiment of the present invention.
[0025] Figure label:
[0026] 1. Silicon wafer; 2. First intrinsic amorphous silicon layer; 3. First doped layer; 4. First TCO layer; 5. First metal electrode; 6. Second intrinsic amorphous silicon layer; 7. Second doped layer; 8. Second TCO layer; 9. Second metal electrode; 10. First side TCO layer; 11. Second side TCO layer; 12. Insulating layer. Detailed Implementation
[0027] To facilitate understanding of this utility model, it will be described in more detail below. However, it should be understood that this utility model can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of this utility model more thorough and complete.
[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of this invention is for the purpose of describing particular embodiments or examples only and is not intended to be limiting of the invention. The optional range of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.
[0029] like Figures 1-3 As shown, the solar cell provided by this utility model includes a silicon wafer 1, which has a first surface, a second surface, and a side surface connecting the first and second surfaces, arranged opposite to each other. A first intrinsic amorphous silicon layer 2, a first doped layer 3, a first TCO layer 4, and a first metal electrode 5 are sequentially stacked on the first surface of the silicon wafer 1. A second intrinsic amorphous silicon layer 6, a second doped layer 7, a second TCO layer 8, and a second metal electrode 9 are sequentially stacked on the second surface of the silicon wafer 1. It can be understood that the first doped layer 3 and the second doped layer 7 have opposite doping types. Either the first doped layer 3 or the second doped layer 7 can be an N-type doped layer or a P-type doped layer. Specifically, when the first doped layer 3 is an N-type doped layer, the second doped layer 7 is a P-type doped layer. In this case, the first surface is the light-receiving surface of the solar cell, i.e., the front surface, and the second surface is the back surface of the solar cell, i.e., the back surface. Similarly, when the first doped layer 3 is a P-type doped layer, the second doped layer 7 is an N-type doped layer. In this case, the first surface is the back surface of the solar cell, and the second surface is the front surface of the solar cell.
[0030] The first TCO layer 4 extends to cover the side of the silicon wafer 1 to form a first side TCO layer 10, and the second TCO layer 8 extends to cover the side of the silicon wafer 1 to form a second side TCO layer 11. An insulating layer 12 is provided between the first side TCO layer 10 and the second side TCO layer 11, and the end of the first side TCO layer 10 and the second TCO layer 8 are separated from each other by a second intrinsic amorphous silicon layer 6 and / or a second doped layer 7.
[0031] The solar cell of this invention, by setting an insulating layer 12 between the first side TCO layer 10 and the second side TCO layer 11, and coordinating the separation between the end of the first side TCO layer 10 and the second TCO layer 8 through a second intrinsic amorphous silicon layer 6 and / or a second doped layer 7, not only achieves complete isolation between the first TCO layer 4 and the second TCO layer 8, but also realizes electrical isolation between the front and back sides of the solar cell by setting the side of the solar cell, completely eliminating the leakage problem of the solar cell caused by short circuit between the first TCO layer 4 and the second TCO layer 8. Furthermore, it allows both the first TCO layer 4 and the second TCO layer 8 to completely cover the entire main surface of the solar cell, effectively increasing the effective area of the solar cell and improving the photoelectric conversion efficiency. Therefore, the solar cell of this invention can increase the effective coverage area of the TCO layer on the surface of the solar cell and improve the photoelectric conversion efficiency while avoiding solar cell leakage.
[0032] Combination Figures 1-3As shown, the end of the first side TCO layer 10 near the second TCO layer 8 is located on the surface of the second intrinsic amorphous silicon layer 6 or the surface of the second doped layer 7. This arrangement effectively ensures that the first side TCO layer 10 and the second TCO layer 8 are mutually isolated by the second intrinsic amorphous silicon layer 6 and / or the second doped layer 7.
[0033] Specifically, in combination Figure 1 As shown, when the end of the first side TCO layer 10 near the second TCO layer 8 is located on the surface of the second intrinsic amorphous silicon layer 6, the end of the insulating layer 12 near the second TCO layer 8 is located on the surface of the second intrinsic amorphous silicon layer 6. It can be understood that in this structure, the insulating layer 12 and the second intrinsic amorphous silicon layer 6 together constitute an isolation portion, realizing complete isolation between the first TCO layer 4, the first side TCO layer 10, the second TCO layer 8, and the second side TCO layer 11.
[0034] Combination Figure 2 As shown, when the end of the first side TCO layer 10 near the second TCO layer 8 is located on the surface of the second intrinsic amorphous silicon layer 6, the end of the insulating layer 12 near the second TCO layer 8 is located on the surface of the second doped layer 7. It can be understood that in this structure, the insulating layer 12 and the second doped layer 7 together constitute an isolation portion, realizing complete isolation between the first TCO layer 4, the first side TCO layer 10, the second TCO layer 8, and the second side TCO layer 11.
[0035] Combination Figure 3 As shown, when the end of the first side TCO layer 10 near the second TCO layer 8 is located on the surface of the second intrinsic amorphous silicon layer 6, the end of the insulating layer 12 near the second TCO layer 8 is located on the surface of the second TCO layer 8. Furthermore, the insulating layer 12 is connected to the edge of the second doped layer 7. It can be understood that in this structure, the insulating layer 12, the second intrinsic amorphous silicon layer 6, and the second doped layer 7 together constitute an isolation portion, achieving complete isolation between the first TCO layer 4, the first side TCO layer 10, the second TCO layer 8, and the second side TCO layer 11.
[0036] In one embodiment, when the end of the first side TCO layer 10 near the second TCO layer 8 is located on the surface of the second doped layer 7, the end of the insulating layer 12 near the second TCO layer 8 is located on the surface of the second intrinsic amorphous silicon layer 6; or, the end of the insulating layer 12 near the second TCO layer 8 is located on the surface of the second doped layer 7, such as... Figure 4 As shown; or, the end of the insulating layer 12 near the second TCO layer 8 is located on the surface of the second TCO layer 8, and the insulating layer 12 is connected to the edge of the second doped layer 7.
[0037] Optionally, the thickness of the insulating layer 12 is 50nm-500nm. Specifically, in this invention, the thickness of the insulating layer 12 includes, but is not limited to, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, and 500nm. This configuration allows for better isolation between the two TCO layers on the front and back sides of the solar cell by adjusting the thickness of the insulating layer 12.
[0038] Furthermore, the insulating layer 12 is made of an inorganic insulating material or an organic insulating material. The inorganic insulating material is selected from at least one of silicon oxide, silicon nitride, or silicon oxynitride, while the organic insulating material can be polymethyl methacrylate (PMMA). This configuration helps to improve the insulation effect of the insulating layer 12, isolating the first TCO layer 4 and the second TCO layer 8 to prevent battery leakage.
[0039] Optionally, silicon wafer 1 is selected from P-type monocrystalline silicon wafer 1 or N-type monocrystalline silicon wafer 1.
[0040] In this invention, the first intrinsic amorphous silicon layer 2 and the second intrinsic amorphous silicon layer 6 have a good passivation effect on the surface of the silicon wafer 1. Superior surface passivation capability is an important condition for obtaining high battery efficiency and can significantly improve the minority carrier lifetime of the battery. In one embodiment, the first intrinsic amorphous silicon layer 2 and the second intrinsic amorphous silicon layer 6 can be hydrogen-containing intrinsic amorphous silicon layers, which mainly function as passivation layers in the solar cell.
[0041] In one embodiment, the first TCO layer 4 and the second TCO layer 8 are selected from transparent conductive oxide layers. Further, the first TCO layer 4 is selected from a single-layer structure or a stacked structure of an indium tin oxide layer, an aluminum-doped zinc oxide layer, or a tungsten-doped indium oxide layer; the second TCO layer 8 is selected from a single-layer structure or a stacked structure of an indium tin oxide layer, an aluminum-doped zinc oxide layer, or a tungsten-doped indium oxide layer. It is understood that the stacked structure can be a composite structure of indium tin oxide and aluminum-doped zinc oxide layers, or a composite structure of indium tin oxide, aluminum-doped zinc oxide, and tungsten-doped indium oxide layers. This configuration effectively increases carrier collection and reduces light reflection.
[0042] It should be noted that in this invention, the first doped layer 3 and the second doped layer 7 form the PN junction and back field of the solar cell, and the first metal electrode 5 and the second metal electrode 9 are used to form the positive and negative electrodes of the solar cell, effectively collecting photogenerated carriers.
[0043] In one embodiment, the first doped layer 3 is selected from a doped amorphous silicon layer or a doped microcrystalline silicon layer; the second doped layer 7 is selected from a doped amorphous silicon layer or a doped microcrystalline silicon layer.
[0044] In one embodiment, the first metal electrode 5 is selected from any one of a copper electrode, a platinum electrode, a silver electrode, and a titanium-nickel electrode, preferably a copper electrode, and the second metal electrode 9 is selected from any one of a copper electrode, a platinum electrode, a silver electrode, and a titanium-nickel electrode, preferably a copper electrode. It is understood that the first metal electrode 5 and the second metal electrode 9 can be the same or different, but are preferably the same.
[0045] It should be noted that the structure of the solar cell of this invention can be applied to heterojunction solar cells, tandem cells, etc.
[0046] In addition, this utility model also provides a photovoltaic module, which includes the solar cell as described above.
[0047] In addition, this utility model also provides a method such as Figure 1 The method for fabricating the solar cell with the structure shown includes the following steps:
[0048] S11, texturing is performed on the first surface, second surface and side surface of silicon wafer 1, and then a first intrinsic amorphous silicon layer 2 and a first doped layer 3 are sequentially deposited on the first surface of silicon wafer 1. A first TCO layer 4 is deposited on the surface of the first doped layer 3, and the first TCO layer 4 is extended to the side surface of silicon wafer 1 to form a first side TCO layer 10.
[0049] In step S11, the first surface, second surface and side surface of silicon wafer 1 are texturized, so that both sides and the side surface of silicon wafer 1 form a pyramid-like textured structure. The texturizing process mainly utilizes the anisotropic corrosion characteristics of silicon in low-concentration alkaline solution. Si undergoes a series of chemical reactions with the alkaline solution to form a pyramid-like textured structure on the surface of silicon wafer 1.
[0050] In one embodiment, a first intrinsic amorphous silicon layer 2 and a first doped layer 3 are sequentially deposited on the first surface of a silicon wafer 1 using plasma-enhanced chemical vapor deposition (PECVD).
[0051] In this invention, when preparing the first TCO layer 4, an unmasked deposition method is adopted, i.e., a zero-mask method. The first TCO layer 4 is uniformly deposited on the surface of the first doped layer 3 using a physical vapor deposition method (PVD), such as magnetron sputtering or vacuum evaporation, and extends to the four sides of the silicon wafer 1 to form the first side TCO layer 10.
[0052] In one embodiment, the material of the first TCO layer 4 is selected from at least one of indium tin oxide, aluminum-doped zinc oxide, or tungsten-doped indium oxide.
[0053] It should be noted that in this utility model, the selection of parameters in the flocking process is not particularly limited, and the specific operation process and process parameters in the PECVD and PVD methods are not particularly limited, so they will not be described in detail here.
[0054] S12, an insulating layer 12 is deposited on the surface of the first side TCO layer 10.
[0055] In step S12, the material of the insulating layer 12 can be an inorganic insulating material or an organic insulating material, wherein the inorganic insulating material is selected from at least one of silicon oxide, silicon nitride, and silicon oxynitride.
[0056] Specifically, when the material of the insulating layer 12 is an inorganic insulating material, the first TCO layer 4 and the second surface of the silicon wafer 1 are masked, and the insulating layer 12 is formed on the surface of the first side TCO layer 10 using physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes.
[0057] S13, a second intrinsic amorphous silicon layer 6, a second doped layer 7, and a second TCO layer 8 are sequentially deposited on the second surface of the silicon wafer 1, and the second TCO layer 8 is extended to the side of the silicon wafer 1 to form a second side TCO layer 11 stacked on the surface of the insulating layer 12.
[0058] Specifically, in step S13, a second intrinsic amorphous silicon layer 6 and a second doped layer 7 are sequentially deposited on the second surface of silicon wafer 1 using plasma-enhanced chemical vapor deposition (PECVD).
[0059] In the preparation of the second TCO layer 8, an unmasked deposition method, i.e. a zero-mask method, is adopted. The second TCO layer 8 is uniformly deposited on the surface of the second doped layer 7 using a physical vapor deposition method, such as magnetron sputtering or vacuum evaporation, and extends to the four sides of the silicon wafer 1 to form a second side TCO layer 11 stacked on the surface of the insulating layer 12.
[0060] Furthermore, the material of the second TCO layer 8 is selected from at least one of indium tin oxide, aluminum-doped zinc oxide, or tungsten-doped indium oxide.
[0061] S14, a first metal electrode 5 is fabricated on the surface of the first TCO layer 4, and a second metal electrode 9 is fabricated on the surface of the second TCO layer 8, resulting in the following: Figure 1 The solar cell shown.
[0062] Specifically, the materials of the first metal electrode 5 and the second metal electrode 9 are independently selected from copper, platinum, silver or titanium nickel, with copper being preferred.
[0063] This utility model also provides a method such as Figure 2The method for fabricating the solar cell with the structure shown includes the following steps:
[0064] S21, texturing is performed on the first surface, second surface and side surface of silicon wafer 1, and then a first intrinsic amorphous silicon layer 2 and a first doped layer 3 are sequentially deposited on the first surface of silicon wafer 1. A first TCO layer 4 is deposited on the surface of the first doped layer 3, and the first TCO layer 4 is extended to the side surface of silicon wafer 1 to form a first side TCO layer 10.
[0065] Specifically, the texturing process for the first surface, second surface and side surface of silicon wafer 1 in step S21, as well as the preparation process for the first intrinsic amorphous silicon layer 2, the first doped layer 3, the first TCO layer 4 and the first side TCO layer 10, can refer to the texturing process in step S11 above, as well as the preparation process for the first intrinsic amorphous silicon layer 2, the first doped layer 3, the first TCO layer 4 and the first side TCO layer 10.
[0066] S22, a second intrinsic amorphous silicon layer 6 is deposited on the second surface of silicon wafer 1, and then an insulating layer 12 is deposited on the surface of the first side TCO layer 10.
[0067] In step S22, the fabrication process of the second intrinsic amorphous silicon layer 6 can refer to the fabrication process of the first intrinsic amorphous silicon layer 2 in step S11 above, and the specific type of material of the insulating layer 12 can refer to the specific type of material of the insulating layer 12 in step S12 above.
[0068] Specifically, when the insulating layer 12 is made of an inorganic insulating material, the surfaces of the first TCO layer 4 and the second intrinsic amorphous silicon layer 6 are masked, and the insulating layer 12 is formed on the surface of the first side TCO layer 10 using physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes.
[0069] S23, a second doped layer 7 and a second TCO layer 8 are sequentially deposited on the surface of the second intrinsic amorphous silicon layer 6, and the second TCO layer 8 is extended to the side of the silicon wafer 1 to form a second side TCO layer 11 stacked on the surface of the insulating layer 12.
[0070] Similarly, in step S23, the fabrication processes of the second doped layer 7 and the second TCO layer 8 can refer to the fabrication processes of the first doped layer 3 and the first TCO layer 4 in step S12 above. The fabrication process of the second side TCO layer 11 can refer to the fabrication process of the second side TCO layer 11 in step S13 above.
[0071] Specifically, when preparing the second TCO layer 8, an unmasked deposition method, i.e. a zero-mask method, is used. The second TCO layer 8 is uniformly deposited on the surface of the second doped layer 7 using a physical vapor deposition method, such as magnetron sputtering or vacuum evaporation, and extends to the four sides of the silicon wafer 1 to form a second side TCO layer 11 stacked on the surface of the insulating layer 12.
[0072] S24, a first metal electrode 5 is fabricated on the surface of the first TCO layer 4, and a second metal electrode 9 is fabricated on the surface of the second TCO layer 8, resulting in the following: Figure 2 The solar cell shown.
[0073] Similarly, in step S24, the specific types of materials for the first metal electrode 5 and the second metal electrode 9 can be referred to in step S14 above.
[0074] This utility model also provides a method such as Figure 3 The method for fabricating the solar cell with the structure shown includes the following steps:
[0075] S31, texturing is performed on the first surface, second surface and side surface of silicon wafer 1, and then a first intrinsic amorphous silicon layer 2 and a first doped layer 3 are sequentially deposited on the first surface of silicon wafer 1. A first TCO layer 4 is deposited on the surface of the first doped layer 3, and the first TCO layer 4 is extended to the side surface of silicon wafer 1 to form a first side TCO layer 10.
[0076] Specifically, the texturing process for the first surface, second surface and side surface of silicon wafer 1 in step S31, as well as the preparation process for the first intrinsic amorphous silicon layer 2, the first doped layer 3, the first TCO layer 4 and the first side TCO layer 10, can refer to the texturing process in step S11 above, as well as the preparation process for the first intrinsic amorphous silicon layer 2, the first doped layer 3, the first TCO layer 4 and the first side TCO layer 10.
[0077] S32, a second intrinsic amorphous silicon layer 6 and a second doped layer 7 are sequentially deposited on the second surface of silicon wafer 1, and then an insulating layer 12 is deposited on the surface of the first side TCO layer 10.
[0078] In step S32, the fabrication process of the second intrinsic amorphous silicon layer 6 and the second doped layer 7 can refer to the fabrication process of the first intrinsic amorphous silicon layer 2 and the first doped layer 3 in step S11 above, and the specific type of material of the insulating layer 12 can refer to the specific type of material of the insulating layer 12 in step S12 above.
[0079] Specifically, when the insulating layer 12 is made of an inorganic insulating material, the surfaces of the first TCO layer 4 and the second doped layer 7 are masked, and the insulating layer 12 is formed on the surface of the first side TCO layer 10 using physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes.
[0080] S33, a second TCO layer 8 is deposited on the surface of the second doped layer 7, and the second TCO layer 8 extends to the side of the silicon wafer 1 to form a second side TCO layer 11 stacked on the surface of the insulating layer 12.
[0081] In step S33, the preparation process of the second TCO layer 8 can refer to the preparation process of the first TCO layer 4 in step S11 above, and the preparation process of the second side TCO layer 11 can refer to the preparation process of the second side TCO layer 11 in step S13 above.
[0082] Specifically, when preparing the second TCO layer 8, an unmasked deposition method, i.e. a zero-mask method, is used. The second TCO layer 8 is uniformly deposited on the surface of the second doped layer 7 using a physical vapor deposition method, such as magnetron sputtering or vacuum evaporation, and extends to the four sides of the silicon wafer 1 to form a second side TCO layer 11 stacked on the surface of the insulating layer 12.
[0083] S34, a first metal electrode 5 is fabricated on the surface of the first TCO layer 4, and a second metal electrode 9 is fabricated on the surface of the second TCO layer 8, resulting in the following: Figure 3 The solar cell shown has the following structure.
[0084] Similarly, in step S34, the specific types of materials for the first metal electrode 5 and the second metal electrode 9 can be referred to in step S14 above.
[0085] It is understandable that in this utility model, regardless of Figure 1 The structure shown Figure 2 The structure shown and Figure 3In the fabrication method of the solar cell with the structure shown, a first intrinsic amorphous silicon layer 2, a first doped layer 3, and a first TCO layer 4 are sequentially deposited on the first surface of the silicon wafer 1, followed by the deposition of the first intrinsic amorphous silicon layer 2 on the second surface of the silicon wafer 1. This allows the end of the first side TCO layer 10 to be isolated from the second TCO layer 8 by the second intrinsic amorphous silicon layer 6 and / or the second doped layer 7. Combined with the insulating layer 12 introduced between the first side TCO layer 10 and the second side TCO layer 11, this completely eliminates the possibility of... In the event of a potential short circuit between the first TCO layer 4 and the second TCO layer 8, a top-down, unmasked deposition method, i.e., a zero-mask PVD method, is employed to fabricate corresponding first side TCO layer 10, second side TCO layer 11, and second side TCO layer 11 on both sides and the side of the silicon wafer 1. This ensures that the first TCO layer 4 and the second TCO layer 8 completely cover the main surface of the solar cell, effectively increasing the light-receiving area of the solar cell and improving its photoelectric conversion efficiency.
[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0087] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.
Claims
1. A solar cell, characterized in that, The solar cell includes: A silicon wafer having a first surface, a second surface, and a side surface connecting the first surface and the second surface, which are disposed opposite to each other; A first intrinsic amorphous silicon layer, a first doped layer, a first TCO layer, and a first metal electrode are sequentially stacked on the first surface of the silicon wafer; A second intrinsic amorphous silicon layer, a second doped layer, a second TCO layer, and a second metal electrode are sequentially stacked on the second surface of the silicon wafer. Wherein, the edge of the first TCO layer extends to cover the side of the silicon wafer to form a first side TCO layer, the edge of the second TCO layer extends to cover the side of the silicon wafer to form a second side TCO layer, an insulating layer is provided between the first side TCO layer and the second side TCO layer, and the end of the first side TCO layer and the second TCO layer are mutually separated by the second intrinsic amorphous silicon layer and / or the second doped layer; the end of the first side TCO layer near the second TCO layer is located on the surface of the second intrinsic amorphous silicon layer or the surface of the second doped layer.
2. The solar cell according to claim 1, characterized in that, The end of the insulating layer near the second TCO layer is located on the surface of the second intrinsic amorphous silicon layer.
3. The solar cell according to claim 1, characterized in that, The end of the insulating layer near the second TCO layer is located on the surface of the second doped layer.
4. The solar cell according to claim 1, characterized in that, The end of the insulating layer near the second TCO layer is located on the surface of the second TCO layer, and the insulating layer is connected to the edge of the second doped layer.
5. The solar cell according to claim 1, characterized in that, The thickness of the insulating layer is 50nm-500nm.
6. The solar cell according to any one of claims 1-5, characterized in that, The first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer; Alternatively, the first doped layer may be an N-type doped layer, and the second doped layer may be a P-type doped layer.
7. The solar cell according to any one of claims 1-5, characterized in that, The silicon wafer is selected from P-type monocrystalline silicon wafers or N-type monocrystalline silicon wafers.
8. A photovoltaic module, characterized in that, The photovoltaic module includes a solar cell as described in any one of claims 1-7.