Semiconductor device, manufacturing method thereof and electronic device
By forming and utilizing a stop layer to repair the gap during semiconductor device manufacturing, and performing a second grinding with the gate structure as the stop layer, the problem of hard mask layer residue was solved, improving device performance and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN PENGXIN MICRO INTEGRATED CIRCUIT MFG CO LTD
- Filing Date
- 2024-10-29
- Publication Date
- 2026-05-01
AI Technical Summary
In the gate planarization process of semiconductor devices, hard mask layer residue exists in areas where trenches are not formed, affecting device performance and product yield.
By forming a first hard mask layer, a stop layer, and a second hard mask layer on the substrate, etching to form trenches and filling them with dielectric layers, using the stop layer as a stop layer for the polishing step to repair the filling gaps, and then performing a second polishing with the gate structure as the stop layer after removing the stop layer, gate planarization is completed.
This eliminates the impact of hard mask layer residue on gate planarization, improving device performance and product yield.
Smart Images
Figure CN121968616A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0002] Currently, for semiconductor devices such as 3D transistors, after forming the fin and dummy gate structure, a single-diffusion break (SDB) process is generally required to form trenches. This process requires the formation of a hard mask layer, which is used as a mask to form the trenches. After the trenches are formed, a multilayer filling dielectric layer is formed to fill the trenches. Then, a gate planarization process is performed to expose the pseudo-polysilicon in the dummy gate structure, so that the dummy gate can be removed and the metal gate can be filled in the subsequent process.
[0003] However, in the gate planarization process of related technologies, when the area with trenches exposes the pseudo-polysilicon, the area without trenches still has residual hard mask layers, which leads to abnormalities in subsequent pseudo-gate removal and metal gate filling steps, affecting device performance.
[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention
[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0006] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising:
[0007] A substrate is provided on which a gate structure is formed, wherein the substrate includes at least a first region and a second region;
[0008] A first hard mask layer, a stop layer, and a second hard mask layer covering the gate structure are sequentially formed on the substrate.
[0009] Etching removes a portion of the gate structure and a portion of the substrate in the second region to form a trench;
[0010] A fill dielectric layer is formed to fill the trench and cover the second hard mask layer;
[0011] Grinding removes the fill dielectric layer and the second hard mask layer located on the stop layer;
[0012] Remove the stop layer;
[0013] Using the gate structure as a stop layer, the first hard mask layer is removed by grinding.
[0014] For example, the first hard mask layer and the second hard mask layer comprise nitrides, and the stop layer is made of amorphous silicon; and / or
[0015] The thickness of the stop layer ranges from 30 angstroms to 80 angstroms.
[0016] Exemplarily, etching away a portion of the gate structure and a portion of the substrate in the second region to form a trench includes:
[0017] An opening is formed in the first hard mask layer, the stop layer, and the second hard mask layer in the second region to expose a portion of the gate structure;
[0018] The exposed gate structure and a portion of the substrate are etched away to form the trench.
[0019] For example, a plurality of gate structures are formed on the substrate, and the plurality of gate structures extend along a first direction;
[0020] The substrate is also formed with a plurality of fins extending along a second direction that intersects the first direction, and the regions on both sides of the gate structure where the fins are located form active regions and drain regions, respectively.
[0021] For example, the gate structure includes a gate electrode layer, and grinding to remove the first hard mask layer with the gate structure as a stop layer includes: grinding to remove the first hard mask layer with the gate electrode layer as a stop layer to expose the gate electrode layer;
[0022] A dielectric layer is also formed between adjacent gate structures, and a contact hole etch stop layer and a gate spacer layer are also formed between the dielectric layer and the gate electrode layer.
[0023] Exemplarily, the filling dielectric layer includes a first filling dielectric layer, a second filling dielectric layer, and a third filling dielectric layer, forming a filling dielectric layer that fills the trench and covers the second hard mask layer, including:
[0024] A first filling dielectric layer is formed, which covers the bottom and sidewalls of the trench and covers the second hard mask layer;
[0025] A second filling dielectric layer is formed, which fills the remaining portion of the trench and covers the first filling dielectric layer. A filling gap is formed on the top surface of the second filling dielectric layer located in the trench region.
[0026] A third fill dielectric layer is formed to cover the second fill dielectric layer.
[0027] For example, the first and third filled dielectric layers comprise oxides, and the second filled dielectric layer comprises a nitride.
[0028] For example, a chemical mechanical polishing process is used to perform the grinding step.
[0029] This application also provides a semiconductor device, which is manufactured using the method described above.
[0030] In another aspect, this application provides an electronic device, which includes the semiconductor device described above.
[0031] The semiconductor device and its manufacturing method, and electronic device of the present application embodiment form a stop layer and use the stop layer as the stop layer in the first polishing step to repair the filling gap; then, after removing the stop layer, a second polishing step is performed using the gate structure as the stop layer to complete the gate planarization, which solves the problem of hard mask layer residue in the area where no trench is formed, eliminates the influence of the filling gap on the gate planarization, and thus improves device performance and product yield. Attached Figure Description
[0032] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0033] In the attached image:
[0034] Figures 1A-1C A cross-sectional schematic diagram of trench formation and gate planarization in semiconductor devices in related technologies is shown;
[0035] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown;
[0036] Figures 3A-3G The diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application.
[0037] Explanation of reference numerals in the attached figures:
[0038] 110 - Trench, 120 - Hard mask layer, 130 - Pseudo-polysilicon, 140 - Fill gap;
[0039] 300-Substrate, 301-Gate electrode layer, 302-Source region, 303-Drain region, 304-Dielectric layer, 305-Contact hole etch stop layer, 306-Gate spacer layer, 3061-First sub-spacer layer, 3062-Second sub-spacer layer, 307-First hard mask layer, 308-Stop layer, 309-Second hard mask layer, 310-Opening, 311-Trench, 312-First fill dielectric layer, 313-Second fill dielectric layer, 314-Third fill dielectric layer, 315-Fill gap. Detailed Implementation
[0040] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0044] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.
[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.
[0046] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods. Figures 1A to 1C As shown, in related technologies, trenches 110 are typically formed in certain areas using an SDB process, followed by filling the trenches 110 with multiple layers of dielectric filler, and finally planarization using a chemical mechanical polishing (CMP) process to expose the pseudo-polysilicon 130 in the pseudo-gate structure. Figure 1A (a) Figure 1B (a) and Figure 1C (a) shows a cross-sectional view of the area in the device where the trench 110 is not formed. Figure 1A (b) Figure 1B (b) and Figure 1C (b) shows a cross-sectional schematic diagram of the region in the device in which the trench 110 is formed.
[0047] The inventors of this application have discovered that in the gate planarization process of related technologies, pseudo-polysilicon is generally used as a stop layer for chemical mechanical polishing. However, as... Figure 1B As shown in (b), a topography / filled gap 140 is formed on the top surface of the filled dielectric layer in the trench 110 region. The density of this fillography / filled gap affects the polishing rate of the chemical mechanical polishing process and constitutes a load. The region with the fillography / filled gap 140 will first come into contact with the pseudo polysilicon 130, thereby prompting the inhibitor to reduce the overall polishing rate of the chemical mechanical polishing process. As a result, the region without the fillography / filled gap will still have the hard mask layer 120 remaining after planarization. The residue of the hard mask layer 120 will cause subsequent pseudo gate removal and abnormal metal gate filling, affecting device performance.
[0048] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, such as... Figure 2 As shown, it mainly includes the following steps:
[0049] Step S1: Provide a substrate and form a gate structure on the substrate, wherein the substrate includes at least a first region and a second region;
[0050] Step S2: A first hard mask layer, a stop layer, and a second hard mask layer covering the gate structure are sequentially formed on the substrate.
[0051] Step S3: Etch away part of the gate structure and part of the substrate in the second region to form a trench;
[0052] Step S4: Form a filled trench and a filled dielectric layer covering the second hard mask layer;
[0053] Step S5: Grind to remove the fill dielectric layer and the second hard mask layer located on the stop layer;
[0054] Step S6: Remove the stop layer;
[0055] Step S7: Using the gate structure as a stop layer, the first hard mask layer is removed by grinding.
[0056] The semiconductor device manufacturing method of this application forms a stop layer and uses this stop layer as a stop layer in the first polishing step to repair the fill gap; then, after removing the stop layer, a second polishing step is performed using the gate structure as the stop layer to complete the gate planarization. This solves the problem of hard mask layer residue in the area where no trench is formed, eliminates the influence of the fill gap on the gate planarization, and thus improves device performance and product yield.
[0057] Below, for reference Figures 2 to 3G The method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown. Figures 3A-3G The diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application.
[0058] For example, the method for manufacturing the semiconductor device of this application includes the following steps:
[0059] First, step S1 is performed, providing a substrate on which a gate structure is formed, wherein the substrate includes at least a first region and a second region.
[0060] The semiconductor device in this application can be any suitable device known to those skilled in the art. In this embodiment, the technical solution of this application is explained and illustrated mainly by taking the case of a three-dimensional transistor as the semiconductor device.
[0061] In one example, such as Figure 3AAs shown, substrate 300 is a silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, substrate 300 may also include silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). Although several examples of materials that can form substrate 300 have been described herein, any material that can serve as substrate 300 falls within the spirit and scope of this application.
[0062] In one example, gate structures are formed on the substrate 300 of both the first and second regions. The substrate 300 may also include other regions besides the first and second regions, which is not a limitation of this application.
[0063] In one example, a plurality of gate structures are formed on substrate 300, and the plurality of gate structures extend along a first direction; such as Figure 3A As shown, a plurality of fins extending along a second direction intersecting the first direction are also formed on the substrate 300. Source regions 302 and drain regions 303 are formed on both sides of the gate structure, respectively. Exemplarily, the source regions 302 and drain regions 303 are epitaxial layers. Grooves can be formed in the predetermined areas where the source regions 302 and drain regions 303 are formed by etching the fins on both sides of the gate structure, and then epitaxial layers can be selectively grown in the grooves. Exemplarily, the second direction is perpendicular to the first direction.
[0064] In one example, the method for forming a fin includes the following steps: forming a patterned mask layer on the surface of a substrate 300, the patterned mask layer defining a pattern of the fin, including the width, length, and position of the fin; etching the substrate 300 using the patterned mask layer as a mask to form the fin; and then removing the mask layer. It should be noted that the method for forming the fin is merely exemplary and is not limited to the methods described above. Exemplarily, the gate structure spans the fin, that is, the upper surface and side surfaces of the fin portion are both formed with gate structures.
[0065] In one example, such as Figure 3A As shown, the gate structure includes a gate electrode layer 301. Exemplarily, the gate structure is a pseudo-gate structure, and the gate electrode layer 301 is a pseudo-gate electrode layer. The material of the gate electrode layer 301 can be a semiconductor material commonly used in the art, such as polysilicon, and is not limited to any one of them, and will not be listed here.
[0066] In one example, such as Figure 3AAs shown, a dielectric layer 304 is formed between adjacent gate structures, and a contact etch stop layer (CESL) 305 and a spacer layer 306 are formed between the dielectric layer 304 and the gate electrode layer 301. The dielectric layer 304 can be made of common insulating materials, such as silicon oxide, and this application does not limit its material composition. Exemplarily, the top surface of the dielectric layer 304 is flush with the top surface of the gate electrode layer 301. Exemplarily, the gate spacer layer 306 is located on both sides of the gate electrode layer 301, and the contact etch stop layer 305 is located between the gate spacer layer 306 and the dielectric layer 304. Exemplarily, the contact etch stop layer 305 and the gate spacer layer 306 can be made of common insulating materials; for example, the contact etch stop layer 305 can be made of silicon nitride, and the gate spacer layer 306 can be made of one or more of silicon oxide, silicon nitride, and silicon oxynitride, and this application does not limit its material composition. In this embodiment, as... Figure 3A As shown, the gate spacer layer 306 is a double-layer structure including a first sub-spacer layer 3061 and a second sub-spacer layer 3062; in other embodiments, the gate spacer layer 306 may also be a single-layer or three-layer or higher structure, and this application is not limited thereto. Exemplarily, the gate structure may also include a gate dielectric layer (not shown) located between the gate electrode layer 301 and the substrate 300, the material of which includes, but is not limited to, silicon oxide. Exemplarily, Figures 3A to 3G These are all schematic cross-sectional views of semiconductor devices along the second direction.
[0067] In one example, various deposition processes commonly used in the art can be employed to form the contact hole etch stop layer 305 and the gate spacer layer 306. The contact hole etch stop layer 305 is used to relieve stress and increase carrier mobility, thereby improving device performance. The gate spacer layer 306 is used to protect the gate structure and reduce the capacitance between the gate structure and the surrounding structure, thereby reducing resistance-capacitance delay.
[0068] Next, proceed to step S2, as follows: Figure 3A As shown, a first hard mask layer 307, a stop layer 308, and a second hard mask layer 309 covering the gate structure are sequentially formed on the substrate 300.
[0069] In one example, such as Figure 3AAs shown, various deposition processes commonly used in the field can be employed to form the first hard mask layer 307, the stop layer 308, and the second hard mask layer 309 covering the gate structure. For example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) can be used to form the first hard mask layer 307, the stop layer 308, and the second hard mask layer 309. Exemplarily, the material of the stop layer 308 includes amorphous silicon. In other embodiments, the material of the stop layer 308 can be any other suitable material suitable for use as a stop layer in a polishing process. Exemplarily, the thickness of the stop layer 308 ranges from 30 angstroms to 80 angstroms. For example, the thickness of the stop layer 308 can be 30 angstroms, 40 angstroms, 45 angstroms, 50 angstroms, 58 angstroms, 60 angstroms, 66 angstroms, 70 angstroms, or 80 angstroms, or any other suitable thickness range. Exemplarily, the first hard mask layer 307 and the second hard mask layer 309 comprise nitrides, such as silicon nitride; in other embodiments, the materials of the first hard mask layer 307 and the second hard mask layer 309 may also be any other suitable materials. Exemplarily, such as Figure 3A As shown, the first hard mask layer 307 also covers the dielectric layer 304, the contact hole etch stop layer 305, and the gate spacer layer 306.
[0070] Next, proceed to step S3, as follows: Figure 3C As shown, etching removes a portion of the gate structure and a portion of the substrate 300 in the second region to form a trench 311. Specifically, etching removes a portion of the gate structure and a portion of the substrate 300 in the second region to form the trench 311, including: first, as shown... Figure 3B As shown, an opening 310 exposing a portion of the gate structure is formed in the first hard mask layer 307, the stop layer 308, and the second hard mask layer 309 in the second region; then, as... Figure 3C As shown, etching removes the exposed gate structure and a portion of the substrate 300 to form a trench 311. Exemplarily, one or more trenches 311 may be formed, and this application is not limited thereto. Exemplarily, no trench is formed in the first region.
[0071] In one example, a commonly used etching process in the art can be used to etch the second hard mask layer 309, the stop layer 308, and the first hard mask layer 307 in the second region to form an opening 310 exposing a portion of the gate structure. Specifically, a third hard mask layer (e.g., a silicon oxide layer) and a mask layer (not shown) can be formed on the second hard mask layer 309 in the second region first. The third hard mask layer, the second hard mask layer 309, the stop layer 308, and the first hard mask layer 307 are then etched using the mask layer as a mask to form the opening 310 exposing a portion of the gate structure. The third hard mask layer is consumed during subsequent etching to form a trench. Exemplarily, the gate structure exposed by the opening 310 is a region where a trench is to be etched, for example, a region where a trench is to be formed by etching the gate structure using an SDB process. Figures 3C to 3G The trenches shown are all formed by SDB etching.
[0072] In one example, the exposed gate structure and a portion of the substrate 300 can be etched away using an SDB process to form a trench 311. Specifically, the exposed gate electrode layer 301 and a portion of the substrate 300 are etched away to form the trench 311, thereby achieving isolation of the active region. Exemplarily, in the step of etching to form the trench 311, a portion of the thickness of the second hard mask layer 309 is consumed. The second hard mask layer 309 should have a certain thickness to ensure that the stop layer 308 is not consumed in the step of etching to form the trench 311.
[0073] In one example, substrate 300 includes different regions, wherein, Figures 3A-3G Figure (a) shows a cross-sectional view of the region in the substrate 300 where the trench 311 is not formed. Figures 3A-3G Figure (b) shows a cross-sectional view of the region in the substrate 300 where the trench 311 is formed; that is, Figures 3A-3G Figure (a) shows a cross-sectional view of the first region in the substrate 300. Figures 3A-3G Figure (b) shows a cross-sectional view of the second region in the substrate 300.
[0074] Next, proceed to step S4, as follows: Figure 3D As shown, a filling dielectric layer forms the filling trench 311 and the second hard mask layer 309. Specifically, as... Figure 3DAs shown, the filling dielectric layer includes a first filling dielectric layer 312, a second filling dielectric layer 313, and a third filling dielectric layer 314. The filling trench 311 and the filling dielectric layer covering the second hard mask layer 309 can be formed by the following steps: First, the first filling dielectric layer 312 is formed, covering the bottom and sidewalls of the trench 311 and covering the second hard mask layer 309; Next, the second filling dielectric layer 313 is formed, filling the remaining part of the trench and covering the first filling dielectric layer 312. A filling gap 315 is formed on the top surface of the second filling dielectric layer 313 located in the trench 311 region; The third filling dielectric layer 314 is formed covering the second filling dielectric layer 313. Due to the presence of the filling gap 315 on the top surface of the second filling dielectric layer 313 located in the trench 311 region, a filling gap 315 is also formed on the top surface of the third filling dielectric layer 314 located in the trench 311 region. Exemplarily, various deposition processes commonly used in the art can be selected to form the first filling dielectric layer 312, the second filling dielectric layer 313, and the third filling dielectric layer 314. For example, the first filling dielectric layer 312 and the second filling dielectric layer 313 can be formed by ALD deposition, and the third filling dielectric layer 314 can be formed by plasma-enhanced chemical vapor deposition (PECVD). Exemplarily, the third filling dielectric layer 314 is used to reduce the filling gap. Exemplarily, the first filling dielectric layer 312, the second filling dielectric layer 313, and the third filling dielectric layer 314 can be selected from commonly used dielectric materials. For example, the first filling dielectric layer 312 and the third filling dielectric layer 314 can be oxides (e.g., silicon oxide), and the second filling dielectric layer 313 can be a nitride (e.g., silicon nitride). This application does not limit this.
[0075] Next, proceed to step S5, as follows: Figure 3E As shown, the fill dielectric layer and the second hard mask layer 309 located on the stop layer 308 are removed by grinding. Exemplarily, the stop layer 308 serves as a stop layer in this grinding step. By stopping the grinding step at the stop layer 308, the fill gap 315 located in the trench 311 region can be repaired. After this grinding step, the thickness of the stop layer 308 in the region where the trench 311 is formed is substantially the same as the thickness of the stop layer 308 in the region where the trench 311 is not formed. This allows for a significant reduction or even elimination of the difference in grinding speed between the region where the trench 311 is not formed and the region where the trench 311 is formed due to the presence of the fill gap 315 in the subsequent second grinding step. Exemplarily, a chemical mechanical polishing process can be used to remove the fill dielectric layer and the second hard mask layer 309 located on the stop layer 308.
[0076] Next, proceed to step S6, as follows: Figure 3FAs shown, the stop layer 308 is removed. Exemplarily, an etching process (e.g., dry etching) or a planarization process (e.g., chemical mechanical polishing) can be used to remove the stop layer 308; this application is not limited in this regard. Exemplarily, while removing the stop layer 308, a portion of the fill dielectric layer is also removed so that the top surface of the remaining fill dielectric layer is flush with the top surface of the first hard mask layer 307.
[0077] Finally, proceed with step S7, as follows: Figure 3G As shown, the first hard mask layer 307 is removed by grinding, using the gate structure as the stop layer. Specifically, removing the first hard mask layer 307 by grinding, using the gate structure as the stop layer, includes: removing the first hard mask layer 307 by grinding, using the gate electrode layer 301 as the stop layer, to expose the gate electrode layer 301. Exemplarily, through the repair of the filling gap 315 in the first grinding step described above, the areas where trenches 311 are not formed and the areas where trenches 311 are formed have the same grinding speed in this grinding step. That is, the areas where trenches 311 are not formed and the areas where trenches 311 are formed can be ground to the contact gate electrode layer 301 almost simultaneously, thereby solving the problem of hard mask layer residue in the areas where trenches 311 are not formed, eliminating the impact of the filling gap on gate planarization, and thus improving device performance and product yield. Exemplarily, a chemical mechanical polishing (CMP) process can be used to perform the above grinding step, that is, a CMP process can be used to remove the first hard mask layer 307 by grinding, using the gate electrode layer 301 as the stop layer, to expose the gate electrode layer 301.
[0078] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The complete semiconductor device fabrication may also include other steps, such as dummy gate removal and metal gate filling processes, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.
[0079] In summary, the semiconductor device manufacturing method of this application embodiment forms a stop layer and uses this stop layer as the stop layer in the first polishing step to repair the fill gap; then, after removing the stop layer, a second polishing step is performed using the gate structure as the stop layer to complete the gate planarization. This solves the problem of hard mask layer residue in the area where no trench is formed, eliminates the influence of the fill gap on the gate planarization, and thus improves device performance and product yield.
[0080] This application also provides a semiconductor device prepared by the method described in Embodiment 1 above. Since the device of this application is prepared using the aforementioned method, it has the same advantages as the aforementioned method.
[0081] The semiconductor device in this application can be any suitable device known to those skilled in the art. In this embodiment, the technical solution of this application is explained and illustrated mainly by taking the case of a three-dimensional transistor as the semiconductor device.
[0082] The semiconductor device of this application embodiment is manufactured using the above method, forming a stop layer, and using this stop layer as the stop layer in the first polishing step to repair the filling gap; then, after removing the stop layer, a second polishing step is performed using the gate structure as the stop layer to complete the gate planarization, which solves the problem of hard mask layer residue in the area where no trench is formed, eliminates the influence of the filling gap on the gate planarization, and thus improves device performance and product yield.
[0083] Another embodiment of this application also provides an electronic device, including the aforementioned semiconductor device.
[0084] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including the aforementioned semiconductor devices. The electronic device in this application embodiment has better performance because it uses the aforementioned semiconductor devices.
[0085] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided on which a gate structure is formed, wherein the substrate includes at least a first region and a second region; A first hard mask layer, a stop layer, and a second hard mask layer covering the gate structure are sequentially formed on the substrate. Etching removes a portion of the gate structure and a portion of the substrate in the second region to form a trench; A fill dielectric layer is formed to fill the trench and cover the second hard mask layer; Grinding removes the fill dielectric layer and the second hard mask layer located on the stop layer; Remove the stop layer; Using the gate structure as a stop layer, the first hard mask layer is removed by grinding.
2. The manufacturing method according to claim 1, characterized in that, The first hard mask layer and the second hard mask layer comprise nitrides, and the stop layer is made of amorphous silicon; and / or The thickness of the stop layer ranges from 30 angstroms to 80 angstroms.
3. The manufacturing method according to claim 1, characterized in that, Etching away a portion of the gate structure and a portion of the substrate in the second region to form a trench includes: An opening is formed in the first hard mask layer, the stop layer, and the second hard mask layer in the second region to expose a portion of the gate structure; The exposed gate structure and a portion of the substrate are etched away to form the trench.
4. The manufacturing method according to claim 1, characterized in that, A plurality of gate structures are formed on the substrate, and the plurality of gate structures extend along a first direction; The substrate is also formed with a plurality of fins extending along a second direction that intersects the first direction, and the regions on both sides of the gate structure where the fins are located form active regions and drain regions, respectively.
5. The manufacturing method according to claim 1, characterized in that, The gate structure includes a gate electrode layer. Using the gate structure as a stop layer, grinding away the first hard mask layer includes: using the gate electrode layer as a stop layer, grinding away the first hard mask layer to expose the gate electrode layer. A dielectric layer is also formed between adjacent gate structures, and a contact hole etch stop layer and a gate spacer layer are also formed between the dielectric layer and the gate electrode layer.
6. The manufacturing method according to claim 1, characterized in that, The filling dielectric layer includes a first filling dielectric layer, a second filling dielectric layer, and a third filling dielectric layer, forming a filling dielectric layer that fills the trench and covers the second hard mask layer, including: A first filling dielectric layer is formed, which covers the bottom and sidewalls of the trench and covers the second hard mask layer; A second filling dielectric layer is formed, which fills the remaining portion of the trench and covers the first filling dielectric layer. A filling gap is formed on the top surface of the second filling dielectric layer located in the trench region. A third fill dielectric layer is formed to cover the second fill dielectric layer.
7. The manufacturing method according to claim 6, characterized in that, The first and third filled dielectric layers comprise oxides, and the second filled dielectric layer comprises a nitride.
8. The manufacturing method according to claim 1, characterized in that, The grinding step is performed using a chemical mechanical polishing process.
9. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-8.
10. An electronic device, characterized in that, The electronic device includes the semiconductor device of claim 9.