Chip structure, semiconductor device structure and preparation method thereof

Abstract

The invention relates to a chip structure, a semiconductor device structure and a preparation method thereof. The chip structure comprises an epitaxial layer; the junction termination extension region is located in the epitaxial layer; the cut-off ring is located in the epitaxial layer and located between the junction termination extension region and the edge of the epitaxial layer, and a distance is formed between the cut-off ring and the edge of the junction termination extension region and the edge of the epitaxial layer; the field plate structure is located on the upper surface of the epitaxial layer and extends to the position over the cut-off ring from the position over the junction termination extension region; the end face of the edge, close to the epitaxial layer, of the field plate structure is an inclined face and is spaced from the outer edge of the cut-off ring. The interlayer dielectric layer covers the field plate structure and the exposed cut-off ring; and the covering dielectric layer covers the interlayer dielectric layer. According to the invention, the long-term reliability of the chip structure under the HV-H3TRB test condition can be remarkably improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip structure, a semiconductor device structure, and a method for fabricating the same. Background Technology

[0002] SiC power MOSFETs, as representatives of third-generation semiconductors, are widely used due to their superior performance. HV-H3TRB (High Voltage, High Humidity, High Temp Reverse Bias) testing is a necessary condition for evaluating the reliability of devices in high-temperature and high-humidity environments. During the HV-H3TRB test, the chip edges are subjected to mechanical and electrical stresses under the combined effects of humidity, high temperature, and high electric field, making the terminals prone to degradation, which is a significant cause of device failure.

[0003] In existing technologies, a stop ring is typically added from the terminal (such as JTE, Junction Termination Extension) to the chip edge as a protection measure to reduce the influence of free ions and alleviate local electric field concentration.

[0004] The cutoff ring is a high-dose ion implantation region with an unstable bonding structure containing dangling bonds. Furthermore, current technologies do not effectively protect the cutoff ring. When the chip is exposed to humid environments such as HV-H3TRB testing, the presence of dangling bonds promotes the reaction of oxygen with Si or C, generating oxides. This leads to delamination of the overlying film interface and the creation of gaps. Moisture and positively charged corrosion products can then penetrate the chip along these gaps, forming corrosion pits or microleakage channels at the cutoff ring. This can cause leakage current failure and voltage degradation, affecting the chip's long-term reliability. Summary of the Invention

[0005] Based on this, it is necessary to provide a chip structure, semiconductor device structure and its fabrication method to address the technical problems in the prior art. This application optimizes the edge protection structure and defines the film layer design at the edge position, so that the stop ring can be effectively protected, avoiding electrochemical corrosion effects and improving the high voltage stability and working life of the chip structure in harsh environments.

[0006] In a first aspect, this application provides a chip structure, including:

[0007] Epitaxial layer;

[0008] The terminal extension region is located within the epitaxial layer;

[0009] The cutoff ring is located within the epitaxial layer and between the junction termination extension region and the edge of the epitaxial layer, and is spaced from both the junction termination extension region and the edge of the epitaxial layer.

[0010] A field plate structure is located on the upper surface of the epitaxial layer, extending from directly above the junction terminal extension region to directly above the stop ring; the end face of the field plate structure near the edge of the epitaxial layer is an inclined surface, and there is a gap between it and the outer edge of the stop ring;

[0011] An interlayer dielectric layer covers the field plate structure and the exposed stop ring;

[0012] Covering the dielectric layer, covering the interlayer dielectric layer.

[0013] In the above embodiments, by setting the interlayer dielectric layer to completely cover the stop ring, and on the other hand, by using a covering dielectric layer to wrap the interlayer dielectric layer (ILD), and the interlayer dielectric layer wrapping the film edge structure of the field structure, the influence of moisture on the stop ring is reduced. The stop ring will not be subject to electrochemical corrosion risk, and there will be no film interface delamination, corrosion points, or microleakage channels. By setting the end face of the edge of the field structure near the epitaxial layer as an inclined surface, and by having the interlayer dielectric layer cover the field structure and the stop ring, and the covering dielectric layer cover the interlayer dielectric layer, stress concentration can be effectively reduced. The film transition at the edge of the chip structure is more natural. Based on the combined effect of the above improvements, the long-term reliability of the chip structure under HV-H3TRB test conditions can be significantly improved.

[0014] In some embodiments, the interlayer dielectric layer extends from the upper surface of the field plate structure via the inclined surface to the upper surface of the epitaxial layer; the orthographic projection of the interlayer dielectric layer on the upper surface of the epitaxial layer covers the orthographic projection of the field plate structure on the upper surface of the epitaxial layer and the stop ring, and has a gap with the edge of the epitaxial layer;

[0015] The covering dielectric layer extends from the upper surface of the interlayer dielectric layer to the upper surface of the epitaxial layer, and has a gap with the edge of the epitaxial layer.

[0016] In some embodiments, the chip structure further includes a molding compound that covers the exposed upper surface of the overlay dielectric layer and the epitaxial layer.

[0017] In some embodiments, the epitaxial layer includes a cell region and a terminal region located around the cell region; the junction terminal extension region, the stop ring, the field plate structure, the interlayer dielectric layer, and the overlay dielectric layer are located within the terminal region.

[0018] In some embodiments, the chip structure further includes a substrate structure, wherein the epitaxial layer is located on the upper surface of the substrate structure.

[0019] Secondly, this application provides a semiconductor device structure, including:

[0020] Substrate structure;

[0021] Multiple chip structures as described in the first aspect are located on the upper surface of the substrate structure;

[0022] The cutting channels are located between each adjacent chip structure.

[0023] In the above embodiments, by setting the interlayer dielectric layer to completely cover the stop ring, and on the other hand, by using a covering dielectric layer to wrap the interlayer dielectric layer (ILD), and the interlayer dielectric layer wrapping the film edge structure of the field structure, the influence of moisture on the stop ring is reduced. The stop ring will not be subject to electrochemical corrosion risk, and there will be no film interface delamination, corrosion points, or microleakage channels. By setting the end face of the edge of the field structure near the epitaxial layer as an inclined surface, and by having the interlayer dielectric layer cover the field structure and the stop ring, and the covering dielectric layer cover the interlayer dielectric layer, stress concentration can be effectively reduced. The film transition at the edge of the chip structure is more natural. Based on the combined effect of the above improvements, the long-term reliability of the chip structure under HV-H3TRB test conditions can be significantly improved.

[0024] Thirdly, this application provides a method for fabricating a semiconductor device structure, comprising:

[0025] Provide substrate structure;

[0026] An epitaxial layer is formed on the upper surface of the substrate structure; the epitaxial layer includes multiple chip regions.

[0027] A junction termination extension region is formed within the epitaxial layer of each of the aforementioned chip regions;

[0028] A cutoff ring is formed in the epitaxial layer of each chip region. The cutoff ring is located between the junction termination extension region and the edge of the chip region, and is spaced from both the junction termination extension region and the edge of the epitaxial layer.

[0029] A field plate structure is formed on the upper surface of the epitaxial layer of each of the chip regions. The field plate structure extends from directly above the junction terminal extension region to directly above the cutoff ring. The end face of the field plate structure near the edge of the chip region is an inclined surface and has a gap with the outer edge of the cutoff ring.

[0030] An interlayer dielectric layer is formed in each of the chip regions, the interlayer dielectric layer covering the field plate structure and the exposed cutoff ring;

[0031] A cover dielectric layer is formed in each of the chip regions, and the cover dielectric layer covers the interlayer dielectric layer;

[0032] Cutting channels are formed between each adjacent chip region.

[0033] In the above embodiments, by setting the interlayer dielectric layer to completely cover the stop ring, and on the other hand, by using a covering dielectric layer to wrap the interlayer dielectric layer (ILD), and the interlayer dielectric layer wrapping the film edge structure of the field structure, the influence of moisture on the stop ring is reduced. The stop ring will not be subject to electrochemical corrosion risk, and there will be no film interface delamination, corrosion points, or microleakage channels. By setting the end face of the edge of the field structure near the epitaxial layer as an inclined surface, and by having the interlayer dielectric layer cover the field structure and the stop ring, and the covering dielectric layer cover the interlayer dielectric layer, stress concentration can be effectively reduced. The film transition at the edge of the chip structure is more natural. Based on the combined effect of the above improvements, the long-term reliability of the chip structure under HV-H3TRB test conditions can be significantly improved.

[0034] In some embodiments, before forming cleavage paths between adjacent chip regions, the method further includes:

[0035] A molding layer is formed, which covers the exposed upper surface of the overlay dielectric layer and the epitaxial layer; the cut path penetrates the molding layer and extends into the epitaxial layer.

[0036] In some embodiments, each of the chip regions includes a cell region and a terminal region located around the cell region; the junction terminal extension region, the cutoff ring, the field plate structure, the interlayer dielectric layer, and the overlay dielectric layer are all located within the terminal region.

[0037] Fourthly, this application provides a method for fabricating a chip structure, comprising:

[0038] The semiconductor device structure is prepared using the method for preparing the semiconductor device structure as described in any third aspect;

[0039] The semiconductor device structure is diced from the dicing line to obtain multiple chip structures.

[0040] In the above embodiments, by setting the interlayer dielectric layer to completely cover the stop ring, and on the other hand, by using a covering dielectric layer to wrap the interlayer dielectric layer (ILD), and the interlayer dielectric layer wrapping the film edge structure of the field structure, the influence of moisture on the stop ring is reduced. The stop ring will not be subject to electrochemical corrosion risk, and there will be no film interface delamination, corrosion points, or microleakage channels. By setting the end face of the edge of the field structure near the epitaxial layer as an inclined surface, and by having the interlayer dielectric layer cover the field structure and the stop ring, and the covering dielectric layer cover the interlayer dielectric layer, stress concentration can be effectively reduced. The film transition at the edge of the chip structure is more natural. Based on the combined effect of the above improvements, the long-term reliability of the chip structure under HV-H3TRB test conditions can be significantly improved. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a top view of a chip structure provided in one embodiment of this application;

[0043] Figure 2 This is a schematic cross-sectional view of the terminal region of a chip structure provided in one embodiment of this application;

[0044] Figure 3 This is a top view of a semiconductor device structure provided in another embodiment of this application;

[0045] Figure 4 This is a flowchart of a method for fabricating a semiconductor device structure provided in another embodiment of this application;

[0046] Figure 5 This is a schematic cross-sectional view of the terminal region of a chip region in the structure obtained in step S11 of the method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0047] Figure 6 This is a schematic cross-sectional view of the terminal region of a chip region in the structure obtained in step S12 of the method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0048] Figure 7 This is a schematic cross-sectional view of the terminal region of a chip region in the structure obtained in step S13 of the method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0049] Figure 8 This is a schematic cross-sectional view of the terminal region of a chip region in the structure obtained in step S14 of the method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0050] Figure 9 This is a schematic cross-sectional view of the terminal region of a chip region in the structure obtained in step S15 of the method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0051] Figure 10 This is a schematic cross-sectional view of the terminal region of a chip region in the structure obtained in step S16 of the method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0052] Figure 11This is a schematic cross-sectional view of the terminal region of a chip region in the structure obtained after forming a molding compound layer in the method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0053] Figure 12 This is a flowchart of a method for fabricating a chip structure provided in another embodiment of this application.

[0054] Explanation of reference numerals in the attached figures:

[0055] 10. Chip structure; 101. Epitaxial layer; 102. Junction termination extension region; 103. Cut-off ring; 104. Field plate structure; 1041. Inclined surface; 105. Interlayer dielectric layer; 1051. First horizontal portion; 1052. Inclined portion; 1053. Second horizontal portion; 106. Cover dielectric layer; 107. Molding layer; 108. Cell region; 109. Termination region; 20. Substrate structure; 30. Drill track. Detailed Implementation

[0056] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application more thorough and complete.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0058] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0059] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0060] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0061] SiC power MOSFETs, as representatives of third-generation semiconductors, are widely used due to their superior performance. The HV-H3TRB evaluation of device reliability in high-temperature and high-humidity environments is a necessary condition. During the HV-H3TRB testing process, the chip edges are subjected to mechanical and electrical stresses under the combined effects of humidity, high temperature, and high electric field, making the terminals prone to degradation, a significant cause of device failure.

[0062] Typically, this can be achieved by adding a cutoff loop (N) from the terminal to the chip edge. + Cut-off ring, P + Cut-off rings (and similar devices) serve as protective measures to reduce the influence of free ions and alleviate local electric field concentration. Furthermore, the relationship between the film layer at the chip edge and the cut-off ring has a certain impact on the interfacial electric field.

[0063] However, the above-mentioned solution of adding a cutoff loop has reliability risks: with N + Taking the (N-type heavily doped) cutoff ring as an example, in the HV-H3TRB test, when it is not effectively protected by SiN, due to N... + The region undergoes high-dose ion implantation, resulting in unstable bonding structures and the presence of dangling bonds. This promotes the reaction of oxygen with Si or C, generating oxides that lead to delamination at the interface with the overlying film, creating leakage paths. Simultaneously, in the HV-H3TRB environment, the interface between the molding compound and SiC is acidic, initiating anodic metal corrosion and generating corrosion products. These positively charged corrosion products exacerbate N2 corrosion. + Electric field concentration occurs at the ring. Moisture and corrosion products penetrate the chip structure along the gaps, causing leakage failure. On the other hand, due to the lack of a clear film definition at the edges of traditional films, high-stress SiN is prone to stress concentration at sharp points, which easily leads to cracking and delamination under HV-H3TRB testing, accelerating moisture penetration and thus accelerating aging.

[0064] In one embodiment, see Figure 1 and Figure 2 This embodiment provides a chip structure 10, which may include: an epitaxial layer 101; a junction termination extension region 102 located within the epitaxial layer 101; a cutoff ring 103 located within the epitaxial layer 101 and between the junction termination extension region 102 and the edge of the epitaxial layer 101, and having a distance between it and both the junction termination extension region 102 and the edge of the epitaxial layer 101; a field plate structure 104 located on the upper surface of the epitaxial layer 101, extending from directly above the junction termination extension region 102 to directly above the cutoff ring 103; the end face of the field plate structure 104 adjacent to the edge of the epitaxial layer 101 is an inclined surface 1041, and has a distance between it and the outer edge of the cutoff ring 103; an interlayer dielectric layer 105 covering the field plate structure 104 and the exposed cutoff ring 103; and a cover dielectric layer 106 covering the interlayer dielectric layer 105.

[0065] In the chip structure of this application, by setting the interlayer dielectric layer 105 to completely cover the stop ring 103, and on the other hand, using a covering dielectric layer 106 to wrap the interlayer dielectric layer (ILD) 105, and the interlayer dielectric layer 105 wrapping the film edge structure of the field structure 104, the influence of moisture on the stop ring 103 is reduced. The stop ring 103 will not have the risk of electrochemical corrosion, will not have film interface delamination, and will not have corrosion points or microleakage channels. By setting the end face of the field structure 104 near the edge of the epitaxial layer 101 as an inclined surface, the interlayer dielectric layer 105 covers the field structure 104 and the stop ring 103, and the covering dielectric layer 106 covers the interlayer dielectric layer 105, which can effectively reduce stress concentration. The film transition at the edge of the chip structure 10 is more natural. Based on the combined effect of the above improvements, the long-term reliability of the chip structure under HV-H3TRB test conditions can be significantly improved.

[0066] As an example, the cutoff ring 103 can be an N-type cutoff ring or a P-type cutoff ring; the cutoff ring 103 can be a heavily doped region. In this example, the cutoff ring 103 is a heavily doped N-type region.

[0067] As an example, the junction termination extension region 102 can be a P-type doped region.

[0068] As an example, the width of the junction termination extension region 102 can be set according to actual needs. It can be greater than the thickness of the epitaxial layer 101, or less than or equal to the thickness of the epitaxial layer 101. In this embodiment, the thickness of the junction termination extension region 102 is greater than the thickness of the epitaxial layer 101.

[0069] As an example, the product of the doping concentration and the width of the junction termination extension region 102 is equal to the product of the doping concentration and the thickness of the epitaxial layer 101. This specific design can make the electric field distribution more uniform and reduce the electric field concentration phenomenon.

[0070] As an example, the interlayer dielectric layer 105 may extend from the upper surface of the field plate structure 104 via the inclined surface 1041 to the upper surface of the epitaxial layer 101; the orthographic projection of the interlayer dielectric layer 105 on the upper surface of the epitaxial layer 101 covers the orthographic projection of the field plate structure 104 on the upper surface of the epitaxial layer 101 and the stop ring 103, and the interlayer dielectric layer 105 has a gap with the edge of the epitaxial layer 101.

[0071] As an example, the interlayer dielectric layer 105 may include a first horizontal portion 1051, an inclined portion 1052, and a second horizontal portion 1053; wherein, the first horizontal portion 1051 covers the upper surface of the field plate structure 104, the inclined portion 1052 covers the inclined surface 1041 of the field plate structure 104, and the second horizontal portion 1053 covers the exposed stop ring 103; one end of the second horizontal portion 1053 away from the inclined portion 1052 extends to the space between the stop ring 103 and the edge of the epitaxial layer 101. The first horizontal portion 1051, the inclined portion 1052, and the second horizontal portion 1053 are integrally formed structures.

[0072] By setting the end face of the field plate structure 104 near the edge of the epitaxial layer 101 as an inclined surface, and setting the interlayer dielectric layer 105 covering the field plate structure 104 and the stop ring 103 as having a structure including a first horizontal part 1051, an inclined part 1052 and a second horizontal part 1053, neither the field plate structure 104 nor the interlayer dielectric layer 105 has sharp right angles, which can effectively reduce stress concentration, prevent the interlayer dielectric layer 105 from cracking and delaminating under HV-H3TRB testing, and prevent the intrusion of water vapor.

[0073] As an example, the distance between the end face of the second horizontal portion 1053 of the interlayer dielectric layer 105 away from the inclined portion 1052 and the stop ring 103 can be no less than one-fifth to one-third of the length of the second horizontal portion 1053, so as to ensure that the interlayer dielectric layer 105 can effectively cover the stop ring 103.

[0074] As an example, the interlayer dielectric layer 105 may include, but is not limited to, a silicon oxide layer.

[0075] As an example, in the interlayer dielectric layer 105, the connection between the upper surface of the first horizontal portion 1051 and the upper surface of the inclined portion 1052 can be arc-shaped to avoid stress concentration due to the presence of sharp corners.

[0076] As an example, the overlay dielectric layer 106 may extend from the upper surface of the interlayer dielectric layer 105 to the upper surface of the epitaxial layer 101, and have a gap with the edge of the epitaxial layer 101.

[0077] As an example, the overlay dielectric layer 106 may include, but is not limited to, a silicon nitride (SiN) layer. In other examples, the overlay dielectric layer 106 may also be other highly moisture-resistant dielectric layers, such as an aluminum nitride (AlN) layer, or a composite stack of aluminum nitride and silicon nitride layers.

[0078] As an example, each corner of the covering medium layer 106 can be rounded to avoid stress concentration caused by sharp corners.

[0079] As an example, the overlay dielectric layer 106 may include an integrally formed first portion (not shown) and a second portion (not shown); wherein the first portion covers the upper surface of the interlayer dielectric layer 105, and the second portion is located on the upper surface of the epitaxial layer 101 between the edge of the interlayer dielectric layer 105 and the epitaxial layer 101.

[0080] As an example, the length of the second part is not less than the length of the second horizontal part 1053, so as to ensure that the covering medium layer 106 and the interlayer medium layer 105 can effectively cover and isolate the stop ring 103.

[0081] As an example, the chip structure 10 may also include a molding layer 107 that covers the exposed upper surface of the dielectric layer 106 and the epitaxial layer 101.

[0082] Since the entire area of ​​the stop ring 103 is completely covered and wrapped by the interlayer dielectric layer 105 and the cover dielectric layer 106, it can ensure that the stop ring 103 and the molding compound 107 are completely physically and electrochemically isolated.

[0083] As an example, the material of the molding layer 107 can be an epoxy resin-based polymer material used for molding chips, which has a certain degree of water absorption.

[0084] As an example, since there is a gap between the edges of the covering dielectric layer 106 and the epitaxial layer 101, the molding compound 107 can cover not only the upper surface of the covering dielectric layer 106, but also the end face of the covering dielectric layer 106 and the exposed upper surface of the epitaxial layer 101. This allows the molding compound 107 to have a better bonding effect with the covering dielectric layer 106 and the epitaxial layer 101, and avoids delamination of the molding compound 107.

[0085] As an example, please continue reading Figure 1 and Figure 2 The epitaxial layer 101 may include a cell region 108 and a terminal region 109 located around the cell region 108, that is, the chip structure 10 may include a cell region 108 and a terminal region 109 located around the cell region 108; the junction termination extension region 102, the cutoff ring 103, the field plate structure 104, the interlayer dielectric layer 105 and the cover dielectric layer 106 are all located within the terminal region 109.

[0086] As an example, the chip structure 10 can be formed with either a planar terminal structure or a trench terminal structure.

[0087] As an example, chip structure 10 may also include a substrate structure ( Figure 1 and Figure 2 (Not shown) The epitaxial layer 101 may be located on the upper surface of the substrate structure.

[0088] As an example, the substrate structure may include, but is not limited to, a silicon carbide (SiC) substrate. The epitaxial layer 101 in this example may include, but is not limited to, a silicon carbide epitaxial layer.

[0089] In another embodiment, please refer to Figure 1 and Figure 2 See Figure 3 This application also provides a semiconductor device structure, which may include: a substrate structure 20; and multiple such... Figures 1 to 2 The chip structure 10 described in the corresponding embodiment is located on the upper surface of the substrate structure 20; the dicing channel 30 is located between each adjacent chip structure 10.

[0090] As an example, substrate structure 20 may include, but is not limited to, a silicon carbide (SiC) substrate; specifically, substrate structure 20 may include an N-type doped silicon carbide substrate. Epitaxial layer 101 in this example may include, but is not limited to, a silicon carbide epitaxial layer; specifically, epitaxial layer 101 may include an N-type doped silicon carbide epitaxial layer.

[0091] It should be noted that the chip structure 10 in the semiconductor device structure in this example does not include the substrate structure.

[0092] As an example, the dicing channel 30 surrounds each chip structure 10 to isolate the chip structures 10 from each other.

[0093] As an example, the dicing channel 30 can extend through the molding layer 107 into the epitaxial layer 101 along the thickness direction, or it can extend through the molding layer 107 and the epitaxial layer 101 along the thickness direction and into the substrate structure 20.

[0094] In yet another embodiment, please refer to Figure 4 This application also provides a method for fabricating a semiconductor device structure, which may include steps S10 to S17.

[0095] S10: Provides substrate structure.

[0096] S11: An epitaxial layer is formed on the upper surface of the substrate structure; the epitaxial layer includes multiple chip regions.

[0097] S12: Junction termination extension regions are formed in the epitaxial layer of each chip region.

[0098] S13: A cutoff ring is formed in the epitaxial layer of each chip region. The cutoff ring is located between the junction termination extension region and the edge of the chip region, and has a gap with both the junction termination extension region and the edge of the epitaxial layer.

[0099] S14: A field plate structure is formed on the upper surface of the epitaxial layer of each chip region. The field plate structure extends from directly above the junction termination extension region to directly above the cutoff ring. The end face of the field plate structure near the edge of the chip region is an inclined surface and has a gap with the outer edge of the cutoff ring.

[0100] S15: An interlayer dielectric layer is formed in each chip region, which covers the field plate structure and the exposed cutoff ring.

[0101] S16: A cover dielectric layer is formed in each chip area, and the cover dielectric layer covers the interlayer dielectric layer.

[0102] S17: Forming cleaving channels between adjacent chip regions.

[0103] In the above embodiments, by setting the interlayer dielectric layer to completely cover the stop ring, and on the other hand, by using a covering dielectric layer to wrap the interlayer dielectric layer (ILD), and the interlayer dielectric layer wrapping the film edge structure of the field structure, the influence of moisture on the stop ring is reduced. The stop ring will not be subject to electrochemical corrosion risk, and there will be no film interface delamination, corrosion points, or microleakage channels. By setting the end face of the edge of the field structure near the epitaxial layer as an inclined surface, and by having the interlayer dielectric layer cover the field structure and the stop ring, and the covering dielectric layer cover the interlayer dielectric layer, stress concentration can be effectively reduced. The film transition at the edge of the chip structure is more natural. Based on the combined effect of the above improvements, the long-term reliability of the chip structure under HV-H3TRB test conditions can be significantly improved.

[0104] As an example, in step S10, the provided substrate structure may include, but is not limited to, a silicon carbide substrate; specifically, the substrate structure may include an N-type doped silicon carbide substrate.

[0105] As an example, in step S11, please refer to Figure 5 The epitaxial layer 101 can be formed using, but is not limited to, epitaxial processes; the epitaxial layer 101 may include, but is not limited to, a silicon carbide epitaxial layer; specifically, the epitaxial layer 101 may include an N-type doped silicon carbide epitaxial layer.

[0106] For example, please refer to Figure 6 In step S12, forming a junction termination extension region 102 in the epitaxial layer 101 of each chip region may include the following steps: S121~S123.

[0107] S121: A first patterned mask layer (not shown) is formed on the upper surface of the epitaxial layer 101. The first patterned mask layer has a first opening in each chip region. The first opening defines the shape and position of the junction terminal extension region 102 of each chip region.

[0108] S122: P-type ion implantation is performed on the epitaxial layer 101 based on the first patterned mask layer to form a junction termination extension region 102 in the epitaxial layer 101 of each chip region.

[0109] S123: Remove the first patterned mask layer; specifically, the first patterned mask layer can be removed by etching or grinding processes.

[0110] As an example, the width of the junction termination extension region 102 can be set according to actual needs. It can be greater than the thickness of the epitaxial layer 101, or less than or equal to the thickness of the epitaxial layer 101. In this embodiment, the thickness of the junction termination extension region 102 is greater than the thickness of the epitaxial layer 101.

[0111] As an example, the product of the doping concentration and the width of the junction termination extension region 102 is equal to the product of the doping concentration and the thickness of the epitaxial layer 101. This specific design can make the electric field distribution more uniform and reduce the electric field concentration phenomenon.

[0112] For example, please refer to Figure 7 In step S13, forming a cutoff ring 103 in the epitaxial layer 101 of each chip region may include the following steps: S131~S133.

[0113] S131: A second patterned mask layer (not shown) is formed on the upper surface of the epitaxial layer 101. The second patterned mask layer has a second opening in each chip region. The second opening defines the shape and position of the cutoff ring 103 in each chip region.

[0114] S132: N-type ion implantation is performed on the epitaxial layer 101 based on the second patterned mask layer to form a cutoff ring 103 in the epitaxial layer 101 of each chip region.

[0115] S133: Remove the second patterned mask layer; specifically, the second patterned mask layer can be removed by etching or grinding processes.

[0116] For example, please refer to Figure 8 In step S14, a field plate structure 104 is formed on the upper surface of the epitaxial layer 101 in each chip region, which may include the following steps: S141~S142.

[0117] S141: A field plate structure material layer (not shown) is formed on the upper surface of the epitaxial layer 101; specifically, the field plate structure material layer may be formed by a deposition process, but is not limited to that used; the field plate structure material layer may include, but is not limited to, a polysilicon layer.

[0118] S142: The field plate structure material layer is etched using photolithography etching process to obtain the field plate structure 104.

[0119] For example, please refer to Figure 9 In step S15, forming an interlayer dielectric layer 105 in each chip region may include the following steps: S151~S152.

[0120] S151: An interlayer dielectric material layer (not shown) is formed on the surface of the epitaxial layer 101; specifically, the interlayer dielectric material layer may be formed using a deposition process, but not limited to the deposition process; the interlayer dielectric material layer may include, but is not limited to, a silicon oxide layer.

[0121] S152: The interlayer dielectric material layer is etched using a photolithography etching process to obtain the interlayer dielectric layer 105.

[0122] As an example, the interlayer dielectric layer 105 may include a first horizontal portion 1051, an inclined portion 1052, and a second horizontal portion 1053; wherein, the first horizontal portion 1051 covers the upper surface of the field plate structure 104, the inclined portion 1052 covers the inclined surface 1041 of the field plate structure 104, and the second horizontal portion 1053 covers the exposed stop ring 103; one end of the second horizontal portion 1053 away from the inclined portion 1052 extends to the space between the stop ring 103 and the edge of the epitaxial layer 101. The first horizontal portion 1051, the inclined portion 1052, and the second horizontal portion 1053 are integrally formed structures.

[0123] By setting the end face of the field plate structure 104 near the edge of the epitaxial layer 101 as an inclined surface, and setting the interlayer dielectric layer 105 covering the field plate structure 104 and the stop ring 103 as having a structure including a first horizontal part 1051, an inclined part 1052 and a second horizontal part 1053, neither the field plate structure 104 nor the interlayer dielectric layer 105 has sharp right angles, which can effectively reduce stress concentration, prevent the interlayer dielectric layer 105 from cracking and delaminating under HV-H3TRB testing, and prevent the intrusion of water vapor.

[0124] For example, please refer to Figure 10 In step S16, forming a cover medium layer 106 in each chip region may include the following steps: S161~S162.

[0125] S161: Form a cover dielectric material layer (not shown); specifically, the cover dielectric material layer may be formed using a deposition process, but not limited to; the cover dielectric material layer may include, but is not limited to, a silicon nitride layer; in other examples, the cover dielectric material layer may also be other highly moisture-resistant dielectric layers, such as an aluminum nitride layer, or a composite stack of aluminum nitride and silicon nitride layers.

[0126] S162: The cover dielectric layer material layer is etched using photolithography etching process to obtain the cover dielectric layer 106.

[0127] For example, please refer to Figure 11 After step S16, the following steps are also included:

[0128] A molding layer 107 is formed, which covers the exposed upper surface of the dielectric layer 106 and the epitaxial layer 101.

[0129] As an example, the material of the molding layer 107 can be an epoxy resin-based polymer material used for molding chips, which has a certain degree of water absorption.

[0130] As an example, in step S17, an etching process can be used to form cleavage paths between adjacent chip regions.

[0131] As an example, the dicing path can penetrate the molding layer 107 along the thickness direction and extend into the epitaxial layer 101, or it can penetrate the molding layer 107 and the epitaxial layer 101 along the thickness direction and extend into the substrate structure 20.

[0132] As an example, please continue reading Figure 1 Each chip region includes a cell region 108 and a terminal region 109 located around the cell region 108; the junction terminal extension region 102, the cutoff ring 103, the field plate structure 104, the interlayer dielectric layer 105, and the cover dielectric layer 106 are all located within the terminal region 109.

[0133] In yet another embodiment, please refer to Figure 12 This application also provides a method for fabricating a chip structure, the method comprising the following steps S20-S21:

[0134] S20: Adopted Figures 4 to 11 The semiconductor device structure is prepared by the method described in the corresponding embodiment.

[0135] S21: The semiconductor device structure is diced using a self-dicing channel to obtain multiple chip structures.

[0136] In the chip structure prepared in the above embodiments, by setting an interlayer dielectric layer to completely cover the stop ring, and by using a covering dielectric layer to wrap the interlayer dielectric layer (ILD), and the interlayer dielectric layer wrapping the edge structure of the field structure, the influence of moisture on the stop ring is reduced. The stop ring will not be subject to electrochemical corrosion risk, and there will be no film interface delamination, corrosion points, or microleakage channels. By setting the end face of the edge of the field structure near the epitaxial layer as an inclined surface, and by having the interlayer dielectric layer cover the field structure and the stop ring, and the covering dielectric layer cover the interlayer dielectric layer, stress concentration can be effectively reduced. The transition of the film layers at the edge of the chip structure is more natural. Based on the combined effect of the above improvements, the long-term reliability of the chip structure under HV-H3TRB test conditions can be significantly improved.

[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A chip structure, characterized in that, include: Epitaxial layer; The terminal extension region is located within the epitaxial layer; The cutoff ring is located within the epitaxial layer and between the junction termination extension region and the edge of the epitaxial layer, and is spaced from both the junction termination extension region and the edge of the epitaxial layer. A field plate structure is located on the upper surface of the epitaxial layer, extending from directly above the junction terminal extension region to directly above the stop ring; the end face of the field plate structure near the edge of the epitaxial layer is an inclined surface, and there is a gap between it and the outer edge of the stop ring; An interlayer dielectric layer covers the field plate structure and the exposed stop ring; Covering the dielectric layer, covering the interlayer dielectric layer.

2. The chip structure according to claim 1, characterized in that, The interlayer dielectric layer extends from the upper surface of the field plate structure through the inclined surface to the upper surface of the epitaxial layer; The orthographic projection of the interlayer dielectric layer on the upper surface of the epitaxial layer covers the orthographic projection of the field plate structure on the upper surface of the epitaxial layer and the cutoff ring, and has a gap with the edge of the epitaxial layer; The covering dielectric layer extends from the upper surface of the interlayer dielectric layer to the upper surface of the epitaxial layer, and has a gap with the edge of the epitaxial layer.

3. The chip structure according to claim 1, characterized in that, It also includes a molding compound that covers the exposed upper surface of the overlay dielectric layer and the epitaxial layer.

4. The chip structure according to claim 1, characterized in that, The epitaxial layer includes a cell region and a terminal region located around the cell region; the junction terminal extension region, the stop ring, the field plate structure, the interlayer dielectric layer and the cover dielectric layer are located within the terminal region.

5. The chip structure according to any one of claims 1 to 4, characterized in that, It also includes a substrate structure, wherein the epitaxial layer is located on the upper surface of the substrate structure.

6. A semiconductor device structure, characterized in that, include: Substrate structure; Multiple chip structures as described in any one of claims 1 to 4 are located on the upper surface of the substrate structure; The cutting channels are located between each adjacent chip structure.

7. A method for fabricating a semiconductor device structure, characterized in that, include: Provide substrate structure; An epitaxial layer is formed on the upper surface of the substrate structure; the epitaxial layer includes multiple chip regions. A junction termination extension region is formed within the epitaxial layer of each of the aforementioned chip regions; A cutoff ring is formed in the epitaxial layer of each chip region. The cutoff ring is located between the junction termination extension region and the edge of the chip region, and is spaced from both the junction termination extension region and the edge of the epitaxial layer. A field plate structure is formed on the upper surface of the epitaxial layer of each of the chip regions. The field plate structure extends from directly above the junction terminal extension region to directly above the cutoff ring. The end face of the field plate structure near the edge of the chip region is an inclined surface and has a gap with the outer edge of the cutoff ring. An interlayer dielectric layer is formed in each of the chip regions, the interlayer dielectric layer covering the field plate structure and the exposed cutoff ring; A cover dielectric layer is formed in each of the chip regions, and the cover dielectric layer covers the interlayer dielectric layer; Cutting channels are formed between each adjacent chip region.

8. The method for fabricating a semiconductor device structure according to claim 7, characterized in that, Before forming a cleaving track between each adjacent chip region, the method further includes: A molding layer is formed, which covers the exposed upper surface of the overlay dielectric layer and the epitaxial layer; the cut path penetrates the molding layer and extends into the epitaxial layer.

9. The method for fabricating a semiconductor device structure according to claim 7, characterized in that, Each of the chip regions includes a cell region and a terminal region located around the cell region; the junction terminal extension region, the cutoff ring, the field plate structure, the interlayer dielectric layer, and the cover dielectric layer are all located within the terminal region.

10. A method for fabricating a chip structure, characterized in that, include: The semiconductor device structure is prepared using the method described in any one of claims 7 to 9; The semiconductor device structure is diced from the dicing line to obtain multiple chip structures.

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