MOS device and forming method
By adding a low-doped region to the LDD region in the NMOS device, the hot carrier effect problem caused by the narrow NLDD region in the NMOS device is solved, the breakdown voltage of the NMOS device is improved, and the performance of the PMOS device is not affected.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-01-27
- Publication Date
- 2026-05-01
AI Technical Summary
In existing NMOS devices, the NLDD region within the P-type well region located on both sides of the second gate polysilicon is too narrow to withstand operating voltages of 7V and above, leading to hot carrier effects and causing NMOS device failure.
During the formation of an NMOS device, the area of the low-doped region in the LDD region is increased by forming a first NLDD region in the N-type well region on both sides of the first gate polysilicon and a second NLDD region in the P-type well region on both sides of the second gate polysilicon, so that its edge is aligned with the gate edge. At the same time, an N+ region and a PLDD region are formed in the NLDD region, and the edge of the PLDD region is aligned with the sidewall edge.
By increasing the area of the low-doped region, the hot carrier effect of the NMOS device is reduced, and the breakdown voltage of the NMOS device is improved, without affecting the PLDD region area of the PMOS device.
Smart Images
Figure CN121968635A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a MOS device and its fabrication method. Background Technology
[0002] MOS (Metal-Oxide-Semiconductor) devices have been widely used in consumer electronics and communication electronics products. MOS devices are divided into PMOS devices and NMOS devices, which can be formed simultaneously on a wafer.
[0003] Please refer to Figure 1 The prior art MOS device includes a substrate 101, an N-type well region 102, a shallow trench isolation structure 103, and a P-type well region 104 located within the substrate 101. The shallow trench isolation structure 103 separates the N-type well region 102 and the P-type well region 104. A gate oxide layer 105 is located on the surface of the substrate 101, and a first gate polysilicon 106 and a second gate polysilicon 107 are located on the surface of the gate oxide layer 105. The first gate polysilicon 106 is located in the N-type well region 102, and the second gate polysilicon 107 is located in the P-type well region 104. First sidewalls 108 are formed on both sides of the first gate polysilicon 106, and the first sidewalls 108, the first gate polysilicon 106, and the gate oxide layer 105 are separated by an L-shaped first ONO layer 109. Second sidewalls 110 are formed on both sides of the second gate polysilicon 107, and the second sidewalls 110 and the second gate polysilicon 107 and the gate oxide layer 105 are separated by an L-shaped second ONO layer 111. A PLDD region 112 and a P+ region 113 located within the PLDD region 112 are formed in the N-type well region 102 on both sides of the first gate polysilicon 106. An NLDD region 114 and an N+ region 115 located within the NLDD region 114 are formed in the P-type well region 104 on both sides of the second gate polysilicon 107. The formation process involves sequentially forming the N-type well region 102, the P-type well region 104, the first gate polysilicon 106, the second gate polysilicon 107, the first ONO layer 109, the second ONO layer 111, the first sidewall 108, the second sidewall 110, the NLDD region 114, the N+ region 115, the PLDD region 112, and the P+ region 113.
[0004] However, product analysis revealed that some NMOS devices exhibited hot carrier effects, leading to device failure. Analysis of the failed NMOS devices showed that the NLDD region within the P-type well region 104 located on both sides of the second gate polysilicon 107 was too narrow, unable to withstand operating voltages of 7V and above, resulting in hot carrier effects and ultimately device failure. PMOS devices, on the other hand, possess superior resistance to hot carrier injection. Summary of the Invention
[0005] The purpose of this invention is to provide a MOS device and a method for forming it, which can increase the area of the low-doped region formed in the LDD region of an NMOS device, thereby reducing the hot carrier effect of the NMOS device.
[0006] To achieve the above objectives, the present invention provides a method for forming a MOS device, comprising:
[0007] A substrate is provided in which an N-type well region and a P-type well region are formed, and the N-type well region and the P-type well region are separated by a shallow trench isolation structure;
[0008] A first gate polysilicon is formed on the surface of the N-type well region, and a second gate polysilicon is formed on the surface of the P-type well region;
[0009] Simultaneously, ions are implanted into the N-type well region and the P-type well region to form a first NLDD region in the N-type well region on both sides of the first gate polysilicon, with the edge of the first NLDD region aligned with the edge of the first gate polysilicon. A second NLDD region is formed in the P-type well region on both sides of the second gate polysilicon, with the edge of the second NLDD region aligned with the edge of the second gate polysilicon.
[0010] A first sidewall is formed on both sides of the first gate, and the first sidewall is separated from the first gate by a first ONO layer. A second sidewall is formed on both sides of the second gate, and the second sidewall is separated from the second gate by a second ONO layer.
[0011] The N-type well region is covered, and ions are injected into the P-type well region to form an N+ region within the second NLDD region, with the edge of the N+ region aligned with the edge of the second sidewall.
[0012] The P-type well region is covered, and ions are injected into the N-type well region. The concentration of injected ions is greater than that of the ions injected when forming the first NLDD region, so as to form a PLDD region in the first NLDD region. The edge of the PLDD region is aligned with the edge of the first sidewall.
[0013] The P-type well region is covered, and ions are injected into the N-type well region to form a P+ region within the PLDD region, with the edge of the P+ region aligned with the edge of the first sidewall.
[0014] Optionally, the method for forming the MOS device includes:
[0015] The first ONO layer also separates the first sidewall from the gate oxide layer, and the second ONO layer also separates the second sidewall from the gate oxide layer.
[0016] Optionally, in the method for forming the MOS device, a first photoresist layer is formed, which covers the N-type well region, and ions are implanted into the P-type well region to form an N+ region in the second NLDD region, wherein the edge of the N+ region is aligned with the edge of the second sidewall.
[0017] Optionally, in the method for forming the MOS device, a second photoresist layer is formed, which covers the P-type well region, and ions are implanted into the N-type well region. The concentration of implanted ions is greater than that of the ions implanted when forming the first NLDD region, so as to form a PLDD region in the first NLDD region, and the edge of the PLDD region is aligned with the edge of the first sidewall.
[0018] Optionally, in the method for forming the MOS device, the second photoresist layer covers the P-type well region, and ions are implanted into the N-type well region to form a P+ region in the PLDD region, wherein the edge of the P+ region is aligned with the edge of the first sidewall.
[0019] Optionally, in the method for forming the MOS device, N-type ions are simultaneously implanted into the N-type well region and the P-type well region to form a first NLDD region in the N-type well region on both sides of the first gate polysilicon, with the edge of the first NLDD region aligned with the edge of the first gate polysilicon. A second NLDD region is formed in the P-type well region on both sides of the second gate polysilicon, with the edge of the second NLDD region aligned with the edge of the second gate polysilicon.
[0020] Optionally, in the method of forming the MOS device, the N-type well region is covered, and N-type ions are implanted into the P-type well region to form an N+ region in the second NLDD region, wherein the edge of the N+ region is aligned with the edge of the second sidewall.
[0021] Optionally, in the method for forming the MOS device, the P-type well region is covered, and P-type ions are implanted into the N-type well region. The concentration of the implanted ions is greater than that of the ions implanted when forming the first NLDD region, so as to form a PLDD region within the first NLDD region, wherein the edge of the PLDD region is aligned with the edge of the first sidewall.
[0022] Optionally, in the method for forming the MOS device, the P-type well region is covered, and P-type ions are implanted into the N-type well region to form a P+ region in the PLDD region, wherein the edge of the P+ region is aligned with the edge of the first sidewall.
[0023] The present invention also provides a MOS device, comprising:
[0024] A substrate in which an N-type well region and a P-type well region are formed, the N-type well region and the P-type well region being separated by a shallow trench isolation structure;
[0025] The first gate polysilicon located on the surface of the N-type well region, and the second gate polysilicon located on the surface of the P-type well region;
[0026] The first NLDD region is located in the N-type well region on both sides of the first gate polysilicon, and the edge of the first NLDD region is aligned with the edge of the first gate polysilicon. The second NLDD region is located in the P-type well region on both sides of the second gate polysilicon, and the edge of the second NLDD region is aligned with the edge of the second gate polysilicon.
[0027] A first sidewall located on both sides of the first gate, the first sidewall being separated from the first gate by a first ONO layer; and a second sidewall located on both sides of the second gate, the second sidewall being separated from the second gate by a second ONO layer.
[0028] The N+ region is located within the second NLDD region, and the edge of the N+ region is aligned with the edge of the second sidewall.
[0029] A PLDD area located within the first NLDD area, wherein the edge of the PLDD area is aligned with the edge of the first sidewall;
[0030] The P+ area is located within the PLDD area, and the edge of the P+ area is aligned with the edge of the first sidewall.
[0031] In the MOS device and formation method provided by this invention, before forming the first and second sidewalls, a first NLDD region is formed in the N-type well regions on both sides of the first gate polysilicon, with the edge of the first NLDD region aligned with the edge of the first gate polysilicon. A second NLDD region is formed in the P-type well regions on both sides of the second gate polysilicon, with the edge of the second NLDD region aligned with the edge of the second gate polysilicon. Before and after forming the first and second sidewalls, a PLDD region is formed in the first NLDD region, with the edge of the PLDD region aligned with the edge of the first sidewall. This invention increases the area of the low-doped region formed in the LDD region of the NMOS device, reducing the hot carrier effect of the NMOS device. Furthermore, it does not change the area of the PLDD region in the PMOS device. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of the structure of a MOS device in the prior art;
[0033] Figure 2 This is a flowchart of a method for forming a MOS device according to an embodiment of the present invention;
[0034] Figures 3 to 8 This is a schematic diagram of the structure during the formation process of the MOS device according to an embodiment of the present invention;
[0035] In the diagram: 101-substrate, 102-N-type well region, 103-shallow trench isolation structure, 104-P-type well region, 105-gate oxide layer, 106-first gate polysilicon, 107-second gate polysilicon, 108-first sidewall, 109-first ONO layer, 110-second sidewall, 111-second ONO layer, 112-PLDD region, 113-P+ region, 114-NLDD region, 115-N+ region, 201-substrate, 202-gate oxide layer. 203-Shallow trench isolation structure, 204-N-type well region, 205-P-type well region, 206-First gate polysilicon, 207-Second gate polysilicon, 208-First NLDD region, 209-Second NLDD region, 210-First sidewall, 212-Second sidewall, 211-First ONO layer, 213-Second ONO layer, 214-First photoresist layer, 215-N+ region, 216-Second photoresist layer, 217-PLDD region, 218-P+ region. Detailed Implementation
[0036] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0037] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0038] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.
[0039] Please refer to Figure 2 The present invention provides a method for forming a MOS device, comprising:
[0040] S11: Provides a substrate in which N-type well regions (NWELL) and P-type well regions (PWELL) are formed, and the N-type well regions and P-type well regions are separated by a shallow trench isolation structure;
[0041] S12: A first gate polysilicon is formed on the surface of the N-type well region, and a second gate polysilicon is formed on the surface of the P-type well region;
[0042] S13: Simultaneously implant ions into the N-type well region and the P-type well region to form a first NLDD region in the N-type well region on both sides of the first gate polysilicon, with the edge of the first NLDD region aligned with the edge of the first gate polysilicon; and form a second NLDD region in the P-type well region on both sides of the second gate polysilicon, with the edge of the second NLDD region aligned with the edge of the second gate polysilicon.
[0043] S14: A first sidewall is formed on both sides of the first gate, and the first sidewall is separated from the first gate by a first ONO layer. A second sidewall is formed on both sides of the second gate, and the second sidewall is separated from the second gate by a second ONO layer.
[0044] S15: Cover the N-type trap region and inject ions into the P-type trap region to form an N+ region in the second NLDD region, with the edge of the N+ region aligned with the edge of the second sidewall.
[0045] S16: Cover the P-type well region and inject ions into the N-type well region. The concentration of injected ions is greater than that of the ions injected when forming the first NLDD region, so as to form a PLDD region in the first NLDD region. The edge of the PLDD region is aligned with the edge of the first sidewall.
[0046] S17: Cover the P-type well region and inject ions into the N-type well region to form a P+ region within the PLDD region, with the edge of the P+ region aligned with the edge of the first sidewall.
[0047] Please refer to Figure 3 A substrate 201 is provided, which may be a silicon wafer. An N-type well region 204, a shallow trench isolation structure 203, and a P-type well region 205 are formed in the substrate 201. The shallow trench isolation structure 203 separates the N-type well region 204 and the P-type well region 205. The N-type well region 204 is used to form a PMOS device, and the P-type well region 205 is used to form an NMOS device. Simultaneously, a shallow trench isolation structure can also be formed in the N-type well region to divide the N-type well into multiple parts, thereby forming multiple PMOS device structures. Similarly, a shallow trench isolation structure can also be formed in the P-type well region to divide the P-type well into multiple parts, thereby forming multiple NMOS device structures.
[0048] Before forming the N-type well region 204, the shallow trench isolation structure 203, and the P-type well region 205, oxides, such as silicon dioxide, can be deposited on the surface of the substrate. Next, the shallow trench isolation structure 203 is formed, and ions are implanted into the substrate 201 to form the N-type well region 204 and the P-type well region 205, respectively. Therefore, the deposited oxides serve as gate oxide layers 202 on the surfaces of the N-type well region 204 and the P-type well region 205, respectively. A first gate polysilicon 206 and a second gate polysilicon 207 are formed on the surface of the gate oxide layers 202, respectively.
[0049] Next, please refer to Figure 4 N-type ions are implanted into the N-type well regions 204 and P-type well regions 205 in a direction perpendicular to the surfaces of the N-type well regions 204 and 205, to form first NLDD regions 208 in the N-type well regions 204 on both sides of the first gate polysilicon 206. The first NLDD regions 208 are located on both sides of the first gate polysilicon 206, and their edges are aligned with the edges of the first gate polysilicon 206. Second NLDD regions 209 are formed in the P-type well regions 205 on both sides of the second gate polysilicon 207. The second NLDD regions 209 are located on both sides of the second gate polysilicon 207, and their edges are aligned with the edges of the second gate polysilicon 207.
[0050] Next, please refer to Figure 5 A first sidewall 210 is formed on the surface of the gate oxide layer 202 on both sides of the first gate polysilicon 206, and a second sidewall 212 is formed on the surface of the gate oxide layer 202 on both sides of the second gate polysilicon 207. Before forming the first sidewall 210 and the second sidewall 212, a first ONO layer 211 and a second ONO layer 213 are formed, both of which are L-shaped. The first ONO layer 211 separates the first sidewall 210 from the first gate polysilicon 206 and the gate oxide layer 202, and the second ONO layer 213 separates the second sidewall 212 from the second gate polysilicon 207 and the gate oxide layer 202. Therefore, the first sidewall 210 and the first ONO layer 211 cover a portion of the first NLDD region 208, and the second sidewall 212 and the second ONO layer 213 cover a portion of the second NLDD region 209.
[0051] Next, please refer to Figure 6 A first photoresist layer 214 is formed, covering the gate oxide layer 202, the first gate polysilicon 206, the first ONO layer 211, and the first sidewall 210 of the N-type well region 204. N-type ions are implanted into the P-type well region 205 on a surface perpendicular to it. An N+ region 215 is formed within the second NLDD region 209, with the edge of the N+ region 215 aligned with the edge of the second sidewall 212.
[0052] Next, please refer to Figure 7 The first photoresist layer 214 is removed to form a second photoresist layer 216, which covers the gate oxide layer 202, the second gate polysilicon layer 207, the second ONO layer 213, and the second sidewall 211 of the P-type well region 205. P-type ions are implanted into the N-type well region 204 on a surface perpendicular to it, with the concentration of P-type ions being greater than the concentration of N-type ions implanted within the N-type well region 204. A PLDD region 217 is formed within the first NLDD region 208, with the edge of the PLDD region 217 aligned with the edge of the first sidewall 210. P-type ions are further implanted into the N-type well region 204 on a surface perpendicular to it, forming a P+ region 218 within the PLDD region 217, with the edge of the P+ region 218 aligned with the edge of the first sidewall 210. Next, please refer to... Figure 8 Remove the second photoresist layer.
[0053] In summary, in the MOS device and formation method provided in this embodiment of the invention, before forming the first and second sidewalls, a first NLDD region is formed in the N-type well regions on both sides of the first gate polysilicon, with the edge of the first NLDD region aligned with the edge of the first gate polysilicon. A second NLDD region is formed in the P-type well regions on both sides of the second gate polysilicon, with the edge of the second NLDD region aligned with the edge of the second gate polysilicon. Before and after forming the first and second sidewalls, a PLDD region is formed in the first NLDD region, with the edge of the PLDD region aligned with the edge of the first sidewall. This invention increases the area of the low-doped region formed in the LDD region of the NMOS device, reducing the hot carrier effect of the NMOS device. Furthermore, it does not change the area of the PLDD region in the PMOS device.
[0054] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for forming a MOS device, characterized in that, include: A substrate is provided in which an N-type well region and a P-type well region are formed, and the N-type well region and the P-type well region are separated by a shallow trench isolation structure; A first gate polysilicon is formed on the surface of the N-type well region, and a second gate polysilicon is formed on the surface of the P-type well region; Simultaneously, ions are implanted into the N-type well region and the P-type well region to form a first NLDD region in the N-type well region on both sides of the first gate polysilicon, with the edge of the first NLDD region aligned with the edge of the first gate polysilicon. A second NLDD region is formed in the P-type well region on both sides of the second gate polysilicon, with the edge of the second NLDD region aligned with the edge of the second gate polysilicon. A first sidewall is formed on both sides of the first gate, and the first sidewall is separated from the first gate by a first ONO layer. A second sidewall is formed on both sides of the second gate, and the second sidewall is separated from the second gate by a second ONO layer. The N-type well region is covered, and ions are injected into the P-type well region to form an N+ region within the second NLDD region, with the edge of the N+ region aligned with the edge of the second sidewall. The P-type well region is covered, and ions are injected into the N-type well region. The concentration of injected ions is greater than that of the ions injected when forming the first NLDD region, so as to form a PLDD region in the first NLDD region. The edge of the PLDD region is aligned with the edge of the first sidewall. The P-type well region is covered, and ions are injected into the N-type well region to form a P+ region within the PLDD region, with the edge of the P+ region aligned with the edge of the first sidewall.
2. The method for forming a MOS device as described in claim 1, characterized in that, The first ONO layer also separates the first sidewall from the gate oxide layer, and the second ONO layer also separates the second sidewall from the gate oxide layer.
3. The method for forming a MOS device as described in claim 1, characterized in that, A first photoresist layer is formed to cover the N-type well region, and ions are implanted into the P-type well region to form an N+ region in the second NLDD region, with the edge of the N+ region aligned with the edge of the second sidewall.
4. The method for forming a MOS device as described in claim 1, characterized in that, A second photoresist layer is formed to cover the P-type well region. Ions are implanted into the N-type well region. The concentration of implanted ions is greater than that of the ions implanted when forming the first NLDD region, so as to form a PLDD region in the first NLDD region. The edge of the PLDD region is aligned with the edge of the first sidewall.
5. The method for forming a MOS device as described in claim 4, characterized in that, The second photoresist layer covers the P-type well region, and ions are implanted into the N-type well region to form a P+ region within the PLDD region, with the edge of the P+ region aligned with the edge of the first sidewall.
6. The method for forming a MOS device as described in claim 1, characterized in that, Simultaneously, N-type ions are implanted into the N-type well region and the P-type well region to form a first NLDD region in the N-type well region on both sides of the first gate polysilicon, with the edge of the first NLDD region aligned with the edge of the first gate polysilicon. A second NLDD region is formed in the P-type well region on both sides of the second gate polysilicon, with the edge of the second NLDD region aligned with the edge of the second gate polysilicon.
7. The method for forming a MOS device as described in claim 1, characterized in that, The N-type well region is covered, and N-type ions are injected into the P-type well region to form an N+ region within the second NLDD region, with the edge of the N+ region aligned with the edge of the second sidewall.
8. The method for forming a MOS device as described in claim 1, characterized in that, The P-type well region is covered, and P-type ions are injected into the N-type well region. The concentration of injected ions is greater than that of the ions injected when forming the first NLDD region, so as to form a PLDD region within the first NLDD region. The edge of the PLDD region is aligned with the edge of the first sidewall.
9. The method for forming a MOS device as described in claim 1, characterized in that, The P-type well region is covered, and P-type ions are injected into the N-type well region to form a P+ region within the PLDD region, with the edge of the P+ region aligned with the edge of the first sidewall.
10. A MOS device formed using the method for forming a MOS device according to any one of claims 1 to 9, characterized in that, include: A substrate in which N-type well regions and P-type well regions are formed, and the N-type well regions and P-type well regions are separated by a shallow trench isolation structure; The first gate polysilicon located on the surface of the N-type well region, and the second gate polysilicon located on the surface of the P-type well region; The first NLDD region is located in the N-type well region on both sides of the first gate polysilicon, and the edge of the first NLDD region is aligned with the edge of the first gate polysilicon. The second NLDD region is located in the P-type well region on both sides of the second gate polysilicon, and the edge of the second NLDD region is aligned with the edge of the second gate polysilicon. The first sidewalls are located on both sides of the first gate, and the first sidewalls are separated from the first gate by a first ONO layer; the second sidewalls are located on both sides of the second gate, and the second sidewalls are separated from the second gate by a second ONO layer. The N+ region is located within the second NLDD region, and the edge of the N+ region is aligned with the edge of the second sidewall. A PLDD area located within the first NLDD area, wherein the edge of the PLDD area is aligned with the edge of the first sidewall; The P+ area is located within the PLDD area, and the edge of the P+ area is aligned with the edge of the first sidewall.