Fin field effect transistor

Abstract

The invention provides a fin type field effect transistor which comprises a semiconductor substrate, a fin-shaped structure and a gate structure, the fin-shaped structure and the gate structure are located above the semiconductor substrate, the fin-shaped structure comprises a source electrode region, a drain electrode region and a channel region located between the source electrode region and the drain electrode region, and the gate structure is arranged across the channel region; the fin-shaped structure further comprises a punch-through region which is doped with the source region in the same type, the punch-through region is located between the source region and the drain region, and the punch-through region, the source region, the drain region and the channel region are arranged in a non-contact mode. The part of the fin-shaped structure wrapping the punch-through region and the punch-through region are used for forming a first PN junction, the source region and the surrounding fin-shaped structure part are used for forming a second PN junction, and the drain region and the surrounding fin-shaped structure part are used for forming a third PN junction; contact interfaces exist between the first PN junction and the second PN junction, between the first PN junction and the third PN junction and between the first PN junction and the channel region; when the fin field effect transistor is in a turn-off state, the first PN junction is a fully depleted region. The effective current of the device can be increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more particularly to a fin field-effect transistor. Background Technology

[0002] With the continuous development of integrated circuits, and in order to continuously reduce device size, traditional MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices have begun to change. From the initial planar structure (such as Planar MOSFET), to the introduction of HKMG (High-K Metal Gate), then to FinFET (Fin Field-Effect Transistor) structure, and now to GAAFET (Gate-All-Around Field-Effect Transistor) structure, Moore's Law continues to firmly guide the development of the entire integrated circuit field. Schematic diagrams of Planar MOSFET, FinFET, and GAAFET structures are shown below. Figure 1 As shown.

[0003] Ideally, transistor development boils down to three things: ① allowing as much current as possible to flow when turned on (i.e., increasing effective current); ② allowing as little current as possible to flow when turned off (i.e., reducing leakage current); and ③ switching between on and off states as quickly as possible (i.e., improving device switching performance). Therefore, based on existing FinFET research, there is an urgent need for a new type of FinFET device to further increase the effective current allowed to flow when the device is turned on. Summary of the Invention

[0004] Therefore, embodiments of this application provide a fin field-effect transistor that can significantly increase the effective current of the device.

[0005] One aspect of this application provides a fin field-effect transistor, which includes a semiconductor substrate and a fin structure and a gate structure located above the semiconductor substrate. The fin structure includes a source region, a drain region, and a channel region located between the source region and the drain region, and the gate structure is disposed across the channel region. The fin structure also includes a punch-through region that is doped in the same way as the source region. The punch-through region is located between the source region and the drain region, and the punch-through region is non-contact with the source region, the drain region and the channel region, respectively. The finned structure surrounding the through-hole region forms the first PN junction; the source region and its surrounding finned structure form the second PN junction; and the drain region and its surrounding finned structure form the third PN junction. The first PN junction has contact interfaces with the second PN junction, the third PN junction, and the channel region, respectively. When the fin field-effect transistor is in the off state, the first PN junction is a fully depleted region; wherein, the first PN junction includes a punch-through region and a channel region.

[0006] In some embodiments of this application, when the fin field-effect transistor is in the on state, the fin field-effect transistor is used to form a first electronic channel in the channel region between the source region and the drain region, and part or all of the fully depleted region forms a second electronic channel between the source region and the drain region that has a contact interface with the first electronic channel, so as to increase the effective current between the source region and the drain region.

[0007] In some embodiments of this application, the fin field-effect transistor further includes a source terminal, a drain terminal, and a gate terminal; One end of the source terminal is connected to the source region of the fin field-effect transistor, and the other end is connected to an external circuit; one end of the drain terminal is connected to the drain region of the fin field-effect transistor, and the other end is connected to an external circuit; one end of the gate terminal is connected to the gate structure, and the other end is connected to an external circuit.

[0008] In some embodiments of this application, the fin field-effect transistor further includes a gate dielectric layer located between the channel region and the gate structure.

[0009] In some embodiments of this application, the gate dielectric layer is a thin film layer prepared using a high dielectric constant material.

[0010] In some embodiments of this application, the fin field-effect transistor further includes a gate oxide structure located between the gate structure and the semiconductor substrate.

[0011] In some embodiments of this application, the fin field-effect transistor further includes a substrate having regions for forming the fin field-effect transistor.

[0012] In some embodiments of this application, the semiconductor substrate is a silicon-based substrate, the fin structure is a silicon epitaxial structure, the gate structure is a structure prepared using metal materials or polycrystalline silicon, and the source region and drain region are homotype doped regions.

[0013] In some embodiments of this application, the fin structure extends along a direction parallel to the upper surface of the semiconductor substrate, and the fin structure is arranged perpendicular to the gate structure.

[0014] In some embodiments of this application, when the fin field-effect transistor includes multiple fin structures, the fin structures are arranged in an array.

[0015] The FinFET proposed in this application adds a punch-through region to the existing FinFET, which not only theoretically increases the device's voltage withstand range, but also, in the off state, the first PN junction corresponding to the punch-through region is designed as a fully depleted region, making it easier for carriers in the channel region to reach the punch-through region when the device is turned on, thereby forming a second electron channel. Therefore, the novel FinFET proposed in this application can effectively increase the current density when the device is turned on, and further reduce leakage current by means of the first PN junction.

[0016] Additional advantages, objectives, and features of this application will be set forth in part in the description which follows, and will in part become apparent to those skilled in the art upon review of the following description, or may be learned by practice of the application. The objectives and other advantages of this application can be realized and obtained by means of the structures specifically pointed out in the specification and drawings.

[0017] Those skilled in the art will understand that the purposes and advantages that can be achieved with this application are not limited to those specifically described above, and that the above and other purposes that this application can achieve will be more clearly understood from the following detailed description. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, do not constitute a limitation thereof. The components in the drawings are not drawn to scale but are merely for illustrating the principles of this application. For ease of illustration and description of certain parts of this application, corresponding portions in the drawings may be enlarged, i.e., may appear larger relative to other components in an exemplary device actually manufactured according to this application. In the drawings: Figure 1 This is a schematic diagram of the structure of Planar MOSFET, FinFET, and GAAFET.

[0019] Figure 2 This is a schematic diagram of the structure of the novel fin field-effect transistor proposed in this application, as shown in one embodiment.

[0020] Figure 3 This is a schematic diagram of the fin field-effect transistor in the off state according to one embodiment of this application.

[0021] Figure 4 This is a schematic diagram of the fin field-effect transistor in a weakly turned-on state according to one embodiment of this application.

[0022] Figure 5This is a schematic diagram of the fin field-effect transistor in the on state according to one embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the embodiments and accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain this application, but are not intended to limit it.

[0024] It should also be noted that, in order to avoid obscuring this application with unnecessary details, only the structures and / or processing steps closely related to the solution according to this application are shown in the accompanying drawings, while other details that are not closely related to this application are omitted.

[0025] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, element, step, or component, but does not exclude the presence or addition of one or more other features, elements, steps, or components.

[0026] It should also be noted that, unless otherwise specified, the term "connection" in this article can refer not only to a direct connection, but also to an indirect connection involving an intermediary.

[0027] In the following description, embodiments of the present application will be illustrated with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar parts, or the same or similar steps.

[0028] FinFETs are metal-oxide-semiconductor field-effect transistors with a Fin structure. By designing the channel as a three-dimensional "fin"-like structure to form a three-sided ring gate structure, the increased channel width effectively solves the short-channel effect problem faced by traditional MOSFETs when their size is reduced to the nanometer scale. However, increasing the effective current and reducing the current during device integration and application are ongoing research topics. Based on this, this application proposes a novel FinFET structure based on existing FinFETs. This structure can not only be improved through a simple doping process but also significantly increase the effective current of the device. Specifically, this application designs a punch-through region in the FinFET that is doped with the same type as the source and drain regions, and when the device is turned off, the first PN junction corresponding to the punch-through region is a fully depleted region.

[0029] Figure 2 This is a schematic diagram of the structure of the fin field-effect transistor proposed in this application. Figure 2 (b) is a partial cross-sectional view of the fin field-effect transistor proposed in this application along the X section. Figure 2 (c) is a cross-sectional view of the fin field-effect transistor proposed in this application along the Y section.

[0030] like Figure 2 As shown, the fin field-effect transistor includes a semiconductor substrate 100 and a fin structure 200 and a gate structure 300 located above the semiconductor substrate 100. The fin structure 200 may include a source region 210, a drain region 220, and a channel region 230 located between the source region and the drain region, and the gate structure 300 is disposed across the channel region 230. The fin structure 200 may also include a punch-through region 240 that is doped with the same type as the source region 210. The punch-through region 240 is located between the source region 210 and the drain region 220, and the punch-through region 240 is disposed in a non-contact manner with the source region 210, the drain region 220, and the channel region 230 (if the punch-through region 240 is in contact with the channel region 230, the device cannot be turned off).

[0031] As an example, the semiconductor substrate 100 is prepared from a semiconductor material (such as a semiconductor silicon-based material). For example, one or more of silicon, silicon germanium, or silicon carbide can be used to prepare the semiconductor substrate 100. The fin structure 200 is prepared from a semiconductor material, and therefore the fin structure 200 can also be referred to as a semiconductor fin. For example, if the semiconductor substrate 100 is a silicon-based substrate, the fin structure 200 can be an epitaxially grown silicon structure. Furthermore, the gate structure 300 can be a structure prepared using a metallic material or polycrystalline silicon (such as silicon dioxide). The above are merely examples, and this application does not specifically limit the materials used to prepare the semiconductor substrate 100, the fin structure 200, and the gate structure 300.

[0032] In some embodiments of this application, the fin structure 200 may extend along a direction parallel to the upper surface of the semiconductor substrate 100, and the fin structure 200 and the gate structure 300 may be arranged perpendicular to each other, that is, the gate structure 300 may extend along a direction perpendicular to the extending direction of the fin structure 200. Moreover, the fin field-effect transistor includes at least one fin structure 200. When the fin field-effect transistor includes multiple fin structures 200, the fin structures 200 may be arranged in an array (in which case the gate structure 300 covers the array of fin structures 200), and the array arrangement requires that all fin structures 200 are parallel to each other.

[0033] The source region 210 and drain region 220 are respectively disposed on both sides of the gate structure 300, and the channel region 230 connects the source region 210 and drain region 220 (or the depletion region in the second PN junction corresponding to the source region 210 and the depletion region in the second PN junction corresponding to the drain region 220 can have contact interfaces with the channel region 230 respectively). The fin-shaped structure 200 covered by the gate structure 300 from both sides and the top, and the portion of the fin-shaped structure 200 covered by the gate structure 300 at a certain depth, is the channel region 230. Therefore, as Figure 5As shown, the channel region in a FinFET may include a first sidewall, a second sidewall, and a top surface. In this application, when a prior art FinFET device is in the ON state, the location of the electron channel formed between the source region 210 and the drain region 220 by gate voltage is the same as the location of the channel region 230 in the device proposed in this application. The purpose of employing a gate structure 300 surrounding three sides of the fin structure 200 in the FinFET device is to control the current flow in the channel region.

[0034] As an example, the fin field-effect transistor may further include a gate dielectric layer 310 formed between the channel region 230 and the gate structure 300 (one side of the gate dielectric layer 310 is the gate structure 300, and the opposite side is the channel region 230), a gate oxide structure 320 located between the gate structure 300 and the semiconductor substrate 100, and a substrate. The gate dielectric layer 310 may be a thin film layer prepared using a high dielectric constant material, the substrate may include a region for forming the fin field-effect transistor, and the substrate may be an insulating substrate or have an insulating layer formed on the region where the fin field-effect transistor is formed.

[0035] Furthermore, such as Figure 2 As shown, there are no contact interfaces between the through-hole region 240 and the source region 210, between the through-hole region 240 and the drain region 220, and between the through-hole region 240 and the channel region 230. Furthermore, due to... Figure 2 As shown in (c), the punch-through region 240 needs to be located between the source region 210 and the drain region 220. Figure 2 As shown in (b), the height of the through-hole area 240 must be less than the height of the fin structure 200, meaning the bottom of the through-hole area 240 does not exceed the fin structure 200, and the top of the through-hole area 240 does not contact the channel area. Furthermore, the through-hole area 240 may include three surfaces disposed opposite to the first sidewall, the second sidewall, and a top surface of the channel area 230. Figure 2 The rectangular through-area is merely an example; this application does not specifically limit the shape of the through-area 240. Figure 2 As shown, the FinFET device containing the punch-through region 240 can be regarded as a sandwich structure, whether viewed from the X-section or the Y-section.

[0036] In some embodiments of this application, the source region 210, the punch-through region 240, and the drain region 220 are homotype doped regions (N-type or P-type doped), while other parts of the fin structure 200 can be inversely doped regions of the source region 210. Therefore, the source region 210, the drain region 220, and the punch-through region 240 can all form corresponding PN junctions with the surrounding fin structure 200, specifically as follows: the fin structure portion surrounding the punch-through region 240 (i.e., the portion of the fin structure 200 that surrounds the punch-through region 240) is used to form a first PN junction with the punch-through region 240; the fin structure portion surrounding the source region 210 is used to form a second PN junction with the source region 210; and the fin structure portion surrounding the drain region 220 is used to form a third PN junction with the drain region 220. That is, the boundaries between the punch-through region 240, the source region 210, and the drain region 220 and the surrounding inversely doped regions can respectively form corresponding first PN junctions, second PN junctions, and third PN junctions. For example, as... Figure 2 As shown, if the through region 240 is rectangular, PN junctions can be formed on all six sides of the through region. Therefore, the PN junctions corresponding to these six sides are collectively referred to as the first PN junction.

[0037] To ensure subsequent carrier flow in the punch-through region, the gaps between the punch-through region 240 and the source region 210, drain region 220, and channel region 230 should not be too large. At least, contact interfaces must exist between the first PN junction and the second PN junction, between the first PN junction and the third PN junction, and between the first PN junction and the channel region 230. Furthermore, even if the thickness of the PN junction changes when the device is in different operating modes, the aforementioned PN junction contact conditions must be maintained. The first PN junction in this application may include the punch-through region 240, the channel region 230, and a fin-shaped structure between the punch-through region 240 and the channel region 230.

[0038] In some embodiments of this application, to enable the device to operate in operating modes (including off state, weak on state, and on state), the fin field-effect transistor may further include a source terminal, a drain terminal, and a gate terminal (which may be simply referred to as source, drain, and gate, respectively). One end of the source terminal is connected to the source region 210 on the fin structure 200 of the fin field-effect transistor, and the other end is connected to an external circuit. One end of the drain terminal is connected to the drain region 220 on the fin structure 200 of the fin field-effect transistor, and the other end is connected to an external circuit. One end of the gate terminal is connected to the gate structure 300, and the other end is connected to an external circuit. The source terminal, drain terminal, and gate terminal may be electrical connectors such as metal wires or pins, and the external circuit is used to apply voltage. Specifically, when the voltage difference applied to the gate and source is less than the threshold voltage, even if a voltage exceeding the threshold voltage is applied between the source and drain, no current will flow between the source and drain regions, and the device is in the off state. When the voltage applied between the source and gate is slightly greater than the threshold voltage but insufficient to make the charge density of the inversion layer (i.e., channel region 230) reach the turn-on state, the FinFET is in the weak turn-on state. When the voltage applied between the source and gate is large enough to make the charge density of the inversion layer on the semiconductor surface reach a certain level, the device is in the turn-on state.

[0039] The following is a detailed description of the device principle of the novel fin field-effect transistor proposed in this application under different operating modes: Figure 3 Images (a) and (c) are schematic diagrams of the existing fin field-effect transistor in the off state. Figure 3 Figures (b) and (d) are schematic diagrams illustrating the device principle of the fin field-effect transistor proposed in this application in the off state. When the fin field-effect transistor is in the off state, the punch-through region 240 and the surrounding fin structure 200 form a lateral electric field, blocking the current flow between the source and drain. At this time, the second PN junction corresponding to the source region 210 and the third PN junction corresponding to the drain region 220 are in a blocked state, and the first PN junction corresponding to the punch-through region 240 is in an insulating depletion state. Furthermore, this application designs that, when the fin field-effect transistor is in the off state, the carriers diffuse with each other, making the first PN junction a fully depleted region (at this time, the fin structure portion covered by the gate structure (including the punch-through region 240) can be exactly in a fully depleted state).

[0040] Figure 4 Images (a) and (c) in the diagram are schematic diagrams of the existing fin field-effect transistor in a weak-on state. Figure 4Figures (b) and (d) are schematic diagrams of the fin field-effect transistor proposed in this application under the weak turn-on state. When the fin field-effect transistor is in the weak turn-on state, the charge accumulation at the silicon-gate oxide interface (i.e., the interface between the gate structure 300 / gate dielectric layer 310 and the fin structure 200) begins to invert (the electric field between the source and the gate begins to repel the majority carriers of the semiconductor substrate near the gate structure, forming a depletion layer), and the current begins to flow from the drain region to the source region, and begins to inject carriers into the fully depleted region (formed by the first PN junction and the punch-through region 240). The carrier distribution in the fully depleted region is disrupted and rearranged to enable partial or complete conduction in the subsequent fully depleted region.

[0041] Figure 5 Images (a) and (c) are schematic diagrams of the existing fin field-effect transistor in the on state. Figure 5 Figures (b) and (d) show schematic diagrams of the fin field-effect transistor (FET) proposed in this application in the on-state. When the FET is in the on-state, it forms a first electronic channel in the channel region between the source region 210 and the drain region 220, and part or all of the total depletion region (formed by the first PN junction) forms a second electronic channel between the source region 210 and the drain region 220, contacting the first electronic channel. That is, minority carriers in the first channel are injected into the total depletion region formed by the first PN junction, forming the second electronic channel, allowing current to flow through the total depletion region. At this time, parts of the first and second electronic channels can overlap, forming an integrated channel, thereby significantly increasing the effective current between the source and drain.

[0042] From the off state, weak on state to on state, as the electron channel is formed, the range of the fully depleted region formed by the first PN junction gradually decreases.

[0043] It should be noted that in the fin field-effect transistor designed in this application, the entire region between the upper surface of the fin structure located between the source region and the drain region and below the gate structure and the bottom of the PN junction formed by the punch-through region (belonging to the fully depleted region) can theoretically serve as an electron channel to realize current flow. However, due to the limitation of carrier concentration, in practical applications, an electron gas may not necessarily be formed in the entire region of the fully depleted region.

[0044] The novel FinFET structure proposed in this application has the following significant advantages: ① In terms of process, this application can simplify the process by adding a punch-through region to the channel region through doping methods such as ion implantation on the existing FinFET structure; ② When the device is turned on, the punch-through region can provide a second electron channel, thereby significantly increasing the effective current of the device by greatly expanding the current path when the device is turned on; ③ The source and drain regions can form PN junctions with the non-punch-through regions respectively, and a PN junction can also be formed between the punch-through and non-punch-through regions. When the device is turned off, the PN junction formed by the source and drain is in a blocking state, and the PN junction formed by the punch-through and non-punch-through regions is in a depletion insulation state. Therefore, the FinFET structure proposed in this application can reduce the leakage current between the source and drain regions.

[0045] Due to the complexity of existing FinFET device structures and fabrication methods, this application does not specifically limit the fabrication scheme of the proposed novel FinFET structure. Based on existing fabrication methods, the proposed device structure can be obtained by creating doped regions at specific locations within the fin structure through ion implantation or impurity atom diffusion. Because the improved process is simple, the novel device proposed in this application is applicable to any existing FinFET structure.

[0046] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0047] In this application, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with or in place of features of other embodiments.

[0048] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to the embodiments of this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A fin field-effect transistor, the fin field-effect transistor comprising a semiconductor substrate (100) and a fin structure (200) and a gate structure (300) disposed above the semiconductor substrate (100), the fin structure (200) comprising a source region (210), a drain region (220) and a channel region (230) disposed between the source region (210) and the drain region (220), and the gate structure (300) being disposed across the channel region (230); characterized in that, The fin structure (200) further includes a through-hole region (240) that is homo-doped with the source region (210). The through-hole region (240) is located between the source region (210) and the drain region (220), and the through-hole region (240) is disposed in a non-contact manner with the source region (210), the drain region (220) and the channel region (230), respectively. The portion of the fin structure (200) surrounding the through-hole region (240) and the through-hole region (240) are used to form a first PN junction, the source region (210) and the surrounding fin structure (200) are used to form a second PN junction, and the drain region (220) and the surrounding fin structure (200) are used to form a third PN junction; the first PN junction has contact interfaces with the second PN junction, the third PN junction and the channel region (230), respectively; as well as When the fin field-effect transistor is in the off state, the first PN junction is a fully depleted region; wherein the first PN junction includes the punch-through region (240) and the channel region (230).

2. The fin field-effect transistor according to claim 1, characterized in that, When the fin field-effect transistor is in the on state, the fin field-effect transistor is used to form a first electronic channel in the channel region between the source region (210) and the drain region (220), and part or all of the total depletion region forms a second electronic channel between the source region (210) and the drain region (220) with a contact interface with the first electronic channel, so as to increase the effective current between the source region (210) and the drain region (220).

3. The fin field-effect transistor according to claim 1, characterized in that, The fin field-effect transistor also includes a source terminal, a drain terminal, and a gate terminal; One end of the source terminal is connected to the source region of the fin field-effect transistor, and the other end is connected to an external circuit; one end of the drain terminal is connected to the drain region of the fin field-effect transistor, and the other end is connected to an external circuit; one end of the gate terminal is connected to the gate structure, and the other end is connected to an external circuit.

4. The fin field-effect transistor according to claim 1, characterized in that, The fin field-effect transistor also includes a gate dielectric layer (310) located between the channel region (230) and the gate structure (300).

5. The fin field-effect transistor according to claim 4, characterized in that, The gate dielectric layer (310) is a thin film layer prepared using a high dielectric constant material.

6. The fin field-effect transistor according to claim 1, characterized in that, The fin field-effect transistor also includes a gate oxide structure (320) located between the gate structure (300) and the semiconductor substrate (100).

7. The fin field-effect transistor according to claim 1, characterized in that, The fin field-effect transistor also includes a substrate having a region for forming the fin field-effect transistor.

8. The fin field-effect transistor according to claim 1, characterized in that, The semiconductor substrate (100) is a silicon-based substrate, the fin structure (200) is a silicon epitaxial structure, the gate structure (300) is a structure prepared using metal materials or polycrystalline silicon, and the source region (210) and drain region (220) are homotype doped regions.

9. The fin field-effect transistor according to claim 1, characterized in that, The fin structure (200) extends along a direction parallel to the upper surface of the semiconductor substrate (100), and the fin structure (200) is perpendicular to the gate structure (300).

10. The fin field-effect transistor according to claim 1, characterized in that, In the case where the fin field-effect transistor includes a plurality of the fin structures (200), the fin structures (200) are arranged in an array.

Images