Semiconductor device and electronic apparatus

Abstract

The embodiment of the invention provides a semiconductor device and electronic equipment, relates to the technical field of semiconductor devices, and is used for suppressing the influence of a radiation effect on the semiconductor device. The semiconductor device comprises a substrate, a first epitaxial layer, a second epitaxial layer, two well regions, a doping part, two shielding layers, a current expansion layer, two grid electrodes, two dielectric layers, a source electrode layer and a drain electrode layer, the first epitaxial layer and the second epitaxial layer are sequentially stacked on one side of the substrate in the first direction, and the first direction is the thickness direction of the substrate; the two well regions and the doping part are arranged on the second epitaxial layer; the two shielding layers and the current expansion layer are arranged in the first epitaxial layer; the two grids are arranged on the side, away from the substrate, of the second epitaxial layer, and each dielectric layer wraps one grid and makes contact with the well region, the doping part and the part between the well region and the doping part. The source electrode layer is arranged on the side, away from the substrate, of the second epitaxial layer and the dielectric layer and makes contact with the doping part, and the drain electrode layer is arranged on the side, opposite to the first epitaxial layer, of the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor devices, and more particularly to a semiconductor device and electronic device. Background Technology

[0002] With the rapid development of space exploration, aerospace equipment such as deep space probes are facing increasingly higher requirements for the durability and driving efficiency of their high-power-density power conversion systems. This necessitates that power semiconductor devices achieve smaller sizes at higher rated voltages. Among these, the metal-oxide-semiconductor field-effect transistor (MOSFET), as a type of power semiconductor device, is the core switching device in the power conversion system, and its performance directly affects the efficiency and reliability of the entire system.

[0003] Currently, silicon carbide (SiC) has become an ideal material for realizing high-performance MOSFETs due to its wide bandgap, high critical breakdown electric field, high electron saturation velocity, excellent thermal conductivity, and good radiation resistance. Compared with traditional silicon-based devices, SiC MOSFETs can operate stably under higher temperatures, higher voltages, and higher frequencies. However, in high-radiation environments such as space, SiC MOSFETs are exposed to high-energy particle radiation for extended periods, making them susceptible to radiation effects that can degrade key electrical parameters and affect their reliability.

[0004] Therefore, effectively suppressing the effects of radiation on SiC MOSFETs and improving their long-term operational reliability in space environments has become a core technological challenge that urgently needs to be overcome. Summary of the Invention

[0005] The purpose of embodiments of this disclosure is to provide a semiconductor device and electronic device for suppressing the effects of radiation on SiC MOSFETs.

[0006] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0007] On one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, two well regions, a doped region, two shielding layers, a current spreading layer, two gates, two dielectric layers, a source layer, and a drain layer. The first epitaxial layer and the second epitaxial layer are stacked on one side of the substrate along a first direction, where the first direction is the thickness direction of the substrate, and the second epitaxial layer is further away from the substrate than the first epitaxial layer.

[0008] The two well regions and the doped portion are disposed in the second epitaxial layer. The two well regions are respectively located on opposite sides of the doped portion along the second direction, and a portion of the second epitaxial layer is located between the well regions and the doped portion. The second direction is perpendicular to the first direction.

[0009] The current spreading layer and the two shielding layers are disposed in the first epitaxial layer. The two shielding layers are respectively located on opposite sides of the current spreading layer along the second direction. Each shielding layer overlaps with one of the well regions along the first direction, and the current spreading layer overlaps with the doped portion along the first direction.

[0010] The two gate electrodes are disposed on the side of the second epitaxial layer away from the substrate and are spaced apart along the second direction. Each dielectric layer encapsulates one gate electrode and contacts the well region, the doped portion, and the portion of the second epitaxial layer located between the well region and the first doped portion. The source layer is disposed on the side of the second epitaxial layer and the dielectric layer away from the substrate, and the source layer contacts the doped portion. The drain layer is disposed on the opposite side of the substrate relative to the first epitaxial layer.

[0011] In the aforementioned semiconductor devices, taking an N-type doped semiconductor device with a P-type doping type as an example (the following descriptions of the effects of each embodiment are also based on an N-type doped semiconductor device). Two well regions and a doped portion are provided in the second epitaxial layer. The source layer is in contact with the doped portion, which makes it easier for holes to be absorbed by the doped portion and enter the source layer, reducing the hole concentration in the well regions. This prevents the parasitic transistor formed by the second epitaxial layer, the well regions, and the N+ regions within the well regions from turning on, thus avoiding current concentration and irreversible burn-out failure of the semiconductor device.

[0012] Furthermore, by setting a dielectric layer to wrap the gate and having the doped portion in contact with the dielectric layer, holes accumulated below the dielectric layer can be extracted into the source layer, preventing holes from inducing electrons in the gate, thereby forming a strong electric field in the dielectric layer, which would lead to increased leakage current or even breakdown of the dielectric layer.

[0013] By incorporating two shielding layers and a current spreading layer in the first epitaxial layer, each shielding layer overlaps with a well region along a first direction, and the current spreading layer overlaps with the doped region along the first direction. In this way, under reverse bias (high voltage at the drain), the electric field distribution can be modulated, ensuring a uniform electric field distribution at the interface between the shielding layer and the current spreading layer. This reduces the local electric field peak at the interface between the well region and the second epitaxial layer, thus preventing irreversible burn-out failure of the semiconductor device under strong electric fields. Furthermore, the reduced electric field effectively mitigates the acceleration of holes, further reducing the number of holes entering the well region and preventing the activation of parasitic transistors.

[0014] In some embodiments, the first epitaxial layer includes a first portion and a second portion disposed along the first direction, the first portion being closer to the substrate than the second portion, the current spreading layer and the two shielding layers being disposed in the second portion, the side surface of each shielding layer away from the substrate contacting one of the well regions, and the side surfaces of the two shielding layers and the current spreading layer near the substrate contacting the first portion.

[0015] In the aforementioned semiconductor device, by setting the side surface of each shielding layer away from the substrate to contact a well region, and the side surfaces of the two shielding layers and the current spreading layer close to the substrate to contact the first part, holes can be extracted to the source layer through the channel formed by the first epitaxial layer, the shielding layer, the well region, and the doped portion. Furthermore, the shielding layer and the substrate are separated by the first part of the first epitaxial layer, which facilitates electrons to sequentially pass through the second epitaxial layer, the current spreading layer, the first part of the first epitaxial layer, and the substrate to finally reach the drain layer.

[0016] In some embodiments, the first epitaxial layer, the second epitaxial layer, and the current spreading layer have the same doping type, the well region, the doped portion, and the shielding layer have the same doping type, and the semiconductor device meets at least one of the following conditions: The doping concentration of the doped portion is greater than the doping concentration of the well region; the doping concentration of the doped portion is greater than the doping concentration of the shielding layer; the doping concentration of the shielding layer is greater than the doping concentration of the well region; the doping concentration of the current spreading layer is greater than the doping concentration of the second epitaxial layer; the doping concentration of the second epitaxial layer is greater than the doping concentration of the first epitaxial layer.

[0017] In the aforementioned semiconductor devices, the semiconductor device meeting at least one of the following conditions means that the semiconductor device can meet one, two or more, or all of the following conditions.

[0018] By setting the doping concentration of the doped region to be greater than that of the well region, it is beneficial to form a good ohmic contact between the doped region and the source layer. This facilitates the absorption of holes by the doped region into the source layer, reducing the hole concentration in the well region. This prevents parasitic transistors from turning on, which can lead to current concentration and irreversible burn-out failure of the semiconductor device. Simultaneously, it also reduces the number of holes accumulating below the dielectric layer, preventing holes from inducing electrons at the gate and creating a strong electric field in the dielectric layer, which could increase leakage current or even cause the dielectric layer to break down.

[0019] By setting the doping concentration of the shielding layer to be lower than that of the first doped part, the strong electric field is prevented from accumulating locally at the corners of the shielding layer, which could cause the semiconductor device to break down prematurely.

[0020] By setting the doping concentration of the shielding layer to be greater than that of the well region, the depletion region formed by the shielding layer under the same voltage can be narrowed. Similarly, by setting the doping concentration of the current spreading layer to be greater than that of the second epitaxial layer, the depletion region formed by the current spreading layer under the same voltage can be narrowed, and its depletion width is correspondingly reduced, thereby lowering the forward conduction resistance.

[0021] By setting the doping concentration of the second epitaxial layer to be greater than that of the first epitaxial layer, the forward conduction resistance of the second epitaxial layer can be reduced, which is beneficial to current transmission.

[0022] In some embodiments, the dimension of the shielding layer at the end near the substrate along the second direction is smaller than the dimension of the shielding layer at the end away from the substrate along the second direction.

[0023] In the aforementioned semiconductor device, since the shielding layer has a smaller dimension along the second direction at the end near the substrate, the current spreading layer, which is disposed in the same layer as the shielding layer and in contact with it, has a larger dimension along the second direction at the end near the substrate. During the forward conduction process of electrons flowing to the drain layer, the larger dimension along the second direction at the end of the current spreading layer near the substrate ensures the lateral expansion of electrons, thereby reducing the forward conduction resistance.

[0024] In some embodiments, a portion of the surface of the shielding layer on the side away from the substrate is in contact with the second epitaxial layer.

[0025] In the aforementioned semiconductor device, a portion of the surface of the shielding layer at the end furthest from the substrate contacts the second epitaxial layer. That is, the dimension of the shielding layer at the end furthest from the substrate along the second direction is larger than the dimension of the well region along the second direction. With this arrangement, under reverse bias, since the electric field is distributed at the interface between the shielding layer and the current spreading layer, and the dimension of the shielding layer at the end furthest from the substrate along the second direction is the same as the dimension of the first well region along the second direction, the peak value of the electric field at the corner of the interface between the well region and the second epitaxial layer can be reduced, thus achieving a shielding effect at the corner of the interface between the well region and the epitaxial layer.

[0026] In some embodiments, along the first direction and from the first epitaxial layer to the second epitaxial layer, the size of the shielding layer increases in a stepwise manner along the second direction; or, the size of the shielding layer gradually increases along the second direction; or, the shielding layer includes a first sub-shielding layer and a second sub-shielding layer, wherein the size of the first sub-shielding layer gradually increases along the second direction, and the size of the second sub-shielding layer remains unchanged along the second direction.

[0027] In the aforementioned semiconductor device, this configuration ensures lateral current expansion while positioning the electric field, which was originally located at the corner between the well region and the second epitaxial layer, at the corner or interface between the shielding layer and the current expansion layer. This further homogenizes the electric field distribution, thereby reducing local peak values ​​and preventing the activation of parasitic transistors.

[0028] In some embodiments, the dimension of the shielding layer at the end near the substrate along the second direction is greater than the dimension of the shielding layer at the end away from the substrate along the second direction.

[0029] In the aforementioned semiconductor device, by setting the dimension of the shielding layer near the substrate along the second direction to be larger than the dimension of the shielding layer away from the substrate along the second direction, that is, the contact area between the shielding layer and the first epitaxial layer along the second direction is larger, which can improve the hole extraction efficiency of the shielding layer and further facilitate the extraction of holes to the source layer.

[0030] In some embodiments, a portion of the surface of the current spreading layer at the end away from the substrate contacts the well region.

[0031] In the aforementioned semiconductor device, a portion of the surface of the current spreading layer at the end furthest from the substrate contacts the well region. That is, the dimension of the end of the current spreading layer furthest from the substrate along the second direction is larger. This arrangement facilitates the lateral expansion of electrons flowing from the second epitaxial layer into the current spreading layer during the process of electron flow to the drain layer, thereby reducing the forward conduction resistance during the process of electrons flowing from the second epitaxial layer into the current spreading layer.

[0032] In some embodiments, along the first direction and from the first epitaxial layer to the second epitaxial layer, the size of the shielding layer decreases in a stepwise manner along the second direction; or, the size of the shielding layer gradually decreases along the second direction; or, the shielding layer includes a first sub-shielding layer and a second sub-shielding layer, wherein the size of the first sub-shielding layer along the second direction remains unchanged, and the size of the second sub-shielding layer gradually decreases along the second direction.

[0033] In the aforementioned semiconductor device, this configuration can effectively increase the hole extraction efficiency of the shielding layer, and can position the electric field at the corner or interface between the shielding layer and the current spreading layer, thereby further homogenizing the electric field distribution and producing an electric field shielding effect at the corner of the interface between the well region and the second epitaxial layer.

[0034] In some embodiments, the shielding layer includes a plurality of shielding portions spaced apart along a third direction; the third direction is perpendicular to the first direction and intersects the second direction; a portion of the current spreading layer is located between two adjacent shielding portions along the third direction.

[0035] In the aforementioned semiconductor device, a shielding layer comprising multiple shielding portions is provided, wherein the multiple shielding portions are spaced apart along a third direction, and a current spreading layer is provided between two adjacent shielding portions. This ensures both the hole extraction efficiency of the shielding layer and the uniform distribution of the electric field, while also increasing the area occupied by the current spreading layer, thereby further optimizing the forward conduction characteristics of the device and reducing the forward conduction resistance.

[0036] On the other hand, an electronic device is provided. The electronic device includes a semiconductor device and a circuit board as described in any of the above embodiments, the semiconductor device being disposed on the circuit board.

[0037] The above-described methods for fabricating electronic devices and semiconductor devices have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above embodiments, and will not be repeated here. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0039] Figure 1 This is a schematic diagram of the structure of an electronic device provided in some embodiments according to the present disclosure; Figure 2 This is a structural diagram of a semiconductor device provided in some embodiments of the present disclosure; Figure 3 This is a structural diagram of another semiconductor device provided in some embodiments of the present disclosure; Figure 4 This is a structural diagram of yet another semiconductor device provided in this disclosure according to some embodiments; Figure 5A This is a structural diagram of yet another semiconductor device provided in this disclosure according to some embodiments; Figure 5B This is a structural diagram of yet another semiconductor device provided in this disclosure according to some embodiments; Figure 6 This is a structural diagram of yet another semiconductor device provided in this disclosure according to some embodiments; Figure 7 This is a structural diagram of yet another semiconductor device provided in this disclosure according to some embodiments; Figure 8AThis is a structural diagram of yet another semiconductor device provided in this disclosure according to some embodiments; Figure 8B This is a structural diagram of yet another semiconductor device provided in this disclosure according to some embodiments; Figure 9 This is a structural diagram of yet another semiconductor device provided in this disclosure according to some embodiments; Figure 10 This is a structural diagram of yet another semiconductor device provided in this disclosure according to some embodiments; Figure 11 This is a top view of a semiconductor device provided according to some embodiments of the present disclosure; Figure 12 This is a comparison graph showing the change of peak electric field of gate oxide layer of a semiconductor device over time in a semiconductor device according to some embodiments of the present disclosure and in related technologies. Figure 13 This is a comparison graph showing the change of drain layer current over time in a semiconductor device according to some embodiments of the present disclosure and in related technologies. Figures 14A-14H This is a structural diagram corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. Detailed Implementation

[0040] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0041] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0042] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0043] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0044] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0045] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0046] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0047] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0048] This application provides an electronic device, which can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, in-vehicle equipment, vehicles, and other different types of user equipment or terminal devices; the electronic device can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device.

[0049] Figure 1 This is a schematic diagram of the structure of an electronic device provided in this disclosure according to some embodiments. Figure 1 As shown, the electronic device 1000 includes a semiconductor device 100 and a circuit board 200. The semiconductor device 100 is disposed on and electrically connected to the circuit board 200. The semiconductor device 100 is a core electronic component of the electronic device 1000, responsible for power conversion, signal processing, and power control. Its performance directly affects the device's efficiency, power consumption, and reliability. The circuit board 200 provides mechanical support, electrical interconnection, and heat dissipation paths for the semiconductor device 100. Through its surface or internal conductive lines, it distributes operating voltage, transmits signals, and dissipates heat from the semiconductor device 100, enabling the semiconductor device 100 to be integrated into the system circuitry of the electronic device 1000 and perform its intended functions.

[0050] Understandable Figure 1 The structure of the electronic device 1000 shown does not constitute a specific limitation on the electronic device 1000, which may include, for example... Figure 1 The components shown may have more or fewer components, or may be combined as follows: Figure 1Some of the components shown, or those that can be combined with, for example Figure 1 The component arrangements shown are different.

[0051] For example, the circuit board 200 can be a flexible printed circuit (FPC) or a rigid printed circuit board (PCB).

[0052] The semiconductor device 100 can be an integrated circuit or a discrete device that performs functions such as signal processing and power conversion. In critical power applications such as switching power supplies, motor drives, and photovoltaic inverters, the semiconductor device 100 is a power switching device that is the core of power conversion.

[0053] Among numerous power switching devices, the metal-oxide-semiconductor field-effect transistor (MOSFET) has become the most widely used and important type due to its high input impedance, fast switching capability, ease of driving, and good thermal stability.

[0054] The static and dynamic losses, voltage / current withstand capability, thermal characteristics, and long-term reliability of these devices directly determine the conversion efficiency, power density, output quality, and overall service life of power electronic systems, and are one of the key factors affecting the overall performance of terminal electronic equipment.

[0055] Currently, silicon carbide (SiC), a third-generation wide-bandgap semiconductor material, has become an ideal material for realizing high-performance MOSFETs due to its wide bandgap, high critical breakdown electric field, high electron saturation velocity, excellent thermal conductivity, and good radiation resistance. Compared with traditional silicon-based devices, SiC MOSFETs can operate stably under higher temperature, higher voltage, and higher frequency conditions.

[0056] The following uses an N-type doped SiC MOSFET semiconductor device as an example to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, these embodiments. Any other semiconductor device can also be considered, as long as the same technical concept is applied.

[0057] refer to Figure 2 , Figure 2 This is a structural diagram of a semiconductor device 100 provided in this disclosure according to some embodiments.

[0058] like Figure 2 As shown, the semiconductor device 100 includes a substrate 10, an epitaxial layer 11, a well region 12, a gate 13, a dielectric layer 14, a source layer 15, and a drain layer 16.

[0059] The substrate 10 serves as the vertical current collection channel and can be made of a heavily doped N+ type semiconductor material, such as silicon or silicon carbide. Due to its extremely high doping concentration, it has extremely low resistance, ensuring that current can flow efficiently to the drain layer 16.

[0060] An epitaxial layer 11 is disposed on one side of the substrate 10 along a first direction X, where the first direction X is the thickness direction of the substrate 10. The doping type of the epitaxial layer 11 is the same as that of the substrate 10, and the doping concentration of the epitaxial layer 11 is less than that of the substrate 10; that is, the epitaxial layer 11 is a lightly doped N-type layer. As the high-voltage bearing component of the semiconductor device 100, its lower doping concentration and specific thickness are crucial for widening the depletion region to create a uniform electric field and prevent breakdown when the device is turned off and subjected to high voltage. This is key to determining the device's withstand voltage rating.

[0061] Well region 12 is located at one end of epitaxial layer 11 and away from substrate 10. Well region 12 has a different doping type than epitaxial layer 11, being P-doped. Well region 12 is the substrate for forming conductive channels. Well region 12 and epitaxial layer 11 can form a PN junction, which is the core that withstands reverse blocking voltage.

[0062] The well region 12 also includes a P+ region 121 and an N+ region 122. The N+ region 122 is responsible for providing abundant electrons as a source of current and forming an ohmic contact with the source layer 15. The P+ region 121 is used to fix the potential of the well region 12 to the potential of the source layer 15 (usually ground potential).

[0063] Gate 13 is located on the side of epitaxial layer 11 away from substrate 10 and is encased by dielectric layer 14. Gate 13 is used to apply a control voltage to control the on and off states of semiconductor device 100. The material of gate 13 can be, for example, polysilicon or metal. When a sufficiently high positive voltage is applied to gate 13, an inversion layer, i.e., an N-type channel, is induced on the surface of well region 12, thereby connecting source layer 15 and drain layer 16. Dielectric layer 14 encapsulates gate 13 to provide electrical isolation.

[0064] In some embodiments, the dielectric layer 14 may include a gate oxide layer 141 and an oxide isolation layer 142, wherein the gate oxide layer 141 is located between the gate 13 and the epitaxial layer 11, and the oxide isolation layer 142 covers the surface of the gate 13 away from the substrate 10 and its two sides. Both the gate oxide layer 141 and the oxide isolation layer 142 may be made of silicon dioxide, and the gate oxide layer 141 may also be made of aluminum oxide or other materials.

[0065] The source layer 15 is disposed on the side of the epitaxial layer 11 and the dielectric layer 14 away from the substrate 10. The drain layer 16 is disposed on the opposite side of the substrate 10 relative to the epitaxial layer 11.

[0066] The aforementioned semiconductor device 100 primarily controls the switching of a strong current between the source layer 15 and the drain layer 16 by a minute change in the voltage of the gate 13, thereby achieving efficient power switching. Its core lies in the formation and disappearance of conductive channels.

[0067] Specifically, when the voltage between the gate 13 and the source layer 15 is lower than a specific value, referred to as the threshold voltage of the semiconductor device 100, an effective conductive channel cannot be formed on the surface of the well region 12 below the gate 13. At this time, if a high voltage is applied to the drain layer 16, the high voltage is mainly applied to the reverse-biased PN junction formed by the well region 12 and the epitaxial layer 11. The high voltage dissipates free electrons and holes near the junction interface, leaving a region filled with fixed charge and almost no free carriers, hereinafter referred to as the depletion region. Under the action of the high voltage, the depletion region of this PN junction mainly widens significantly towards the lightly doped epitaxial layer 11. The mobile carriers in this depletion region are almost completely depleted, thereby establishing a strong electric field from the N-type epitaxial layer 11 to the P-type well region 12 to withstand the applied high voltage and effectively block the current between the source layer 15 and the drain layer 16. At this time, the semiconductor device 100 is in the off state.

[0068] When the voltage at gate 13 increases and exceeds the threshold voltage, the electric field generated by the positive charge at gate 13 penetrates the extremely thin gate oxide layer 141, repelling holes on the surface of the well region 12 and attracting electrons within it. When the electron concentration is sufficiently high, the surface of the P-type well region 12 inverts into an N-type conductive channel, connecting the source layer 15 and the drain layer 16. At this point, if a voltage is applied between the source layer 15 and the drain layer 16, electrons can flow from the source layer 15 to the drain layer 16 through the channel, the MOSFET enters the conducting state, and its on-resistance is extremely low.

[0069] However, semiconductor devices 100 operating in a radiation environment are susceptible to degradation or even failure due to radiation effects, especially single-particle gate penetration and single-particle burn-out caused by heavy ions, where heavy ions refer to charged particles with high atomic numbers and extremely high energies.

[0070] When heavy ions are incident perpendicularly from above the semiconductor device 100 into the material, the energy of the particles is deposited along the incident path into the semiconductor material, ionizing and generating a large number of electron-hole pairs. Electrons and holes separate under the bias voltage of the drain layer 16; electrons pass through the substrate 10 into the drain layer 16, while holes accumulate under the gate oxide layer 141 above the junction field-effect transistor (JFET) region. The JFET region is located between the two well regions 12, covered by the gate oxide layer 141 above and the epitaxial layer 11 below. The large number of holes accumulated here induces a large number of electrons in the gate 13, thereby forming a strong electric field in the gate oxide layer 141, leading to an increase in leakage current and causing the gate oxide layer 141 to break down.

[0071] Furthermore, some of the holes generated during the irradiation process flow into the source layer 15 through the well region 12. This current constitutes the base current of the parasitic NPN transistor, causing the parasitic NPN transistor to turn on and forming a stable high-current path within the semiconductor device 100. The parasitic NPN transistor is composed of the N+ region 122 (emitter), the well region 12 (base), and the epitaxial layer 11 (collector).

[0072] Meanwhile, under the bias of the drain layer 16, the peak electric field first appears at the interface between the well region 12 and the epitaxial layer 11. As time increases, the depletion region gradually expands, and eventually the peak electric field stabilizes at the interface between the substrate 10 and the epitaxial layer 11. Under the influence of the strong electric field and high current, a large amount of Joule heat is generated locally, exceeding its thermal limit, thereby initiating a material phase transition and causing the semiconductor device 100 to burn out.

[0073] Based on the aforementioned technical problems, two semiconductor devices have been proposed in related technologies to solve the problems of heavy ion-induced particle gate penetration and single-particle burn-out.

[0074] refer to Figure 3 , Figure 3 This is a structural diagram of another semiconductor device 300 provided in this disclosure according to some embodiments.

[0075] like Figure 3 As shown, the semiconductor device 300 also includes a substrate 20, an epitaxial layer 21, a well region 22, a gate 23, a dielectric layer 24, a source layer 25, and a drain layer 26. Furthermore, by setting a split-layer structure for the gate 23 in the semiconductor device 300—that is, removing the gate 23 above the JFET region and retaining only a thicker dielectric layer 24—a large number of accumulated holes are prevented from inducing a large number of electrons in the gate 23, thereby forming a strong electric field in the dielectric layer 24, which would increase leakage current and potentially cause the dielectric layer 24 to break down. This improves the radiation resistance of the semiconductor device 300.

[0076] However, the semiconductor device 300 does not fundamentally solve the problem of a large number of holes accumulating under the dielectric layer 24. It may still induce a strong electric field at the bottom corner of the gate 23, thereby inducing the degradation and breakdown of the dielectric layer 24.

[0077] refer to Figure 4 , Figure 4 This disclosure provides a structural diagram of another semiconductor device 400 according to some embodiments.

[0078] like Figure 4 As shown, the semiconductor device 400 also includes a substrate 30, an epitaxial layer 31, a well region 32, a gate 33, a dielectric layer 34, a source layer 35, and a drain layer 36. In addition, the semiconductor device 400 also includes a buffer layer 37 disposed between the epitaxial layer 31 and the substrate 30, wherein the buffer layer 37 is N-doped, and its doping concentration varies in a gradient manner.

[0079] During irradiation, the buffer layer 37 effectively slows down the downward depletion of the electric field depletion region, reduces the peak intensity of the electric field, and optimizes the longitudinal electric and thermal field distribution. However, the multilayer structure with a concentration gradient places high demands on the epitaxial process, making it difficult to guarantee a low defect concentration in the buffer layer 37. Furthermore, from a mechanistic perspective, this structure does not solve the fundamental problem of heat generation, and its protective effect is significantly weakened by fluctuations in the epitaxial fabrication process and changes in the irradiation environment.

[0080] Based on this, this application proposes another semiconductor device to solve the problems of heavy ion-induced particle gate penetration and single-event burn-out.

[0081] refer to Figure 5A , Figure 5A This is a structural diagram of another semiconductor device 1 provided in this disclosure according to some embodiments.

[0082] Semiconductor device 1 includes a substrate 51, a first epitaxial layer 52, a second epitaxial layer 53, two well regions 531, a doped region 54, two shielding layers 59, a current spreading layer 60, two gates 55, two dielectric layers 56, a source layer 57, and a drain layer 58.

[0083] The first epitaxial layer 52 and the second epitaxial layer 53 are stacked on one side of the substrate 51 along the first direction X, where the first direction X is the thickness direction of the substrate 51, and the second epitaxial layer 53 is farther away from the substrate 51 than the first epitaxial layer 52.

[0084] Two well regions 531 and a doped portion 54 are disposed in the second epitaxial layer 53. The two well regions 531 are located on opposite sides of the doped portion 54 along the second direction Y, and a portion of the second epitaxial layer 53 is located between the well regions 531 and the doped portion 54. The second direction Y is perpendicular to the first direction X.

[0085] Taking an N-type doped semiconductor device as an example, the substrate 51, the first epitaxial layer 52, and the second epitaxial layer 53 are all N-type doped, while the well region 531 and the doped part 54 are all P-type doped.

[0086] In addition, the trap region 531 also includes a P+ region 5311 and an N+ region 5312.

[0087] The above concept also applies to P-type doped semiconductor devices; simply invert the doping type of each layer involved. By having two well regions 531 located on opposite sides of the doped portion 54 along the second direction Y, a symmetrical conductive structure with dual current paths can be achieved, improving current conduction capability and optimizing breakdown voltage characteristics. In semiconductor device 1, two gates 55 are disposed on the side of the second epitaxial layer 53 away from the substrate 51, and the two gates 55 are spaced apart along the second direction Y. Each dielectric layer 56 encapsulates one gate 55 and is in contact with the well region 531, the doped portion 54, and the portion of the second epitaxial layer 53 located between the well region 531 and the doped portion 54. The dielectric layer 56 includes a gate oxide layer 561 and an oxide isolation layer 562. The gate oxide layer 561 is located between the gate 55 and the epitaxial layer 52, and the oxide isolation layer 562 covers the surface of the gate 55 away from the substrate 51 and its two sides, thus encapsulating the gate 55. A source layer 57 is disposed on the side of the second epitaxial layer 53 and the dielectric layer 56 away from the substrate 51, and the source layer 57 contacts the doped portion 54 to form an ohmic contact. A drain layer 58 is disposed on the opposite side of the substrate 51 relative to the first epitaxial layer 52, and the drain layer 58 contacts the substrate 51 to form an ohmic contact.

[0088] By setting the doped portion 54 to contact the source layer 57, especially when the doped portion 54 and the source layer 57 form a good ohmic contact, holes can be more easily absorbed by the doped portion 54 and enter the source layer 57, thereby reducing the hole concentration in the well region 531. This prevents the parasitic transistor composed of the second epitaxial layer 53, the first well region 531, and the N+ region 5311 in the first well region 531 from turning on, which would lead to current concentration and irreversible burn-out failure of the semiconductor device 1.

[0089] Furthermore, by setting the dielectric layer 56 to wrap the gate 55 and the doped portion 54 to contact the dielectric layer 56, the holes accumulated below the dielectric layer 56 can be extracted into the source layer 57, preventing the holes from inducing electrons in the gate 55, thereby forming a strong electric field in the dielectric layer 56, which would lead to an increase in leakage current or even breakdown of the dielectric layer 56.

[0090] Continue to refer to Figure 5AThe semiconductor device 1 also includes two shielding layers 59 and a current spreading layer 60. The shielding layers 59 and the current spreading layer 60 are disposed in the first epitaxial layer 52. The two shielding layers 59 are located on opposite sides of the current spreading layer 60 along the second direction Y. Each shielding layer 59 and a well region 531 overlap along the first direction X, and the current spreading layer 60 overlaps with the doped portion 54 along the first direction X.

[0091] In the semiconductor device 1 described above, under reverse bias, the two shielding layers 59 can modulate the distribution of the electric field, making the electric field uniformly distributed at the interface between the shielding layer 59 and the current spreading layer 60. This reduces the local electric field peak at the interface between the well region 531 and the second epitaxial layer 53, thereby effectively mitigating the acceleration effect on holes. In some embodiments, reference continues to... Figure 5A The first epitaxial layer 52 includes a first portion 521 and a second portion 522 disposed along a first direction X. The first portion 521 is closer to the substrate 51 than the second portion 522. Two shielding layers 59 and a current spreading layer 60 are disposed in the second portion 522. The side surface of each shielding layer 59 away from the substrate 51 is in contact with a well region 531. The side surfaces of the two shielding layers 59 and the current spreading layer 60 close to the substrate 51 are in contact with the first portion 521 of the first epitaxial layer 52.

[0092] By setting the side surface of each shielding layer 59 away from the substrate 51 to contact a well region 531, and the side surface of the two shielding layers 59 and the current spreading layer 60 close to the substrate 51 to contact the first portion 521 of the first epitaxial layer 52, holes can be extracted to the source layer 57 through the channel formed by the first epitaxial layer 52, the shielding layer 59, the well region 531, and the doped portion 54. The shielding layer 59 and the substrate 51 are separated by the first portion 521 of the first epitaxial layer 52, which facilitates electrons to reach the drain layer 58 by passing through the second epitaxial layer 53, the current spreading layer 60, the first portion 521 of the first epitaxial layer 52, and the substrate 51 in sequence.

[0093] In some embodiments, the first epitaxial layer 52, the second epitaxial layer 53, and the current spreading layer 60 have the same doping type, and the well region 531, the doped portion 54, and the shielding layer 59 have the same doping type. Furthermore, the semiconductor device 1 meets at least one of the following conditions, wherein the semiconductor device 1 may meet one, two, or more of the following conditions, or all of them. The conditions are: The doping concentration of doped portion 54 is greater than the doping concentration of well region 531. The doping concentration of doped portion 54 is greater than the doping concentration of shielding layer 59. The doping concentration of shielding layer 59 is greater than the doping concentration of well region 531. The doping concentration of current spreading layer 60 is greater than the doping concentration of second epitaxial layer 53; the doping concentration of second epitaxial layer 53 is greater than the doping concentration of first epitaxial layer 52.

[0094] Setting the doping concentration of the doped portion 54 to be greater than that of the well region 531 helps the doped portion 54 to form a good ohmic contact with the source layer 57. This facilitates the absorption of holes by the doped portion 54 into the source layer 57, reducing the hole concentration in the well region 531. This prevents parasitic transistors from turning on, which could lead to current concentration and irreversible burn-out failure of the semiconductor device. Simultaneously, it also reduces the number of holes accumulating below the gate oxide layer 561, preventing holes from inducing electrons at the gate and creating a strong electric field in the gate oxide layer 561, which could increase leakage current or even cause the gate oxide layer 561 to break down.

[0095] Setting the doping concentration of the shielding layer 59 to be less than that of the doped portion 54 can prevent the strong electric field from accumulating locally at the corner between the shielding layer 59 and the second epitaxial layer 53, which could cause the semiconductor device 1 to break down prematurely.

[0096] By setting the doping concentration of the shielding layer 59 to be greater than that of the well region 531, the depletion region formed by the shielding layer 59 under the same voltage can be narrowed, suppressing its lateral depletion effect. By setting the doping concentration of the current spreading layer 60 to be greater than that of the second epitaxial layer 53, the depletion region formed by the current spreading layer 60 under the same voltage can be narrowed, and its depletion width is correspondingly reduced, suppressing its lateral depletion effect, thereby reducing the forward conduction resistance.

[0097] By setting the doping concentration of the second epitaxial layer 53 to be greater than that of the first epitaxial layer 52, the forward conduction resistance of the second epitaxial layer 53 can be reduced, which is beneficial for current transmission. In some embodiments, a portion of the second epitaxial layer 53 is located on the side of the first doped portion 54 closer to the first epitaxial layer 52. The surface of the current spreading layer 60 away from the substrate 51 is in contact with the second epitaxial layer 53. That is, the first doped portion 54 and the current spreading layer 60 are separated by the second epitaxial layer 53, and one surface of the current spreading layer 60 is in contact with the second epitaxial layer 53.

[0098] With the above configuration, electrons can pass through the second epitaxial layer 53, the current spreading layer 60, and the first epitaxial layer 52 in sequence to finally reach the drain layer 58.

[0099] In some embodiments, continue to refer to Figure 5A , Figure 5B The dimension H2 of the shielding layer 59 along the second direction Y at the end near the substrate 51 is smaller than the dimension H1 of the shielding layer 59 along the second direction Y at the end away from the substrate 51.

[0100] The shielding layer 59 has a smaller dimension H2 along the second direction Y at the end near the substrate 51. As a result, the current spreading layer 60, which is in the same layer as the shielding layer 59 and in contact with it, has a larger dimension along the second direction Y at the end near the substrate 51. During the forward conduction of electrons to the drain layer 58, the larger dimension along the second direction Y at the end of the current spreading layer 60 near the substrate 51 ensures the lateral expansion of electrons, thereby reducing the forward conduction resistance.

[0101] In some embodiments, continue to refer to Figure 5A , Figure 5B The portion of the surface of the shielding layer 59 away from the substrate 51 is in contact with the second epitaxial layer 53, that is, the dimension of the shielding layer 59 away from the substrate 51 along the second direction Y is greater than the dimension of the well region 531 along the second direction Y.

[0102] Under reverse bias, since the electric field is distributed at the interface between the shielding layer 59 and the current spreading layer 60, and the dimension of the shielding layer 59 away from the substrate 51 along the second direction Y is larger than the dimension of the well region 531 along the second direction Y, the peak value of the electric field at the corner of the interface between the well region 531 and the second epitaxial layer 53 can be further reduced, thus playing a shielding role at the corner of the interface between the first well region 531 and the second epitaxial layer 53.

[0103] In some embodiments, such as Figure 5A , Figure 5B As shown, along the first direction X and from the first epitaxial layer 52 to the second epitaxial layer 53, the size of the shielding layer 59 increases in a stepped manner along the second direction Y, where there may be one step or multiple steps.

[0104] By setting the size of the shielding layer 59 to increase in a stepped manner along the second direction Y, while ensuring the lateral expansion of the current, the electric field originally located at the corner between the well region 531 and the second epitaxial layer 53 can be distributed by multiple corners of the shielding layer 59 and the current expansion layer 60, so as to uniformly distribute the electric field and reduce the local peak of the electric field, thereby avoiding the turn-on of parasitic transistors.

[0105] In some embodiments, such as Figure 6 As shown, along the first direction X and from the first epitaxial layer 52 to the second epitaxial layer 53, the size of the shielding layer 59 gradually increases along the second direction Y.

[0106] By gradually increasing the size of the shielding layer 59 along the second direction Y, a more uniform electric field distribution can be achieved.

[0107] In some embodiments, such as Figure 7As shown, the shielding layer 59 includes a first sub-shielding layer 5911 and a second sub-shielding layer 5912. Along the first direction X and from the first epitaxial layer 52 to the second epitaxial layer 53, the size of the first sub-shielding layer 5911 gradually increases along the second direction Y, while the size of the second sub-shielding layer 5912 remains unchanged along the second direction Y.

[0108] By setting the shielding layer 59 to include a first sub-shielding layer 5911 and a second sub-shielding layer 5912, wherein the first sub-shielding layer 5911 gradually increases in size along the second direction Y, while the second sub-shielding layer 5912 remains unchanged in size along the second direction Y, the electric field distribution can be further homogenized while ensuring the lateral expansion of the current.

[0109] In some embodiments, such as Figure 8A , Figure 8B As shown, the dimension H2 of the shielding layer 59 along the second direction Y at the end near the substrate 51 is greater than the dimension H1 of the shielding layer 59 along the second direction Y at the end away from the substrate 51.

[0110] By setting the dimension H2 of the shielding layer 59 along the second direction Y at the end near the substrate 51 to be greater than the dimension H1 of the shielding layer 59 along the second direction Y at the end away from the substrate 51, that is, the contact area between the shielding layer 59 and the first epitaxial layer 52 along the second direction Y is larger, which is beneficial to the hole extraction efficiency of the shielding layer 59 and further facilitates the extraction of holes to the source layer 57.

[0111] In some embodiments, continue to refer to Figure 8A , Figure 8B The surface portion of the current spreading layer 60 at the end furthest from the substrate 51 contacts the well region 531. That is, the dimension of the end of the current spreading layer 60 furthest from the substrate 51 along the second direction Y is larger.

[0112] With the above settings, during the process of electrons flowing to the drain layer 58, it helps the electrons to expand laterally from the second epitaxial layer 53 into the current extension layer 60, and reduces the forward conduction resistance of electrons during the process of electrons flowing from the second epitaxial layer 53 into the current extension layer 60.

[0113] In some embodiments, continue to refer to Figure 8A , Figure 8B Along the first direction X, from the first epitaxial layer 52 to the second epitaxial layer 53, the size of the shielding layer 59 decreases in a stepped manner along the second direction Y. This can be one or more steps.

[0114] This configuration effectively increases the hole extraction efficiency of the shielding layer 59 and allows the electric field to be located at multiple corners or interfaces between the shielding layer 59 and the current extension layer 60, resulting in a uniform electric field distribution and an electric field shielding effect at the corner of the interface between the well region 531 and the second epitaxial layer 53.

[0115] In some embodiments, such as Figure 9 As shown, along the first direction X and from the first epitaxial layer 52 to the second epitaxial layer 53, the size of the shielding layer 59 gradually decreases along the second direction Y.

[0116] In some embodiments, such as Figure 10 As shown, along the first direction X and from the first epitaxial layer 52 to the second epitaxial layer 53, the shielding layer 59 further includes a first sub-shielding layer 5911 and a second sub-shielding layer 5912. The size of the first sub-shielding layer 5911 along the second direction Y remains unchanged, while the size of the second sub-shielding layer 5912 gradually decreases along the second direction Y.

[0117] This setup effectively increases the hole extraction efficiency of the shielding layer 59 and further unifies the electric field distribution.

[0118] In some embodiments, such as Figure 11 As shown, the shielding layer 59 includes a plurality of shielding portions 59A, which are spaced apart along a third direction Z. The third direction Z is perpendicular to the first direction X and intersects the arrangement direction of the second direction Y. A portion of the current spreading layer 60 is located between two adjacent shielding portions 59A along the third direction Z.

[0119] By configuring the shielding layer 59 to include multiple shielding portions 59A, wherein the multiple shielding portions 59A are spaced apart along the third direction Z, and a current spreading layer 60 is disposed between two adjacent shielding portions 59A, the hole extraction efficiency of the shielding layer 59 and the uniform distribution of the electric field can be guaranteed, while the area occupied by the current spreading layer 60 can be increased, thereby further optimizing the forward conduction characteristics of the device and reducing the forward conduction resistance.

[0120] Based on the above semiconductor device 1, this application also tested the peak electric field at the gate oxide layer 561 and the drain layer 58 current during irradiation to analyze the suppression effect of semiconductor device 1 on radiation effect during irradiation.

[0121] refer to Figure 12 , Figure 12 A comparison curve showing the change of peak electric field (MV / cm) of gate oxide layer of a semiconductor device 1 provided in some embodiments of this disclosure and that of a semiconductor device 300 in related technologies over time (s).

[0122] like Figure 12 As shown, compared with the peak electric field of the gate oxide layer of semiconductor device 300 in the related art, the gate oxide layer of semiconductor device 1 has a peak electric field of 10. -10The smaller internal electric field and smaller peak electric field of semiconductor device 1 are due to the fewer holes accumulated under the gate oxide layer of semiconductor device 1, which avoids the large number of holes accumulating to induce a large number of electrons in the gate to form a strong electric field. Therefore, semiconductor device 1 has better resistance to strong electric fields caused by radiation.

[0123] refer to Figure 13 , Figure 13 A comparison graph showing the change of drain layer current (A) over time (s) of a semiconductor device 1 provided in some embodiments of this disclosure and a semiconductor device 300 in related technologies.

[0124] like Figure 13 As shown, the drain layer current of semiconductor device 1 has two peaks, the first peak being located at 10. -12 S-10 -11 Within the time interval of s, the second peak is located at 10. -10 S-10 -9 The drain layer current of semiconductor device 300 has only one peak value, located at 10. -10 S-10 -9 s.

[0125] Among them, the first peak value of semiconductor device 1 is the current generated when holes are extracted to the source layer through the doped part. It can be seen that semiconductor device 1 can effectively extract holes to the source layer by setting the doped part, thereby avoiding the stacking of holes under the gate oxide layer.

[0126] Furthermore, compared to semiconductor device 300 in related technologies, semiconductor device 1 has a lower performance in 10... -10 S-10 -9 The peak current of the drain layer is smaller during the time interval s, which means that during irradiation, the transient hole current generated by the ionization of high-energy particles, when flowing through the resistance in the well region, does not produce a forward bias voltage sufficient to turn on the parasitic NPN transistor, thus suppressing single-event burn-out. Therefore, semiconductor device 1 has better resistance to strong irradiation electric fields.

[0127] Some embodiments of this disclosure also provide a method for fabricating semiconductor device 1. Figures 14A-14H The diagram shows the structural diagrams corresponding to each step in the fabrication method of the semiconductor device 1 provided in some embodiments.

[0128] S1, such as Figure 14A As shown, a first epitaxial layer 52 is formed on one side of the substrate 51 along the first direction X, where the first direction X is the thickness direction of the substrate 51.

[0129] The material of the first epitaxial layer 52 can be, for example, semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3), and the preparation method of the first epitaxial layer 52 can be, for example, an epitaxial process.

[0130] S2, such as Figure 14B As shown, two shielding layers 59 and a current spreading layer 60 are formed in the first epitaxial layer 52, with the two shielding layers 59 located on opposite sides of the current spreading layer 60 along the second direction Y.

[0131] The two shielding layers 59 and the current spreading layer 60 can be prepared by, for example, an ion implantation process. The current spreading layer 60 is formed by general ion implantation in the upper half of the first epitaxial layer 52 away from the substrate 51, and then the shielding layer 59 is formed by selective ion implantation.

[0132] Specifically, the number of ion implantation processes for the shielding layer 59 is selected based on the target shape of the shielding layer 59. For example, if the shielding layer 59 has a three-step shape, it needs to be achieved through three independent masking and ion implantation processes. Each masking process defines an implantation window along the second direction Y using a mask with a specific opening width. Subsequent ion implantation under this window forms a doped step with a corresponding lateral width. Through three such process cycles, three decreasing (or increasing) widths are defined respectively, ultimately stacked in the vertical direction to form the desired three-step shielding layer 59.

[0133] S3, such as Figure 14C As shown, a second epitaxial layer 53 is formed on the side of the first epitaxial layer 52 away from the substrate 51.

[0134] The second epitaxial layer 53 can also be a semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3), and the preparation method of the second epitaxial layer 53 can be an epitaxial process. The second epitaxial layer 53 can be doped at a higher concentration through a secondary epitaxial process to reduce the on-resistance.

[0135] S4, such as Figure 14D As shown, two well regions 531 and a doped portion 54 are formed in the second epitaxial layer 53. The two well regions 531 are located on opposite sides of the doped portion 54 along the second direction Y. The portion 53 of the second epitaxial layer is located between the well regions 531 and the doped portion 54. The second direction Y is perpendicular to the first direction X. Each shielding layer 59 and one well region 531 overlap along the first direction X.

[0136] While forming the doped portion 54, the P+ region 5311 within the well region 531 can also be formed simultaneously, followed by the formation of the N+ region 5312 via ion implantation. The well region 531, doped portion 54, P+ region 5311, and N+ region 5312 can be fabricated, for example, by ion implantation. The implantation depth of the well region 531 along the first direction X must be at least greater than the thickness of the second epitaxial layer 53 to achieve regional contact or overlap between the well region 531 and the first epitaxial layer 52. The implantation depth of the doped portion 54 along the first direction X is less than the implantation depth of the well region 531 along the first direction X.

[0137] Each well region 531 and a shielding layer 59 overlap along the first direction X to control the potential of the shielding layer 59 by a subsequently formed source layer.

[0138] S5. Two gates 55 and two dielectric layers 56 are formed on the side of the second epitaxial layer 53 away from the substrate 51. The two gates 55 are spaced apart along the second direction Y. Each dielectric layer 56 encloses one gate 55 and contacts the well region 531, the doped portion 54, and the portion of the second epitaxial layer 53 located between the well region 531 and the doped portion 54.

[0139] The dielectric layer 56 includes a gate oxide layer 561 and an oxide isolation layer 562. The gate oxide layer 561 is located between the gate 55 and the epitaxial layer 52. The oxide isolation layer 562 covers the surface of the gate 55 away from the substrate 51 and the two sides, thereby achieving the encapsulation of the gate 55.

[0140] During the fabrication of gate 55 and dielectric layer 56, such as Figure 14E As shown, an initial gate oxide layer 561' is first formed on the side of the second epitaxial layer 53 away from the substrate 51. The initial gate oxide layer 561' can be fabricated by, for example, a thermal oxidation process, and its thickness is relatively thin, about 50 nm. Then, a gate layer is deposited on the side of the initial gate oxide layer 561' away from the second epitaxial layer 53, and the gate layer is etched to form the first gate 55.

[0141] like Figure 14F As shown, an initial oxide isolation layer is then deposited on the side of the gate 55 and the initial oxide layer away from the second epitaxial layer 53. Finally, a mask process can be used to selectively etch the initial oxide isolation layer and the initial gate oxide layer to form the gate oxide layer 561 and the oxide isolation layer 562, which together form the dielectric layer 56. This exposes the doped portion 54 in the underlying second epitaxial layer 53 and the P+ region 5311 and N+ region 5312 in the well region 531. The gate oxide layer 561 can also contact the well region 531, the doped portion 54, and the portion of the second epitaxial layer 53 located between the well region 531 and the doped portion 54.

[0142] S6, such as Figure 14GAs shown, a source layer 57 is formed on the side of the second epitaxial layer 53 and the dielectric layer 56 away from the substrate 51, and the source layer 57 is in contact with the first doped portion 54.

[0143] The source layer 57 can be formed by deposition process, or by, for example, high-temperature thermal annealing process to form an ohmic contact between the source layer 57 and the first doped part 54.

[0144] S7, such as Figure 14H As shown, a drain layer 58 is formed on the opposite side of the substrate 51 relative to the first epitaxial layer 52.

[0145] The drain layer 58 can also be formed by deposition process, or by, for example, high-temperature laser annealing process to form ohmic contact between the drain layer 58 and the substrate 51.

[0146] The method for fabricating semiconductor device 1 has the same beneficial technical effects as the semiconductor device 1 provided in some of the above embodiments, and will not be described again here.

[0147] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A first epitaxial layer and a second epitaxial layer are stacked on one side of the substrate along a first direction, the first direction being the thickness direction of the substrate, and the second epitaxial layer is further away from the substrate than the first epitaxial layer; A doped portion and two well regions are disposed in the second epitaxial layer. The two well regions are respectively located on opposite sides of the doped portion along a second direction, and a portion of the second epitaxial layer is located between the well regions and the doped portion. The second direction is perpendicular to the first direction. A current spreading layer and two shielding layers are disposed in the first epitaxial layer; the two shielding layers are respectively located on opposite sides of the current spreading layer along the second direction, each shielding layer overlaps with a well region along the first direction, and the current spreading layer overlaps with the doped portion along the first direction; Two gates are disposed on the side of the second epitaxial layer away from the substrate and are spaced apart along the second direction; Two dielectric layers, each of which encloses one of the gates and is in contact with the well region, the doped portion, and the portion of the second epitaxial layer located between the well region and the doped portion; A source layer is disposed on the side of the second epitaxial layer and the dielectric layer away from the substrate, and the source layer is in contact with the doped portion; A drain layer is disposed on the substrate opposite to the first epitaxial layer.

2. The semiconductor device according to claim 1, characterized in that, The first epitaxial layer includes a first portion and a second portion disposed along the first direction, wherein the first portion is closer to the substrate than the second portion, and the current spreading layer and the two shielding layers are both disposed in the second portion; The surface of each shielding layer away from the substrate contacts one of the well regions; the surfaces of the two shielding layers and the current spreading layer near the substrate contact the first portion.

3. The semiconductor device according to claim 1, characterized in that, The first epitaxial layer, the second epitaxial layer, and the current spreading layer have the same doping type, and the well region, the doped portion, and the shielding layer have the same doping type. The semiconductor device meets at least one of the following conditions: The doping concentration of the doped region is greater than the doping concentration of the well region; The doping concentration of the doped portion is greater than the doping concentration of the shielding layer; The doping concentration of the shielding layer is greater than the doping concentration of the well region; The doping concentration of the current spreading layer is greater than the doping concentration of the second epitaxial layer; The doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer.

4. The semiconductor device according to claim 1, characterized in that, The dimension of the shielding layer at the end near the substrate along the second direction is smaller than the dimension of the shielding layer at the end away from the substrate along the second direction.

5. The semiconductor device according to claim 4, characterized in that, A portion of the surface of the shielding layer on the side away from the substrate is in contact with the second epitaxial layer.

6. The semiconductor device according to claim 4, characterized in that, Along the first direction and from the first epitaxial layer to the second epitaxial layer, The dimensions of the shielding layer increase in a stepped manner along the second direction; or... The dimension of the shielding layer gradually increases along the second direction; or... The shielding layer includes a first sub-shielding layer and a second sub-shielding layer. The size of the first sub-shielding layer gradually increases along the second direction, while the size of the second sub-shielding layer remains unchanged along the second direction.

7. The semiconductor device according to claim 1, characterized in that, The dimension of the shielding layer at the end near the substrate along the second direction is greater than the dimension of the shielding layer at the end away from the substrate along the second direction.

8. The semiconductor device according to claim 7, characterized in that, A portion of the surface of the current spreading layer at the end furthest from the substrate is in contact with the first well region.

9. The semiconductor device according to claim 7, characterized in that, Along the first direction and from the first epitaxial layer to the second epitaxial layer, The dimensions of the shielding layer decrease in a stepped manner along the second direction; or... The dimension of the shielding layer gradually decreases along the second direction; or... The shielding layer includes a first sub-shielding layer and a second sub-shielding layer. The first sub-shielding layer has a constant dimension along the second direction, while the second sub-shielding layer has a gradually decreasing dimension along the second direction.

10. The semiconductor device according to claim 1, characterized in that, The shielding layer includes a plurality of shielding portions, which are spaced apart along a third direction; the third direction is perpendicular to the first direction and intersects the second direction. A portion of the current spreading layer is located between two adjacent shielding portions along the third direction.

11. An electronic device, characterized in that, include: The semiconductor device and circuit board as described in any one of claims 1 to 10, wherein the semiconductor device is disposed on the circuit board.

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