Thin film transistor, manufacturing method thereof and array substrate

Abstract

The invention provides a thin film transistor, a manufacturing method thereof and an array substrate. The thin film transistor comprises a substrate; the first electrode is arranged on one side of the substrate, and the first insulating layer is arranged on the side, away from the substrate, of the first part; the second electrode is arranged on the side, away from the substrate, of the first insulating layer; at least part of the carrier isolation layer is arranged on the side, away from the substrate, of the second electrode; the semiconductor layer is arranged on the side, away from the substrate, of the first area and covers the second side wall and at least part of the third area; the carrier concentration of the carrier isolation layer is smaller than that of the semiconductor layer. The carrier isolation layer is arranged between the second electrode and the semiconductor layer and covers part of the first electrode, and the carrier concentration of the carrier isolation layer is lower than that of the semiconductor layer, so that carrier injection from the first electrode and the second electrode to the semiconductor layer is effectively inhibited, and the reliability of the device is improved. Therefore, the threshold voltage stability of the thin film transistor is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a thin-film transistor, its fabrication method, and an array substrate. Background Technology

[0002] In current display panels composed of multiple pixel units, each pixel unit or sub-pixel unit is equipped with at least one thin-film transistor (TFT). The core function of the TFT is to turn on in precise timing in response to a scan signal, and to write the voltage or current corresponding to the data signal to the pixel electrode electrically connected to the TFT. After the scan signal is removed, the TFT turns off, and the voltage or current written to the pixel electrode is substantially maintained for one frame, thereby controlling the light emission brightness or light transmission state of the pixel unit during display, thus achieving image display.

[0003] However, the performance of thin-film transistors still needs improvement. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a thin-film transistor, a method for fabricating the same, and an array substrate, which are beneficial for improving the performance of thin-film transistors.

[0005] To achieve the above objectives, one embodiment of this application provides a thin-film transistor, comprising: a substrate; a first electrode disposed on one side of the substrate, including a first portion and a second portion disposed adjacent to each other; a first insulating layer disposed on the side of the first portion away from the substrate; the first insulating layer including a first sidewall; a second electrode disposed on the side of the first insulating layer away from the substrate; a carrier isolation layer, at least a portion of the carrier isolation layer disposed on the side of the second electrode away from the substrate; at least a portion of the carrier isolation layer also covers the first sidewall and a portion of the second portion; the carrier isolation layer including a second sidewall covering the first sidewall; a semiconductor layer disposed on the side of the carrier isolation layer away from the substrate and covering the second sidewall; the carrier concentration of the carrier isolation layer is less than the carrier concentration of the semiconductor layer.

[0006] In some embodiments, the semiconductor layer includes a third sidewall covering the second sidewall; the thin-film transistor further includes: a second insulating layer disposed on the side of the semiconductor layer away from the substrate and covering the third sidewall; the second insulating layer includes a fourth sidewall covering the third sidewall; and a control electrode disposed on the side of the second insulating layer away from the substrate and covering the fourth sidewall.

[0007] In some embodiments, the thin-film transistor further includes a carrier protection layer, which is disposed at least between the second insulating layer and the semiconductor layer.

[0008] In some embodiments, the proportion of indium atoms in the carrier protection layer among all metal atoms in the carrier protection layer ranges from 0% to 30%.

[0009] In some embodiments, the thickness of the carrier protection layer ranges from 0.1 nm to 5 nm.

[0010] In some embodiments, the orthographic projection of the carrier isolation layer on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate.

[0011] In some embodiments, the orthographic projection of the carrier isolation layer on the substrate overlaps with the orthographic projection of the semiconductor layer on the substrate.

[0012] In some embodiments, the orthographic projection of the charge carrier isolation layer on the substrate is within the orthographic projection of the semiconductor layer on the substrate.

[0013] In some embodiments, the orthographic projection of the semiconductor layer on the substrate is within the orthographic projection of the charge carrier isolation layer on the substrate.

[0014] In some implementations, the first sidewall is a non-annular surface.

[0015] In some embodiments, the first sidewall is an annular surface.

[0016] In some embodiments, the second sidewall is an annular surface.

[0017] In some embodiments, the carrier concentration of the semiconductor layer ranges from 10. 17 ~10 per cubic centimeter 20 Each cubic centimeter.

[0018] In some embodiments, the proportion of indium atoms in the semiconductor layer among all metal atoms in the semiconductor layer ranges from 40% to 100%.

[0019] In some embodiments, the carrier concentration of the carrier isolation layer ranges from 10. 15 ~10 per cubic centimeter 17 Each cubic centimeter.

[0020] In some embodiments, the proportion of indium atoms in the carrier isolation layer among all metal atoms in the carrier isolation layer ranges from 0% to 50%.

[0021] In some embodiments, the metal element of the semiconductor layer includes indium and at least one of gallium, zinc, tin, germanium or aluminum.

[0022] In some embodiments, the thickness of the semiconductor layer ranges from 5 nm to 20 nm; In some embodiments, the metal element of the carrier isolation layer includes at least one of indium, gallium, zinc, tin, germanium, or aluminum.

[0023] In some embodiments, the thickness of the carrier isolation layer is greater than 0.1 nm and less than or equal to 10 nm.

[0024] In some embodiments, at least a portion of the orthographic projection of the charge carrier protection layer onto the substrate overlaps with the orthographic projection of the semiconductor layer onto the substrate.

[0025] In some embodiments, the orthographic projection of the charge carrier protection layer on the substrate overlaps with the orthographic projection of the semiconductor layer on the substrate.

[0026] In some embodiments, the orthographic projection of the semiconductor layer on the substrate is within the orthographic projection of the charge carrier protection layer on the substrate.

[0027] This application provides an array substrate including thin-film transistors as described in any of the above descriptions.

[0028] This application provides a method for fabricating a thin-film transistor, comprising: providing a substrate; disposing a first electrode on one side of the substrate; the first electrode comprising a first portion and a second portion disposed adjacent to each other; disposing a first insulating layer on the side of the first portion away from the substrate; the first insulating layer comprising a first sidewall; disposing a second electrode on at least a portion of the first insulating layer away from the substrate; disposing a carrier isolation layer on the side of the second electrode away from the substrate; the carrier isolation layer covering the first sidewall and a portion of the second portion; the carrier isolation layer comprising a second sidewall covering the first sidewall; disposing a semiconductor layer on the carrier isolation layer away from the substrate; the semiconductor layer covering the second sidewall; and the carrier concentration of the carrier isolation layer being less than the carrier concentration of the semiconductor layer.

[0029] In some embodiments, the step of forming a carrier isolation layer on the side of the second electrode away from the substrate includes: forming the carrier isolation layer on the side of the second electrode away from the substrate using an atomic layer deposition process; correspondingly, the step of forming a semiconductor layer on the side of the carrier isolation layer away from the substrate includes: forming the semiconductor layer on the side of the carrier isolation layer away from the substrate using the atomic layer deposition process.

[0030] One embodiment of this application provides a thin-film transistor that, compared with the prior art, has the following advantages: a first electrode, a first insulating layer, and a second electrode are sequentially stacked on a substrate, and a semiconductor layer constitutes a vertical electrode structure, i.e., a thin-film transistor. By providing a carrier isolation layer between the second electrode and the semiconductor layer, the carrier isolation layer extends to cover a portion of the first electrode. The carrier concentration of the carrier isolation layer is lower than that of the semiconductor layer, effectively suppressing carrier injection from the first electrode and the second electrode into the semiconductor layer, thereby improving the threshold voltage stability of the thin-film transistor. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A schematic diagram of a related thin-film transistor is provided for one embodiment of this application; Figure 2 A schematic diagram of a related thin-film transistor is provided for one embodiment of this application; Figure 3 A schematic diagram of a related thin-film transistor is provided for one embodiment of this application; Figure 4 A partial top view of a related thin-film transistor provided for one embodiment of this application; Figure 5 A schematic diagram of a related thin-film transistor is provided for one embodiment of this application; Figure 6 A partial top view of a related thin-film transistor provided for one embodiment of this application; Figure 7 A schematic diagram of a related thin-film transistor is provided for one embodiment of this application; Figure 8 A partial top view of a related thin-film transistor provided for one embodiment of this application; Figure 9 A flowchart of a related thin-film transistor fabrication method provided for one embodiment of this application.

[0033] Marker explanation: 100, Thin-film transistor; 110, Substrate; 120, First electrode; 121, First portion; 122, Second portion; 130, First insulating layer; 131, First sidewall; 140, Second electrode; 150, Carrier isolation layer; 151, First region; 152, Second sidewall; 153, Third region; 160, Semiconductor layer; 161, Fourth region; 162, Third sidewall; 163, Fifth region; 170, Second insulating layer; 180, Control electrode; 190, Carrier protection layer. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0035] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] With the rapid development of high-resolution display technology, the size of thin-film transistors (TFTs) needs to be continuously reduced to meet requirements such as narrow bezels and high pixel density. However, the size of traditional planar TFT structures is limited by the resolution of photolithography equipment, making further miniaturization difficult. Against this backdrop, vertical-channel (VCC) TFT structures have attracted attention because their channel length can be defined by the thickness of the insulating layer, thus avoiding limitations imposed by photolithography resolution. Especially when using high-mobility materials such as metal-oxide-semiconductor (MOS) semiconductors as the active layer, VCC structures demonstrate potential for achieving high driving performance and high integration density. However, new technical challenges have arisen when applying high-mobility materials to VCC structures in related technologies.

[0037] Specifically, the relevant technologies mainly suffer from two problems: First, during the formation of the key structure of the vertical channel—the sidewalls—the etched sidewall surfaces contain a large number of lattice defects and unsaturated chemical bonds (dangling bonds). These defect states directly contact the high-mobility active layer that forms the channel, severely affecting the stability of the thin-film transistor. Second, when the vertical channel length shrinks to less than 1 micrometer, the short-channel effect becomes significant, especially when using high-mobility oxide semiconductors. Charge carriers are more easily injected into the channel from the source / drain electrodes, causing the threshold voltage of the thin-film transistor to easily drift negatively or even fail to turn off normally. Therefore, how to achieve stable threshold voltage control in high-mobility vertical-channel thin-film transistors has become an urgent problem to be solved.

[0038] Please see Figure 1 To address the aforementioned problems, one embodiment of this application provides a thin-film transistor 100, which includes: a substrate 110; a first electrode 120 disposed on one side of the substrate 110, including a first portion 121 and a second portion 122 disposed adjacent to each other; a first insulating layer 130 disposed on the side of the first portion 121 away from the substrate 110; the first insulating layer 130 includes a first sidewall 131; a second electrode 140 disposed on the side of the first insulating layer 130 away from the substrate 110; and a carrier isolation layer 150, to... A small portion of the carrier isolation layer 150 is disposed on the side of the second electrode 140 away from the substrate 110; at least a portion of the carrier isolation layer 150 covers the first sidewall 131 and a portion of the second portion 122; the carrier isolation layer 150 includes a second sidewall 152 covering the first sidewall 131; a semiconductor layer 160 is disposed on the side of the carrier isolation layer 150 away from the substrate 110 and covers the second sidewall 152 and at least a portion of the third region 153; the carrier concentration of the carrier isolation layer 150 is less than the carrier concentration of the semiconductor layer 160.

[0039] In this embodiment, the thin-film transistor 100 may include a first electrode 120, a first insulating layer 130, and a second electrode 140 stacked together. Then, a carrier isolation layer 150 is disposed on the side of the second electrode 140 away from the substrate 110. The carrier isolation layer 150 extends to cover the first sidewall 131 and a portion of the second portion 122 of the first insulating layer 130. A semiconductor layer 160 is disposed on the side of the carrier isolation layer 150 away from the substrate 110 and covers the second sidewall 152, thereby improving the performance of the thin-film transistor 100.

[0040] The substrate 110 can be a base used to carry and support all subsequent thin film layers and structures. For example, the substrate 110 can be a glass substrate 110, a silicon substrate 110, or a flexible polymer substrate 110, etc.

[0041] The first electrode 120 may be a conductive layer disposed on one side of the substrate 110, serving as the source or drain of the thin-film transistor 100. The first electrode 120 includes a first portion 121 and a second portion 122 disposed adjacent to each other. This means that the first portion 121 and the second portion 122 are adjacent to each other in a direction parallel to the plane of the substrate 110, and together they form the pattern of the first electrode 120. For example, the first portion 121 and the second portion 122 may be formed from the same metal layer in the same patterning process, wherein the first portion 121 is used for subsequent stacking with insulating layers and electrodes, while the second portion 122 is directly exposed to contact the semiconductor layer 160.

[0042] The first insulating layer 130 may be a dielectric layer disposed on the side of the first portion 121 away from the substrate 110, and its function is to provide electrical isolation in the vertical direction. The first insulating layer 130 includes a first sidewall 131. The first sidewall 131 is the side of the first insulating layer 130 in the direction perpendicular to the substrate 110. Specifically, since the first insulating layer 130 covers the first portion 121, its edge near the second portion 122 forms the first sidewall 131, thereby defining a stepped structure together with the second portion 122.

[0043] The second electrode 140 may be another conductive layer disposed on the side of the first insulating layer 130 away from the substrate 110, and its function is to serve as the drain or source of the thin-film transistor 100 (with the opposite polarity to the first electrode 120). The second electrode 140 achieves vertical electrical isolation from the first electrode 120 (first portion 121) below it through the first insulating layer 130.

[0044] At least a portion of the carrier isolation layer 150 is disposed on the side of the second electrode 140 away from the substrate 110. The function of this carrier isolation layer 150 is to modulate and isolate the transport behavior of carriers (such as electrons) through its specific material properties. Specifically, the carrier isolation layer 150 covers the first sidewall 131 and a portion of the second portion 122. That is, the carrier isolation layer 150 is not only deposited on the top surface of the second electrode 140, but also continuously covers the first sidewall 131 formed by the edge of the first insulating layer 130, and further extends to the surface of the second portion 122 of the first electrode 120. Through this coverage, the carrier isolation layer 150 simultaneously forms a contact interface with the second electrode 140, the first sidewall 131, and the second portion 122.

[0045] The carrier isolation layer 150 may include a second sidewall 152 covering the first sidewall 131. The carrier isolation layer may also include a first region covering at least a portion of the second electrode and a third region 153 covering at least a portion of the second portion. Specifically, the portion of the carrier isolation layer 150 covering the top surface of the second electrode 140 is defined as the first region 151, and the portion of the carrier isolation layer 150 covering the first sidewall 131 of the first insulating layer 130, due to its vertical or inclined side surface, is defined as the second sidewall 152. The portion of the carrier isolation layer 150 covering the surface of the second portion 122 of the first electrode 120 is defined as the third region 153. The first region 151, the second sidewall 152, and the third region 153 are portions of the continuous thin film of the carrier isolation layer 150 at different geometric locations, thus enabling the carrier isolation layer 150 to collectively form a continuous thin film covering a stepped structure.

[0046] Semiconductor layer 160 is a semiconductor material layer disposed on the side of carrier isolation layer 150 away from substrate 110, and its function is to form a channel through which carriers flow in thin-film transistor 100. Semiconductor layer 160 covers the second sidewall 152 and at least a portion of the third region 153. Semiconductor layer 160 is deposited on carrier isolation layer 150 and continuously covers the second sidewall 152 of carrier isolation layer 150, and further extends to cover at least a portion of the third region 153 of carrier isolation layer 150.

[0047] The carrier concentration of semiconductor layer 160 is greater than that of carrier isolation layer 150. Carrier concentration is a physical parameter that measures the number of freely moving charge carriers (electrons) within a unit volume of semiconductor material, and its unit is usually the number per cubic centimeter.

[0048] Semiconductor layer 160 has a high carrier concentration, thus exhibiting good conductivity and serving as the material basis for forming an efficient channel. Carrier isolation layer 150 has a low carrier concentration, thus exhibiting high resistance or weak conductivity. The carrier concentration difference between the two layers leads to a carrier concentration gradient at the interface, inducing band bending. Specifically, the lower carrier concentration causes the Fermi level of carrier isolation layer 150 to be relatively far from its conduction band bottom. When in contact with the semiconductor layer 160, which has a higher Fermi level, electrons tend to diffuse from semiconductor layer 160 to carrier isolation layer 150 to achieve thermal equilibrium, thus forming a depletion region near the interface of carrier isolation layer 150 and establishing an energy barrier that inhibits electron movement from carrier isolation layer 150 to semiconductor layer 160 (channel). This built-in barrier effectively suppresses harmful electron injection from the lower first electrode 120 and second electrode 140 through carrier isolation layer 150 into semiconductor layer 160 (channel) when thin-film transistor 100 is operating. Therefore, the higher carrier concentration of the semiconductor layer 160 ensures the driving capability of the thin film transistor 100, while the lower carrier concentration of the carrier isolation layer 150 ensures the stability of the thin film transistor 100 by building an interface barrier. Together, they achieve a balance between high mobility and high stability.

[0049] By setting the carrier isolation layer 150, direct contact between the first electrode 120, the second electrode 140, and the semiconductor layer 160 is physically isolated, and the interface band structure between the electrodes and the semiconductor layer 160 is electrically modulated. This structure can effectively suppress carrier injection from the first electrode 120 and the second electrode 140 into the semiconductor layer 160, thereby avoiding negative drift of the threshold voltage of the thin-film transistor 100 or even abnormal conduction caused by the electrode injection effect, and improving the electrical stability of the thin-film transistor 100.

[0050] The carrier isolation layer 150 can also buffer or passivate the influence of defect states that may exist on the sidewalls of the first insulating layer 130 on the channel. Specifically, during the etching or deposition process, the first insulating layer 130 may introduce lattice defects and unsaturated chemical bonds on the surface of its first sidewall 131. The carrier isolation layer 150 covers the surface of the first sidewall 131 and physically passivates and electrically shields these defect states through its material interface properties, blocking the carrier capture or scattering path between them and the semiconductor layer 160, thereby suppressing the drift of electrical parameters of the thin-film transistor 100 caused by interface defects and improving its long-term operational reliability.

[0051] The thin-film transistor 100 employs a vertical channel device structure. Its channel length is defined by the thickness of the first insulating layer 130 or the stacked thickness of the carrier isolation layer 150 and the semiconductor layer 160 in the vertical direction, rather than by the horizontal linewidth limitation of the photolithography process. Therefore, it can overcome the resolution limitations of traditional photolithography equipment. By controlling the thin-film deposition thickness, the channel length can be precisely fabricated to less than 1 micrometer. Consequently, the area occupied by the thin-film transistor 100 in the plane of the substrate 110 is significantly reduced, enabling higher device integration density in the array substrate 110, which is beneficial for fabricating display panels with higher pixel density (PPI).

[0052] Please see Figure 2 In some embodiments, the semiconductor layer 160 includes a third sidewall 162 covering the second sidewall 152, and the thin-film transistor 100 further includes: a second insulating layer 170 disposed on the side of the semiconductor layer 160 away from the substrate 110 and covering the third sidewall 162; the second insulating layer 170 includes a fourth sidewall covering the third sidewall 162; and a control electrode 180 disposed on the side of the second insulating layer 170 away from the substrate 110 and covering the fourth sidewall.

[0053] In this embodiment, the semiconductor layer 160 may include a third sidewall 162 covering the second sidewall 152. The semiconductor layer 160 may also include a third region covering at least a portion of the first region and a fifth region covering at least a portion of the third region. Specifically, the portion of the semiconductor layer 160 covering the first region 151 of the carrier isolation layer 150 is defined as the fourth region 161, the portion of the semiconductor layer 160 covering the second sidewall 152 of the carrier isolation layer 150 is defined as the third sidewall 162, and the portion of the semiconductor layer 160 covering the third region 153 of the carrier isolation layer 150 is defined as the fifth region 163. The fourth region 161, the third sidewall 162, and the fifth region 163 are also portions of the continuous thin film 160 at different locations.

[0054] The thin-film transistor 100 may further include a second insulating layer 170. The second insulating layer 170 is disposed on the side of the semiconductor layer 160 away from the substrate 110 and covers the third sidewall 162 of the semiconductor layer 160. The function of the second insulating layer 170 is to serve as a gate insulating layer, electrically isolating the semiconductor layer 160 from the control electrode 180. Specifically, since the second insulating layer 170 covers the surface of the semiconductor layer 160, which has a three-dimensional morphology, it itself also forms a corresponding three-dimensional structure. The second insulating layer 170 includes a fourth sidewall covering the third sidewall 162, and may further include a sixth region and a seventh region. The portion covering the fourth region 161 of the semiconductor layer 160 constitutes the sixth region, the portion covering the third sidewall 162 of the semiconductor layer 160 constitutes the fourth sidewall due to its vertical or inclined side surface, and the portion covering the fifth region 163 of the semiconductor layer 160 constitutes the seventh region.

[0055] The thin-film transistor 100 may further include a control electrode 180. The control electrode 180 is disposed on the side of the second insulating layer 170 away from the substrate 110 and covers the fourth sidewall of the second insulating layer 170. Specifically, the control electrode covers at least a portion of the sixth region and at least a portion of the seventh region. The function of the control electrode 180 is to act as the gate of the thin-film transistor 100, controlling the conduction and turn-off of the transistor by applying a gate voltage to regulate the carrier concentration in the channel (semiconductor layer 160) of the semiconductor layer 160. The structure of the control electrode 180 covering the fourth sidewall allows the gate electric field to be effectively applied laterally to the channel located near the third sidewall 162 of the semiconductor layer 160, enhancing the gate's control over the channel. Simultaneously, the control electrode 180 only covers a portion of the seventh region, which helps to reduce parasitic capacitance associated with the control electrode 180 in the layout.

[0056] By setting a second insulating layer 170 and a control electrode 180, and having them sequentially cover the three-dimensional surface formed by the fourth region 161, the third sidewall 162, and the fifth region 163 of the semiconductor layer 160, a three-dimensional gate structure is formed in which the gate can effectively control the channel from both the top and the side. This structure is particularly beneficial for improving the gate control efficiency of vertical or large-angle tilted channels and enhancing the subthreshold swing and switching characteristics of the thin-film transistor 100.

[0057] Please see Figure 3 In some embodiments, the thin-film transistor 100 further includes a carrier protection layer 190, which is disposed at least between the second insulating layer 170 and the semiconductor layer 160.

[0058] In this embodiment, the thin-film transistor 100 may further include a carrier protection layer 190. The carrier protection layer 190 may be at least partially disposed between the second insulating layer 170 and the semiconductor layer 160. The function of the carrier protection layer 190 is as an additional interface modification and protection structure. Specifically, by being inserted between the second insulating layer 170 and the semiconductor layer 160, the carrier protection layer 190 can further modulate the interface characteristics between the gate insulating layer and the gate metal. For example, the carrier protection layer 190 may be fabricated using a semiconductor material with low carrier concentration or a specific dielectric material, and its band structure is configured to optimize the electric field coupling efficiency between the control electrode 180 and the semiconductor layer 160, while suppressing interface charge injection or ion migration phenomena that may occur when a bias voltage is applied to the control electrode 180. Furthermore, the carrier protection layer 190 may also serve as an etch stop layer or diffusion barrier layer in subsequent processes to protect the underlying second insulating layer 170 and semiconductor layer 160 from damage. The carrier protection layer 190 helps to further improve the threshold voltage stability and long-term reliability of the thin-film transistor 100 under harsh operating conditions such as high temperature and high bias voltage.

[0059] In some embodiments, the proportion of indium atoms in the carrier protection layer 190 among all metal atoms in the carrier protection layer 190 ranges from 0 to 30%.

[0060] In this embodiment, the proportion of indium atoms in the charge carrier protection layer 190 ranges from 0% to 30% among all metal atoms. This material composition characteristic determines the basic electrical properties of the charge carrier protection layer 190. For example, when the proportion of indium atoms approaches 0%, the charge carrier protection layer 190 can be composed of gallium oxide, aluminum oxide, zinc oxide, or a combination thereof, exhibiting extremely high resistivity and good insulation properties; when the proportion of indium atoms is between 1% and 30%, the charge carrier protection layer 190 exhibits weak conductivity or semiconductor properties, and its Fermi level position can be finely adjusted by the indium content to achieve optimal band alignment with the adjacent second insulating layer 170 and control electrode 180. A lower indium content helps ensure that the charge carrier protection layer 190 has a lower charge carrier concentration, thereby effectively suppressing leakage current through the layer and enhancing its passivation effect on charge traps as an interface buffer layer.

[0061] Specifically, the proportion of indium atoms in all metal atoms of the charge carrier protection layer 190 can be 0, 0.5%, 1%, 5%, 6%, 10%, 11%, 12%, 15%, 18%, 20%, 22%, 25%, 28%, or 30%.

[0062] If the proportion of indium atoms in the carrier protection layer 190 is greater than 30% among all metal atoms in the carrier protection layer 190, it will lead to a significant increase in its carrier concentration and an upward shift of the Fermi level, causing the layer to shift from an interface modification function to a conductive property.

[0063] In some implementations, the thickness of the carrier protection layer 190 ranges from 0.1 nm to 5 nm.

[0064] In this embodiment, the thickness of the carrier protection layer 190 can range from 0.1 nm to 5 nm, which can ensure the formation of a continuous thin film with effective coverage, give full play to its interface passivation and band modulation functions, and minimize the negative impact on the overall electrical performance of the device.

[0065] Specifically, the thickness of the carrier protection layer 190 can be 0.1nm, 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 2nm, 2.4nm, 2.5nm, 3nm, 3.5nm, 3.8nm, 4nm, 4.4nm, 4.5nm, or 5nm.

[0066] When the thickness of the charge carrier protection layer 190 is less than 0.1 nm, it is difficult to form a continuous and uniform thin film, and its interface modification and protection functions will be significantly weakened. When the thickness of the carrier protection layer 190 is greater than 5 nm, although the protection effect is enhanced, the gate control efficiency of the control electrode 180 to the semiconductor layer 160 may be degraded due to the introduction of excessive series resistance or capacitance, and the process complexity and cost may be increased.

[0067] In some embodiments, the orthographic projection of the carrier isolation layer 150 on the substrate 110 at least partially overlaps with the orthographic projection of the semiconductor layer 160 on the substrate 110.

[0068] In this embodiment, orthographic projection can be a two-dimensional pattern formed by projecting the three-dimensional shapes of the carrier isolation layer 150 and the semiconductor layer 160 onto the plane of the substrate 110 along a direction perpendicular to the plane of the substrate 110. At least partial overlap means that there are overlapping areas of the two two-dimensional patterns on the plane, that is, they are not completely offset in the vertical direction.

[0069] The carrier isolation layer 150 is at least partially in contact with the semiconductor layer 160, ensuring that the carrier isolation layer 150 is always located between the semiconductor layer 160 and the first electrode 120 and the second electrode 140 of the lower layer in the vertical direction, thereby ensuring that it can perform the core functions of interface isolation and modification.

[0070] In some embodiments, the orthographic projection of the carrier isolation layer 150 on the substrate 110 overlaps with the orthographic projection of the semiconductor layer 160 on the substrate 110.

[0071] In this embodiment, the orthographic projection of the carrier isolation layer 150 onto the substrate 110 can overlap with the orthographic projection of the semiconductor layer 160 onto the substrate 110. This overlap is achieved when viewed along a direction perpendicular to the plane of the substrate 110, the area covered by the carrier isolation layer 150 and the area covered by the semiconductor layer 160 have identical two-dimensional graphic contours and areas on the plane of the substrate 110. This means that, from a top-down view, the semiconductor layer 160 is precisely positioned directly above the carrier isolation layer 150, and the two are precisely aligned in planar layout.

[0072] This fully overlapping layout achieves maximum interface protection and isolation for the semiconductor layer 160. Since any region beneath the semiconductor layer 160 is covered by the carrier isolation layer 150, all possible paths for injecting carriers from the first electrode 120 and the second electrode 140 into the semiconductor layer 160 are effectively modulated by the carrier isolation layer 150. Simultaneously, defects on the sidewalls of the first insulating layer 130 are completely shielded, improving the stability of the thin-film transistor 100. Secondly, this layout simplifies the photolithographic alignment process requirements. During fabrication, the same mask or a self-aligned process can be used to pattern the carrier isolation layer 150 and the semiconductor layer 160, thereby reducing the number of masks, lowering process complexity, and improving manufacturing yield.

[0073] In some embodiments, the orthographic projection of the carrier isolation layer 150 on the substrate 110 lies within the orthographic projection of the semiconductor layer 160 on the substrate 110.

[0074] In this embodiment, the orthographic projection of the carrier isolation layer 150 onto the substrate 110 can be located inside the orthographic projection of the semiconductor layer 160 onto the substrate 110. Viewed from a top-down direction perpendicular to the plane of the substrate 110, the two-dimensional pattern corresponding to the carrier isolation layer 150 is completely contained within the two-dimensional pattern corresponding to the semiconductor layer 160. That is, the coverage area of ​​the semiconductor layer 160 on the plane is larger than that of the carrier isolation layer 150, and the carrier isolation layer 150 only occupies a portion of the area below the semiconductor layer 160.

[0075] The carrier isolation layer 150 is precisely positioned directly beneath the electrically critical channel. Specifically, the carrier isolation layer 150 can primarily cover the portion corresponding to the effective control region of the control electrode 180 (gate), thereby concentrating its interface modification and carrier modulation functions. In non-critical areas, the carrier isolation layer 150 can be omitted to simplify the structure. Secondly, this layout helps reduce the material usage of the carrier isolation layer 150 and its potential parasitic capacitance. Because the carrier isolation layer 150 has a smaller area, the additional capacitance formed between it and the first electrode 120 and the second electrode 140 is correspondingly reduced, which is advantageous for applications requiring high switching speeds and low power consumption. Furthermore, in terms of process implementation, this may mean forming the smaller pattern of the carrier isolation layer 150 first, followed by the larger pattern of the semiconductor layer 160, enabling certain specific integration process sequences.

[0076] In some embodiments, the orthographic projection of the semiconductor layer 160 on the substrate 110 lies within the orthographic projection of the carrier isolation layer 150 on the substrate 110.

[0077] In this embodiment, the orthographic projection of the semiconductor layer 160 onto the substrate 110 lies within the orthographic projection of the carrier isolation layer 150 onto the substrate 110. Viewed from a top-down direction perpendicular to the plane of the substrate 110, the two-dimensional pattern corresponding to the semiconductor layer 160 is completely contained within the two-dimensional pattern corresponding to the carrier isolation layer 150. That is, the coverage area of ​​the carrier isolation layer 150 on the plane is larger than that of the semiconductor layer 160, and the semiconductor layer 160 is completely supported and surrounded by the region extending from below and laterally of the carrier isolation layer 150.

[0078] This layout of the thin-film transistor 100 achieves the most thorough bottom and lateral interface protection for the semiconductor layer 160. Since the carrier isolation layer 150 completely covers and extends beyond the boundary of the semiconductor layer 160 from below, it not only isolates the first electrode 120 and the second electrode 140, but also more effectively encapsulates and passivates potential defects at the edges of the semiconductor layer 160, creating a "microenvironment" for the semiconductor layer 160 surrounded by low-defect interface material. A larger carrier isolation layer 150 helps to distribute carriers injected by the electrodes more uniformly, or provides additional lateral depletion control capability, which may positively impact the uniformity and reliability of the thin-film transistor 100.

[0079] Please see Figure 2 and Figure 4 In some embodiments, the first sidewall 131 is a non-annular surface.

[0080] In this embodiment, the first sidewall 131 can be a non-annular surface, which can realize a high-density, easily integrated, and highly compatible thin-film transistor 100 with the pixel structure of the display panel.

[0081] The non-annular surface can be viewed from a direction perpendicular to the plane of the substrate 110, where the projected trace of the first sidewall 131 on the horizontal plane does not form a closed annulus or circle. In other words, the opening shape enclosed by the first sidewall 131 is open or non-rotationally symmetric. For example, the first sidewall 131 can be a combination of one or more planar sidewalls, thereby forming an opening profile such as a rectangle, strip, polygon, or a portion thereof on the plane; or, the first sidewall 131 can also be a continuous curved surface, but the curved surface does not form a complete, end-to-end loop.

[0082] The shape of the first sidewall 131 defines the planar shape of the stepped structure formed by the second portion 122 of the first electrode 120, the first insulating layer 130, and the second electrode 140. A non-annular opening (e.g., a slit or a rectangular window) allows the second portion 122 of the first electrode 120 to extend in one or more directions, thereby allowing the formation of linear or strip-shaped vertical or inclined channels on a single step, rather than necessarily forming a columnar annular channel, thus increasing the integration density of the thin-film transistor 100 on the substrate 110. Secondly, the non-annular sidewall structure can generally be more easily achieved through conventional linear or patterned etching processes, offering a wider process window and higher fabrication yield compared to complex annular etching processes. Furthermore, the linear or strip-shaped channel shape helps to precisely control the aspect ratio of the channel and better adapts to the shapes of pixel electrodes or signal lines commonly found in display panels, thus facilitating higher aperture ratios and superior electrical performance.

[0083] Please see Figure 5 and Figure 6 In some embodiments, the first sidewall 131 is an annular surface.

[0084] In this embodiment, the first sidewall 131 can be an annular surface. When viewed from a direction perpendicular to the plane of the substrate 110, the projection trace of the first sidewall 131 on the horizontal plane forms a continuous, closed ring. Specifically, the ring can be circular, elliptical, annular, rectangular, or other closed annular geometric shapes. This means that a through-hole in the first insulating layer 130, extending through its thickness in the form of a cylinder, frustum, or similar shape of a body of revolution, is formed, and the first sidewall 131 is the inner wall surface of this through-hole.

[0085] This structure defines a columnar vertical channel. The subsequently formed carrier isolation layer 150 and semiconductor layer 160 cover the annular sidewalls, naturally forming a channel surrounding the columnar region, the length of which is precisely determined by the thickness of the first insulating layer 130. This all-around channel structure allows the gate to apply electric field control to the channel from multiple directions, even circumferentially (if the gate is also annular), contributing to better gate control efficiency, higher on-state current, and more uniform electrical characteristics. Secondly, the annular structure is physically symmetrical, helping to reduce device performance dispersion caused by process variations and improve the consistency of transistor characteristics within the array, which is crucial for the uniformity of the display panel. Furthermore, in certain high-density integration designs, the annular channel structure can further reduce the area occupied by the thin-film transistors 100 on the plane, achieving higher pixel density.

[0086] Please see Figure 7 and Figure 8 In some embodiments, the second sidewall 152 is an annular surface.

[0087] In this embodiment, the second sidewall 152 can be an annular surface. An annular surface is the side profile formed by the charge carrier isolation layer 150 in a vertical or inclined direction when it covers the first sidewall 131 of the first insulating layer 130 and extends to the surface of the second portion 122 of the first electrode 120. Its projection onto the horizontal plane forms a continuous, closed annulus. Specifically, when the first sidewall 131 of the first insulating layer 130 itself is an annular surface, the second sidewall 152 of the charge carrier isolation layer 150 covering it naturally inherits and exhibits the same annular surface characteristics.

[0088] The carrier isolation layer 150 itself constitutes a three-dimensional structure with annular sidewalls, such as a thin-walled cylinder or annular column. This structure allows the carrier isolation layer 150 to continuously and uniformly wrap and modify the interface below it (including the annular first sidewall 131 and part of the electrode surface) in a 360-degree manner without dead angles, providing a substrate interface with consistent electrical properties in the circumferential direction for the semiconductor layer 160 above it. This is crucial for the subsequent formation of the third sidewall 162 (channel) of the semiconductor layer 160 on the second sidewall 152 of the carrier isolation layer 150, ensuring that the channel carriers face the same interface conditions along the annular path, thereby achieving higher mobility uniformity and more stable threshold voltage characteristics. In addition, the annular second sidewall 152 structure also facilitates more uniform thin film coverage in subsequent processes, reducing the risk of performance defects caused by insufficient corner coverage.

[0089] In some embodiments, the carrier concentration of semiconductor layer 160 ranges from 10. 17 ~10 per cubic centimeter 20 Each cubic centimeter.

[0090] In this embodiment, the carrier concentration of the semiconductor layer 160 can be in the range of 10. 17 ~10 per cubic centimeter 20 Carrier concentration is the primary parameter determining the conductivity of the semiconductor layer 160, and its unit is the number of carriers per cubic centimeter. The lower limit of carrier concentration is set at 10. 17 Each cubic centimeter ensures that the semiconductor layer 160 has a sufficiently high intrinsic carrier count to meet the basic requirements for forming a low-resistance, high-drive-capability channel. The upper limit is set to 10. 20 A concentration of 1000 m³ / cm² prevents problems such as ineffective device turn-off, deterioration of subthreshold characteristics, and decreased stability caused by excessively high carrier concentration. Within this concentration range, semiconductor layer 160 can simultaneously achieve good conduction characteristics and effective gate switching characteristics.

[0091] Specifically, the carrier concentration of semiconductor layer 160 can be 10. 17 per cubic centimeter, 10 18 per cubic centimeter, 10 19 Each cubic centimeter or 10 20 Each cubic centimeter, etc.

[0092] If the carrier concentration of semiconductor layer 160 is less than 10 17 A concentration of only a few carriers per cubic centimeter will result in insufficient mobile carriers in the channel (semiconductor layer 160), significantly reducing the current-carrying capacity of the thin-film transistor 100 and making it difficult to meet the driving performance requirements of high-resolution displays. Simultaneously, excessively low concentrations will weaken the shielding effect of carriers against interface traps, exacerbate threshold voltage drift, and potentially degrade the subthreshold characteristics of the device.

[0093] If the carrier concentration of semiconductor layer 160 is greater than 10 20 An excessively high carrier concentration per cubic centimeter will result in an excessively high carrier concentration in the channel (semiconductor layer 160), making it difficult for the thin-film transistor 100 to be effectively depleted or turned off by the gate voltage, severely degrading the subthreshold swing and on / off ratio. At the same time, the excessively high concentration will exacerbate the short-channel effect, causing a significant threshold voltage roll-off and drain-induced barrier reduction, impairing the device's ability to shrink in size.

[0094] In some embodiments, the proportion of indium atoms in semiconductor layer 160 among all metal atoms in semiconductor layer 160 ranges from 40% to 100%.

[0095] In this embodiment, the proportion of indium atoms in the semiconductor layer 160 among all metal atoms in the semiconductor layer 160 can range from 40% to 100%. Indium atoms are key elements providing high mobility; their 5s orbitals constitute the main body of the conduction band bottom of the metal oxide semiconductor, determining the effective mass and transport velocity of electrons. Setting the lower limit of the indium atom proportion to 40% ensures that the semiconductor layer 160 has a sufficiently high intrinsic electron mobility potential, which can reach above 10 cm² / V·s, meeting the switching speed and drive current requirements of the high-performance thin-film transistor 100. Setting the upper limit of the proportion to 100% means that the semiconductor layer 160 can be composed of indium oxide or its high-indium-content derivatives to pursue the ultimate mobility.

[0096] Specifically, the stability, bandgap, and compatibility with amorphous structures of materials can be adjusted by incorporating no more than 60% of other metal atoms (such as gallium, zinc, tin, aluminum, etc.). For example, when the proportion of indium atoms is 40% to 80%, an indium gallium zinc oxide semiconductor layer 160 with balanced performance can be formed by combining appropriate amounts of gallium and zinc.

[0097] Specifically, the proportion of indium atoms in semiconductor layer 160 among all metal atoms in semiconductor layer 160 can be 40%, 42%, 43%, 45%, 50%, 54%, 55%, 60%, 66%, 70%, 74%, 77%, 80%, 85%, 88%, 90%, 93%, 95%, or 100%, etc.

[0098] If the proportion of indium atoms in the semiconductor layer 160 is less than 40% of all metal atoms in the semiconductor layer 160, the density of electronic states at the bottom of the conduction band will be insufficient, making it difficult to form an efficient carrier transport channel. This will significantly reduce the intrinsic electron mobility of the channel, preventing the thin-film transistor 100 from obtaining sufficient drive current and switching speed, making it difficult to meet the requirements of high-performance thin-film transistors 100 for high-resolution displays. At the same time, excessively low indium content may also lead to an excessively wide bandgap or an increase in defect states, further degrading the subthreshold characteristics and stability of the thin-film transistor 100.

[0099] In some embodiments, the carrier concentration of the carrier isolation layer 150 ranges from 10. 15 ~10 per cubic centimeter 17 Each cubic centimeter.

[0100] In this embodiment, the carrier concentration of the carrier isolation layer 150 can be in the range of 10. 15 ~10 per cubic centimeter 17 Each cubic centimeter. The upper limit for carrier concentration is set to 10. 17The low carrier concentration ensures that the carrier isolation layer 150 is in a low conductivity state, with a resistivity significantly higher than that of the upper semiconductor layer 160. This lower carrier concentration causes the Fermi level of the carrier isolation layer 150 to be located far from its conduction band bottom. When the carrier isolation layer 150 comes into contact with the semiconductor layer 160, which has a higher carrier concentration, the difference in their Fermi levels induces significant band bending at the interface, thus forming an effective energy barrier. This barrier strongly suppresses the uncontrolled injection of carriers (electrons) from the lower first electrode 120 and second electrode 140 through the carrier isolation layer 150 into the channel of the semiconductor layer 160. This is the physical basis for solving the problem of negative threshold voltage drift in devices.

[0101] At the same time, the lower limit of carrier concentration is set to 10. 15 The density per cubic centimeter ensures that the carrier isolation layer 150 still possesses certain semiconductor properties, rather than being completely insulating. This moderate conductivity allows the gate electric field to penetrate or couple through the layer to some extent during device operation, thus preventing complete isolation of the gate's control over the channel.

[0102] The carrier concentration of the carrier isolation layer 150 is within the above range, which effectively forms an interface barrier to suppress harmful injection and maintain the basic gate control performance of the device. This achieves the best balance between these two aspects and is the key guarantee for the carrier isolation layer 150 to realize its intended interface modification and carrier modulation functions.

[0103] If the carrier concentration in carrier isolation layer 150 is too low as 10 15 If the carrier isolation layer 150 is reduced to a density of 1 cubic centimeter, it will approach that of an insulator, potentially introducing excessive series resistance and parasitic capacitance, severely degrading the switching speed and gate control efficiency of the device.

[0104] If the carrier concentration in carrier isolation layer 150 is too high as 10 17 Each cubic centimeter will significantly shift its Fermi level upward, resulting in a reduction in the carrier concentration gradient between it and the semiconductor layer 160. This severely weakens the band barrier at the interface that suppresses carrier injection, making it impossible to effectively block the injection of harmful electrons into the channel from the first electrode 120 and the second electrode 140, and causing the threshold voltage negative bias problem to reappear.

[0105] In some embodiments, the proportion of indium atoms in the carrier isolation layer 150 among all metal atoms in the carrier isolation layer 150 ranges from 0% to 50%.

[0106] In this embodiment, the proportion of indium atoms in the carrier isolation layer 150 among all metal atoms in the carrier isolation layer 150 can range from 0% to 50%, which ensures from the source that the carrier isolation layer 150 can achieve low carrier concentration and specific band structure, thereby reliably fulfilling its interface modification and carrier modulation functions.

[0107] Indium atoms are the main contributing element for high carrier concentration and high mobility, and their abundance directly determines the Fermi level position and conductivity of the material.

[0108] Setting the indium atom ratio upper limit to 50% ensures that the carrier isolation layer 150 maintains its low-mobility and isolation characteristics. When the indium atom ratio is controlled to no more than 50%, the conduction band of the material is mainly influenced or dominated by the orbital characteristics of other metal atoms (such as gallium, zinc, aluminum, etc.), which can typically form wider band gaps and deeper defect levels. This allows the intrinsic carrier concentration of the carrier isolation layer 150 to be suppressed to a low level, and its Fermi level to be set far from the bottom of the conduction band. This is the chemical basis for its ability to form an effective interface barrier with the high-indium-content semiconductor layer 160.

[0109] Setting the lower limit of the indium atomic ratio to 0 provides maximum flexibility in the material selection of the carrier isolation layer 150. For example, the carrier isolation layer 150 can be completely indium-free and composed of gallium oxide, aluminum oxide, zinc oxide, or their multi-component composite oxides. These indium-free or extremely low-indium materials typically possess extremely high resistivity and excellent stability, providing strong carrier blocking and interface passivation capabilities. When the indium atomic ratio is between 1% and 50%, the work function and band structure of the carrier isolation layer 150 can be fine-tuned by precisely controlling the indium content to achieve optimal band matching with the upper and lower layers. This can further optimize the subthreshold characteristics or stability of the device while ensuring isolation performance.

[0110] Specifically, for example, the proportion of indium atoms can be 0, 5%, 8%, 10%, 12%, 15%, 20%, 22%, 25%, 30%, 34%, 40%, 42%, 45%, or 50%.

[0111] If the proportion of indium atoms exceeds 50%, the carrier isolation layer 150 will gradually exhibit high conductivity characteristics similar to the semiconductor layer 160, and its Fermi level will shift significantly upward, resulting in the weakening or even disappearance of the interface barrier, thereby losing its key function of suppressing carrier injection.

[0112] In some embodiments, the metal element of the semiconductor layer 160 includes indium and at least one of gallium, zinc, tin, germanium or aluminum.

[0113] In this embodiment, the metal element of the semiconductor layer 160 may include indium, and at least one element selected from the group consisting of gallium, zinc, tin, germanium, and aluminum. The semiconductor layer 160 may be a multi-metal oxide with indium as a major or necessary component. Indium atoms are the core element providing high electron mobility, and their 5s orbitals constitute the main body of the conduction band bottom of the material, responsible for high-speed electron transport.

[0114] At least one of gallium, zinc, tin, germanium, or aluminum is introduced as a co-doping or alloying element. These elements are not randomly combined but each plays a specific regulatory role. For example, the addition of gallium helps improve the amorphous formation capability of the material, enhances large-area uniformity, and widens the bandgap through its strong Ga-O bonds, thereby reducing the off-state current of the device. The incorporation of zinc can adjust the work function of the material, optimize the device threshold, and enhance the environmental stability of the thin film. Tin can partially replace indium, contributing high mobility at specific ratios, while potentially introducing different band and defect state characteristics. The introduction of germanium and aluminum focuses more on the deep manipulation of the material's defect states and carrier concentration. Aluminum, due to its extremely strong aluminum-oxygen bonds, is often used as a carrier suppressor.

[0115] By selecting one or more of the above elements and combining them with indium, multiple key performance indicators of semiconductor layer 160, such as electron mobility, carrier concentration, defect state density, optical bandgap, and environmental stability, can be synergistically designed and finely controlled, thereby fabricating customized semiconductor layer 160 that can meet the needs of different circuit application scenarios (such as high-speed switching, high drive current, or high stability requirements).

[0116] In some implementations, the thickness of the semiconductor layer 160 ranges from 5 nm to 20 nm.

[0117] In this embodiment, the thickness of the semiconductor layer 160 can range from 5 nm to 20 nm. This thickness range is one of the key physical parameters to ensure that the semiconductor layer 160 performs optimally in the thin-film transistor 100. Setting the lower limit of the semiconductor layer 160 thickness to 5 nm is mainly to ensure the formation of a continuous, uniform thin film with complete semiconductor properties. Setting the upper limit of the semiconductor layer 160 thickness to 20 nm is mainly based on considerations of gate control efficiency and process integration. In the thin-film transistor 100, the modulation effect of the gate electric field on channel carriers weakens as the channel (i.e., semiconductor layer 160) thickness increases.

[0118] If the thickness of the semiconductor layer 160 is less than 5 nm, the semiconductor layer 160 film is prone to significant performance fluctuations due to island-like growth or discontinuity, and carrier transport may be severely affected by surface scattering, leading to decreased mobility and unstable electrical characteristics. At the same time, sufficient thickness also provides the necessary carrier volume for the channel, ensuring the drive current capability that the device can obtain.

[0119] If the thickness of semiconductor layer 160 is greater than 20nm, the region of semiconductor layer 160 far from the interface of the second insulating layer 170 may be difficult to be effectively depleted or inverted by the gate voltage, which will lead to a deterioration of subthreshold characteristics (such as an increase in subthreshold swing), a decrease in the on / off ratio, and may cause an aggravation of short-channel effects.

[0120] In some embodiments, the metal element of the charge carrier isolation layer 150 includes at least one of indium, gallium, zinc, tin, germanium, or aluminum.

[0121] In this embodiment, the metal element of the charge carrier isolation layer 150 may include at least one of indium, gallium, zinc, tin, germanium, or aluminum. Specifically, the metal element of the charge carrier isolation layer 150 may include only one of indium, gallium, zinc, tin, germanium, or aluminum, or it may include two, three, four, five, six, or seven of indium, gallium, zinc, tin, germanium, or aluminum.

[0122] In some implementations, the thickness of the carrier isolation layer 150 is greater than 0.1 nm and less than or equal to 10 nm.

[0123] In this embodiment, the thickness of the carrier isolation layer 150 can be greater than 0.1 nm and less than or equal to 10 nm. This is the optimal choice to minimize its negative impact on the intrinsic electrical performance of the device (such as gate control capability and series resistance) and ensure process feasibility, while ensuring that it forms an effective functional layer and realizes the core isolation and modulation function.

[0124] Setting the lower limit of the carrier isolation layer 150 to 0.1 nm is fundamentally aimed at ensuring that the carrier isolation layer 150 can form a continuous thin film with well-defined material properties. Theoretically, at least one or several atomic layers are required to form a solid layer with a tunable band structure and stable interface properties.

[0125] Setting the upper limit of the thickness of the carrier isolation layer 150 to 10 nm is based on a comprehensive trade-off between electrical performance and process feasibility. On the one hand, as an insertion layer, the thickness of the carrier isolation layer 150 directly affects the total gate capacitance and series resistance of the device.

[0126] Specifically, for example, the thickness of the carrier isolation layer 150 can be 0.1nm, 1nm, 1.5nm, 1.6nm, 2nm, 2.2nm, 2.5nm, 3nm, 3.4nm, 4nm, 4.5nm, 5nm, 5.4nm, 5.5nm, 6nm, 6.3nm, 6.5nm, 7nm, 7.5nm, 7.8nm, 8nm, 8.5nm, 9nm, 9.5nm, 9.7nm, or 10nm, etc.

[0127] If the thickness of the carrier isolation layer 150 is less than 0.1 nm, the carrier isolation layer 150 will not be able to form an effective continuous coverage, and its expected interface barrier modulation and defect passivation functions will not be realized. This is equivalent to the semiconductor layer 160 being in direct contact with the lower electrode and the sidewall of the insulating layer, thus losing the purpose of setting this layer.

[0128] If the carrier isolation layer thickness exceeds 10 nm, it will significantly increase the equivalent physical distance between the gate and the channel, weakening the gate control capability and leading to a decrease in device transconductance and a slower switching speed. Furthermore, an excessively thick low-conductivity layer may introduce non-negligible series resistance, affecting the drive current.

[0129] In some embodiments, at least a portion of the carrier protection layer 190 is projected onto the substrate 110 in orthogonal projection, which overlaps with the semiconductor layer 160 on the substrate 110 in orthogonal projection.

[0130] In this embodiment, when viewed along a direction perpendicular to the plane of the substrate 110, at least a portion of the area covered by the carrier protection layer 190 corresponds vertically to the area covered by the semiconductor layer 160 in planar position. The carrier protection layer 190 is located directly above the semiconductor layer 160 or has a vertical correspondence with the semiconductor layer 160 in at least a portion, ensuring that the carrier protection layer 190 can provide direct, positionally corresponding protection to the underlying semiconductor layer 160.

[0131] Specifically, in the overlapping region, the carrier protection layer 190 is located directly between the second insulating layer 170 and the control electrode 180, and directly above the channel or other critical region of the semiconductor layer 160. This configuration allows the carrier protection layer 190 to most effectively modulate the local interface characteristics of the second insulating layer 170 / control electrode 180 corresponding to the overlapping region, thereby optimizing the gate electric field coupling of the corresponding channel in this region and suppressing possible interface charge injection or ion migration.

[0132] In some embodiments, the orthographic projection of the carrier protection layer 190 on the substrate 110 overlaps with the orthographic projection of the semiconductor layer 160 on the substrate 110.

[0133] In this embodiment, the orthographic projection of the carrier protection layer 190 on the substrate 110 overlaps with the orthographic projection of the semiconductor layer 160 on the substrate 110, and the carrier protection layer 190 achieves direct interface protection of the semiconductor layer 160 over the maximum range.

[0134] The overlap is defined as follows: when viewed along a direction perpendicular to the plane of the substrate 110, the two-dimensional region covered by the carrier protection layer 190 and the two-dimensional region covered by the semiconductor layer 160 have completely identical contours and areas on the plane of the substrate 110. That is, from a top view, the carrier protection layer 190 exactly covers the area directly above the semiconductor layer 160, and the two are precisely aligned in planar layout.

[0135] Since the carrier protection layer 190 covers the entire area above the semiconductor layer 160, the metal interfaces of the second insulating layer 170 / control electrode 180 above all channels corresponding to the semiconductor layer 160 are modified and protected by the carrier protection layer 190. This helps to obtain uniformly improved interface characteristics throughout the channel, enhancing the uniformity of device performance. Secondly, this layout may simplify the process. For example, the same mask as the patterned semiconductor layer 160 can be used to pattern the carrier protection layer 190, or it can be achieved during deposition through a self-aligned process, thereby reducing photolithography alignment steps and improving process integration and yield. In addition, the fully overlapping structure ensures that the protection effect of the carrier protection layer 190 has no blind spots, and can comprehensively suppress various degradation mechanisms that may be caused by the bias voltage applied by the control electrode 180 at the interface above the entire channel, providing the most complete reliability guarantee for the device.

[0136] In some embodiments, the orthographic projection of the semiconductor layer 160 on the substrate 110 lies within the orthographic projection of the carrier protection layer 190 on the substrate 110.

[0137] In this embodiment, the orthographic projection of the semiconductor layer 160 onto the substrate 110 lies within the orthographic projection of the carrier protection layer 190 onto the substrate 110. Specifically, viewed from a top-down direction perpendicular to the plane of the substrate 110, the two-dimensional pattern corresponding to the semiconductor layer 160 is completely contained within the two-dimensional pattern corresponding to the carrier protection layer 190. That is, the coverage area of ​​the carrier protection layer 190 on the plane is larger than that of the semiconductor layer 160, extending beyond the region of the semiconductor layer 160.

[0138] The carrier protection layer 190 not only covers the area directly above the semiconductor layer 160 (i.e., the channel), but also extends to the area surrounding the semiconductor layer 160, such as over parts of the source / drain electrode contact area or isolation region. This extended coverage provides more comprehensive interface protection for the device, especially protecting the edge regions of the semiconductor layer 160, which may be more vulnerable or susceptible to damage during the process.

[0139] The carrier protection layer 190 effectively blocks the diffusion of oxygen and hydrogen atoms from the environment into the high-mobility active layer, suppressing the resulting interfacial redox reactions and carrier concentration drift. This dense film effectively blocks the diffusion of oxygen and hydrogen atoms from the environment into the high-mobility active layer, suppressing the resulting interfacial redox reactions and carrier concentration drift. The carrier protection layer 190 also acts as a diffusion barrier layer for indium atoms. Through the elemental chemical potential difference and lattice matching characteristics between it and adjacent layers, it suppresses the outward diffusion of indium atoms in the high-mobility active layer under thermal processing or electrical stress, maintaining the stability of the active layer's elemental composition.

[0140] The present application provides an array substrate 110, which includes any of the thin-film transistors 100 described above.

[0141] In this embodiment, the array substrate 110 may include one or more thin-film transistors 100, which can be used as a switching transistor, a driving transistor, or a thin-film transistor 100 in a peripheral circuit.

[0142] Please see Figure 9 The method for fabricating a thin-film transistor 100 provided in this application may include the following steps: Step S110: Provide substrate 110.

[0143] In this embodiment, a substrate material is prepared or acquired to support all subsequent thin film layers and device structures, forming the basis for the thin film transistor 100.

[0144] Step S120: A first electrode 120 is disposed on one side of the substrate 110; the first electrode 120 includes a first portion 121 and a second portion 122 disposed adjacent to each other.

[0145] In this embodiment, a conductive structure, namely the first electrode 120, with a predetermined pattern can be formed on a selected main surface of the substrate 110 using thin film deposition and patterning processes. This conductive structure will serve as a source / drain electrode of the thin film transistor 100. Specifically, firstly, a conductive thin film material is deposited on the surface of the substrate 110 using processes such as sputtering, thermal evaporation, or chemical vapor deposition; subsequently, the conductive thin film material is patterned using standard photolithography processes, including photoresist coating, exposure, development, and dry or wet etching, to form the final pattern of the first electrode 120.

[0146] In a direction parallel to the plane of substrate 110, the first electrode 120 is a continuous conductive pattern, but its pattern design distinguishes it into two adjacent and electrically conductive regions: a first portion 121 and a second portion 122. For example, the first portion 121 can be a large contact pad region, while the second portion 122 can be a narrower channel contact region extending from the first portion 121. This design, which divides a single electrode pattern into adjacent portions with different functions, is crucial for the subsequent formation of the three-dimensional device structure. The first portion 121 is primarily used for perpendicular stacking with the subsequently deposited insulating layer and another electrode, while the second portion 122 is primarily used for establishing electrical connections with the subsequently formed semiconductor channel layer. The pattern shape, dimensional accuracy, and edge morphology of the first electrode 120 have a decisive influence on the step coverage of the subsequent thin film, the channel definition of the device, and the final electrical characteristics.

[0147] Step S130: A first insulating layer 130 is provided on the side of the first portion 121 away from the substrate 110; the first insulating layer 130 includes a first sidewall 131.

[0148] In this embodiment, a dielectric layer, namely a first insulating layer 130, can be formed on the surface of the first portion 121 of the first electrode 120 using thin-film deposition and patterning processes. This first insulating layer 130 provides electrical isolation in the vertical direction, separating the first portion 121 of the first electrode 120 from the subsequently formed second electrode 140. Specifically, processes such as chemical vapor deposition, atomic layer deposition, or sputtering can be used to deposit an insulating thin film material, such as silicon dioxide, silicon nitride, or a high-dielectric-constant oxide, on the patterned first electrode 120 and the exposed substrate 110 surface. Subsequently, the insulating film is patterned using photolithography and etching processes to form the final structure of the first insulating layer 130.

[0149] During or after patterning the first insulating layer 130, the first insulating layer 130 may include a first sidewall 131. The first sidewall 131 refers to a vertical or inclined side of the first insulating layer 130 at the edge of the first portion 121 of the first electrode 120 or at a specific opening. Specifically, since the first insulating layer 130 covers the first portion 121, its patterning etching stops at its edge on the second portion 122 of the first electrode 120 or the surface of the substrate 110, thus naturally forming this first sidewall 131. For example, when the pattern of the first insulating layer 130 is an island-shaped or strip-shaped pattern covering the first portion 121 but exposing the second portion 122, its edge side near the second portion 122 is the first sidewall 131. The morphology (such as tilt angle, roughness) of the first sidewall 131 is determined by the deposition and etching process conditions. The formation of the first insulating layer 130 and its first sidewall 131, together with the first part 121 and the second part 122 of the lower first electrode 120, defines a stepped structure or a trench structure, laying the core physical foundation for the subsequent construction of vertical or three-dimensional channels.

[0150] Step S140: A second electrode 140 is disposed on the side of the first insulating layer 130 away from the substrate 110.

[0151] In this embodiment, a second electrode 140 with a predetermined pattern can be formed on the upper surface of the first insulating layer 130 using thin-film deposition and patterning processes. This second electrode 140 will serve as another source / drain electrode of the thin-film transistor 100, forming the source-drain pair of the thin-film transistor 100 together with the first electrode 120. Specifically, a conductive thin-film material is deposited on the surface of the first insulating layer 130 and any potentially exposed underlying structures using processes such as sputtering or chemical vapor deposition. Subsequently, the conductive thin-film material is patterned using photolithography processes including photoresist coating, exposure, development, and etching to form the final pattern of the second electrode 140.

[0152] The second electrode 140 is disposed above the first insulating layer 130, meaning that the second electrode 140 is electrically isolated vertically from the first portion 121 of the underlying first electrode 120 through the first insulating layer 130. Simultaneously, the pattern of the second electrode 140 is positioned at least partially directly above the first insulating layer 130. Its pattern may completely cover the first insulating layer 130 or only a portion thereof. The second electrode 140 and the second portion 122 of the first electrode 120 are generally separated horizontally by the area containing the first insulating layer 130 or its first sidewall 131. The second electrode 140, together with the previously formed first portion 121, second portion 122 of the first electrode 120, and the first insulating layer 130, constitute an electrode-insulator-electrode basic structure with a clearly defined vertical stacking relationship and horizontal spacing. This is a key prefabricated structure for enabling vertical or three-dimensional current transmission in the subsequently formed semiconductor layer 160.

[0153] Step S150: A carrier isolation layer 150 is provided on the side of the second electrode 140 away from the substrate 110; at least a portion of the carrier isolation layer 150 covers the first sidewall 131 and a portion of the second portion 122; the carrier isolation layer 150 includes a second sidewall 152 covering the first sidewall 131.

[0154] In this embodiment, a functional semiconductor thin film with specific electrical properties can be conformally formed on the upper surface of the second electrode 140 and on the area exposed by the first sidewall 131 of the first insulating layer 130 and a portion of the second portion 122 of the first electrode 120 by a thin film deposition process.

[0155] During the deposition process, the carrier isolation layer 150 is formed to cover three key surfaces: it covers the top surface of the second electrode 140; it continuously covers the entire side of the first sidewall 131 of the first insulating layer 130; and it further extends and covers at least a portion of the upper surface of the second portion 122 of the first electrode 120. Through this conformal coverage, the carrier isolation layer 150 naturally exhibits a three-dimensional structure.

[0156] Due to the aforementioned coverage relationship, the carrier isolation layer 150 itself includes a second sidewall 152 covering the first sidewall 131. The portion covering the first sidewall 131 of the first insulating layer 130 forms the second sidewall 152 due to its vertical or inclined geometry. This continuous thin film of the carrier isolation layer 150, located at different geometric positions within the first insulating layer 130, collectively constitutes a complete functional layer spanning a stepped structure. In this step, the uniformity, thickness control, and interface quality of the carrier isolation layer 150 with the underlying surface are crucial to its effective suppression of carrier injection and passivation of interface defects.

[0157] Step S160: A semiconductor layer 160 is disposed on the carrier isolation layer 150 away from the substrate 110; the semiconductor layer 160 covers the second sidewall 152; the carrier concentration of the carrier isolation layer 150 is less than the carrier concentration of the semiconductor layer 160.

[0158] In this embodiment, a functional semiconductor thin film with a high carrier concentration can be conformally formed on the surface of the carrier isolation layer 150 away from the substrate 110 using a thin film deposition process. Specifically, atomic layer deposition, physical vapor deposition, or other similar processes can be used.

[0159] During the deposition process, the semiconductor layer 160 is formed to cover the second sidewall 152 of the carrier isolation layer 150 and at least a portion of the other parts of the carrier isolation layer 150. Through this conformal coverage, the semiconductor layer 160 naturally exhibits a three-dimensional structure.

[0160] The carrier concentration of the carrier isolation layer 150 is configured to be lower than that of the semiconductor layer 160. This concentration difference is the basis for the two layers to form a functional heterojunction. In terms of fabrication, this is achieved by precisely controlling the material composition (especially the indium content) and deposition conditions of the two thin films. For example, the carrier isolation layer 150 with a low carrier concentration and the semiconductor layer 160 with a high carrier concentration can be deposited sequentially by switching the reactive precursor or changing the process parameters in the same deposition equipment. Establishing this concentration relationship allows a band barrier that is conducive to blocking carrier injection to be spontaneously formed at the interface between the two layers, thereby ensuring the threshold voltage stability of the thin-film transistor 100 while achieving high mobility of the semiconductor layer 160.

[0161] In some embodiments, the step of forming a carrier isolation layer 150 on the side of the second electrode 140 away from the substrate 110 includes: forming the carrier isolation layer 150 on the side of the second electrode 140 away from the substrate 110 using an atomic layer deposition process; correspondingly, the step of forming a semiconductor layer 160 on the side of the carrier isolation layer 150 away from the substrate 110 includes: forming the semiconductor layer 160 on the side of the carrier isolation layer 150 away from the substrate 110 using an atomic layer deposition process.

[0162] In this embodiment, an atomic layer deposition (ALD) process can be used to form a carrier isolation layer 150 on the side of the second electrode 140 away from the substrate 110. ASD is a thin film deposition technique based on sequential surface chemical reactions, which can achieve sub-nanometer-level thickness control, excellent three-dimensional conformality, and uniform film composition. Using this process to form the carrier isolation layer 150 ensures that the functional layer achieves uniform and continuous coverage on complex three-dimensional morphologies such as the top surface of the second electrode 140, the first sidewall 131 of the first insulating layer 130, and the surface of the second portion 122 of the first electrode 120, and its thickness can be precisely controlled within the range defined in the claims. This is crucial for achieving stable and repeatable interface modification effects.

[0163] A semiconductor layer 160 is formed on the side of the carrier isolation layer 150 away from the substrate 110 using atomic layer deposition (ALD). That is, the semiconductor layer 160 is also fabricated using ALD. Sequentially depositing the carrier isolation layer 150 and the semiconductor layer 160 using the same ALD technology platform offers significant process integration advantages. First, it can be performed continuously without disrupting the vacuum or altering the core reaction chamber environment, avoiding potential contamination from atmospheric exposure and resulting in a cleaner, steeper heterojunction. Second, the precise control of the thin film composition by ALD allows for easy switching of the metal precursor and reactant gas to achieve differentiated material properties for the carrier isolation layer 150 (low indium content, low carrier concentration) and the semiconductor layer 160 (high indium content, high carrier concentration). Finally, this process ensures that the semiconductor layer 160 achieves perfect conformal coverage over the three-dimensional structure formed by the carrier isolation layer 150, reproducing the underlying morphology and forming a channel with uniform thickness and consistent quality.

[0164] It should be noted that some embodiments of this application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result.

[0165] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the above embodiments of this application, which are not provided in detail for the sake of brevity.

[0166] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A thin-film transistor, characterized in that, include: substrate; The first electrode is disposed on one side of the substrate, comprising a first portion and a second portion disposed adjacent to each other; A first insulating layer is disposed on the side of the first portion away from the substrate; the first insulating layer includes a first sidewall; The second electrode is disposed on the side of the first insulating layer away from the substrate; A carrier isolation layer, at least a portion of which is disposed on the side of the second electrode away from the substrate; at least a portion of which also covers the first sidewall and a portion of the second portion; the carrier isolation layer includes a second sidewall covering the first sidewall; A semiconductor layer is provided on the side of the carrier isolation layer away from the substrate and covers the second sidewall; the carrier concentration of the carrier isolation layer is less than the carrier concentration of the semiconductor layer.

2. The thin-film transistor according to claim 1, characterized in that, The semiconductor layer includes a third sidewall covering the second sidewall, and the thin-film transistor further includes: A second insulating layer is disposed on the side of the semiconductor layer away from the substrate and covers the third sidewall; the second insulating layer includes a fourth sidewall covering the third sidewall; A control electrode is disposed on the side of the second insulating layer away from the substrate and covers the fourth sidewall; Preferably, the thin-film transistor further includes a carrier protection layer, which is disposed at least between the second insulating layer and the semiconductor layer; Preferably, the proportion of indium atoms in the carrier protection layer among all metal atoms in the carrier protection layer ranges from 0% to 30%. Preferably, the thickness of the carrier protection layer ranges from 0.1 nm to 5 nm.

3. The thin-film transistor according to claim 1, characterized in that, The orthographic projection of the charge carrier isolation layer on the substrate and the orthographic projection of the semiconductor layer on the substrate at least partially overlap; Preferably, the orthographic projection of the charge carrier isolation layer on the substrate overlaps with the orthographic projection of the semiconductor layer on the substrate; Preferably, the orthographic projection of the charge carrier isolation layer on the substrate is within the orthographic projection of the semiconductor layer on the substrate; Preferably, the orthographic projection of the semiconductor layer on the substrate is within the orthographic projection of the carrier isolation layer on the substrate.

4. The thin-film transistor according to claim 1, characterized in that, The first sidewall is a non-annular surface; Preferably, the first sidewall is an annular surface; Preferably, the second sidewall is an annular surface.

5. The thin-film transistor according to claim 1, characterized in that, The carrier concentration of the semiconductor layer ranges from 10. 17 ~10 per cubic centimeter 20 per cubic centimeter; Preferably, the proportion of indium atoms in the semiconductor layer among all metal atoms in the semiconductor layer ranges from 40% to 100%. Preferably, the carrier concentration of the carrier isolation layer is in the range of 10. 15 ~10 per cubic centimeter 17 per cubic centimeter; Preferably, the proportion of indium atoms in the carrier isolation layer among all metal atoms in the carrier isolation layer ranges from 0% to 50%.

6. The thin-film transistor according to claim 1, characterized in that, The metallic element of the semiconductor layer includes indium and at least one of gallium, zinc, tin, germanium or aluminum; Preferably, the thickness of the semiconductor layer ranges from 5 nm to 20 nm; Preferably, the metallic element of the carrier isolation layer includes at least one selected from indium, gallium, zinc, tin, germanium, or aluminum; Preferably, the thickness of the carrier isolation layer is greater than 0.1 nm and less than or equal to 10 nm.

7. The thin-film transistor according to claim 2, characterized in that, At least a portion of the orthographic projection of the charge carrier protection layer onto the substrate overlaps with the orthographic projection of the semiconductor layer onto the substrate; Preferably, the orthographic projection of the charge carrier protection layer on the substrate overlaps with the orthographic projection of the semiconductor layer on the substrate; Preferably, the orthographic projection of the semiconductor layer on the substrate is within the orthographic projection of the charge carrier protection layer on the substrate.

8. An array substrate, characterized in that, Including the thin-film transistor as described in any one of claims 1 to 7 above.

9. A method for fabricating a thin-film transistor, characterized in that, include: Provide substrate; A first electrode is disposed on one side of the substrate; The first electrode includes a first portion and a second portion disposed adjacent to each other; A first insulating layer is disposed on the side of the first portion away from the substrate; the first insulating layer includes a first sidewall; A second electrode is disposed on the side of the first insulating layer away from the substrate; A carrier isolation layer is disposed on the side of the second electrode away from the substrate; at least a portion of the carrier isolation layer covers the first sidewall and a portion of the second portion; the carrier isolation layer includes a second sidewall covering the first sidewall; A semiconductor layer is disposed away from the substrate in the carrier isolation layer; the semiconductor layer covers the second sidewall; the carrier concentration of the carrier isolation layer is less than the carrier concentration of the semiconductor layer.

10. The manufacturing method according to claim 9, characterized in that, The step of forming a carrier isolation layer on the side of the second electrode away from the substrate includes: The carrier isolation layer is formed on the side of the second electrode away from the substrate using an atomic layer deposition process; Accordingly, the step of setting the semiconductor layer away from the substrate in the carrier isolation layer includes: The semiconductor layer is formed on the side of the charge carrier isolation layer away from the substrate using the atomic layer deposition process.

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