Semiconductor structure and manufacturing method thereof, semiconductor device and manufacturing method thereof, and electronic equipment

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof, and electronic equipment. The semiconductor structure comprises a plurality of first semiconductor layers and second semiconductor layers which are alternately stacked; the first semiconductor layer comprises a first sub-layer and a second sub-layer; the first sub-layers are located on the two opposite sides of the second sub-layer in the first direction, and the first direction is parallel to the stacking direction of the first semiconductor layer and the second semiconductor layer; a first etch selection ratio between the first sub-layer and the second semiconductor layer is different from a second etch selection ratio between the second sub-layer and the second semiconductor layer. According to the embodiment of the invention, when the first semiconductor layer is removed and the second semiconductor layer is reserved, the first semiconductor layer can be removed more accurately, so that the reserved second semiconductor layer serving as the channel layer has good morphology, and meanwhile, lattice mismatch between the first semiconductor layer and the second semiconductor layer is reduced; and the stacking layer number is prevented from being influenced by dislocation defects.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of semiconductor manufacturing, specifically to semiconductor structures and their manufacturing methods, semiconductor devices and their manufacturing methods, and electronic devices. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, while the types and number of devices contained in a single chip are increasing. The complexity of manufacturing processes means that even minor differences in the production process can affect device performance, posing challenges to device yield and reliability. To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. As the demand for integrated circuits continues to grow, the requirement for device miniaturization is becoming increasingly stringent. However, limited by existing structures and processes, achieving device miniaturization while simultaneously improving device yield and reliability presents numerous challenges. Summary of the Invention

[0003] In view of the above, embodiments of this disclosure provide a semiconductor structure and a method for manufacturing the same, a semiconductor device and a method for manufacturing the same, and an electronic device.

[0004] In a first aspect, this disclosure provides a semiconductor structure, comprising:

[0005] Alternating stacked first semiconductor layers and second semiconductor layers;

[0006] The first semiconductor layer includes a first sublayer and a second sublayer; the first sublayer is located on opposite sides of the second sublayer along a first direction, the first direction being parallel to the stacking direction of the first semiconductor layer and the second semiconductor layer; the first etch selectivity between the first sublayer and the second semiconductor layer is different from the second etch selectivity between the second sublayer and the second semiconductor layer.

[0007] In some embodiments, the first etching selectivity is greater than the second etching selectivity.

[0008] In some embodiments, the first sublayer and the second sublayer contain the same material elements, but the proportion of the first element in the first sublayer and the second sublayer is different.

[0009] In some embodiments, in the direction from the first sub-layer to the second semiconductor layer in contact with the first sub-layer, the proportion of the first element in the first sub-layer remains unchanged; the proportion of the first element in the first sub-layer is greater than the proportion of the first element in the second sub-layer.

[0010] In some embodiments, in the direction from the first sublayer to the second semiconductor layer in contact with the first sublayer, the proportion of the first element in the first sublayer increases; the minimum proportion of the first element in the first sublayer is greater than the proportion of the first element in the second sublayer.

[0011] In some embodiments, the first sublayer and the second sublayer both contain Si and Ge as material elements, and the first element is either Ge or Si.

[0012] In some embodiments, the first sublayer and the second sublayer contain different material elements.

[0013] In some embodiments, the first sublayer contains Si and Ge as material elements, and the second sublayer contains Si and B as material elements.

[0014] In some embodiments, the second sublayer contains the same material elements as the second semiconductor layer.

[0015] In some embodiments, the second semiconductor layer and the second sublayer are both made of Ge, and the first sublayer is made of Si and Ge.

[0016] or,

[0017] The second semiconductor layer and the second sublayer are both made of Si, and the first sublayer is made of Si and Ge.

[0018] In some embodiments, the dimension of the second sublayer along the first direction is smaller than the dimension of the second semiconductor layer along the first direction.

[0019] In some embodiments, the first etching selectivity is less than the second etching selectivity.

[0020] In some embodiments, the first sublayer contains the material elements Ge and Sn, and the second sublayer contains the material elements Ge and B.

[0021] In some embodiments, the first sublayer and the second semiconductor layer contain the same material elements; the proportion of the first element in the first sublayer is greater than the proportion of the first element in the second semiconductor layer; the first element is Ge. In a second aspect, this disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0022] Several alternating stacked first semiconductor layers and second semiconductor layers are formed;

[0023] The first semiconductor layer includes a first sublayer and a second sublayer; the first sublayer is located on opposite sides of the second sublayer along a first direction, the first direction being parallel to the stacking direction of the first semiconductor layer and the second semiconductor layer; the first etch selectivity between the first sublayer and the second semiconductor layer is different from the second etch selectivity between the second sublayer and the second semiconductor layer.

[0024] Thirdly, this disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0025] A plurality of alternating first semiconductor layers and second semiconductor layers are formed; the first semiconductor layer includes a first sublayer and a second sublayer, the first sublayer being located on opposite sides of the second sublayer along a first direction, the first direction being parallel to the stacking direction of the first semiconductor layer and the second semiconductor layer;

[0026] At least the first sub-layer and the second sub-layer are removed to form a first groove; wherein, the first etch selectivity ratio between the first sub-layer and the second semiconductor layer is different from the second etch selectivity ratio between the second sub-layer and the second semiconductor layer;

[0027] A gate structure covering the second semiconductor layer is formed within the first groove;

[0028] A memory structure and bit lines are formed, wherein the memory structure and the bit lines are respectively connected to the two ends of the second semiconductor layer opposite to each other along a second direction, the second direction being perpendicular to the first direction.

[0029] In some embodiments, the first etching selectivity is greater than the second etching selectivity; the first groove includes a first sub-groove and a second sub-groove; the step of removing at least the first sub-layer and the second sub-layer to form the first groove includes:

[0030] Remove the first sub-layer of the first semiconductor layer to form the first sub-groove;

[0031] The second sub-layer and a portion of the second semiconductor layer are removed to form the second sub-groove.

[0032] In some embodiments, the first sublayer and the second sublayer contain the same material elements, but the proportion of the first element in the first sublayer and the second sublayer is different.

[0033] In some embodiments, in the direction from the first sublayer to the second semiconductor layer in contact with the first sublayer, the proportion of the first element in the first sublayer remains unchanged, and the proportion of the first element in the first sublayer is greater than the proportion of the first element in the second sublayer.

[0034] In some embodiments, in the direction from the first sub-layer to the second semiconductor layer in contact with the first sub-layer, the proportion of the first element in the first sub-layer increases, and the minimum proportion of the first element in the first sub-layer is greater than the proportion of the first element in the second sub-layer.

[0035] In some embodiments, the first sublayer and the second sublayer contain different material elements.

[0036] In some embodiments, the second sublayer contains the same material elements as the second semiconductor layer.

[0037] In some embodiments, the dimension of the second sublayer along the first direction is smaller than the dimension of the second semiconductor layer along the first direction.

[0038] In some embodiments, the first etching selectivity is less than the second etching selectivity; the first groove includes a first sub-groove and a second sub-groove; the step of removing at least the first sub-layer and the second sub-layer to form the first groove includes:

[0039] Remove the second sub-layer of the first semiconductor layer to form the first sub-groove;

[0040] The first sub-layer of the first semiconductor layer and a portion of the second semiconductor layer are removed to form the second sub-groove.

[0041] In some embodiments, the first sublayer contains the material elements Ge and Sn, and the second sublayer contains the material elements Ge and B.

[0042] In some embodiments, the first sublayer and the second semiconductor layer contain the same material elements;

[0043] The proportion of the first element in the first sub-layer is greater than the proportion of the first element in the second semiconductor layer; the first element is Ge.

[0044] In some embodiments, the method further includes:

[0045] A first epitaxial layer and a second epitaxial layer are sequentially formed along the first direction; wherein the growth temperature of the first epitaxial layer is lower than the growth temperature of the second epitaxial layer;

[0046] A plurality of alternating stacked first semiconductor layers and second semiconductor layers are formed on the second epitaxial layer.

[0047] In some embodiments, before at least the first sublayer and the second sublayer are removed to form the first groove, the method further includes:

[0048] A portion of the first semiconductor layer and the second semiconductor layer are removed along the first direction, and a first trench is formed on both sides of the first semiconductor layer and the second semiconductor layer along the second direction;

[0049] A support structure is formed in the first trench.

[0050] In some embodiments, the first groove includes a second trench, a first sub-groove, and a second sub-groove; the step of removing at least the first sub-layer and the second sub-layer to form the first groove includes:

[0051] A plurality of second trenches are formed that penetrate the first semiconductor layer and the second semiconductor layer along a first direction, the plurality of second trenches extending along the second direction and spaced apart along a third direction;

[0052] The first sub-groove is formed based on the second groove;

[0053] The second sub-groove is formed based on the second groove;

[0054] Wherein, the third direction intersects the second direction and is perpendicular to the first direction.

[0055] Fourthly, this disclosure provides a semiconductor device, comprising:

[0056] Substrate;

[0057] A memory array located on the substrate, the memory array comprising a plurality of memory cell layers stacked along a first direction perpendicular to the substrate, each memory cell layer comprising a plurality of memory cells arranged in an array; each memory cell comprising a transistor, the transistor comprising a channel layer extending along a second direction parallel to the substrate and a gate structure surrounding the channel layer.

[0058] In some embodiments, the gate structure surrounds a plurality of channel layers arranged in a third direction parallel to the substrate in the same memory cell layer; wherein the second direction intersects with the third direction.

[0059] In some embodiments, the semiconductor device further includes:

[0060] A first epitaxial layer and a second epitaxial layer are sequentially stacked along the first direction and located between the substrate and the memory array; wherein the growth temperature of the first epitaxial layer is lower than the growth temperature of the second epitaxial layer.

[0061] In some embodiments, the semiconductor device further includes:

[0062] The storage structure and the bit line are respectively connected to a first end and a second end of the channel layer that are opposite to each other along a second direction.

[0063] Each bitline is connected to the second end of a plurality of channel layers arranged along the first direction.

[0064] In some embodiments, the channel layer comprises at least one of the material elements selected from Si, Ge, or Sn.

[0065] Fifthly, this disclosure provides an electronic device, including a semiconductor device prepared according to a semiconductor device manufacturing method provided in any embodiment of the third aspect, or a semiconductor device as provided in any embodiment of the fourth aspect.

[0066] In the technical solution provided in the embodiments of this disclosure, the first semiconductor layer is configured as a first sub-layer and a second sub-layer with different etching selectivity ratios than the second semiconductor layer. When the first semiconductor layer is removed and the second semiconductor layer is retained, the first semiconductor layer can be removed more precisely so that the retained second semiconductor layer has a good morphology. At the same time, the setting of the second sub-layer reduces the lattice mismatch between the first semiconductor layer and the second semiconductor layer, and avoids dislocation defects from affecting the number of stacked layers.

[0067] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0068] Figure 1A This is a cross-sectional schematic diagram of some process steps in the formation of a semiconductor device according to an embodiment of the present disclosure;

[0069] Figure 1B This is a cross-sectional schematic diagram of some process steps in the formation of a semiconductor device according to an embodiment of the present disclosure;

[0070] Figure 1C This is a cross-sectional schematic diagram of some process steps in the formation of a semiconductor device according to an embodiment of the present disclosure. Figure 3 ;

[0071] Figure 2A A three-dimensional structural schematic diagram of a semiconductor structure provided in yet another embodiment of this disclosure;

[0072] Figure 2B To and Figure 2A Corresponding top view structural diagram;

[0073] Figure 2C for Figure 2BThe cross-sectional view shown is along the tangent AA' direction and the BB' direction;

[0074] Figure 2D for Figure 2B Enlarged view of the structure within the dashed box;

[0075] Figure 2E for Figure 2B Another schematic diagram of the area shown in the dashed box;

[0076] Figure 3 This is a schematic diagram illustrating the specific implementation flow of a semiconductor device manufacturing method according to an embodiment of the present disclosure;

[0077] Figure 4A A three-dimensional structural schematic diagram of a semiconductor device during the manufacturing process provided in this embodiment of the disclosure;

[0078] Figure 4B To and Figure 4A Corresponding top view structural diagram;

[0079] Figure 4C for Figure 4B The cross-sectional view shown is along the tangent AA' and BB' directions;

[0080] Figure 5A A second three-dimensional structural schematic diagram of a semiconductor device during the manufacturing process, provided as an embodiment of this disclosure;

[0081] Figure 5B To and Figure 5A Corresponding top view structural diagram;

[0082] Figure 5C for Figure 5B The cross-sectional view shown is along the tangent AA' and BB' directions;

[0083] Figure 6A A three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment. Figure 3 ;

[0084] Figure 6B To and Figure 6A Corresponding top view structural diagram;

[0085] Figure 6C for Figure 6B The cross-sectional view shown is along the tangent AA' and BB' directions;

[0086] Figure 7A Four three-dimensional structural diagrams of semiconductor devices during the manufacturing process provided in this disclosure embodiment;

[0087] Figure 7B To and Figure 7ACorresponding top view structural diagram;

[0088] Figure 7C for Figure 7B The cross-sectional view shown is along the tangent AA' and BB' directions;

[0089] Figure 8A Five are three-dimensional structural diagrams of semiconductor devices during the manufacturing process provided in this disclosure embodiment;

[0090] Figure 8B To and Figure 8A Corresponding top view structural diagram;

[0091] Figure 8C for Figure 8B The cross-sectional view shown is along the tangent AA' and BB' directions;

[0092] Figure 9A Sixth, a three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this disclosure embodiment;

[0093] Figure 9B To and Figure 9A Corresponding top view structural diagram;

[0094] Figure 9C for Figure 9B The cross-sectional view shown is along the tangent AA' and BB' directions;

[0095] Figure 10A Seven is a three-dimensional structural diagram of a semiconductor device during the manufacturing process provided in this embodiment of the disclosure.

[0096] Figure 10B To and Figure 10A Corresponding top view structural diagram;

[0097] Figure 10C for Figure 10B The cross-sectional view shown is along the tangent AA' and BB' directions;

[0098] Figure 11 Schematic diagram nine showing the three-dimensional structure of a semiconductor device during the manufacturing process, provided as an embodiment of this disclosure. Detailed Implementation

[0099] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0100] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0101] In this disclosure, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order, sequence, quantity, or importance.

[0102] In the embodiments of this disclosure, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" may be used to describe the positional relationships of the constituent elements with reference to the accompanying drawings. These terms are used solely for ease of description and simplification and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. The positional relationships and orientations of the constituent elements may change depending on the placement direction of each constituent element.

[0103] In this embodiment of the disclosure, "parallel" means approximately parallel or nearly parallel, and the included angle between the two elements defined therein may be within the allowable range of process tolerance. Similarly, "perpendicular" means approximately perpendicular or nearly perpendicular, and the included angle between the two elements defined therein may be an error angle relative to a 90° right angle that is within the allowable range of process tolerance.

[0104] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict. In the methods involved in the embodiments of this disclosure, unless otherwise specified or described, the execution order of each step can be adjusted according to actual circumstances or needs. That is, different combinations of the sequences of steps involved in the embodiments of this disclosure all fall within the protection scope of this disclosure.

[0105] The deposition processes involved in the embodiments of this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0106] The growth processes described in this disclosure include, but are not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), ion beam epitaxy, solid phase epitaxy, and combinations thereof.

[0107] The etching processes described in this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0108] Figures 1A to 1C This is a cross-sectional schematic diagram of some process steps in the formation of a semiconductor device according to an embodiment of the present disclosure. The following is in conjunction with... Figures 1A to 1C This embodiment describes a method for manufacturing a semiconductor device.

[0109] like Figure 1A As shown, a number of germanium-silicon (SiGe) layers 101 and silicon (Si) layers 102 are alternately stacked on a substrate 100 to form a silicon / germanium-silicon stack 103.

[0110] like Figure 1B As shown, the germanium-silicon (SiGe) layer 101 is removed, and the silicon (Si) layer 102 is retained.

[0111] like Figure 1C As shown, the silicon (Si) layer 102 is trimmed. Exemplarily, a portion of the silicon (Si) layer 102 is etched away to construct the channel layer of the semiconductor device. In subsequent processes, word lines, bit lines, capacitors, and other structures are formed on the remaining silicon (Si) layer 102.

[0112] The silicon / germanium silicon stack 103 is used to construct the channel layer of the semiconductor device; therefore, the structural design of the silicon / germanium silicon stack 103 directly affects the subsequent process difficulty and the overall number of stacked layers of the semiconductor device. See also Figures 1A to 1CWhen the thickness of the germanium-silicon (SiGe) layer 101 is large, it can provide sufficient space between the upper and lower silicon (Si) layers 102, facilitating subsequent processes (such as word line formation). However, excessive thickness of the germanium-silicon (SiGe) layer 101 will reduce the overall stacked layer count and decrease the storage density of the semiconductor device. In addition, excessive space between the upper and lower silicon (Si) layers 102 may lead to overall collapse. When the thickness of the germanium-silicon (SiGe) layer 101 is small, the stacked layer count of the semiconductor device can be significantly increased. However, the space between the upper and lower silicon (Si) layers 102 becomes smaller, requiring significant adjustments to the retained silicon (Si) layer 102 to obtain the channel layer of the target thickness. This increases the difficulty of subsequent processes. Specifically, during significant adjustments to the retained silicon (Si) layer 102, the formed channel layer morphology is prone to be poor, causing leakage current in subsequent semiconductor devices, thereby reducing the reliability of the semiconductor device.

[0113] Based on this, the present disclosure provides a semiconductor structure and its manufacturing method, a semiconductor device and its manufacturing method, and an electronic device.

[0114] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including: a plurality of alternately stacked first semiconductor layers and second semiconductor layers; the first semiconductor layer includes a first sublayer and a second sublayer; the first sublayer is located on opposite sides of the second sublayer along a first direction, the first direction being parallel to the stacking direction of the first semiconductor layer and the second semiconductor layer; a first etch selectivity ratio between the first sublayer and the second semiconductor layer is different from a second etch selectivity ratio between the second sublayer and the second semiconductor layer.

[0115] It should be noted that, here and below, the first direction is parallel to the stacking direction of the first and second semiconductor layers, and both the second and third directions are parallel to the plane containing the first and second semiconductor layers. Both the second and third directions are perpendicular to the first direction, and the second and third directions intersect each other. In some specific embodiments, the second direction is perpendicular to the third direction. For example, the first direction may be the extension direction of the Z-axis shown in the figures, the second direction may be the extension direction of the X-axis shown in the figures, and the third direction may be the extension direction of the Y-axis shown in the figures.

[0116] like Figure 2A , Figure 2B and 2CAs shown, the semiconductor structure includes: a plurality of alternatingly stacked first semiconductor layers 202 and second semiconductor layers 203; the first semiconductor layer 202 includes a first sublayer 2021 and a second sublayer 2022; the first sublayer 2021 is located on opposite sides of the second sublayer 2022 along a first direction, the first direction being parallel to the stacking direction of the first semiconductor layer 202 and the second semiconductor layer 203; a first etch selectivity ratio between the first sublayer 2021 and the second semiconductor layer 203 is different from a second etch selectivity ratio between the second sublayer 2022 and the second semiconductor layer 203.

[0117] In some embodiments, the semiconductor structure further includes a substrate 201, and a stacked layer 204 formed by a plurality of first semiconductor layers 202 and second semiconductor layers 203 is located on the substrate 201. Exemplarily, the substrate 201 may be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc. It may also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), or silicon-germanium-on-insulator (SGOI), etc.

[0118] By configuring the first semiconductor layer 202 as a first sublayer 2021 and a second sublayer 2022 with different etching selectivity ratios to the second semiconductor layer 203, the first semiconductor layer 202 can be removed more precisely when the first semiconductor layer 202 is removed and the second semiconductor layer 203 is retained, so that the retained second semiconductor layer 203 has a good morphology. At the same time, the configuration of the second sublayer 2022 reduces the lattice mismatch between the first semiconductor layer 202 and the second semiconductor layer 203, so as to ensure that a sufficient number of stacked layers can be achieved.

[0119] In some embodiments, the first etch selectivity ratio between the first sublayer 2021 and the second semiconductor layer 203 is greater than the second etch selectivity ratio between the second sublayer 2022 and the second semiconductor layer 203.

[0120] In some embodiments, the first sublayer and the second sublayer contain the same material elements, but the proportion of the first element in the first sublayer and the second sublayer is different.

[0121] It should be noted that the percentage of the first element refers to the atomic percentage of the first element in the first or second sublayer of the material, which can also be called atomic concentration (at%) or mass percentage.

[0122] In some implementations, the etching selectivity ratio between the first sublayer 2021 and the second sublayer 2022 and the second semiconductor layer 203 increases as the proportion of the first element increases.

[0123] In some embodiments, in the direction from the first sub-layer 2021 to the second semiconductor layer 203 in contact with the first sub-layer 2021, the proportion of the first element in the first sub-layer 2021 remains unchanged; the proportion of the first element in the first sub-layer 2021 is greater than the proportion of the first element in the second sub-layer 2022. For example, the first element is uniformly distributed in both the first sub-layer 2021 and the second sub-layer 2022. The greater proportion of the first element in the first sub-layer 2021 compared to the second sub-layer 2022 helps to improve the etching selectivity at the contact portion between the second semiconductor layer 203 and the first semiconductor layer 202. Furthermore, by controlling the equivalent proportion (content) of the first element in the stacked layer 204 through the second sub-layer 2022, the lattice mismatch between the first semiconductor layer 202 and the second semiconductor layer 203 caused by an excessively high overall proportion of the first element in the first semiconductor layer 202 is reduced.

[0124] In some embodiments, in the direction from the first sub-layer 2021 to the second semiconductor layer 203 in contact with the first sub-layer 2021, the proportion of the first element in the first sub-layer 2021 increases; the minimum proportion of the first element in the first sub-layer 2021 is greater than the proportion of the first element in the second sub-layer 2022.

[0125] In some implementations, the proportion of the first element in the first sub-layer 2021 gradually increases in the direction close to the second semiconductor layer 203, so as to ensure that the etching selectivity of the contact portion between the first sub-layer 2021 and the second semiconductor layer 203 is relatively large. At the same time, the stress distribution in the stacked layer 204 is optimized by the gradient of the first element in the first sub-layer 2021 to reduce the formation of dislocations.

[0126] In some embodiments, the first element is evenly distributed in the second sub-layer 2022, and the minimum proportion of the first element in the first sub-layer 2021 is greater than the proportion of the first element in the second sub-layer 2022. In other words, the proportion of the first element in the first sub-layer 2021 is the smallest in the part where the first sub-layer 2021 contacts the second sub-layer 2022, and the minimum proportion of the first element in the first sub-layer 2021 is greater than the proportion of the first element in the second sub-layer 2022.

[0127] In other embodiments, the first element in the second sub-layer 2022 also exhibits a gradual distribution. Specifically, along the direction closer to the first sub-layer 2021, the proportion of the first element in the second sub-layer 2022 gradually increases. The proportion of the first element in the second sub-layer 2022 is the largest in the portion where the second sub-layer 2022 contacts the first sub-layer 2021, and the minimum proportion of the first element in the first sub-layer 2021 is greater than the maximum proportion of the first element in the second sub-layer 2022. Setting the second sub-layer 2022 as a structure with a gradually changing proportion of the first element can further optimize the stress distribution in the stacked layer 204.

[0128] In some embodiments, the first sublayer and the second sublayer both contain Si and Ge as material elements, and the first element is either Ge or Si.

[0129] For example, the second semiconductor layer 203 is made of Si, and both the first sublayer 2021 and the second sublayer 2022 are made of Si and Ge, with Ge as the first element. As the proportion of Ge increases, the etching selectivity between Si and SiGe increases. Specifically, the first sublayer 2021 is made of Si. 1-x Ge x This indicates that the material of the second sublayer 2022 is Si. 1- y Ge y Both x and y are greater than 0 and less than or equal to 1, with x being greater than y. This means that the proportion of the first element Ge in the first sub-layer 2021 and the second sub-layer 2022 is greater than 0 and less than or equal to 100%. For example, the proportion of the first element Ge in the first sub-layer 2021 is 20% to 30%, and the proportion of the first element Ge in the second sub-layer 2022 is 5% to 10%.

[0130] In some implementations, the distribution of the first element Ge in the first sublayer 2021 gradually changes in the direction from the first sublayer 2021 to the second semiconductor layer 203 that contacts the first sublayer 2021. For example, the proportion of the first element Ge in the first sublayer 2021 increases from 10% to 30%, and the proportion of the first element Ge in the second sublayer 2022 is 5%.

[0131] For example, the second semiconductor layer 203 contains Ge as its material element, and the first sublayer 2021 and the second sublayer 2022 both contain Si and Ge as their material elements, with Si as the first element. As the proportion of the first element Si increases, the etching selectivity ratio between Ge and SiGe increases. Specifically, the first sublayer 2021 is made of Si. m Ge 1-m This indicates that the material of the second sublayer 2022 is Si. n Ge 1-nBoth m and n are greater than 0 and less than or equal to 1, with m being greater than n. That is, the proportion of the first element Si in the first sublayer 2021 and the second sublayer 2022 is greater than 0% and less than or equal to 100%. For example, the proportion of the first element Si in the first sublayer 2021 is 15% to 25%, and the proportion of the first element Si in the second sublayer 2022 is 0% to 5%.

[0132] In some embodiments, in the direction from the first sub-layer 2021 to the second semiconductor layer 203 that is in contact with the first sub-layer 2021, the distribution of the first element Si in the first sub-layer 2021 gradually changes. For example, the proportion of the first element Si in the first sub-layer 2021 increases from 15% to 25%, and the proportion of the first element Ge in the second sub-layer 2022 is 10%.

[0133] It should be noted that, in practical use, provided that the first etch selectivity ratio between the first sublayer and the second semiconductor layer is greater than the second etch selectivity ratio between the second sublayer and the second semiconductor layer, the proportion of the first element in the first sublayer and the second sublayer can be reasonably set according to the actual required equivalent proportion (content) of the first element in the stacked layers. The numerical range of the proportion of the first element in the first sublayer and the second sublayer here is only an example and should not unduly limit the scope of protection of this disclosure.

[0134] In some embodiments, the first sublayer and the second sublayer contain different material elements.

[0135] In some embodiments, the first sublayer comprises Si and Ge, and the second sublayer comprises Si and B (boron). For example, the second semiconductor layer 203 is made of Si, and the first sublayer 2021 is made of Si. 0.8 Ge 0.2 The material of the second sublayer 2022 is SiB, where Si 0.8 Ge 0.2 The etching selectivity between Si and SiB is greater than that between SiB and Si.

[0136] In some embodiments, the second sublayer contains the same material elements as the second semiconductor layer.

[0137] In some embodiments, the second semiconductor layer 203 and the second sub-layer 2022 are both composed of Ge, and the first sub-layer 2021 is composed of Si and Ge; or, the second semiconductor layer 203 and the second sub-layer 2022 are both composed of Si, and the first sub-layer 2021 is composed of Si and Ge. It is understood that the second semiconductor layer 203 and the second sub-layer 2022 containing the same material elements represent the case where the proportion of the first element in the second sub-layer 2022 is 0.

[0138] In some embodiments, the first semiconductor layer further includes: a third sublayer located between the first sublayer and the second sublayer; the magnitude of a third etch selectivity between the third sublayer and the second semiconductor layer is between the first etch selectivity and the second etch selectivity.

[0139] In some implementations, such as Figure 2E As shown, the first semiconductor layer 202 may further include a third sub-layer 2023, and the third etch selectivity between the third sub-layer 2023 and the second semiconductor layer 203 is between the first etch selectivity and the second etch selectivity.

[0140] Here, the third etch selectivity ratio between the third sub-layer 2023 and the second semiconductor layer 203 is greater than the second etch selectivity ratio between the second sub-layer 2022 and the second semiconductor layer 203, and less than the first etch selectivity ratio between the first sub-layer 2021 and the second semiconductor layer 203.

[0141] In some implementations, the first sub-layer 2021, the second sub-layer 2022, and the third sub-layer 2023 contain the same material elements, but the proportion of the first element in the first sub-layer 2021 is greater than the proportion of the first element in the third sub-layer 2023, and the proportion of the first element in the third sub-layer 2023 is greater than the proportion of the first element in the second sub-layer 2022. For example, the second semiconductor layer 203 contains Si, and the first sub-layer 2021, the second sub-layer 2022, and the third sub-layer 2023 all contain Si and Ge. The proportion of Ge in the first sub-layer 2021 is 30%, the proportion of Ge in the third sub-layer 2023 is 20%, and the proportion of Ge in the second sub-layer 2022 is 5%. By setting the first semiconductor layer 202 as more sublayers, the sudden change in the proportion of the first element in the first semiconductor layer 202 is avoided, which is conducive to further optimizing the stress distribution in the first semiconductor layer 202 and reducing the overall dislocation density. Furthermore, by controlling the equivalent proportion (content) of the first element in the stacked layer 204 through more sublayers, the lattice mismatch between the first semiconductor layer 202 and the second semiconductor layer 203 is further reduced.

[0142] It should be noted that, provided that the second etch selectivity between the second sublayer and the second semiconductor is less than the etch selectivity between the first sublayer and the third sublayer and the second semiconductor layer, the proportion of the first element in the first sublayer, the second sublayer, and the third sublayer can be reasonably set according to the actual situation. The specific values ​​of the proportion of the first element in the first sublayer, the second sublayer, and the third sublayer here are only examples and should not unduly limit the scope of protection of this disclosure.

[0143] In some embodiments, the dimension of the second sublayer along the first direction is smaller than the dimension of the second semiconductor layer along the first direction. For example, as... Figure 2D As shown, W1 is the dimension of the second sublayer 2022 along the first direction, and W2 is the dimension of the second semiconductor layer 203 along the first direction, where W1 is smaller than W2. After removing the first sublayer 2021 of the first semiconductor layer 202 and retaining the second semiconductor layer 203, the second sublayer 2022 is removed simultaneously when the second semiconductor layer 203 is trimmed. The dimension W1 of the second sublayer 2022 along the first direction is set as the target dimension for trimming. In other words, the thickness of the portion of the second semiconductor layer 203 removed during trimming is the thickness of the second sublayer 2022. The dimension of the second semiconductor layer 203 retained as the channel layer along the first direction is W2-W1. This avoids over-etching of the second semiconductor layer 203, resulting in a good morphology for the ultimately retained second semiconductor layer 203 used as the channel layer.

[0144] In some embodiments, the first etch selectivity is less than the second etch selectivity. For example, the first etch selectivity between the first sublayer 2021 and the second semiconductor layer 203 is less than the second etch selectivity between the second sublayer 2022 and the second semiconductor layer 203.

[0145] In some embodiments, the first sublayer 2021 contains the material elements Ge and Sn (tin), and the second sublayer 2022 contains the material elements Ge and B.

[0146] In some embodiments, the first sublayer 2021 and the second semiconductor layer 203 contain the same material elements; the proportion of the first element in the first sublayer 2021 is greater than the proportion of the first element in the second semiconductor layer 203; the first element is Ge.

[0147] For example, the material of the second semiconductor layer 203 is Ge. 0.9 Sn 0.1 The material of the first sublayer 2021 is Ge. 0.97 Sn 0.03 The material of the second sublayer 2022 is GeB, wherein GeB and Ge 0.9 Sn 0.1 The etching selectivity between them is greater than that of Ge. 0.97 Sn 0.03 With Ge 0.9 Sn 0.1 The etching selectivity ratio between them.

[0148] In some implementations, such as Figure 2EAs shown, the first semiconductor layer 202 may further include a third sub-layer 2023, and the third etch selectivity between the third sub-layer 2023 and the second semiconductor layer 203 is between the first etch selectivity and the second etch selectivity.

[0149] Here, the third etch selectivity ratio between the third sub-layer 2023 and the second semiconductor layer 203 is less than the second etch selectivity ratio between the second sub-layer 2022 and the second semiconductor layer 203, and greater than the first etch selectivity ratio between the first sub-layer 2021 and the second semiconductor layer 203.

[0150] In some embodiments, the material of the second semiconductor layer 203 is Ge. 0.9 Sn 0.1 The material of the first sublayer 2021 is Ge. 0.97 Sn 0.03 The material of the second sublayer 2022 is GeB, and the material of the third sublayer 2023 is Ge. Among these, Ge and Ge... 0.9 Sn 0.1 The etching selectivity between GeB and GeB is smaller. 0.9 Sn 0.1 The etching selectivity ratio between them is greater than that of Ge. 0.97 Sn 0.03 With Ge 0.9 Sn 0.1 The etching selectivity ratio between them.

[0151] By setting the first semiconductor layer 202 as more sublayers, the sudden change in the proportion of the first element in the first semiconductor layer 202 is avoided, which is conducive to further optimizing the stress distribution in the first semiconductor layer 202 and reducing the overall dislocation density. Furthermore, by controlling the equivalent proportion (content) of the first element in the stacked layer 204 through more sublayers, the lattice mismatch between the first semiconductor layer 202 and the second semiconductor layer 203 is further reduced.

[0152] In a second aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising: forming a plurality of alternately stacked first semiconductor layers and second semiconductor layers; the first semiconductor layer comprising a first sublayer and a second sublayer; the first sublayer being located on opposite sides of the second sublayer along a first direction, the first direction being parallel to the stacking direction of the first semiconductor layer and the second semiconductor layer; and a first etch selectivity ratio between the first sublayer and the second semiconductor layer being different from a second etch selectivity ratio between the second sublayer and the second semiconductor layer.

[0153] In some embodiments, a plurality of alternatingly stacked first and second semiconductor layers can be formed on a substrate using an epitaxy process. The etching selectivity ratios between the first and second sublayers of the first semiconductor layer and the second semiconductor layer are different. For example, the different etching selectivity ratios between the first and second sublayers and the second semiconductor layer can be achieved by adjusting the epitaxy process parameters to change the elemental composition and proportions of the materials contained in the first and second sublayers.

[0154] Thirdly, embodiments of this disclosure provide a method for manufacturing a semiconductor device. Figure 3 This is a schematic diagram illustrating a specific implementation flow of a semiconductor device manufacturing method provided in an embodiment of this disclosure. For example... Figure 3 As shown, the specific steps of the manufacturing method of this semiconductor device include:

[0155] Step S10: Form a plurality of alternating stacked first semiconductor layers and second semiconductor layers; the first semiconductor layer includes a first sublayer and a second sublayer, the first sublayer being located on opposite sides of the second sublayer along a first direction, the first direction being parallel to the stacking direction of the first semiconductor layer and the second semiconductor layer.

[0156] Step S20: At least the first sublayer and the second sublayer are removed to form a first groove; wherein the first etch selectivity between the first sublayer and the second semiconductor layer is different from the second etch selectivity between the second sublayer and the second semiconductor layer.

[0157] Step S30: Form a gate structure covering the second semiconductor layer in the first groove.

[0158] Step S40: Form a memory structure and bit lines. The memory structure and bit lines are respectively connected to the two ends of the second semiconductor layer opposite to each other along the second direction, which is perpendicular to the first direction.

[0159] It should be understood that Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs.

[0160] Please refer to the following. Figures 2A to 2E as well as Figures 4A to 11 and combined Figure 3 The present disclosure provides a more detailed description of the manufacturing process of the semiconductor device provided in the embodiments.

[0161] refer to Figures 2A to 2C Execute step S10.

[0162] like Figure 2A , Figure 2B and Figure 2C As shown, a plurality of alternatingly stacked first semiconductor layers 202 and second semiconductor layers 203 are formed on a substrate 201. The first semiconductor layer 202 includes a first sublayer 2021 and a second sublayer 2022, wherein the first sublayer 2021 is located on opposite sides of the second sublayer 2022 along a first direction, which is parallel to the stacking direction of the first semiconductor layer 202 and the second semiconductor layer 203. The plurality of first semiconductor layers 202 and second semiconductor layers 203 constitute a stacked layer 204.

[0163] In some embodiments, the method for manufacturing the semiconductor device further includes: sequentially forming a first epitaxial layer (not shown) and a second epitaxial layer (not shown) along a first direction; wherein the growth temperature of the first epitaxial layer is lower than the growth temperature of the second epitaxial layer; and forming a plurality of alternately stacked first semiconductor layers and second semiconductor layers on the second epitaxial layer.

[0164] For example, the growth temperature of the first epitaxial layer is 200°C to 450°C. The first epitaxial layer is used to release strain, so that more dislocations and defects in the subsequently formed stacked layers are confined in the first epitaxial layer. The growth temperature of the second epitaxial layer is 450°C to 950°C to form a semiconductor device with higher carrier mobility.

[0165] refer to Figures 4A to 6C Step S20 is executed to form the first groove.

[0166] refer to Figure 4A , Figure 4B and Figure 4C A portion of the first semiconductor layer 202 and the second semiconductor layer 203 is removed along the first direction, and a first trench is formed on both sides of the first semiconductor layer 202 and the second semiconductor layer 203 along the second direction. Figures 4B to 4C (Not shown); a support structure 205 is formed in the first trench.

[0167] In some embodiments, the material of the support structure 205 includes, but is not limited to, silicon nitride.

[0168] In some embodiments, the first groove includes a second trench, a first sub-groove, and a second sub-groove; at least the first sub-layer and the second sub-layer are removed to form the first groove, which includes: forming a plurality of second trenches extending through the first semiconductor layer and the second semiconductor layer along a first direction, the plurality of second trenches extending along the second direction and spaced apart along a third direction; forming a first sub-groove based on the second trenches; forming a second sub-groove based on the second trenches; wherein the third direction intersects the second direction and is perpendicular to the first direction.

[0169] In some implementations, such as Figures 4A to 4CAs shown, a plurality of second trenches 206 are formed that penetrate the first semiconductor layer 202 and the second semiconductor layer 203 along a first direction. The plurality of second trenches 206 extend along a second direction and are spaced apart along a third direction. The third direction intersects the second direction and is perpendicular to the first direction.

[0170] In some embodiments, the first etch selectivity is greater than the second etch selectivity. For example, the first etch selectivity between the first sublayer 2021 and the second semiconductor layer 203 is greater than the second etch selectivity between the second sublayer 2022 and the second semiconductor layer 203.

[0171] In some implementations, such as Figure 5A , Figure 5B and Figure 5C As shown, the first sub-layer 2021 of the first semiconductor layer 202 is removed based on the second trench 206 to form a first sub-groove 207. The first sub-groove 207 extends along the second direction and is spaced apart along the first direction.

[0172] Since the first semiconductor layer 202 includes a first sub-layer 2021 and a second sub-layer 2022 with different etching selectivity ratios than the second semiconductor layer 203, it helps to improve the etching selectivity ratio of the contact portion between the second semiconductor layer 203 and the first semiconductor layer 202. Therefore, when removing the first sub-layer 2021 of the first semiconductor layer 202 to form the first sub-groove 207, the first sub-layer 2021 can be removed more precisely. The second semiconductor layer 203 in contact with the first sub-layer 2021 has a good morphology, which improves the reliability of the subsequently formed semiconductor device.

[0173] In some implementations, such as Figure 6A , Figure 6B and Figure 6C As shown, a second sub-groove is formed by removing a second sub-layer 2022 and a portion of the second semiconductor layer 203 from the first semiconductor layer 202 based on the second trench 206.

[0174] In some embodiments, the etching selectivity between the second sublayer 2022 and the second semiconductor layer 203 is less than the etching selectivity between the first sublayer 2021 and the second semiconductor layer 203. For example, the etching selectivity between the second sublayer 2022 and the second semiconductor layer 203 can be set to be small or even 0, so that the second sublayer 2022 can be removed while the second semiconductor layer 203 is being adjusted after the first sublayer is removed.

[0175] In some implementations, the dimension of the second sublayer along the first direction is smaller than the dimension of the second semiconductor layer along the first direction. (See reference...) Figure 2DW1 is the dimension of the second sub-layer 2022 along the first direction, and W2 is the dimension of the second semiconductor layer 203 along the first direction, where W1 is less than W2. Based on the second trench 206, the second sub-layer 2022 and part of the second semiconductor layer 203 of the first semiconductor layer 202 are removed. While adjusting the second semiconductor layer 203, the second sub-layer 2022 is removed to form a second sub-groove. The dimension W1 of the second sub-layer 2022 along the first direction is set as the target dimension for adjustment. In other words, the thickness of the part of the second semiconductor layer 203 removed when adjusting the second semiconductor layer 203 is the thickness of the second sub-layer 2022. The dimension of the second semiconductor layer 203 along the first direction is reduced by W1, and the final dimension of the second semiconductor layer 203 used as the channel layer along the first direction is W2-W1.

[0176] When forming the stacked layer 204, if the second sub-layer 2022 is not provided, the dimension of the second semiconductor layer 203 along the first direction is W2 + W1. In order to ensure that the final dimension of the second semiconductor layer 203 used as the channel layer along the first direction is W2 - W1, the dimension of the second semiconductor layer 203 along the first direction needs to be reduced by 2W1 when adjusting the second semiconductor layer 203. When adjusting the second semiconductor layer 203 to a larger size, defects and uneven etching are more likely to occur, reducing the reliability of the subsequently formed semiconductor device.

[0177] Based on the above analysis, it is understandable that the second sub-layer 2022, as a virtual channel layer, will be removed during the formation of the channel layer. The second sub-layer 2022 is used to reduce the size of the second semiconductor layer 203, avoid over-etching of the second semiconductor layer 203, and facilitate more precise control of the channel layer thickness, so that the second semiconductor layer 203 ultimately retained as the channel layer has a good morphology.

[0178] here, Figure 6C The third groove 208 shown is composed of a first sub-groove 207 and a second sub-groove. The third groove 208 and the second trench 206 constitute the first groove. Thus, while forming the first groove, the remaining second semiconductor layer 203 is strip-shaped along the second direction.

[0179] In other embodiments, the first groove includes a first sub-groove and a second sub-groove, i.e., the process step of forming the second trench is omitted; at least the first sub-layer and the second sub-layer are removed to form the first groove, including: removing the first sub-layer of the first semiconductor layer to form the first sub-groove; removing the second sub-layer of the first semiconductor layer and a portion of the second semiconductor layer to form the second sub-groove. Thus, while forming the first groove, the remaining second semiconductor layer is layered along the second direction.

[0180] In some embodiments, the first sublayer and the second sublayer contain the same material elements, but the proportion of the first element in the first sublayer and the second sublayer is different.

[0181] In some embodiments, in the direction from the first sub-layer 2021 to the second semiconductor layer 203 in contact with the first sub-layer 2021, the proportion of the first element in the first sub-layer 2021 remains unchanged; the proportion of the first element in the first sub-layer 2021 is greater than the proportion of the first element in the second sub-layer 2022. For example, the first element is uniformly distributed in both the first sub-layer 2021 and the second sub-layer 2022. The greater proportion of the first element in the first sub-layer 2021 compared to the second sub-layer 2022 helps to improve the etching selectivity at the contact between the second semiconductor layer 203 and the first semiconductor layer 202. Furthermore, by controlling the equivalent proportion (content) of the first element in the stacked layer 204 of the second sub-layer 2022, the lattice mismatch between the first semiconductor layer 202 and the second semiconductor layer 203 is reduced.

[0182] In some embodiments, in the direction from the first sub-layer 2021 to the second semiconductor layer 203 in contact with the first sub-layer 2021, the proportion of the first element in the first sub-layer 2021 increases; the minimum proportion of the first element in the first sub-layer 2021 is greater than the proportion of the first element in the second sub-layer 2022.

[0183] In some implementations, the proportion of the first element in the first sub-layer 2021 gradually increases in the direction close to the second semiconductor layer 203, so as to ensure that the etching selectivity of the contact portion between the first sub-layer 2021 and the second semiconductor layer 203 is relatively large. At the same time, the stress distribution in the stacked layer 204 is optimized by the gradient of the first element in the first sub-layer 2021 to reduce the formation of dislocations.

[0184] In some embodiments, the first element is evenly distributed in the second sub-layer 2022, and the minimum proportion of the first element in the first sub-layer 2021 is greater than the proportion of the first element in the second sub-layer 2022. In other words, the proportion of the first element in the first sub-layer 2021 is the smallest in the part where the first sub-layer 2021 contacts the second sub-layer 2022, and the minimum proportion of the first element in the first sub-layer 2021 is greater than the proportion of the first element in the second sub-layer 2022.

[0185] In other embodiments, the first element in the second sub-layer 2022 also exhibits a gradual distribution. Specifically, along the direction closer to the first sub-layer 2021, the proportion of the first element in the second sub-layer 2022 gradually increases. The proportion of the first element in the second sub-layer 2022 that is in contact with the first sub-layer 2021 is the largest, and the minimum proportion of the first element in the first sub-layer 2021 is greater than the maximum proportion of the first element in the second sub-layer 2022. Setting the second sub-layer 2022 as a structure with a gradually changing proportion of the first element can further optimize the stress distribution in the stacked layer 204.

[0186] It should be noted that the dimension W1 of the second sublayer 2022 along the first direction is set according to the target thickness of the second semiconductor layer and the final channel layer. For example, if the dimension of the second semiconductor layer along the first direction is W2 and the target thickness of the final channel layer is W3, then the dimension W1 of the second sublayer 2022 along the first direction is equal to the difference between W2 and W3.

[0187] In some embodiments, the first sublayer and the second sublayer both contain Si and Ge as material elements, and the first element is either Ge or Si.

[0188] For example, the second semiconductor layer 203 is composed of Si, and both the first sublayer 2021 and the second sublayer 2022 are composed of Si and Ge, with Ge as the first element. The percentage of Ge as the first element in the first sublayer 2021 and the second sublayer 2022 is greater than 0 and less than or equal to 100%. For example, the percentage of Ge as the first element in the first sublayer 2021 is 20% to 30%, and the percentage of Ge as the first element in the second sublayer 2022 is 5% to 10%.

[0189] In some embodiments, when the distribution of the first element Ge in the first sublayer 2021 gradually changes in the direction of the first sublayer 2021 pointing towards the second semiconductor layer 203 in contact with the first sublayer 2021, the proportion of the first element Ge in the first sublayer 2021 increases from 10% to 30%, and the proportion of the first element Ge in the second sublayer 2022 is 5%.

[0190] For example, the second semiconductor layer 203 contains Ge as the material element, and both the first sublayer 2021 and the second sublayer 2022 contain Si and Ge as the material elements, with Si as the first element. As the proportion of the first element Si increases, the etching selectivity ratio between Ge and SiGe increases. The proportion of the first element Si in the first sublayer 2021 and the second sublayer 2022 ranges from greater than 0% to less than or equal to 100%. For example, the proportion of the first element Si in the first sublayer 2021 is 15% to 25%, and the proportion of the first element Si in the second sublayer 2022 is 0% to 5%.

[0191] As the distribution of the first element Si in the first sublayer 2021 gradually changes in the direction from the first sublayer 2021 to the second semiconductor layer 203 that contacts the first sublayer 2021, the proportion of the first element Si in the first sublayer 2021 increases from 15% to 25%, and the proportion of the first element Ge in the second sublayer 2022 is 10%.

[0192] It should be noted that, in practical use, provided that the etch selectivity between the first sublayer and the second semiconductor layer is greater than that between the second sublayer and the second semiconductor layer, the proportion of the first element in the first sublayer and the second sublayer can be reasonably set according to the actual required equivalent proportion (content) of the first element in the stacked layers. The numerical range of the proportion of the first element in the first sublayer and the second sublayer here is only an example and should not unduly limit the scope of protection of this disclosure.

[0193] In some embodiments, the first sublayer and the second sublayer contain different material elements.

[0194] In some embodiments, the first sublayer comprises materials of Si and Ge, and the second sublayer comprises materials of Si and B. For example, the second semiconductor layer 203 is made of Si, and the first sublayer 2021 is made of Si. 0.8 Ge 0.2 The material of the second sublayer 2022 is SiB, where Si 0.8 Ge 0.2 The etching selectivity between Si and SiB is greater than that between SiB and Si.

[0195] In some embodiments, the second sublayer contains the same material elements as the second semiconductor layer.

[0196] In some embodiments, the second semiconductor layer 203 and the second sub-layer 2022 are both composed of Ge, and the first sub-layer 2021 is composed of Si and Ge; or, the second semiconductor layer 203 and the second sub-layer 2022 are both composed of Si, and the first sub-layer 2021 is composed of Si and Ge. It is understood that the second semiconductor layer 203 and the second sub-layer 2022 containing the same material elements represent the case where the proportion of the first element in the second sub-layer 2022 is 0.

[0197] In some embodiments, the first semiconductor layer further includes: a third sublayer located between the first sublayer and the second sublayer; the magnitude of a third etch selectivity between the third sublayer and the second semiconductor layer is between the first etch selectivity and the second etch selectivity.

[0198] In some implementations, such as Figure 2E As shown, the first semiconductor layer 202 may further include a third sub-layer 2023, and the third etch selectivity between the third sub-layer 2023 and the second semiconductor layer 203 is between the first etch selectivity and the second etch selectivity.

[0199] Here, the etching selectivity ratio between the third sub-layer 2023 and the second semiconductor layer 203 is greater than that between the second sub-layer 2022 and the second semiconductor layer 203, but less than that between the first sub-layer 2021 and the second semiconductor layer 203. For example, the first sub-layer 2021, the second sub-layer 2022, and the third sub-layer 2023 contain the same material elements, with the proportion of the first element in the first sub-layer 2021 being greater than the proportion of the first element in the third sub-layer 2023, and the proportion of the first element in the third sub-layer 2023 being greater than the proportion of the first element in the second sub-layer 2022. For example, the second semiconductor layer 203 contains Si, and the first sub-layer 2021, the second sub-layer 2022, and the third sub-layer 2023 all contain Si and Ge. The proportion of the first element Ge in the first sub-layer 2021 is 30%, the proportion of the first element in the third sub-layer 2023 is 20%, and the proportion of the first element in the second sub-layer 2022 is 5%. Since the etching selectivity between the second sub-layer 2022 and the second semiconductor layer 203 is smaller than that between the first sub-layer 2021 and the third sub-layer 2023 and the second semiconductor layer 203, when forming the first trench, the first sub-layer 2021 and the third sub-layer 2023 are removed first to form the first sub-trench; then the second sub-layer 2022 and part of the second semiconductor layer 203 are removed to form the second sub-trench.

[0200] In some embodiments, the first etch selectivity is less than the second etch selectivity; the first trench includes a first sub-trench and a second sub-trench; the step of removing at least the first sub-layer and the second sub-layer to form the first trench includes: removing the second sub-layer of the first semiconductor layer to form the first sub-trench; and removing the first sub-layer of the first semiconductor layer and a portion of the second semiconductor layer to form the second sub-trench.

[0201] For example, the first etch selectivity ratio between the first sublayer 2021 and the second semiconductor layer 203 is less than the second etch selectivity ratio between the second sublayer 2022 and the second semiconductor layer 203.

[0202] In some embodiments, the first sublayer 2021 contains material elements Ge and Sn, and the second sublayer 2022 contains material elements Ge and B.

[0203] In some embodiments, the first sub-layer 2021 and the second semiconductor layer 203 contain the same material elements; the proportion of the first element in the first sub-layer 2021 is greater than the proportion of the first element in the second semiconductor layer 203; the first element is Ge. For example, the material of the second semiconductor layer 203 is Ge. 0.9 Sn 0.1 The material of the first sublayer 2021 is Ge. 0.97 Sn 0.03 The material of the second sublayer 2022 is GeB, wherein GeB and Ge 0.9 Sn 0.1 The etching selectivity between them is greater than that of Ge. 0.97 Sn 0.03 With Ge 0.9 Sn 0.1 The etching selectivity ratio between them.

[0204] Since the second etch selectivity ratio between the second sub-layer 2022 and the second semiconductor layer 203 is greater than the first etch selectivity ratio between the first sub-layer 2021 and the third sub-layer 2023 and the second semiconductor layer 203, when forming the first groove, the second sub-layer 2022 is removed first to form the first sub-groove; then the first sub-layer 2021 and part of the second semiconductor layer 203 are removed to form the second sub-groove.

[0205] Since the first semiconductor layer includes a first sub-layer and a second sub-layer with different etching selectivity ratios than the second semiconductor layer, the first sub-layer protects the second semiconductor layer from damage during the removal of the second sub-layer to form the first sub-groove. This facilitates more precise control of the channel layer thickness, resulting in the second semiconductor layer that is ultimately retained as the channel layer having a good morphology and improving the reliability of the subsequently formed semiconductor device.

[0206] In some implementations, such as Figure 2E As shown, the first semiconductor layer 202 may further include a third sub-layer 2023, and the third etch selectivity between the third sub-layer 2023 and the second semiconductor layer 203 is between the first etch selectivity and the second etch selectivity.

[0207] Here, the third etch selectivity ratio between the third sub-layer 2023 and the second semiconductor layer 203 is less than the second etch selectivity ratio between the second sub-layer 2022 and the second semiconductor layer 203, and greater than the first etch selectivity ratio between the first sub-layer 2021 and the second semiconductor layer 203.

[0208] In some embodiments, the material of the second semiconductor layer 203 is Ge. 0.9 Sn 0.1 The material of the first sublayer 2021 is Ge. 0.97 Sn 0.03The material of the second sublayer 2022 is GeB, and the material of the third sublayer 2023 is Ge. Among these, Ge and Ge... 0.9 Sn 0.1 The etching selectivity between GeB and GeB is smaller. 0.9 Sn 0.1 The etching selectivity ratio between them is greater than that of Ge. 0.97 Sn 0.03 With Ge 0.9 Sn 0.1 The etching selectivity ratio between them.

[0209] Since the etching selectivity between the second sub-layer 2022 and the second semiconductor layer 203 is greater than that between the first sub-layer 2021 and the third sub-layer 2023 and the second semiconductor layer 203, when forming the first trench, the second sub-layer 2022 and the third sub-layer 2023 are removed first to form the first sub-trench; then the first sub-layer 2021 and part of the second semiconductor layer 203 are removed to form the second sub-trench.

[0210] refer to Figures 7A to 10C Step S30 is executed to form a gate structure covering the second semiconductor layer in the first groove.

[0211] like Figure 7A , Figure 7B and Figure 7C As shown, an insulating material is deposited into a first groove to form a first insulating structure 209 that at least covers the second semiconductor layer 203, wherein the second semiconductor layer 203 is a portion of the second semiconductor layer 203 retained after a trimming operation. Exemplarily, the insulating material includes, but is not limited to, silicon oxide.

[0212] like Figure 8A , Figure 8B and Figure 8C As shown, an opening 210 is formed using a photolithography process, exposing a portion of the second semiconductor layer 203. Exemplarily, in... Figure 7A A patterned mask structure is formed on the first insulating structure 209 shown. The material of the mask structure includes at least one of photoresist (PR), spin-on hard mask (SOH), and silicon oxynitride (SiON). The mask structure can be a single-layer mask or a multi-layer composite mask, preferably a multi-layer composite mask. A portion of the first insulating structure 209 is removed using the patterned mask structure to form an opening 210. In some embodiments, a plasma etching process can be used to remove a portion of the first insulating structure 209. Exemplarily, a gas containing chlorine (Cl) or fluorine (F) is used as the etching source to remove a portion of the first insulating structure 209.

[0213] like Figure 9A , Figure 9B and Figure 9C As shown, a gate dielectric layer 212 and a gate electrode layer 211, covering the second semiconductor layer 203, are sequentially formed within the first groove. The gate dielectric layer 212 and the gate electrode layer 211 constitute a gate structure 213. In some embodiments, the material of the gate dielectric layer 212 can be an insulating material with a high dielectric constant (High-K, HK), such as a dielectric material with a dielectric constant K greater than or equal to 3.9. Examples include, but are not limited to, high-K materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2). The material of the gate electrode layer 211 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and nickel (Ni).

[0214] Reference 10A to Figure 11 Step S40 is executed to form the storage structure and bit lines.

[0215] like Figure 10A , Figure 10B and Figure 10C As shown, a second insulating structure 214 is formed to cover the gate structure 213.

[0216] The second insulating structure 214 is removed, exposing the two ends of the retained portion of the second semiconductor layer 203 that are opposite each other along the second direction. The source and drain of the transistor are formed at the two ends of the retained portion of the second semiconductor layer 203 that are opposite each other along the second direction, so that a channel layer is formed on the second semiconductor layer 203 of the transistor in the second direction X (i.e., the direction of the line connecting the source and drain).

[0217] It should be noted that, Figure 10B and Figure 10C The second insulating structure 214 in Figure 9B and Figure 9C The first insulating structure 209 in the middle is integrated into one.

[0218] like Figure 11 As shown, a memory structure 216 and a bit line 215 are formed at the first and second ends (source and drain) of the second semiconductor layer 203, which are opposite each other along the second direction. The bit line 215 extends along the first direction, and each bit line is connected to a transistor in a different layer. The memory structure 216 extends along the second direction and is stacked in a three-dimensional manner on the surface of the substrate 201. Stacking transistors and memory structures in a three-dimensional manner on the surface of the substrate 201 helps to increase the memory density of the semiconductor device. The sharing of bit lines between transistors in different layers helps to reduce the load and improve the performance of the semiconductor device. Furthermore, the gate structure 213 surrounds the channel layer (the reserved portion of the second semiconductor layer 203), which improves the gate structure's control over the channel.

[0219] The semiconductor device manufacturing method provided in this disclosure, by setting a first semiconductor layer as a first sub-layer and a second sub-layer with different etching selectivity ratios than the second semiconductor layer, allows for more precise removal of the first semiconductor layer while retaining the second semiconductor layer, thus optimizing the morphology of the retained second semiconductor layer and improving the reliability of the semiconductor device. Furthermore, the second sub-layer reduces lattice mismatch between the first and second semiconductor layers and also reduces the need for trimming the second semiconductor layer, avoiding over-etching and achieving more precise control over the channel layer thickness.

[0220] Fourthly, embodiments of this disclosure provide a semiconductor device, such as... Figure 11 As shown, the semiconductor device includes: a substrate 201; a memory array located on the substrate 201, the memory array including a plurality of memory cell layers stacked along a first direction perpendicular to the substrate 201, each memory cell layer including a plurality of memory cells arranged in an array, each memory cell including a transistor, the transistor including a channel layer (a reserved portion of the second semiconductor layer 203) extending along a second direction parallel to the substrate 201 and a gate structure 213 surrounding the channel layer.

[0221] In some embodiments, the gate structure 213 includes a gate dielectric layer 212 and a gate electrode layer 211.

[0222] In some embodiments, each gate structure surrounds a channel layer.

[0223] In some embodiments, the gate structure 213 surrounds a plurality of channel layers arranged in a third direction parallel to the substrate 201 in the same memory cell layer; wherein the second direction intersects with the third direction. Thus, the plurality of channel layers arranged in a third direction parallel to the substrate 201 share a gate structure, which is beneficial for reducing load and improving the performance of semiconductor devices.

[0224] In some embodiments, the semiconductor device further includes: a first epitaxial layer sequentially stacked along a first direction. Figure 11 (not shown in the image) and the second epitaxial layer ( Figure 11 (not shown in the image), located between the substrate and the memory array; wherein the growth temperature of the first epitaxial layer is lower than the growth temperature of the second epitaxial layer.

[0225] For example, the growth temperature of the first epitaxial layer is 200℃ to 450℃. The first epitaxial layer is used to release strain, which helps to reduce dislocations and defects in the semiconductor device and improve the performance of the semiconductor device. The growth temperature of the second epitaxial layer is 450℃ to 950℃, which helps to improve the carrier mobility of the semiconductor device.

[0226] In some embodiments, such as Figure 11 As shown, the semiconductor device further includes a memory structure 216 and a bit line 215. The memory structure 216 and the bit line 215 are respectively connected to a first end and a second end of the channel layer opposite to each other along the second direction. Each bit line 215 is connected to the second end of a plurality of channel layers arranged along the first direction. The sharing of bit lines by the channel layers of transistors of different layers is beneficial to reducing the load and improving the performance of the semiconductor device.

[0227] In some embodiments, the channel layer comprises at least one material element selected from Si, Ge, or Sn. Exemplarily, the channel layer is made of Si, Ge, or Ge 0.9 Sn 0.1 .

[0228] In some implementations, Ge or Ge 0.9 Sn 0.1 As a material for the channel layer, Ge and Ge2 can effectively improve the carrier mobility of the channel layer, thus significantly enhancing the performance of semiconductor devices. Furthermore, Ge2 and Ge2 are also important materials for this purpose. 0.9 Sn 0.1 Ge and Ge have the same crystal structure as Si, therefore Ge and Ge are used. 0.9 Sn 0.1 Materials used as channel layers have the advantage of being compatible with Si-based semiconductor device manufacturing platforms.

[0229] The semiconductor device provided in this disclosure has the same technical effect as the manufacturing method of the semiconductor device provided in this disclosure, and will not be described again here.

[0230] Based on the same inventive concept, this disclosure also provides an electronic device, which includes a semiconductor device prepared according to the manufacturing method of the semiconductor device provided in any of the above embodiments, or a semiconductor device provided in any of the above embodiments. The electronic device may be: a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0231] It should be understood that the phrases "some embodiments," "one embodiment," or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0232] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0233] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Alternating stacked first semiconductor layers and second semiconductor layers; The first semiconductor layer includes a first sublayer and a second sublayer; the first sublayer is located on opposite sides of the second sublayer along a first direction, the first direction being parallel to the stacking direction of the first semiconductor layer and the second semiconductor layer; the first etch selectivity between the first sublayer and the second semiconductor layer is different from the second etch selectivity between the second sublayer and the second semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that, The first etching selectivity is greater than the second etching selectivity.

3. The semiconductor structure according to claim 2, characterized in that, The first sublayer and the second sublayer contain the same material elements, but the proportion of the first element in the first sublayer and the second sublayer is different.

4. The semiconductor structure according to claim 3, characterized in that, In the direction from the first sublayer to the second semiconductor layer in contact with the first sublayer, the proportion of the first element in the first sublayer remains unchanged; the proportion of the first element in the first sublayer is greater than the proportion of the first element in the second sublayer.

5. The semiconductor structure according to claim 3, characterized in that, In the direction from the first sublayer to the second semiconductor layer in contact with the first sublayer, the proportion of the first element in the first sublayer increases; the minimum proportion of the first element in the first sublayer is greater than the proportion of the first element in the second sublayer.

6. The semiconductor structure according to any one of claims 3 to 5, characterized in that, Both the first sublayer and the second sublayer contain Si and Ge as material elements, with the first element being either Ge or Si.

7. The semiconductor structure according to claim 2, characterized in that, The first sublayer and the second sublayer contain different material elements.

8. The semiconductor structure according to claim 7, characterized in that, The first sublayer contains Si and Ge as material elements, and the second sublayer contains Si and B as material elements.

9. The semiconductor structure according to claim 7, characterized in that, The second sublayer contains the same material elements as the second semiconductor layer.

10. The semiconductor structure according to claim 9, characterized in that, The second semiconductor layer and the second sublayer are both made of Ge, and the first sublayer is made of Si and Ge. or, The second semiconductor layer and the second sublayer are both made of Si, and the first sublayer is made of Si and Ge.

11. The semiconductor structure according to claim 2, characterized in that, The dimension of the second sublayer along the first direction is smaller than the dimension of the second semiconductor layer along the first direction.

12. The semiconductor structure according to claim 1, characterized in that, The first etching selectivity is less than the second etching selectivity.

13. The semiconductor structure according to claim 12, characterized in that, The first sublayer contains the material elements Ge and Sn, and the second sublayer contains the material elements Ge and B.

14. The semiconductor structure according to claim 13, characterized in that, The first sublayer and the second semiconductor layer contain the same material elements; The proportion of the first element in the first sub-layer is greater than the proportion of the first element in the second semiconductor layer; the first element is Ge.

15. The semiconductor structure according to claim 2 or 12, characterized in that, The first semiconductor layer further includes: a third sublayer located between the first sublayer and the second sublayer; the magnitude of the third etch selectivity between the third sublayer and the second semiconductor layer is between the first etch selectivity and the second etch selectivity.

16. A method for manufacturing a semiconductor structure, characterized in that, The method includes: Several alternating stacked first semiconductor layers and second semiconductor layers are formed; The first semiconductor layer includes a first sublayer and a second sublayer; the first sublayer is located on opposite sides of the second sublayer along a first direction, the first direction being parallel to the stacking direction of the first semiconductor layer and the second semiconductor layer; the first etch selectivity between the first sublayer and the second semiconductor layer is different from the second etch selectivity between the second sublayer and the second semiconductor layer.

17. A method for manufacturing a semiconductor device, characterized in that, The method includes: A plurality of alternating first semiconductor layers and second semiconductor layers are formed; the first semiconductor layer includes a first sublayer and a second sublayer, the first sublayer being located on opposite sides of the second sublayer along a first direction, the first direction being parallel to the stacking direction of the first semiconductor layer and the second semiconductor layer; At least the first sub-layer and the second sub-layer are removed to form a first groove; wherein, the first etch selectivity ratio between the first sub-layer and the second semiconductor layer is different from the second etch selectivity ratio between the second sub-layer and the second semiconductor layer; A gate structure covering the second semiconductor layer is formed within the first groove; A memory structure and bit lines are formed, wherein the memory structure and the bit lines are respectively connected to the two ends of the second semiconductor layer opposite to each other along a second direction, the second direction being perpendicular to the first direction.

18. The manufacturing method according to claim 17, characterized in that, The first etching selectivity is greater than the second etching selectivity; the first groove includes a first sub-groove and a second sub-groove; the step of removing at least the first sub-layer and the second sub-layer to form the first groove includes: Remove the first sub-layer of the first semiconductor layer to form the first sub-groove; The second sub-layer and a portion of the second semiconductor layer are removed to form the second sub-groove.

19. The manufacturing method according to claim 17 or 18, characterized in that, The first sublayer and the second sublayer contain the same material elements, but the proportion of the first element in the first sublayer and the second sublayer is different.

20. The manufacturing method according to claim 19, characterized in that, In the direction from the first sublayer to the second semiconductor layer in contact with the first sublayer, the proportion of the first element in the first sublayer remains unchanged, while the proportion of the first element in the first sublayer is greater than the proportion of the first element in the second sublayer.

21. The manufacturing method according to claim 19, characterized in that, In the direction from the first sublayer to the second semiconductor layer in contact with the first sublayer, the proportion of the first element in the first sublayer increases, and the minimum proportion of the first element in the first sublayer is greater than the proportion of the first element in the second sublayer.

22. The manufacturing method according to claim 17, characterized in that, The first sublayer and the second sublayer contain different material elements.

23. The manufacturing method according to claim 22, characterized in that, The second sublayer contains the same material elements as the second semiconductor layer.

24. The manufacturing method according to claim 17, characterized in that, The dimension of the second sublayer along the first direction is smaller than the dimension of the second semiconductor layer along the first direction.

25. The manufacturing method according to claim 17, characterized in that, The first etching selectivity is less than the second etching selectivity; the first groove includes a first sub-groove and a second sub-groove; the step of removing at least the first sub-layer and the second sub-layer to form the first groove includes: Remove the second sub-layer of the first semiconductor layer to form the first sub-groove; The first sub-layer of the first semiconductor layer and a portion of the second semiconductor layer are removed to form the second sub-groove.

26. The manufacturing method according to claim 25, characterized in that, The first sublayer contains the material elements Ge and Sn, and the second sublayer contains the material elements Ge and B.

27. The manufacturing method according to claim 26, characterized in that, The first sublayer and the second semiconductor layer contain the same material elements; The proportion of the first element in the first sub-layer is greater than the proportion of the first element in the second semiconductor layer; the first element is Ge.

28. The manufacturing method according to claim 17, characterized in that, The method further includes: A first epitaxial layer and a second epitaxial layer are sequentially formed along the first direction; wherein the growth temperature of the first epitaxial layer is lower than the growth temperature of the second epitaxial layer; A plurality of alternating stacked first semiconductor layers and second semiconductor layers are formed on the second epitaxial layer.

29. The manufacturing method according to claim 17, characterized in that, Before at least the first sublayer and the second sublayer are removed to form the first groove, the method further includes: A portion of the first semiconductor layer and the second semiconductor layer are removed along the first direction, and a first trench is formed on both sides of the first semiconductor layer and the second semiconductor layer along the second direction; A support structure is formed in the first trench.

30. The manufacturing method according to claim 18 or 25, characterized in that, The first groove includes a second trench, a first sub-groove, and a second sub-groove; the step of removing at least the first sub-layer and the second sub-layer to form the first groove includes: A plurality of second trenches are formed that penetrate the first semiconductor layer and the second semiconductor layer along a first direction, the plurality of second trenches extending along the second direction and spaced apart along a third direction; The first sub-groove is formed based on the second groove; The second sub-groove is formed based on the second groove; Wherein, the third direction intersects the second direction and is perpendicular to the first direction.

31. A semiconductor device, characterized in that, include: Substrate; A memory array located on the substrate, the memory array comprising a plurality of memory cell layers stacked along a first direction perpendicular to the substrate, each memory cell layer comprising a plurality of memory cells arranged in an array; each memory cell comprising a transistor, the transistor comprising a channel layer extending along a second direction parallel to the substrate and a gate structure surrounding the channel layer.

32. The semiconductor device according to claim 31, characterized in that, The gate structure surrounds a plurality of channel layers arranged in a third direction parallel to the substrate in the same memory cell layer; wherein the second direction intersects with the third direction.

33. The semiconductor device according to claim 31, characterized in that, The semiconductor device further includes: A first epitaxial layer and a second epitaxial layer are sequentially stacked along the first direction and located between the substrate and the memory array; wherein the growth temperature of the first epitaxial layer is lower than the growth temperature of the second epitaxial layer.

34. The semiconductor device according to claim 31, characterized in that, The semiconductor device further includes: The storage structure and the bit line are respectively connected to a first end and a second end of the channel layer that are opposite to each other along a second direction. Each bitline is connected to the second end of a plurality of channel layers arranged along the first direction.

35. The semiconductor device according to claim 31, characterized in that, The channel layer contains at least one of the material elements selected from Si, Ge, or Sn.

36. An electronic device, characterized in that, This includes semiconductor devices manufactured by the method of manufacturing a semiconductor device according to any one of claims 17 to 30, or semiconductor devices according to any one of claims 31 to 35.

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