Manufacturing method of semiconductor structure

Abstract

One embodiment of the invention provides a manufacturing method of a semiconductor structure. A method includes: in a first device region and in a second device region: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; forming a sacrificial gate over the stack; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layer to form a plurality of slits; and depositing an interposer material over the bottom surface and in the slit; in the first device region: an anisotropic etch is performed on the interposer material positioned over the bottom surface; and in the first device region and in the second device region: performing an isotropic etch on the interposer material to remove the interposer material positioned over the bottom surface and laterally recess the interposer material in the slit.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor structure. Background Technology

[0002] The electronics industry has experienced a growing demand for increasingly smaller and faster electronic devices capable of simultaneously supporting a larger number of increasingly complex and sophisticated functions. Consequently, there is a persistent trend in the semiconductor industry to manufacture low-cost, high-efficiency, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down semiconductor IC dimensions (e.g., minimizing feature size) and thereby improving production efficiency and reducing associated costs. However, such scaling has also introduced increased complexity into semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies. Summary of the Invention

[0003] According to one embodiment of this disclosure, a method for manufacturing a semiconductor structure includes, in a first device region and a second device region: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; forming a sacrificial gate over the stack; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form a plurality of gaps; and depositing an interposer material over the bottom surface and in the gaps. In the first device region: anisotropic etching is performed on the interposer material positioned over the bottom surface. In both the first and second device regions: isotropic etching is performed on the interposer material to remove the interposer material positioned over the bottom surface and to laterally recess the interposer material in the gaps.

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor structure includes forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form a plurality of gaps; depositing an interposer material above the bottom surface and in the gaps; recessing the interposer material positioned above the bottom surface, wherein a remaining portion of the interposer material remains above the bottom surface; and performing isotropic etching on the interposer material to remove the remaining portion of the interposer material positioned above the bottom surface and to laterally recess the interposer material in the gaps.

[0005] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor structure includes forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; forming a plurality of sacrificial gates over the stack; etching the stack to form a plurality of cavities having a plurality of bottom surfaces; removing the first epitaxial layers to form a plurality of gaps; depositing an interposer material over the bottom surfaces and in the gaps; directionally etching the interposer material positioned over a plurality of selected bottom surfaces; and isotropically etching the interposer material to remove the interposer material positioned over the bottom surfaces and to laterally recess the interposer material in the gaps. Attached Figure Description

[0006] One embodiment of this disclosure is in conjunction with the accompanying documentation. Figure 1 The best way to understand this text is by referring to the detailed description below. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 The flowchart illustrates a method according to some embodiments;

[0008] Figures 2 to 6 This is a perspective view of the structure of a semiconductor device during a continuous manufacturing phase, according to some embodiments;

[0009] Figure 7 According to some embodiments Figure 6 Cross-sectional view of the structure of a semiconductor device;

[0010] Figure 8 A cross-sectional view of the structure of a semiconductor device according to some embodiments during a continuous manufacturing stage;

[0011] Figures 9 to 11 A perspective view of the structure of a semiconductor device according to some embodiments during a continuous manufacturing stage;

[0012] Figures 12 to 17 A cross-sectional view of the structure of a semiconductor device according to some embodiments during a continuous manufacturing stage;

[0013] Figures 18 to 19 A perspective view of the structure of a semiconductor device according to some embodiments at a selected manufacturing stage;

[0014] Figure 20 This is a cross-sectional view of the structure of a semiconductor device according to some embodiments at a selected manufacturing stage.

[0015] [Symbol Explanation]

[0016] 200: Substrate

[0017] 210: Bottom section / Countertop section

[0018] 212: Epitaxial Stacking

[0019] 213: Temporary gap

[0020] 214: Epitaxial layer

[0021] 215: Cavity

[0022] 216: Semiconductor layer / epitaxy layer

[0023] 217: Mask

[0024] 218: First mask layer

[0025] 219: Second masking layer

[0026] 220: Fins

[0027] 220a: Partial

[0028] 221: Isolation Features

[0029] 222: Sacrificial (dummy) gate structure

[0030] 223: Sacrificial gate dielectric

[0031] 224: Sacrificial gate electrode

[0032] 225: Mask

[0033] 226: Masking layer

[0034] 227: Masking layer

[0035] 230: Spacer

[0036] 231: Lining layer

[0037] 232: Main spacer layer

[0038] 233: Bottom cavity surface

[0039] 234: Cavity

[0040] 235: Fin section

[0041] 380: Metal gate

[0042] 382: Filler material

[0043] 400: Internal spacers

[0044] 440: Dielectric liner

[0045] 450: Dielectric

[0046] 499: Gate cavity

[0047] 500: Source / Drain Characteristics

[0048] 501: First Floor

[0049] 502: Second layer

[0050] 503: Third Floor

[0051] 511: Maximum vertical thickness

[0052] 600: Metal gate

[0053] 610: Dielectric layer or lining

[0054] 620: Filler material

[0055] 700: Intermediary layer

[0056] 710: Sidewall section

[0057] 711: Recessed upper surface

[0058] 720: Bottom section

[0059] 730: Intersection of Nanosheets

[0060] 731: Through the recessed surface

[0061] 732: Lateral concave portion

[0062] 800: Semiconductor device / structure

[0063] 801: Zone 1

[0064] 802: Second District

[0065] 811: OD width

[0066] 822: OD width

[0067] 831: First Thickness

[0068] 832: Second thickness

[0069] 850: Mask

[0070] 900: Method

[0071] 2161: Outer surface

[0072] S902: Operation

[0073] S904: Operation

[0074] S906: Operation

[0075] S908: Operation

[0076] S910: Operation

[0077] S912: Operation

[0078] S914: Operation

[0079] S916: Operation

[0080] S918: Operation

[0081] S919: Operation

[0082] S920: Operation

[0083] S921: Operation

[0084] S922: Operation

[0085] S924: Operation

[0086] S926: Operation

[0087] S928: Operation

[0088] S930: Operation

[0089] S932: Operation

[0090] S934: Operation

[0091] S936: Operation

[0092] S938: Operation Detailed Implementation

[0093] The following disclosure provides numerous different embodiments or instances for implementing various features of the subject matter. Specific examples of components and configurations are described below to simplify one implementation of this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. As used herein, “directly above” refers to the vertical alignment of features such that when the overlying feature is directly above the underlying feature, the vertical axis passes through both features. Furthermore, one implementation of this disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0094] Additionally, spatial relative terms such as “directly above,” “above,” “overlapping,” “upper,” “top,” “top,” “lower,” “subducting,” “below,” “below,” “under,” “bottom,” “side,” “positive slope,” and “negative slope,” and similar terms, may be used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0095] All figures indicating quantities, material ratios, physical properties of materials, and / or uses in this description should be understood as being modified by the word "about," unless otherwise expressly indicated. When modifying numerical values ​​in a specification or claim, "about" indicates a range of accuracy familiar and acceptable to those skilled in the art. Generally, this range of accuracy is ±10%. Therefore, "about ten" means nine to eleven.

[0096] In some embodiments herein, a “material layer” is a layer comprising at least 50 wt.% of the identified material, such as at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, or at least 99 wt.% of the identified material; and a layer that is “material” comprises at least 50 wt.% of the identified material, such as at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, or at least 99 wt.% of the identified material. For example, certain embodiments of a titanium nitride layer and a layer that is a titanium nitride layer are layers of at least 50 wt.%, at least 60 wt.%, at least 75 wt.% titanium nitride, or at least 90 wt.% titanium nitride, or at least 99 wt.% titanium nitride.

[0097] For the sake of brevity, well-known techniques for manufacturing semiconductor devices may not be described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more complex procedures or processes with additional functionality not described in detail herein. Specifically, the various processes in manufacturing semiconductor devices are well-known, and therefore, for the sake of brevity, many processes will be briefly mentioned herein or omitted entirely without providing well-known process details. As will be readily apparent to those skilled in the art, after a complete reading of one embodiment disclosed herein, the structures disclosed herein can be used with various techniques and incorporated into various semiconductor devices and products. Additionally, it should be noted that the semiconductor device structure includes a varying number of components, and a single component shown in the illustrations may represent multiple components.

[0098] Some embodiments described herein generally relate to multi-gate transistors. Multi-gate transistors include those transistors in which gate structures are formed on at least two sides of a channel region. These multi-gate devices may include p-type metal-oxide-semiconductor devices or n-type metal-oxide-semiconductor multi-gate devices. Specific examples may be shown and referred to herein as gate-all-around (GAA) devices. A GAA device includes any means in which a gate structure or a portion thereof is formed on all four sides of a channel region (e.g., surrounding a portion of the channel region).

[0099] Please note that although the figures and descriptions depict the structure of a gate all around (GAA) device, it is anticipated that the methods described herein can be used to facilitate other types of devices, and that the devices described herein may be of other types.

[0100] The structures presented herein also include embodiments having channel regions in the form of nanosheets. The term "nanosheet" refers to any material portion having a nanoscale or even micrometer-scale size and an elongated shape without regard to the cross-sectional shape of this portion. Thus, this term refers to elongated material portions with circular and substantially circular cross-sections, such as nanowires, and rod-shaped material portions including, for example, rods or rod-shaped material portions with cylindrical or substantially rectangular cross-sections.

[0101] In devices such as NSFET / GAAFET, achieving good top-to-bottom loading in the full-around gate (dummy gate replacement) is critical for device performance and yield. Controlling pattern loading in the full-around process is also important in systems-on-chip (SoC) with numerous devices. However, OD width (OD) loading issues can lead to residual discardable oxide in the full-around process. The oxide diffusion region, or OD region, or active region in a semiconductor device is the active region of each transistor. This is where the source, drain, and channel are formed below the transistor gate. OD exists between non-active regions, such as shallow trench isolation (STI) or field oxide (FOX) regions.

[0102] In an embodiment, a method is provided to remove residual discardable oxides in the source / drain region where source / drain features are formed, such as source / drain features.

[0103] Some embodiments provide the removal of more disposable oxide in the vertical direction compared to the lateral direction. For example, directional etching can be used to remove the bottom portion of the trench of disposable oxide or to make the bottom portion of the trench recessed, while the lateral surfaces of the nanosheet portion of the disposable oxide are not etched, or are etched only in a negligible amount in the lateral direction.

[0104] Some embodiments provide a mask in which the device has a large OD width, i.e., a semiconductor device region from 5 nm to 100 nm, while having a small OD width, i.e., a semiconductor device region from 2 nm to 30 nm, through directional etching to remove or recess the disposable oxide layer. In some embodiments, the large OD width is at least 2 nm larger than the small OD width.

[0105] See now Figure 1According to one embodiment of this disclosure, a method 900 for forming a structure such as a multi-gate device is illustrated in the flowchart. As used herein, the term "multi-gate device" is used to describe a device (e.g., a semiconductor transistor) having at least some gate materials disposed on multiple sides of at least one channel of the device. In some instances, a multi-gate device may be referred to as a GAA device, which has gate materials disposed on four sides of at least one channel component of the device. The channel component may be referred to as a "nanosheet".

[0106] Figure 1 Combination Figures 2 to 17 describe, Figures 2 to 17 The illustrations depict a semiconductor device 800 at various manufacturing stages according to some embodiments of this disclosure, illustrating method 900. Method 900 is merely an example and is not intended to limit one embodiment of this disclosure to anything beyond what is expressly described in the claims. Additional steps may be provided before, during, and after method 900, and some of the steps described above for additional embodiments of method 900 may be removed, replaced, or eliminated. Additional features may be added to the semiconductor device depicted in the figures, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device.

[0107] As with other method embodiments and exemplary devices discussed herein, it should be understood that portions of semiconductor device 800 can be manufactured using typical semiconductor technology processes, and therefore some processes are described only briefly herein. Additionally, exemplary semiconductor devices may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, but have been simplified for better understanding of the concepts of one embodiment of this disclosure. In some embodiments, exemplary devices include multiple semiconductor devices (e.g., transistors), including interconnectable PFETs, NFETs, etc. Furthermore, please note that, as with the remainder of the methods and exemplary figures provided in one embodiment of this disclosure, the process steps of method 900, including any descriptions given with reference to the figures, are merely illustrative and are not intended to limit the scope beyond what is specifically described in the following claims.

[0108] At operation S902, method 900 ( Figure 1 Provide substrate 200, such as Figure 2The illustration is shown in the figure. In some embodiments, substrate 200 may be a semiconductor substrate such as a silicon (Si) substrate. Substrate 200 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 200 may include various doping configurations according to design requirements known in the art. For example, different doping profiles (e.g., p-type wells, n-type wells) may be formed on substrate 200 in regions designed for different device types (e.g., n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs)). Suitable doping may include dopant ion implantation and / or diffusion processes, such as boron (B) for p-type wells and phosphorus (P) for n-type wells. In some embodiments, substrate 200 includes a single-crystal semiconductor layer at least on its surface portion. Substrate 200 may contain single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 200 may include compound semiconductors and / or alloy semiconductors. In the illustrated embodiment, substrate 200 is made of crystalline Si.

[0109] like Figure 2 As shown in the diagram, at operation S904, method 900 ( Figure 1 One or more epitaxial layers are formed over substrate 200. In some embodiments, an epitaxial stack 212 is formed over substrate 200. The epitaxial stack 212 includes an epitaxial layer 214 of a first composite into which an epitaxial layer 216 of a second composite is inserted. The first composite and the second composite may be different. Embodiments including those providing first and second composites with different oxidation rates and / or etch selectivity are possible. Thus, epitaxial layer 214 may be selectively removed to define semiconductor layer 216 as a nanosheet channel layer. In an embodiment, epitaxial layer 214 is SiGe and epitaxial layer 216 is silicon. In embodiments where epitaxial layer 214 comprises SiGe and epitaxial layer 216 comprises silicon, the silicon oxidation rate is less than the SiGe oxidation rate. Note that the three layers of epitaxial layer 214 and the three layers of epitaxial layer 216 are illustrated in the figure. Figure 2 middle, Figure 2 This is for illustrative purposes only and is not intended to be limited to anything beyond the scope of the claims. It will be understood that any number of epitaxial layers may be formed in the epitaxial stack 212; the number of layers depends on the desired number of channel regions of the GAA device 800. In some embodiments, the number of epitaxial layers 216 is between two and ten, such as six or seven.

[0110] In some embodiments, epitaxial layer 214 has a thickness ranging from about 5 nm to about 15 nm. The thickness of epitaxial layer 214 may be substantially uniform. In some embodiments, epitaxial layer 216 has a thickness ranging from about 5 nm to about 15 nm. In some embodiments, the stacked epitaxial layer 216 has a substantially uniform thickness. As described in more detail below, epitaxial layer 216 may serve as a channel region of a subsequently formed multi-gate device and has a thickness selected based on device performance considerations. Epitaxial layer 214 may be used to define gaps between adjacent channel regions of a subsequently formed multi-gate device and has a thickness selected based on device performance considerations.

[0111] By way of example, the epitaxial growth of the epitaxial stack 212 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) processes, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial layer 216 may comprise the same material as the substrate 200. In some embodiments, the epitaxial growth layers 214 and 216 comprise materials different from those of the substrate 200. As stated above, in at least some embodiments, the epitaxial layer 214 comprises epitaxially grown Si. 1-x Ge x The epitaxial layer 214 (where x is from 0.10 to 0.55, and epitaxial layer 216 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of epitaxial layers 214 and 216 may comprise other materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. As discussed above, the materials of epitaxial layers 214 and 216 may be selected based on providing different oxidation and etch selectivity properties. In various embodiments, epitaxial layers 214 and 216 are substantially doped (i.e., having a dopant range of 0 cm⁻¹). −3 Up to 1×10 17 cm −3 The intrinsic dopant concentration), wherein, for example, unintentional doping is not performed during the epitaxial growth process. In some embodiments, the bottom and top layers of the epitaxial stack 212 are SiGe layers (not shown). In an alternative embodiment, the bottom layer of the epitaxial stack 212 is a Si layer, and the top layer of the epitaxial stack 212 is a SiGe layer.

[0112] like Figure 3 As shown in the diagram, at operation S906, method 900 ( Figure 1Patterning the epitaxial stack 212 to form semiconductor fins 220. In some embodiments, operation S906 includes forming a mask 217 over the epitaxial stack 212, such as... Figure 2 As illustrated in the figure. Mask 217 includes a first mask layer 218 and a second mask layer 219. The exemplary first mask layer 218 is a pad oxide layer made of silicon oxide, which can be formed by thermal oxidation. The exemplary second mask layer 219 is made of silicon nitride (SiN) and can be formed by: chemical vapor deposition (CVD), including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD); physical vapor deposition (PVD); atomic layer deposition (ALD) or other suitable processes. Mask 217 is patterned into a mask pattern using patterning operations including optical lithography and etching.

[0113] like Figure 3 As illustrated, operation S906 then patterns the epitaxial stack 212 via openings defined in the patterned mask 217 in an etching process, such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. The stacked epitaxial layers 214 and 216 are thereby patterned into fins 220. Although Figure 3 The illustration shows the formation of one fin 220, but any suitable number of fins can be formed. Grooves are etched between adjacent fins 220.

[0114] In various embodiments, each fin 220 includes an upper portion of staggered epitaxial layers 214 and 216 and a bottom portion or mesa portion 210 formed from an etched substrate 200. Each fin 220 projects upward from the substrate 200 in the Z direction and extends longitudinally in the Y direction. The sidewalls of each fin 220 may be vertical or inclined (not shown). Figure 3 In the middle, the additional fins will be spaced apart along the X direction. Fins 220 may have the same width or different widths.

[0115] like Figure 4 As shown in the diagram, at operation S908, method 900 ( Figure 1An isolation feature (also referred to as a shallow trench isolation or STI feature) 221 is formed, wherein the dielectric layer is in a trench adjacent to each fin 220. The STI feature 221 can be formed by first filling the trench around each fin 220 with a dielectric material layer to cover the top surface and sidewalls (not shown) of the fin 220. The dielectric material layer may include one or more dielectric materials. Suitable dielectric materials for the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique including thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD, and / or spin coating. The dielectric material layer is then planarized using, for example, chemical mechanical planarization (CMP) until the top surface of the mask 217 is exposed, and the dielectric material layer is recessed to form a shallow trench isolation (STI) feature (also referred to as STI feature) 221, as shown. Figure 4 As illustrated in the figure. In the illustrated embodiment, STI feature 221 is formed on substrate 200. Any suitable etching technique, including dry etching, wet etching, RIE and / or other etching methods, can be used to recess the isolation feature 221, and in the exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation feature 221 without etching the fin 220. Mask 217 (illustrated in the figure) Figure 3 The mask 217 may also be removed before, during, and / or after recessing the isolation feature 221. In some embodiments, the mask 217 is removed by a CMP process performed before recessing the isolation feature 221. In some embodiments, the mask 217 is removed by an etchant used to recess the isolation feature 221.

[0116] like Figure 5 As shown in the diagram, at operation S910, method 900 ( Figure 1 A sacrificial (dummy) gate structure 222 is formed. The sacrificial gate structure 222 is formed above the portion of the fin 220 that will be the channel region. Specifically, the sacrificial gate structure 222 is located directly above and defines the channel region of the GAA device to be formed. The sacrificial gate structure 222 may extend above a plurality of adjacent fins (not shown). Each of the sacrificial gate structures 222 includes a sacrificial gate dielectric 223 and a sacrificial gate electrode 224 above the sacrificial gate dielectric 223. As illustrated, the gate structures 222 extend longitudinally in the X direction and are spaced apart in the Y direction.

[0117] The sacrificial gate structure 222 is formed by first blanket deposition of a sacrificial gate dielectric layer over fin 220. A sacrificial gate electrode layer is then blanket deposited over the sacrificial gate dielectric layer and over fin 220. The sacrificial gate dielectric layer comprises silicon oxide, silicon nitride, or a combination thereof. The thickness of the sacrificial gate electrode layer is in some embodiments ranging from about 100 to about 200 nm. The sacrificial gate electrode 224 comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate dielectric layer is in some embodiments ranging from about 1 to about 5 nm. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, PVD, ALD, or other suitable processes including LPCVD and PECVD. A mask 225 is formed over the sacrificial gate electrode layer. The mask 225 may include a mask layer 226 such as silicon oxide and a mask layer 227 such as silicon nitride. Subsequently, a patterning operation is performed on the mask 225, and the sacrificial gate electrode layer and the sacrificial gate dielectric layer are patterned into a sacrificial gate structure 222, including a sacrificial gate dielectric 223 and a sacrificial gate electrode 224.

[0118] As illustrated, fin 220 is partially exposed, that is, between the opposite sides of the sacrificial gate structure 222 and not covered by the overlying structure, thereby defining the source / drain (S / D) region. As used herein, "source / drain region" or "source / drain feature" may refer individually or collectively to the source or drain depending on the context.

[0119] See also Figure 5 At operation S912, method 900 ( Figure 1 Spacers 230 are formed on the sidewalls of the sacrificial gate structure 222 and the sidewalls of the fin 220 by depositing spacer material and then etching. Spacers 230 may include spacer materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, each of the spacers 230 includes multiple layers, such as a liner layer 231 and a primary spacer layer 232 above the liner layer 231.

[0120] By way of example, spacer 230 is formed over sacrificial gate structure 222 by depositing spacer layers comprising a liner material layer and a dielectric material layer using processes such as subatmospheric CVD (SACVD), flow CVD, ALD, PVD or other suitable processes.

[0121] like Figure 6 and Figure 7As illustrated, the deposited liner material layer and dielectric material layer are then subjected to an etch-back (e.g., anisotropic) process at operation S914 to expose and remove the portion 220a (e.g., source / drain region) of the fin 220 adjacent to the sacrificial gate structure 222 and not covered by the sacrificial gate structure 222. Specifically, method 900 ( Figure 1 The portion of fin 220 not covered by sacrificial gate structure 222 is recessed to form a slot, recess, or cavity 234 in the source / drain region. Note that... Figure 6 The diagram shows only one adjacent portion of the sacrificial gate structure 222 and the fin 220, such that... Figure 5 The etching of the S / D region between the sacrificial gate structure 222 can be viewed more clearly. Figure 7 For along Figure 6 The cross-sectional view taken from line 6-6 in the diagram is similar to... Figure 5 , Figure 7 The figure shows two sacrificial gate structures 222 and fins 220 adjacent to the two sacrificial gate structures 222.

[0122] The liner material layer and dielectric material layer may remain on the sidewalls of the sacrificial gate structure 222 as sidewall spacers 230, and also remain on the sidewalls of the fins as fin sidewall spacers 230. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The spacers 230 may have a thickness ranging from about 5 nm to about 20 nm.

[0123] like Figure 7 As most clearly illustrated, the upper portion of the fin 220 forming the stacked epitaxial layers 214 and 216 and the substrate 200 is etched downwards in the S / D region. Therefore, a bottom cavity surface 233 is formed in the fin 220. In some embodiments, operation S914 forms the cavity 234 by a suitable etching process, such as a dry etching process, a wet etching process, or a combination thereof. As a result of the etching process, the fin segments 235 of the upper portion of the fin 220 are defined and separated from each other by the cavity 234.

[0124] Figure 8 Provide in subsequent manufacturing stages and Figure 7 The same cross-sectional view. (e.g.) Figure 8 As shown in the diagram, at operation S916, method 900 ( Figure 1 The first epitaxial layer 214, such as the SiGe layer 214, is removed. Therefore, a temporary gap 213 is formed between the remaining second epitaxial layers 216. In an embodiment, layer 214 can be removed using a wet etching process that selectively removes the material of the first layer (e.g., silicon-germanium (SiGe)) without significantly removing the material of the second layer 216 (e.g., silicon (Si)). However, any suitable removal process can be used.

[0125] Figure 9 A perspective view of the lower portion of the device 800 at a subsequent manufacturing stage is provided. The mask 225 covering the sacrificial gate electrode 224 is not shown. Figure 9 As shown in the diagram, at operation S918, method 900 ( Figure 1 A discardable or sacrificial interposer material or layer 700 is formed above the structure of device 800. As illustrated, the interposer 700 is conformally deposited on the surface of the sidewall spacers 230, above the bottom cavity surface 233, and within the temporary gap 213. The interposer 700 may fill the temporary gap 213. The interposer 700 includes a sidewall portion 710, a bottom portion 720, and a nanosheet portion 730. Additionally, the interposer 700 may be formed above a mask (not shown) to cover the sacrificial gate electrode 224.

[0126] In some embodiments, the interposer 700 is an oxide material. For example, the interposer 700 may be silicon oxide. In some embodiments, the interposer 700 is formed by a refill process. In some embodiments, the interposer 700 is formed by a flow chemical vapor deposition (FCVD) process. In some embodiments, the interposer 700 comprises multiple layers formed to control the loading and / or shape of the layer 700. Additionally, in some embodiments, the interposer 700 is formed by an initial deposition process followed by a refill process, such as atomic layer deposition (ALD).

[0127] Figure 10 Provide in subsequent manufacturing stages and Figure 9 The same perspective. (e.g.) Figure 10 As shown in the diagram, at operation S920, method 900 ( Figure 1 This includes performing an etching process to recess the interposer layer 700.

[0128] In some embodiments, operation S920 includes performing anisotropic or directional etching processes, such as in the vertical direction, i.e., the Z-direction. For example, operation S920 may include performing a plasma etching process by using bias power for directional control. The anisotropic etching process may use a gaseous plasma, such as CF4+CHF3, C5F8, and / or C4F8 with added gases such as N2, Ar, and / or O2. The etching reactor used may be a parallel-plate type with or without commercially available magnetic field or electron cyclotron resonance (ECR) type enhancement. The process formulation may include a gas mixture of 400 watts RF power, 80 millitor pressure, and 10 sccm CF4 + 90 sccm CHF3 + 80 sccm Ar, wherein the etching time is approximately 15 seconds.

[0129] like Figure 10 As illustrated, the directional etching process allows the sidewall portion 710 to be recessed into the recessed upper surface 711. As shown, the recessed upper surface 711 of the sidewall portion 710 can be located above the substrate 200, i.e., at a greater height than the uppermost nanosheet portion 730, such as being located above the substrate 200, i.e., at a greater height than the uppermost nanosheet 216.

[0130] like Figure 10 The diagram further illustrates that the directional etching process can completely remove the bottom portion 720, leaving an interposer-free layer 700 on the bottom cavity surface 233. In other embodiments, after the directional etching process is performed, a residual portion of the bottom portion 720 may remain on the bottom cavity surface 233.

[0131] like Figure 10 As seen in the embodiments, the portion 730 between the nanosheets was not etched by a directional etching process.

[0132] Figure 11 Provide in subsequent manufacturing stages and Figure 10 The same perspective. (e.g.) Figure 11 As shown in the diagram, at operation S922, method 900 ( Figure 1 This includes performing an etching process to laterally recess the nanosheet portion 730 of the interlayer 700.

[0133] In some embodiments, operation S922 includes performing an isotropic etching or non-directional etching process. For example, operation S922 may include performing wet etching. In some embodiments, operation S922 includes performing a wet etching process using a diluted HF solution and / or an aqueous buffered HF solution. In some embodiments, the etchant is selected to exhibit high selectivity relative to removing substrate 200, nanosheet 216, or sidewall spacers 230 to remove interposer 700.

[0134] like Figure 11 As shown in the diagram, operation S922 can remove a portion of the sidewall portion 710. Additionally, if any remaining portion of the bottom portion 720 remains after operation S920, operation S922 can remove all remaining portions of the bottom portion 720.

[0135] In some embodiments, the vertical thickness of any residual portion of the bottom portion 720 remaining on the bottom cavity surface 233 after operation S922 is completed is less than 0.4 nm, such as less than 0.3 nm, less than 0.25 nm, less than 0.2 nm, less than 0.15 nm, less than 0.1 nm, or less than 0.5 nm.

[0136] As illustrated, operation S922 causes the inter-nanosheet portion 730 to be laterally recessed into the recessed surface 731. As illustrated, the recessed surface 731 is spaced apart in the X direction from the outer surface 2161 of the nanosheet 216. Therefore, the lateral recess 732 is formed below / above the nanosheet 216 and laterally adjacent to the recessed surface 731 of the inter-nanosheet portion 730.

[0137] Figure 12 Providing device 800 such as along with Figure 8 Cross-sectional views taken from the same cross-section during subsequent manufacturing stages. For example... Figure 12 As shown in the diagram, at operation S924, method 900 ( Figure 1 The laterally recessed nanosheet portion 730 adjacent to the interlayer 700 forms an internal spacer 400 in the lateral recess 732.

[0138] For example, operation S924 may include depositing an internal spacer material layer in the cavity 234 on the sidewall of the slit, including the recessed surface 731 of the inter-nanosheet portion 730, the end of the epitaxial layer 216, and on the top and bottom surfaces, and on the bottom cavity surface 233. The internal spacer material layer may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon carbonoxynitride, and / or other suitable dielectric materials. In some embodiments, the internal spacer material layer is deposited as a conformal layer. The internal spacer material layer may be formed by ALD or any other suitable method. The internal spacer material layer may have a thickness ranging from 1 to 5 nm, for example, 1 to 4 nm, 1 to 3 nm, or 1 to 2 nm.

[0139] Operation S924 may further include trimming the internal spacer material layer. The removal of the internal spacer material layer may be performed by an etching process, such as anisotropic etching, for example, a dry etching process. In some embodiments, the dry etching process uses an etchant including fluorine-containing gases (e.g., SF6, CF4, CHF3, CH2F2, and / or C2F6), chlorine-containing gases (e.g., Cl2), bromine-containing gases (e.g., HBr and / or CHBR3), oxygen-containing gases (e.g., O2), helium-containing gases (e.g., He), argon-containing gases (e.g., Ar), other suitable gases, or combinations thereof. In this etching, the internal spacer material layer remains substantially within the lateral recess 732.

[0140] Figure 13 Provide with in subsequent manufacturing stages Figure 12 The same cross-sectional view. (e.g.) Figure 13 As shown in the figure, method 900 ( Figure 1 The operation S926, which can form source / drain characteristics 500 in cavity 234, continues.

[0141] For example, operation S926 may include growing epitaxial material in cavity 234 to form source / drain feature 500. Note that source / drain feature 500 may be formed from subsequently formed layers. In an exemplary embodiment, source / drain feature 500 is a strained source / drain feature 500. Furthermore, source / drain feature 500 may be formed with layers selected for use in NFETs or PFETs. In an exemplary embodiment, source / drain feature 500 may include N-type epitaxial material source / drain features and P-type epitaxial material source / drain features. Epitaxial material may include one or more Si, SiP, SiC, and SiCP layers for N-type channel FETs, or one or more Si, SiGe, and Ge layers for P-type channel FETs. For P-type channel FETs, boron (B) may also be present in the source / drain. The source / drain epitaxial layers can be formed by epitaxial growth methods such as CVD, ALD, or molecular beam epitaxy (MBE).

[0142] Figure 14 Provide in subsequent manufacturing stages and Figure 13 The same cross-sectional view. (e.g.) Figure 14 As shown in the figure, method 900 ( Figure 1 The operation of S928 can continue by covering the source / drain feature 500 with dielectric material.

[0143] Specifically, a dielectric liner 440 may be formed over the source / drain feature 500 and along the sidewall spacer 230. Additionally, a dielectric 450 may be formed over the dielectric liner 440 over the source / drain feature 500. Specifically, the cavity 234 is filled with the dielectric 450. In an exemplary embodiment, the dielectric 450 is a first interlayer dielectric layer (ILD). The dielectric 450 may be silicon oxide or other suitable dielectric material. In some embodiments, the dielectric liner 440 is a dielectric, such as silicon nitride or another suitable material.

[0144] like Figure 14 As illustrated, structure 800 can be planarized, for example, by a chemical-mechanical planarization (CMP) process. Planarization removes the mask 225 and exposes the sacrificial gate electrode 224.

[0145] Method 900 ( Figure 1Operation S930 can be initiated to perform the process for activating the source / drain feature 500. In some embodiments, operation S930 may be a high-temperature annealing process. For example, a high-temperature annealing process may be performed at a temperature of at least 1000 degrees Celsius. In other embodiments, the process may be a low-temperature annealing process. For example, a low-temperature annealing process may be performed at a temperature of less than 1000 degrees Celsius. During the annealing process, the interposer 700 can prevent interdiffusion in the nanosheet layer 216. Specifically, the interposer 700 forms a barrier layer that resists the diffusion of impurities such as SiGe or Ge through vacancies in the nanosheet layer 216.

[0146] Figure 15 Provide in subsequent manufacturing stages and Figure 14 The same cross-sectional view. (e.g.) Figure 15 As shown in the figure, method 900 ( Figure 1 Operation S932 can continue by removing the sacrificial gate structure 222. As illustrated, the sacrificial gate electrode 224 is removed to form a gate cavity 499 between the sidewall spacers 230.

[0147] Figure 16 Provide in subsequent manufacturing stages and Figure 15 The same cross-sectional view. (e.g.) Figure 16 As shown in the figure, method 900 ( Figure 1 The operation S934 continues, which removes the inter-nanosheet portion 730 of the inter-nanosheet channel layer 700 between the nanosheet channel layers 216.

[0148] Removing the inter-nanosheet portion 730 creates a cavity 215 around the semiconductor layer 216. In some embodiments, operation S934 may include a wire release process to form vertically spaced nanosheets. The wire release process step may also be referred to as a sheet release process step, a sheet formation process step, a nanosheet formation process step, or a wire formation process step. In embodiments, the inter-nanosheet portion 730 may be removed using a wet etching process that selectively removes material from the inter-nanosheet portion 730 without significantly removing material from the second layer 216 (e.g., silicon (Si)). However, any suitable removal process may be used.

[0149] Figure 17 Provide in subsequent manufacturing stages and Figure 16 The same cross-sectional view. (e.g.) Figure 17 As shown in the figure, method 900 ( Figure 1 The operation S936, in which a metal gate 380 can be formed in the gate cavity 499, continues.

[0150] Specifically, method 900 may include lining the gate cavity 499 with a dielectric layer or liner 610. For example, a high-K gate dielectric liner 610 may be deposited on the sidewalls of the gate cavity 499 and around the nanosheet channel layer 216.

[0151] As used and described herein, high-k gate dielectrics include dielectric materials having a high dielectric constant, for example, greater than that of thermally heated silicon oxide (about 3.9). An exemplary high-k gate dielectric liner 610 may include a high-k dielectric material such as hafnium oxide (HfO2). Alternatively, the high-k gate dielectric liner 610 may include other high-k dielectric materials such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable materials. The high-k gate dielectric liner 610 can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation and / or other suitable methods.

[0152] The metal gate 600 is further filled with a filler material 620 to fill the gate cavity 499. The filler material 620 may comprise multiple layers of metal, metal alloy, or metal silicide. The filler material 620 may comprise a single layer or alternatively a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesive layer, a metal alloy, or various combinations of metal silicides. By way of example, the filler material 620 may comprise Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In various embodiments, the filler material 382 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Additionally, the filler material 382 may be formed separately for N-type and P-type transistors that may use different metal layers. Furthermore, the filler material 620 may provide an N-type or P-type work function, serving as a transistor gate electrode, and in at least some embodiments, the filler material 620 may include a polysilicon layer. In some instances, the filler material 620 may include selectively grown tungsten (W) and / or fluorine-free tungsten (FFW) layers.

[0153] like Figure 17As illustrated, a chemical mechanical planarization (CMP) process can be performed to remove the overloaded portions of the liner 610 and filler material 620 to define the metal gate 600 in the gate cavity 499.

[0154] like Figure 1 As indicated in the document, method 900 may further process, such as performing middle end of line (MEOL) processing and back end of line (BEOL) processing, and operation S938 continues.

[0155] Figure 1 and Figures 2 to 17 The illustrated method 900 ensures that all of the interposer 700 is removed from the bottom cavity surface 233 before the source / drain feature 500 is formed on the bottom cavity surface 233, or at least minimizes the amount of interposer 700 remaining on the bottom cavity surface 233. Therefore, the epitaxial growth of the material forming the source / drain feature 500 is improved.

[0156] Figure 18 Other embodiments of the illustrated execution method 900.

[0157] Figure 18 The diagram illustrates a first region 801 and a second region 802 of a device 800. Regions 801 and 802 are formed in different regions of the substrate 200. Although shown in vertical alignment in the figures, regions 801 and 802 are separated from each other in the X direction within the device 800. In the first region 801, the device 800 has a small active region or OD width 811 in the Y direction, i.e., an OD width 811 from 2 nm to 30 nm. In the second region 802, the device 800 has a large active region or OD width 822 in the Y direction, i.e., an OD width 822 from 5 nm to 100 nm. In some embodiments, the large OD width 822 is at least 2 nm larger than the small OD width 811.

[0158] Figure 18The diagram illustrates apparatus 800 after the formation of interposer 700 according to operation S918. Specifically, the deposition process is performed across apparatus 800, including apparatus regions 801 and 802. Due to the difference between OD widths 811 and 822, the bottom portion 720 is formed with different heights or vertical thicknesses. Specifically, the bottom portion 720 in region 801 has a first thickness 831, and the bottom portion 720 in region 802 has a second thickness 832. As illustrated, the first thickness 831 is greater than the second thickness 832. For example, the first thickness 831 may be at least 1 nm larger than the second thickness 832, such as at least 2 nm, at least 3 nm, at least 5 nm, at least 8 nm, or at least 10 nm larger than the second thickness 832.

[0159] Therefore, extensive etching is required to remove the bottom portion 720 in the first region 801.

[0160] During operation S920, directional etching is used to simultaneously recess the bottom portions 720 in regions 801 and 802. High-selectivity etching is used, such as by controlling C... x F y With the O2 ratio, the bottom portion of the over-etched area 802 can be avoided. Thereafter, method 900 can continue as described in operation S922 above.

[0161] Figure 19 Other embodiments of the illustrated execution method 900.

[0162] exist Figure 19 The diagram illustrates a first region 801 and a second region 802 of a device 800. Regions 801 and 802 are formed in different regions of a substrate 200. Although shown in vertical alignment in the figures, regions 801 and 802 are separated from each other in the X direction within the device 800. In the first region 801, the device 800 has a small active region or OD width 811, i.e., an OD width 811 from 2 nm to 30 nm. In the second region 802, the device 800 has a large active region or OD width 822, i.e., an OD width 822 from 5 nm to 100 nm. In some embodiments, the large OD width 822 is at least 2 nm larger than the small OD width 821.

[0163] Figure 19The diagram illustrates the apparatus 800 after the formation of the intermediate layer 700 according to operation S918. Specifically, the deposition process is performed across apparatus 800, including apparatus regions 801 and 802. Due to the difference between OD widths 811 and 822, the bottom portion 720 is formed with different heights or vertical thicknesses. Specifically, the bottom portion 720 in region 801 has a first thickness 831, and the bottom portion 720 in region 802 has a second thickness 832. As illustrated, the first thickness 831 is greater than the second thickness 832.

[0164] Therefore, extensive etching is required to remove the bottom portion 720 in the first region 801.

[0165] exist Figure 19 In one embodiment, prior to operation S920, a mask 850 is formed over device region 802 in operation S919 of method 900 as illustrated. The mask 850 may be formed of photoresist. Therefore, operation S920 may be performed with directional etching, which recesses the bottom portion 720 in region 801 but does not etch the bottom portion in region 802. In some embodiments, the bottom portion 720 in region 801 is recessed, and the first thickness 831 is reduced until the difference between thicknesses 831 and 832 is no greater than 0.5 nm. Specifically, the absolute value operation S920 may be performed until the absolute value of the first thickness 831 minus the second thickness 832 is less than or equal to 0.5 nm.

[0166] After performing operation S920, the mask can be removed in operation S921. Thereafter, method 900 can continue as described above in operation S922. By reducing the difference between thicknesses 831 and 832, the load is reduced during the isotropic etching in operation S922, and operation S922 can remove all the interposer layer 700 from the bottom cavity surface 233 without laterally etching too much of the inter-nanosheet portion 730, i.e., forming a disk shape.

[0167] Figure 20 The device 800 after the sacrificial gate has been removed is similar to the one shown in the illustration. Figure 15 The cross-sectional view is shown in the figure. As illustrated, the source / drain feature 500 comprises three distinct layers: a first layer 501, a second layer 502, and a third layer 503. The first layer 501 is grown directly on the bottom cavity surface 233.

[0168] The first layer 501, the second layer 502, and the third layer 503 can be formed from different materials. For example, layers 510, 502, and 503 can be silicon, silicon phosphide (SiP), silicon carbide, or silicon arsenide (SiAs). In some other embodiments, another pentavalent material can be used to form a silicon compound, such as antimony (Sb), bismuth (Bi), molybdenum (Mc), other pentavalent silicon compounds, or combinations thereof. Each layer 501, 502, and 503 can be formed by an epitaxial growth process. The epitaxial growth process can be an LPCVD process with silicon-based precursors, a selective epitaxial growth (SEG) process, a cyclic deposition and etching (CDE) process, other suitable processes, or combinations thereof. For example, silicon phosphide crystals can be formed by a chemical gas (Si3H8, SiH3CH3, and / or PH3) deposition process combined with a selective chemical vapor deposition (SCVD) process. In another example, silicon crystals can be grown via LLPCVD using dichlorosilane (SiH2Cl2) as a precursor. The precursor can be doped with n-type dopants, such as phosphorus (P) for the first layer 501 and the second layer 502, and arsenic (As) for the third layer 503, either in situ (during the epitaxial growth process) or externally (after the epitaxial growth process is completed), to form different epitaxial layers of the epitaxial S / D feature 500. In some embodiments, the different epitaxial layers of the epitaxial S / D feature 500 are doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the different layers of the epitaxial S / D feature 500 are doped by an ion implantation process after the deposition process. The implantation energy and dosage during the ion implantation process can be configured, depending on the design of the apparatus 800. For example, the first epitaxial layer 501 can be formed by ion implantation doping of the silicon precursor with a low concentration of P (e.g., the molar ratio of P is less than about 2%) to a thickness of about 1 nm to about 10 nm; the second epitaxial layer 502 can be formed by ion implantation doping of the silicon precursor with a higher concentration of P (e.g., the molar ratio of P is about 2% to about 10%) to a thickness of about 10 nm to about 40 nm; and the third epitaxial layer 503 can be formed by As (e.g., about 1 × 10⁻⁶ ppm). 22 Up to 1×10 23 atoms / cm 3 Arsenic (in some embodiments, about 2% to about 10% As) is formed by ion implantation doping of silicon precursor to a thickness of about 0.1 nm to about 20 nm.

[0169] like Figure 20 As shown in the figure, the first layer 501 has a maximum vertical thickness 511 from the lowest surface to the highest surface.

[0170] In this embodiment, where device 800 is simultaneously formed in device region 801 with a small OD width and device region 802 with a large OD width, and device region 802 is not masked (i.e., operation S919 is not performed), the maximum vertical thickness 511 of device 800 in region 801 is from 1 to 30 nm, and the maximum vertical thickness 511 of device 800 in region 802 is from 1 to 30 nm. Furthermore, in this type of embodiment, due to the high amount of oxide etched in region 802, the maximum vertical thickness 511 in region 802 is at least 0.2 nm greater than the maximum vertical thickness 511 in region 801.

[0171] These dimensions are achieved through an etching process that removes more oxides in device region 802 compared to device region 801.

[0172] In this embodiment, where device 800 is simultaneously formed in device region 801 with a small OD width and device region 802 with a large OD width, and device region 802 is masked (i.e., operation S919 is performed), the maximum vertical thickness 511 of device 800 in region 801 is from 1 to 30 nm, and the maximum vertical thickness 511 of device 800 in region 802 is from 1 to 30 nm. Furthermore, in this embodiment, the difference in maximum vertical thickness 511 between regions 801 and 802 is attributed to a selective region of no more than 0.5 nm provided by the selective etching of the thicker bottom portion 720 in region 801 while region 802 is masked.

[0173] In one embodiment, a method includes: in a first device region and in a second device region: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; forming a sacrificial gate over the stack; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form a plurality of slots; and depositing an interposer material over the bottom surface and in the slots; in the first device region: performing an anisotropic etching on the interposer material positioned over the bottom surface; and in the first device region and the second device region: performing an isotropic etching on the interposer material to remove the interposer material positioned over the bottom surface and to laterally recess the interposer material in the slots.

[0174] In some embodiments of the method, isotropic etching is performed to form a plurality of lateral recesses, and the method further includes: forming a plurality of internal spacers in the lateral recesses; forming a source / drain feature in the cavity; removing the sacrificial gate to form a gate cavity; and forming a metal gate in the gate cavity.

[0175] In some embodiments, the method further includes: masking the second device region with a mask before performing anisotropic etching; and removing the mask from the second device region before performing isotropic etching.

[0176] In some embodiments, the method further includes: forming a source / drain feature in the cavity, including a first epitaxial material layer formed on the bottom surface, wherein in a first device region, the first epitaxial material layer has a first thickness of 1 to 30 nm; in a second device region, the first epitaxial material layer has a second thickness of 1 to 30 nm; and a difference between the first thickness and the second thickness is at least 0.2 nm.

[0177] In some embodiments of the method, anisotropic etching of the interlayer material located above the bottom surface is performed in the second device region.

[0178] In some embodiments of the method, after depositing the interposer material, the interposer material above the bottom surface in the first device region has a first initial thickness, and the interposer material above the bottom surface in the second device region has a second initial thickness; a difference between the first initial thickness and the second initial thickness is at least 1 nm; after performing anisotropic etching on the interposer material positioned above the bottom surface, the interposer material above the bottom surface in the first device region has a first recessed thickness, and the interposer material above the bottom surface in the second device region has a second initial thickness; and a difference between the first recessed thickness and the second initial thickness is not greater than 0.5 nm.

[0179] In some embodiments, the method further includes: forming a source / drain feature in the cavity, including a first epitaxial material layer formed on the bottom surface, wherein in a first device region, the first epitaxial material layer has a first thickness of 1 to 30 nm; in a second device region, the first epitaxial material layer has a second thickness of 1 to 30 nm; and a difference between the first thickness and the second thickness is less than 0.5 nm.

[0180] In some embodiments of the method, depositing an intermediate layer material above the bottom surface and in the gap includes filling the gap with the intermediate layer material.

[0181] In some embodiments of the method, the interlayer material is silicon oxide.

[0182] In some embodiments of the method, a residual portion of the interposer material remains on the bottom surface after isotropic etching is performed, and wherein the residual portion has a vertical thickness of less than 0.2 nm.

[0183] In another embodiment, a method includes: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form a plurality of slots; depositing an interposer material above the bottom surface and in the slots; recessing the interposer material positioned above the bottom surface, wherein a remaining portion of the interposer material remains above the bottom surface; and performing an isotropic etching on the interposer material to remove the remaining portion of the interposer material positioned above the bottom surface and to laterally recess the interposer material in the slots.

[0184] In some embodiments of the method, isotropic etching is performed to form a plurality of lateral recesses, and the method further includes: forming a plurality of internal spacers in the lateral recesses; forming a source / drain feature in the cavity; and forming a metal gate adjacent to the source / drain feature.

[0185] In some embodiments of the method, depositing an intermediate layer material above the bottom surface and in the gap includes filling the gap with the intermediate layer material.

[0186] In some embodiments of the method, the interlayer material is silicon oxide.

[0187] In some embodiments of the method, a residual portion of the interposer material remains on the bottom surface after isotropic etching is performed, and wherein the residual portion has a vertical thickness of less than 0.2 nm.

[0188] In another embodiment, a method includes: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; forming a plurality of sacrificial gates over the stack; etching the stack to form a plurality of cavities having a plurality of bottom surfaces; removing the first epitaxial layers to form a plurality of slots; depositing an interposer material over the bottom surfaces and in the slots; directionally etching the interposer material positioned over a plurality of selected bottom surfaces; and isotropically etching the interposer material to remove the interposer material positioned over the bottom surfaces and to laterally recess the interposer material in the slots.

[0189] In some embodiments, the method further includes masking a plurality of non-selected bottom surfaces before directional etching of an interposer material positioned above the selected bottom surfaces; and exposing the non-selected bottom surfaces before isotropically etching the interposer material.

[0190] In some embodiments of the method, the method includes directional etching of an interposer material positioned above a plurality of non-selected bottom surfaces, while simultaneously directional etching of an interposer material positioned above a selected bottom surface.

[0191] In some embodiments, the method further includes forming a source / drain feature in the cavity, including a first epitaxial material layer formed on a bottom surface, wherein: the first epitaxial material layer has a first thickness of 1 to 30 nm above a plurality of selected bottom surfaces; the first epitaxial material layer has a second thickness of 1 to 30 nm above a plurality of non-selected bottom surfaces; and a difference between the first thickness and the second thickness is at least 0.2 nm.

[0192] In some embodiments, the method further includes: forming a source / drain feature in the cavity, including a first epitaxial material layer formed on a bottom surface, wherein: the first epitaxial material layer has a first thickness of 1 to 30 nm above a plurality of selected bottom surfaces; the first epitaxial material layer has a second thickness of 1 to 30 nm above a plurality of non-selected bottom surfaces; and a difference between the first thickness and the second thickness is not greater than 0.5 nm.

[0193] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of one embodiment of this disclosure. Those skilled in the art will understand that one embodiment of this disclosure can be easily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same benefits. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of one embodiment of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of one embodiment of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: In a first device area and in a second device area: A stack of multiple first epitaxial layers and multiple second epitaxial layers is formed; A sacrificial gate is formed above the stack; The stack is etched to form a cavity with a bottom surface; Remove the plurality of first epitaxial layers to form a plurality of gaps; as well as An intermediate layer material is deposited above the bottom surface and in the plurality of gaps; In the first device area: An anisotropic etching is performed on the intermediate layer material positioned above the bottom surface; as well as In the first device area and in the second device area: An isotropic etching is performed on the interposer material to remove the interposer material positioned above the bottom surface and to laterally recess the interposer material in the plurality of gaps.

2. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The isotropic etching step forms a plurality of lateral recesses, and the method further includes the following steps: Multiple internal spacers are formed in the plurality of lateral recesses; A source / drain feature is formed in this cavity; Remove the sacrificial gate to form a gate cavity; and A metal gate is formed in the gate cavity.

3. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, Further steps include: The second device area is shielded with a mask before performing the anisotropic etching; and The mask is removed from the second device area before performing the isotropic etching.

4. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The anisotropic etching of the intermediate layer material positioned above the bottom surface is performed in the second device region.

5. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The step of depositing the intermediary material above the bottom surface and in the plurality of gaps includes the following steps: filling the plurality of gaps with the intermediary material.

6. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: A stack of multiple first epitaxial layers and multiple second epitaxial layers is formed; The stack is etched to form a cavity with a bottom surface; Remove the plurality of first epitaxial layers to form a plurality of gaps; An intermediate layer material is deposited above the bottom surface and in the plurality of gaps; The intermediate layer material positioned above the bottom surface is recessed, wherein a remaining portion of the intermediate layer material remains above the bottom surface; as well as An isotropic etching is performed on the interposer material to remove the remaining portion of the interposer material positioned above the bottom surface and to cause the interposer material in the plurality of gaps to be laterally recessed.

7. The method for manufacturing a semiconductor structure as described in claim 6, characterized in that, The isotropic etching step forms a plurality of lateral recesses, and the method further includes the following steps: Multiple internal spacers are formed in the plurality of lateral recesses; A source / drain characteristic is formed in the cavity; and A metal gate is formed adjacent to this source / drain feature.

8. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: A stack of multiple first epitaxial layers and multiple second epitaxial layers is formed; Multiple sacrificial gates are formed above this stack; The stack is etched to form multiple cavities with multiple bottom surfaces; Remove the plurality of first epitaxial layers to form a plurality of gaps; An intermediate layer material is deposited above the plurality of bottom surfaces and in the plurality of gaps; The intermediate layer material is directionally etched onto multiple selected bottom surfaces; as well as The interposer material is etched isotropically to remove the interposer material positioned above the plurality of bottom surfaces and to cause the interposer material in the plurality of gaps to be laterally recessed.

9. The method for manufacturing a semiconductor structure as described in claim 8, characterized in that, Further steps include: Multiple non-selected bottom surfaces are masked before the intermediate layer material positioned above the multiple selected bottom surfaces is oriented and etched; and The plurality of non-selective bottom surfaces are exposed before isotropic etching of the interposer material.

10. The method for manufacturing a semiconductor structure as described in claim 8, characterized in that, The method includes the following steps: directional etching of the interposer material positioned above a plurality of non-selected bottom surfaces, and directional etching of the interposer material positioned above the plurality of selected bottom surfaces.

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