Semiconductor processing for facet suppression or capture in epitaxial growth

Abstract

The invention relates to semiconductor processing for facet suppression or capture in epitaxial growth. In an example, a device includes a semiconductor substrate, a pedestal dielectric stack over the substrate, and a BJT on the substrate. The susceptor dielectric stack includes nitrogen at an interface between a first sub-layer and a second sub-layer of the susceptor dielectric stack. An opening passes through the base dielectric stack to the substrate. The opening is at least partially defined by a retrograde sidewall that retrograde into the susceptor dielectric stack from away from the substrate to close to the substrate. At least a first portion of the BJT is located on an upper surface of the substrate and in the opening through the base dielectric stack. At least a second portion of the BJT is over the base dielectric stack.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to semiconductor processing for facet suppression or trapping in epitaxial growth. Background Technology

[0002] Integrated circuits may include bipolar junction transistors (BJTs). BJTs may be desired to meet high-performance and high-current drive requirements due to their high-gain characteristics. Scaling devices in integrated circuits to smaller nodes typically requires novel semiconductor processing methods to fabricate these devices. Furthermore, integrating BJTs with other devices can complicate the semiconductor processing. Summary of the Invention

[0003] The example described herein is a semiconductor device. The semiconductor device includes a semiconductor substrate, a base dielectric stack located above the semiconductor substrate, and a bipolar junction transistor (BJT) located on the semiconductor substrate. The base dielectric stack contains nitrogen at the interface between a first sublayer and a second sublayer of the base dielectric stack. An opening extends through the base dielectric stack to the semiconductor substrate. The opening is at least partially defined by retrograde sidewalls. The retrograde sidewalls extend retrogradely from away from the semiconductor substrate to near the semiconductor substrate into the base dielectric stack. At least a first portion of the BJT is located on the upper surface of the semiconductor substrate and in the opening through the base dielectric stack. At least a second portion of the BJT is further located above the base dielectric stack.

[0004] Another example is a method. A dielectric stack is formed. Forming the dielectric stack includes: forming a first oxide sublayer over a semiconductor substrate; depositing a sacrificial nitride sublayer over the first oxide sublayer; and an oxide sacrificial nitride sublayer. A second oxide sublayer is formed over the first oxide sublayer using the oxide sacrificial nitride sublayer. The dielectric stack is etched with an etchant. The etching of the dielectric stack forms an opening through the dielectric stack to the semiconductor substrate. The opening is at least partially defined by a reverse sidewall.

[0005] Another example is a method. Forming a dielectric stack. Forming a dielectric stack includes: forming a first dielectric layer over a semiconductor substrate; depositing a second dielectric layer over the first dielectric layer; and treating the second dielectric layer such that the lateral etch rate of the second dielectric layer to an etchant is less than the lateral etch rate of the first dielectric layer to the etchant. The second dielectric layer (e.g., the deposited layer) comprises nitrogen. An opening is formed through the dielectric stack. Forming the opening includes etching the dielectric stack using an etchant.

[0006] The foregoing summary provides a fairly broad overview of the various features of the examples disclosed herein in order to better understand the following detailed description. Various features and advantages of such examples will be described below. The described examples can be readily used as the basis for modifications or designs of other examples within the scope of the appended claims. Attached Figure Description

[0007] To understand the above features in detail, please refer to the following detailed description in conjunction with the accompanying drawings.

[0008] Figure 1A and 1B arrive Figure 37A and 37B This is a cross-sectional view of a semiconductor device in an intermediate manufacturing stage, based on some examples.

[0009] Figure 38A and 38B arrive Figure 44A and 44B This is a cross-sectional view of a semiconductor device in an intermediate manufacturing stage, based on some examples.

[0010] The drawings and accompanying detailed description are provided to help understand the features of the various examples and do not limit the scope of the appended claims. Examples illustrated in the drawings and described in the accompanying detailed description can be readily used as the basis for modifications or designs of other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to the same elements common in the drawings. The drawings are drawn to clearly illustrate the relevant elements or features, and are not necessarily drawn to scale. Detailed Implementation

[0011] Various features are described below with reference to diagrams. Other examples may include any arrangement that includes or excludes the described aspects or features. The illustrated examples may not possess all the aspects or advantages shown. The aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example, even if not so stated or explicitly described. Furthermore, the methods described herein may be described with a specific order of operations, but other methods according to other examples may be implemented with more or fewer operations in various other orders (e.g., different serial or parallel executions involving various operations).

[0012] This disclosure generally, but not exclusively, relates to semiconductor processing involving the epitaxial growth of semiconductor material, and more specifically, for some instances, to the semiconductor processing integration of bipolar junction transistors (BJTs). Some instances include semiconductor devices comprising BJTs located on a semiconductor substrate. A pedestal dielectric stack is located above the semiconductor substrate. The pedestal dielectric stack may contain nitrogen at the interface between a first sublayer and a second sublayer of the pedestal dielectric stack. An opening is formed through the pedestal dielectric stack to reach the semiconductor substrate and is at least partially defined by a reverse sidewall. At least a portion of the BJT is located on the semiconductor substrate and in the opening through the pedestal dielectric stack, and another portion of the BJT is located above the pedestal dielectric stack.

[0013] More broadly, a substrate dielectric stack is formed over a semiconductor substrate. The substrate dielectric stack has a gradient lateral etch rate to an etchant, wherein the lower portion (e.g., a lower sublayer) has a greater lateral etch rate to the etchant than the upper portion (e.g., an upper sublayer). For example, multiple dielectric layers may be formed over the semiconductor substrate with varying lateral etch rates. An opening is formed to extend through the substrate dielectric stack to the semiconductor substrate. The substrate dielectric stack is etched using an etchant to form the opening. The etchant laterally etches the lower portion faster than the upper portion, thereby forming a reverse sidewall defining at least a portion of the opening. Semiconductor material may then be epitaxially grown in the opening and on the semiconductor substrate. The reverse sidewall of the opening can remove a template effect that could lead to the formation of facets during epitaxial growth, and therefore, the reverse sidewall can suppress the formation of facets during epitaxial growth. Furthermore, the reverse sidewall may have a geometry configured to capture the facets formed during epitaxial growth, thereby suppressing further propagation of the facets during epitaxial growth after capture. By suppressing or trapping facets, the semiconductor material subsequently grown epitaxially can avoid having facets, which can improve the performance of devices (e.g., BJTs) formed with one or more epitaxial growth materials. Other benefits and advantages can be achieved.

[0014] The substrate dielectric stack can be formed using any dielectric material, for example, a dielectric material capable of achieving the lateral etch rate required to form the retrograde sidewalls. Specific examples described below implement oxide sublayers in the substrate dielectric stack used to form BJTs. As described subsequently, different oxide sublayers have different lateral etch rates to achieve the retrograde sidewalls. Different examples, particularly those implemented using different devices, may implement one or more different dielectric materials.

[0015] Various examples are then described. While a particular example may illustrate aspects of the features generally described above, examples may be incorporated into any combination of features generally described above (which are described in more detail in the examples below).

[0016] Figure 1A and 1B arrive Figure 37A and 37B These are corresponding cross-sectional views of semiconductor devices at intermediate manufacturing stages, based on some examples. The methods illustrated in these figures are formed... Figure 37A and 37B The semiconductor device 3700. As an example, a pFET with a lower rated operating voltage (e.g., having a lower threshold voltage) is formed in a pFET region (e.g., as illustrated subsequently by a thinner gate oxide layer), and an nFET with a higher rated operating voltage (e.g., having a higher threshold voltage) is formed in an nFET region (e.g., as illustrated subsequently by a thicker gate oxide layer). In other examples, the pFET with the higher rated operating voltage may alternatively or additionally be formed in the pFET region. In other examples, the nFET with the lower rated operating voltage may alternatively or additionally be formed in the nFET region.

[0017] refer to Figure 1A and 1B A semiconductor substrate 102 is provided. The semiconductor substrate 102 includes a BJT region 104, a first transition region 106, a second transition region 108, a p-type FET (pFET) region 110, and an n-type FET (nFET) region 112. The pFET region 110 and the nFET region 112 are together contained within a complementary field-effect transistor (CFET) region. In the following description and in the figures, some structures are formed in the first transition region 106. Although not stated and / or described, such structures may also be formed in the second transition region 108, such as in a mirror configuration relative to the structures formed in the first transition region 106. For brevity, further explicit descriptions of such structures in the second transition region 108 are omitted.

[0018] Semiconductor substrate 102 may be or comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate. Semiconductor substrate 102 may also comprise a support (or processing) substrate and an epitaxial layer epitaxially grown on the support substrate. In some examples, semiconductor substrate 102 is or comprises a silicon substrate (which may be separated from a bulk silicon wafer at the end of semiconductor processing). In other examples, semiconductor substrate 102 comprises a silicon substrate on which an epitaxial silicon layer is grown. Semiconductor substrate 102 is or comprises semiconductor materials, such as BJTs, pFETs, and nFETs (as described below), in which and / or on these devices are formed. In some examples, the semiconductor material is or comprises silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), the like, or combinations thereof. Semiconductor substrate 102 has an upper surface 120 in which devices (e.g., BJTs, pFETs, and nFETs) are formed. In the illustrated example, the semiconductor material of the semiconductor substrate 102 is p-type doped with a p-type dopant. In some examples, the semiconductor substrate 102 uses a p-type dopant with a concentration of 1 × 10⁻⁶. 14 cm -3 Up to 1×10 15 cm -3 p-type dopant (e.g., boron (B)) within the range can be p-type doped. Another dopant type and / or other doping concentrations may be implemented.

[0019] A first substrate oxide sublayer 122 is located above (e.g., above) the upper surface 120 of the semiconductor substrate 102, and a second substrate oxide sublayer 124 is located above (e.g., above) the first substrate oxide sublayer 122. Isolation structures 132 (including a first portion 132a and a second portion 132b), 134 (including a first portion 134a and a second portion 134b), 136, 138, and 140 are formed through the first substrate oxide sublayer 122 and the second substrate oxide sublayer 124 and are formed in the semiconductor substrate 102. In the illustrated example, isolation structures 132 to 140 are shallow trench isolation structures (STI) extending from the upper surface 120 of the semiconductor substrate 102 into the semiconductor substrate 102. As illustrated, isolation structures 132 to 140 also protrude above the upper surface 120 of the semiconductor substrate 102, and in other embodiments, isolation structures 132 to 140 may have a corresponding upper surface coplanar with and / or below the upper surface 120 of the semiconductor substrate 102. Isolation structures 132 to 140 may include, for example: a liner layer, such as comprising silicon oxide or silicon nitride, conformally along the surface of a corresponding trench in the semiconductor substrate 102; and a filling isolation material, such as silicon oxide, located above and on the liner layer.

[0020] A first substrate oxide sublayer 122 is formed on the upper surface of the semiconductor substrate 102. The first substrate oxide sublayer 122 is or comprises an oxide, such as silicon oxide, formed using a suitable formation or deposition process. In some examples, the first substrate oxide sublayer 122 is or comprises silicon oxide formed using in-situ vapor generation (ISSG) oxidation, thermal oxidation, another oxidation process, etc. A second substrate oxide sublayer 124 is formed on the first substrate oxide sublayer 122. The second substrate oxide sublayer 124 is or comprises an oxide, such as silicon oxide, formed using a suitable formation or deposition process. In some examples, the second substrate oxide sublayer 124 is or comprises silicon oxide formed by high-temperature oxide (HTO) low-pressure chemical vapor deposition (LPCVD), etc.

[0021] A hard mask layer may then be deposited over the second pedestal oxide sublayer 124. The hard mask layer may be any suitable material, such as silicon nitride, silicon oxynitride, etc., and may be deposited using any suitable deposition process, such as chemical vapor deposition (CVD). The hard mask layer may be patterned, for example, by using photolithography and etching processes (e.g., reactive ion etching (RIE)). Using the patterned hard mask layer as a mask, grooves or trenches may be etched through the first pedestal oxide sublayer 122 and the second pedestal oxide sublayer 124 and into the semiconductor substrate 102, for example, by RIE etching. A liner layer may then be conformally deposited in the grooves or trenches and over the patterned hard mask layer, for example, by plasma-enhanced CVD (PECVD), or (e.g., by an oxidation process) on the exposed surface of the grooves or trenches, and a filling isolation material may be deposited over the liner layer, for example, by high aspect ratio CVD (HAR-CVD), flowable CVD (FCVD), etc. Excess filler material and liner layer can be removed from above the hard mask layer using planarization processes such as chemical mechanical polishing (CMP). The hard mask layer can then be removed by selective etching, which can be a wet etching process. In other examples, isolation structures 132 to 140 can be field oxide structures, such as localized oxidation of silicon (LOCOS) structures, at the upper surface 120 of the semiconductor substrate 102, which can be formed using a LOCOS process. Isolation structures 132 to 140 can be further produced by further processing (e.g., by etching, oxidation, deposition, etc.), but not specifically described or illustrated.

[0022] An isolation structure 132 laterally defines an active region on the upper surface 120 of a semiconductor substrate 102, on which a BJT will be formed. The isolation structure 132 laterally surrounds or encloses the active region on the upper surface 120 of the semiconductor substrate 102, on which the BJT will be formed. As indicated below, the active portion of the BJT (e.g., a base layer) extends laterally beyond the active region on the upper surface 120 of the semiconductor substrate 102, and extends over a first portion 132a of the isolation structure 132. Furthermore, an isolation structure 134 defines the lateral boundary of the BJT region 104. The isolation structure 134 laterally surrounds or encloses the isolation structure 132, with a doped isolation or protective well between them, as described below.

[0023] Isolation structures 136 and 138 at least partially laterally define the active regions of the upper surface 120 of the semiconductor substrate 102, on which pFETs will be formed. The active regions on the upper surface 120 of the semiconductor substrate 102 where pFETs are formed define the lateral boundaries of the pFET region 110. Similarly, isolation structures 138 and 140 at least partially laterally define the active regions of the upper surface 120 of the semiconductor substrate 102, on which nFETs will be formed. The active regions on the upper surface 120 of the semiconductor substrate 102 where nFETs are formed define the lateral boundaries of the nFET region 112. The CFET region includes the pFET region 110 and the nFET region 112. The lateral outer boundaries of the pFET region 110 and / or the nFET region 112 (or other pFETs and / or nFET regions) define the lateral boundaries of the CFET region.

[0024] The first transition region 106 is defined as the lateral boundary from the BJT region 104 to the nearest lateral boundary of the CFET region (which, in the illustrated example, is the boundary of the pFET region 110). The first transition region 106 includes isolation structure 136 and a first portion 134a of isolation structure 134. As illustrated, a portion of the upper surface 120 of the semiconductor substrate 102 lies within the first transition region 106 between the first portion 134a of isolation structure 134 and isolation structure 136. In other embodiments, the first transition region 106 may have lateral isolation structures throughout the entire first transition region 106. The second transition region 108 is defined as the lateral boundary from the BJT region 104 to the nearest lateral boundary of another region (not illustrated). The second transition region 108 includes a second portion 134b of isolation structure 134. The second transition region 108 may be formed and / or constructed similarly to the first transition region 106.

[0025] refer to Figure 2A and 2BAn n-type doped well 202 is formed in the semiconductor substrate 102 within the pFET region 110. The n-type doped well 202 can be formed by masking (e.g., using photolithography through a photoresist) regions of the semiconductor substrate 102 where an n-type doped well would not form and by implanting an n-type dopant into the semiconductor substrate 102. The n-type doped well 202 extends from the upper surface 120 of the semiconductor substrate 102 to a certain depth within the semiconductor substrate 102 and is laterally located between the isolation structures 136 and 138 in the pFET region 110. The concentration of the n-type dopant in the n-type doped well 202 is greater than the concentration of the p-type dopant in the p-type doped semiconductor substrate 102. In some examples, the n-type doped well 202 uses a concentration of 1 × 10⁻⁶. 15 cm -3 Up to 1×10 17 cm -3 Doping with n-type dopants (e.g., phosphorus (P) or arsenic (As)) within the range. Another dopant and / or other doping concentrations may be implemented.

[0026] An n-type doped sub-collector diffusion region 204 is formed in the semiconductor substrate 102 within the BJT region 104 and laterally located between portions 132a and 132b of the isolation structure 132. The n-type doped sub-collector diffusion region 204 can be formed by masking (e.g., using photolithography with a photoresist) regions of the semiconductor substrate 102 that would not be doped and by implanting an n-type dopant into the semiconductor substrate 102. The n-type doped sub-collector diffusion region 204 extends from the upper surface 120 of the semiconductor substrate 102 to a certain depth within the semiconductor substrate 102 and laterally located between portions 132a and 132b of the isolation structure 132 within the BJT region 104. The concentration of the n-type doped sub-collector diffusion region 204 is greater than the concentration of the p-type dopant in the semiconductor substrate 102. In some examples, the n-type doped sub-collector diffusion region 204 uses a concentration of 1 × 10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 Doping with n-type dopant within the range. Another dopant and / or other doping concentrations may be implemented.

[0027] p-type doped wells 206 and 208 are formed in the semiconductor substrate 102. The p-type doped wells 206 and 208 can be formed by masking (e.g., using photolithography with a photoresist) regions of the semiconductor substrate 102 where p-type doped wells will not form and by implanting p-type dopants into the semiconductor substrate 102. The p-type doped well 206 extends from the upper surface 120 of the semiconductor substrate 102 to a certain depth within the semiconductor substrate 102 and is laterally located between isolation structures 132 and 134 in the BJT region 104. The p-type doped well 206 is an isolation ring or protective ring that laterally surrounds or encloses the active region where the BJT will be formed. The p-type doped well 208 extends from the upper surface 120 of the semiconductor substrate 102 to a depth within the semiconductor substrate 102 and is laterally located between isolation structures 138 and 140 in the nFET region 112. The concentration of p-type dopant in p-type doped wells 206 and 208 is greater than the concentration of p-type dopant in the p-type doped semiconductor substrate 102. In some examples, p-type doped wells 206 and 208 use p-type dopant with a concentration of 1×10⁻⁶. 15 cm -3 Up to 1×10 17 cm -3 Doping with p-type dopant within the range. Another dopant and / or other doping concentrations may be implemented.

[0028] Although the semiconductor substrate 102, n-type doped well 202, n-type doped subcollector diffusion region 204, and p-type doped wells 206, 208 are described herein as being doped with a certain dopant conductivity type, in other instances such components may be doped with the opposite conductivity type (e.g., n-type doping instead of p-type doping, and vice versa). Similarly, components subsequently described as being doped with a certain dopant conductivity type may in other instances be doped with the opposite conductivity type.

[0029] As detailed below, the first substrate oxide sublayer 122 and the second substrate oxide sublayer 124 form portions of a substrate oxide stack with gradient lateral etch rates. Within the substrate oxide stack, the corresponding lateral etch rate of the dielectric layer typically increases from the upper portion of the substrate oxide stack to the lower portion (e.g., from away from the upper surface 120 to near the upper surface 120). In examples where the first substrate oxide sublayer 122 and the second substrate oxide sublayer 124 are silicon oxides formed by ISSG oxidation and HTO LPCVD, respectively (as formed or deposited on the semiconductor substrate 102), the first substrate oxide sublayer 122 and the second substrate oxide sublayer 124 may have relatively low etch rates. However, implantation to form the n-type doped sub-collector diffusion region 204 and / or any other implantation of dopant into the semiconductor substrate laterally located between the first portion 132a and the second portion 132b of the isolation structure 132 may damage the first base oxide sublayer 122 and the second base oxide sublayer 124, which may increase the lateral etch rate of these sublayers. For example, one or more implantations may be high-dose implantations that damage the first base oxide sublayer 122 and the second base oxide sublayer 124, such that the lateral etch rate of the first base oxide sublayer 122 and the second base oxide sublayer 124 may be greater than that of the third base oxide sublayer 302 to be formed thereon as described below.

[0030] refer to Figure 3A and 3B A third substrate oxide sublayer 302 is formed over (e.g., on top of) the second substrate oxide sublayer 124 and the isolation structures 132 to 140, and a fourth substrate sacrificial nitride sublayer 304 is formed over (e.g., on top of) the third substrate oxide sublayer 302. The third substrate oxide sublayer 302 is or comprises an oxide, such as silicon oxide, deposited by any suitable deposition process. Generally, the lateral etch rate of the third substrate oxide sublayer 302 is less than the corresponding lateral etch rates of the first substrate oxide sublayer 122 and the second substrate oxide sublayer 124 (e.g., damaged by high-dose implantation). In some instances, the third substrate oxide sublayer 302 is silicon oxide (e.g., tetraethyl orthosilicate (TEOS) oxide) deposited by CVD. The fourth substrate sacrificial nitride sublayer 304 is or comprises a nitride, such as silicon nitride, deposited by any suitable deposition process. In some instances, the fourth pedestal sacrificial nitride sublayer 304 is or contains silicon nitride deposited by CVD, atomic layer deposition (ALD), or the like.

[0031] refer to Figure 4A and 4BThe base sublayers 304, 302, 124, and 122 are removed from the upper surface 120 of the semiconductor substrate 102 in the nFET region 112, such that the fourth base sacrificial nitride sublayer 304a, the third base oxide sublayer 302a, the second base oxide sublayer 124a, and the first base oxide sublayer 122a remain in the other regions 104 to 110. In the illustrated example, portions of the base sublayers 304, 302, 124, and 122 are removed using appropriate photolithography and etching processes. A photoresist 402 is deposited (e.g., by spin coating) over the fourth base sacrificial nitride sublayer 304 and patterned using photolithography. The photoresist 402 is patterned to remain in the regions 104 to 110 where the base sublayers 304, 302, 124, and 122 will remain, and has openings that expose the portions of the layers in the nFET region 112 that will be removed. Using patterned photoresist 402 as a mask, an etching process, such as anisotropic etching similar to RIE, is performed to remove the exposed portions of the substrate sublayers 304, 302, 124, and 122, and to pattern the substrate sublayers 304a, 302a, 124a, and 122a. After the etching process, the photoresist 402 is removed, for example, by ashing.

[0032] refer to Figure 5A and 5B A gate oxide layer 502 is formed over (e.g., on) the upper surface 120 of the semiconductor substrate 102 in the nFET region 112. An oxidation process is used to form the gate oxide layer 502. Therefore, in some instances, the gate oxide layer 502 may be an oxide, such as silicon oxide, and may be formed using ISSG oxidation or another oxidation process.

[0033] The oxidation process for forming the gate oxide layer 502 oxidizes at least the upper portion 504 of the fourth base sacrificial nitride sublayer 304a to form a fourth base partially oxidized sacrificial nitride sublayer 304b. The oxidation process allows oxygen free radicals to react with the fourth base sacrificial nitride sublayer 304a, which degasses nitrogen from the fourth base sacrificial nitride sublayer 304a to form the fourth base partially oxidized sacrificial nitride sublayer 304b.

[0034] refer to Figure 6A and 6BThe base sublayers 304b, 302a, 124a, and 122a are removed from the upper surface 120 of the semiconductor substrate 102 in a portion of the pFET region 110 and the first transition region 106, such that the fourth base portion of the sacrificial nitride oxide sublayer 304c (containing the oxidized upper portion 504a), the third base oxide sublayer 302b, the second base oxide sublayer 124b, and the first base oxide sublayer 122b remain in portions of the BJT region 104 and the transition regions 106 and 108. In the illustrated example, portions of the base sublayers 304b, 302a, 124a, and 122a are removed using appropriate photolithography and etching processes. A photoresist 602 is deposited (e.g., by spin coating) over the fourth base portion of the sacrificial nitride oxide sublayer 304b and patterned using photolithography. Photoresist 602 is patterned to remain in regions 104 to 108 where base sublayers 304b, 302a, 124a, and 122a will be retained, and has openings exposing the portions of the layers to be removed in the pFET region 110 and the first transition region 106. Using the patterned photoresist 602 as a mask, an etching process, such as anisotropic etching similar to RIE, is performed to remove the exposed portions of base sublayers 304b, 302a, 124a, and 122a, and to pattern the fourth base portion of the sacrificial nitride oxide sublayer 304c, the third base oxide sublayer 302b, the second base oxide sublayer 124b, and the first base oxide sublayer 122b. After the etching process, the photoresist 602 is removed, for example, by ashing.

[0035] refer to Figure 7A and 7B A gate oxide layer 702 is formed over (e.g., on) the upper surface 120 of the semiconductor substrate 102 in the pFET region 110. An oxidation process is used to form the gate oxide layer 702. Therefore, in some instances, the gate oxide layer 702 may be an oxide, such as silicon oxide, and may be formed using ISSG oxidation or another oxidation process. Furthermore, the oxidation process further oxidizes the gate oxide layer 502 to form a gate oxide layer 502a. Therefore, the thickness of the gate oxide layer 502a may be greater than the thickness of the gate oxide layer 702. Additionally, the oxidation process may form an oxide layer 704 on the upper surface 120 of the semiconductor substrate 102, which is exposed in the first transition region 106.

[0036] The oxidation process forming the gate oxide layer 702 further oxidizes the fourth base partially oxidized sacrificial nitride sublayer 304c to form the fourth base oxide sublayer 304d. The oxidation process allows oxygen radicals to react with the fourth base partially oxidized sacrificial nitride sublayer 304c, which degasses nitrogen from the fourth base partially oxidized sacrificial nitride sublayer 304c to form the fourth base oxide sublayer 304d. Although the fourth base oxide sublayer 304d is described as an oxide layer after the oxidation process, in other instances, it may be a partially oxidized nitride layer (e.g., one or more oxidation processes do not completely oxidize the fourth base sacrificial nitride sublayer 304). In such instances, some nitrogen may remain in the fourth base oxide sublayer 304d at the interface between the third base oxide sublayer 302b and the fourth base oxide sublayer 304d.

[0037] In some instances, one or more oxidation processes do not penetrate the fourth substrate sacrificial nitride sublayer 304 to oxidize the third substrate oxide sublayer 302b, but in other instances, one or more oxidation processes may oxidize at least a portion of the third substrate oxide sublayer 302b. Oxidizing the third substrate oxide sublayer 302b may increase the density of the third substrate oxide sublayer 302b (e.g., in at least the upper portion of the third substrate oxide sublayer 302b) and reduce the etch rate of the third substrate oxide sublayer 302b. Therefore, according to some instances, it may be selected such as in Figure 3A and 3B The thickness of the fourth base sacrificial nitride sublayer 304 deposited in the middle is to avoid or reduce the oxidation of the third base oxide sublayer 302b by one or more oxidation processes of the fourth base sacrificial nitride sublayer 304.

[0038] In some instances, additional gate oxide layers of different thicknesses can be formed in different regions to form pFETs and / or nFETs with different rated operating voltages (e.g., in high-voltage, medium-voltage, or low-voltage applications). In such instances, this can be achieved by extending the... Figure 4A and 4B arrive Figure 7A and 7B The described process is used to perform an iterative process for the upper surface 120 of the oxidized semiconductor substrate 102.

[0039] refer to Figure 8A and 8BA gate layer 802 is formed over a semiconductor substrate 102, and a dielectric protective layer 804 is formed over the gate layer 802. The gate layer 802 is formed over (e.g., on) gate oxide layers 502a, 702, oxide layer 704, isolation structures 136 to 140, and a fourth pedestal oxide sublayer 304d. In some instances, the gate layer 802 is or contains a semiconductor material, such as polycrystalline silicon, and can be formed by any deposition process, such as CVD. In some instances, the semiconductor material can be in-situ doped during deposition and / or implanted with dopant after deposition. For example, the gate layer 802 can be in-situ doped with p-type dopant during deposition, and after deposition, a portion of the gate layer 802 can be implanted with n-type dopant at a higher concentration than the p-type dopant, while another portion of the gate layer 802 is masked (e.g., by photoresist formed by photolithography). In some instances, the gate layer 802 in BJT region 104, transition region 106, 108, and pFET region 110 is deposited and / or implanted with a concentration of 1×10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 The p-type doped polysilicon within the range, the gate layer 802 in the nFET region 112 is doped with a concentration of 5 × 10⁻⁶ after implantation. 19 cm -3 Up to 5×10 21 cm -3 The polysilicon is doped with n-type dopant within the range. Other materials (e.g., conductive materials) may be implemented as gate layer 802, which may be formed by any deposition process. In some instances, dielectric protective layer 804 is silicon oxide (e.g., TEOS oxide) deposited by CVD, but in other instances, other dielectric materials and / or other deposition processes may be used.

[0040] refer to Figure 9A and 9BThe dielectric protective layer 804 and the gate layer 802 are etched to form an opening 902 extending through the dielectric protective layer 804a and the gate layer 802a to the fourth base oxide sublayer 304d. The opening 902 is located in the BJT region 104 and the transition regions 106, 108. The formation of the opening 902 removes the dielectric protective layer 804 and the gate layer 802 from the BJT region 104. The opening 902 is at least partially defined by the sidewall 904 of the gate layer 802a (and further defined by corresponding sidewalls of the dielectric protective layer 804a not indicated by reference numerals). The sidewall 904 of the gate layer 802a is located above the fourth base oxide sublayer 304d in the first transition region 106. Although not shown, another sidewall of the gate layer 802a may be located above the fourth base oxide sublayer 304d in the second transition region 108. As will be shown later, the BJT is formed through an opening 902 that passes through the gate layer 802a.

[0041] In the illustrated example, appropriate photolithography and etching processes are used to pattern the dielectric protective layer 804 and the gate layer 802. A photoresist 912 is deposited (e.g., by spin coating) over the dielectric protective layer 804 and patterned using photolithography. The photoresist 912 is patterned to remain in the regions where the dielectric protective layer 804 and the gate layer 802 will be retained, and has openings corresponding to the openings 902. Using the patterned photoresist 912 as a mask, an etching process, such as anisotropic etching similar to RIE, is performed to remove portions of the dielectric protective layer 804 and the gate layer 802 and pattern the dielectric protective layer 804a and the gate layer 802a. Figure 9A and 9B The indicated sidewalls (including sidewall 904) of the gate layer 802a are disposed within the transition regions (including transition regions 106, 108) surrounding the BJT region 104. The photoresist 912 is removed, for example, by ashing, after an etching process.

[0042] refer to Figure 10A and 10B A hard mask layer 1002 is conformally formed over the fourth substrate oxide sublayer 304d and the gate layer 802a. The hard mask layer 1002 is formed on the sidewall 904 of the gate layer 802a in the first transition region 106. In some instances, the hard mask layer 1002 is or contains silicon nitride deposited by CVD, but in other instances, other hard mask (e.g., dielectric) materials and / or other deposition processes may be used.

[0043] refer to Figure 11A and 11BThe hard mask layer 1002 and the base oxide sublayers 304d, 302b, 124b, and 122b are etched to form a collector groove 1102 that extends through the hard mask layer 1002a, the fourth base oxide sublayer 304e, the third base oxide sublayer 302c, and the second base oxide sublayer 124c to reach and / or enter the first base oxide sublayer 122c. The collector groove 1102 is laterally formed in the BJT region 104 above the n-type doped sub-collector diffusion region 204 between the first portion 132a and the second portion 132b of the isolation structure 132. In the illustrated example, the collector groove 1102 is formed using appropriate photolithography and etching processes. A photoresist 1012 (e.g., a three-layer photoresist structure) is deposited (e.g., by spin coating) on ​​or above the hard mask layer 1002 and patterned using photolithography. The photoresist 1012 is patterned to have openings corresponding to the collector recess 1102. Using the patterned photoresist 1012 as a mask, an etching process, such as anisotropic etching similar to RIE, is performed to etch the hard mask layer 1002 and the substrate oxide sublayers 304d, 302b, 124b, and 122b. After the etching process, the photoresist 1012 is removed, for example, by ashing. A portion of the first substrate oxide sublayer 122c may remain below the collector recess 1102 above the upper surface 120 of the semiconductor substrate 102. In some embodiments, the collector recess 1102 may be an opening exposing the upper surface 120 of the semiconductor substrate 102.

[0044] refer to Figure 12A and 12BAn etching process including a lateral etching component is performed, wherein the lateral etching component etches the base oxide sublayers 304e, 302c, 124c, and 122c at the collector recess 1102, and forms a collector opening 1102a through the fourth base oxide sublayer 304f, the third base oxide sublayer 302d, the second base oxide sublayer 124d, and the first base oxide sublayer 122d. The etching process can be an isotropic etching process, such as a wet etching process. In an example where the base oxide sublayers 304e, 302c, 124c, and 122c are silicon oxide, the etching process includes etching using hydrofluoric acid (HF). For example, the etching process can use diluted hydrofluoric acid (dHF), buffered oxide etch (BOE), etc. The etching process etches through the first substrate oxide sublayer 122c to expose the upper surface 120 of the semiconductor substrate 102 through the collector opening 1102a, and laterally etches the substrate oxide sublayers 304e, 302c, 124c, and 122c to form a retrograde sidewall 1202 in the substrate oxide sublayers 304f, 302d, 124d, and 122d that at least partially defines the collector opening 1102a. Each retrograde sidewall 1202 runs retrogradely from a distance away from the upper surface 120 of the semiconductor substrate 102 toward the upper surface 120 into the substrate oxide sublayers 304f, 302d, 124d, and 122d. The collector opening 1102a is generally close to (or a certain lateral distance from) the first portion 132a of the isolation structure 132 in the BJT region 104 and is located above the n-type doped sub-collector diffusion region 204.

[0045] Due to the different lateral etch rates of the etchant in the etching process to the substrate oxide sublayers 304e, 302c, 124c, and 122c, the reverse sidewall 1202 can be formed. In some instances, the corresponding lateral etch rates of the first substrate oxide sublayer 122c and the second substrate oxide sublayer 124c to the etchant are greater than the lateral etch rate of the third substrate oxide sublayer 302c to the etchant, and the etch rate of the third substrate oxide sublayer 302c to the etchant is greater than the lateral etch rate of the fourth substrate oxide sublayer 304e to the etchant. In some instances, such as the first substrate oxide sublayer 122 initially formed on the semiconductor substrate 102, which may be high-density silicon oxide formed by an oxidation process, which may have a low lateral etch rate to the etchant, and such as the second substrate oxide sublayer 124 initially deposited above the semiconductor substrate 102, which may be high-density silicon oxide deposited by HTO-LPCVD, which may also have a low lateral etch rate to the etchant. However, in such instances, subsequent implantation (e.g., high-dose implantation) may damage the first base oxide sublayer 122 and the second base oxide sublayer 124, causing the first base oxide sublayer 122 and the second base oxide sublayer 124 to... Figure 12A The etchant used in the etching process has a high lateral etch rate. Therefore, during the etching process, the first and second base oxide sublayers 122c and 124c can be etched laterally from the sidewalls of the collector recess 1102 more than the third and fourth base oxide sublayers 302c and 304e, respectively, and the third base oxide sublayer 302c can be etched laterally from the sidewalls of the collector recess 1102 more than the fourth base oxide sublayer 304e. The lower lateral etch rate of the fourth base oxide sublayer 304e allows the lateral width and / or length of the collector opening 1102a at the fourth base oxide sublayer 304e to be approximately equal to the corresponding lateral width and / or length of the collector recess 1102.

[0046] In some instances, forming the reverse sidewall 1202 removes the template effect, thereby suppressing facet formation during subsequent epitaxial growth in the collector opening 1102a. In some instances, the upper surface 120 is a single-crystal surface with a (001) or (100) surface orientation, and the reverse sidewall 1202 has a (110) surface orientation. In this case, with the vertical sidewall, the template effect can cause facets with a (111) surface orientation to form during subsequent epitaxial growth in the collector opening. With the reverse sidewall 1202, the template effect can be removed, and the formation of such facets can be suppressed.

[0047] In some instances, the retrograde sidewall 1202 can trap a facet formed during subsequent epitaxial growth in the collector opening 1102a. Any portion of the retrograde sidewall 1202 can have a geometry that traps the facet. For such portions, the ratio of the vertical dimension from the lower retrograde portion to the upper overhang portion to the lateral dimension from the lower retrograde portion to the upper retrograde portion allows the facet to be trapped. For example, as illustrated, the retrograde sidewall 1202 has a vertical dimension 1212 from the lower retrograde portion (e.g., the lower point in the retrograde sidewall 1202) to the upper overhang portion (e.g., the upper point in the retrograde sidewall 1202 relative to the lower point) and a lateral dimension 1214 from the lower retrograde portion to the upper retrograde portion. The vertical dimension 1212 is orthogonal to the upper surface 120 of the semiconductor substrate 102, and the lateral dimension 1214 is parallel to the upper surface 120 of the semiconductor substrate 102. The vertical dimension 1212 and the lateral dimension 1214 form an angle 1218 between the upper surface 120 of the semiconductor substrate 102 and the line from the lower reverse portion to the upper overhang portion. Angle 1218 is laterally located inside the collector opening 1102a. Angle 1218 is the arctangent of the ratio of the vertical dimension 1212 to the lateral dimension 1214 (e.g., ...). ,in The angle is 1218. The vertical dimension is 1212, and (The lateral dimension is 1214). In some instances, the lateral dimension 1214 is equal to or greater than 10 nm, such as equal to or greater than 20 nm.

[0048] Angle 1218 (and therefore the ratio of vertical dimension 1212 to lateral dimension 1214) causes the facets formed in subsequent epitaxial growth to be captured by the reverse sidewall 1202. For example, when the upper surface 120 is a (001) or (100) plane of monocrystalline silicon, and silicon is epitaxially grown on the upper surface 120, the epitaxially grown silicon may have facets with a (111) surface orientation. In such examples, angle 1218 may be equal to or less than 54.7° (e.g., equal to or less than 54°). Correspondingly, the ratio of vertical dimension 1212 to lateral dimension 1214 may be equal to or less than 1.376. In the case of this angle 1218, the facets with a (111) surface orientation may intersect with the reverse sidewall 1202 when the silicon grows to a sufficient thickness, which may cause the propagation of the facets to be terminated in subsequent epitaxial growth. Angle 1218 can be another angle, depending on which surface orientation of the facet can be intercepted, for example, by the retrograde sidewall 1202.

[0049] refer to Figure 13A and 13B A collector layer 1302 is formed above (e.g., on) the upper surface 120 of the semiconductor substrate 102 and in the collector opening 1102a. In some examples, the collector layer 1302 is or comprises a semiconductor layer doped with an n-type dopant (e.g., the same type of dopant as the n-type dopant collector diffusion region 204). In some examples, the collector layer 1302 is or comprises silicon. In some examples, the collector layer 1302 is doped with a concentration of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3The collector layer 1302 is doped with an n-type dopant within the specified range. It can be epitaxially grown on the upper surface 120 of the semiconductor substrate 102. In some instances, the collector layer 1302 can be epitaxially grown using a selective epitaxial growth process. Epitaxial growth of the collector layer 1302 on the upper surface 120 of the semiconductor substrate 102 allows the collector layer 1302 to be a single crystal. Furthermore, the collector layer 1302 can be in-situ doped during the epitaxial growth process (e.g., a selective epitaxial growth process). The epitaxial growth process can be a CVD process, such as LPCVD, reduced-pressure CVD (RPCVD), metal-organic CVD (MOCVD), etc. The reverse sidewall 1202 of the collector opening 1102a can suppress (e.g., include trapping) facet growth and / or propagation during the epitaxial growth of the collector layer 1302. Therefore, the upper surface of the collector layer 1302 can replicate the upper surface 120 of the semiconductor substrate 102. Other materials, dopant types, dopant concentrations, and / or deposition processes can be implemented.

[0050] See Figure 14A and 14B The hard mask layer 1002b is removed. The hard mask layer 1002b can be removed using an etching process that is selective to the material of the hard mask layer 1002b. The etching process can be a wet or dry etching process and can be isotropic. For example, when the hard mask layer 1002b is silicon nitride, the etching process can include or incorporate the use of phosphoric acid (H3PO4).

[0051] refer to Figure 15A and 15B A base layer 1502 is formed above the collector layer 1302. The base layer 1502 comprises a single-crystal base layer 1502a and a polycrystalline base layer 1502b. The single-crystal base layer 1502a and the polycrystalline base layer 1502b are formed together as the base layer 1502. In some examples, the base layer 1502 is or comprises a semiconductor layer doped with a p-type dopant (e.g., a dopant type opposite to that of the collector layer 1302). In some examples, the base layer 1502 is or comprises silicon germanium. In some examples, the base layer 1502 is doped with a concentration of 1 × 10⁻⁶. 17 cm -3 Up to 1×10 21 cm -3The base layer 1502 is doped with p-type dopants within the specified range. It may also be doped with carbon (C) to prevent or reduce the diffusion of p-type dopants. The base layer 1502 may be epitaxially grown on the collector layer 1302 and conformally located on the sidewalls 904 of the fourth pedestal oxide sublayer 304f, the dielectric protection layer 804a, and the gate layer 802a. In some instances, the base layer 1502 may be epitaxially grown using a non-selective epitaxial growth process. This non-selective epitaxial growth process grows a single-crystal base layer 1502a from the collector layer 1302 and a polycrystalline base layer 1502b on other amorphous or polycrystalline surfaces (such as the fourth pedestal oxide sublayer 304f and the dielectric protection layer 804a). The single-crystal base layer 1502a may meet the polycrystalline base layer 1502b at a facet not specifically described. The non-selective deposition of the base layer 1502 conformally forms the base layer 1502. The base layer 1502 can be doped in situ during the epitaxial growth process. The base layer 1502 (e.g., a single-crystal base layer 1502a and a polycrystalline base layer 1502b, respectively) may further comprise multiple sublayers, such as a nucleation sublayer of the same material as the collector layer 1302, an undoped sublayer, a doped sublayer, and a capping layer of the same material as the emitter layer (described later). The epitaxial growth process can be a CVD process, such as LPCVD, RPCVD, MOCVD, etc. Other materials, dopant types, dopant concentrations, and / or deposition processes can be implemented.

[0052] refer to Figure 16A and 16B A first dielectric spacer layer 1602 is conformally formed over a base layer 1502. A second dielectric spacer layer 1604 is conformally formed over the first dielectric spacer layer 1602, and a third dielectric spacer layer 1606 is conformally formed over the second dielectric spacer layer 1604. In some examples, the first dielectric spacer layer 1602 and the third dielectric spacer layer 1606 are made of the same dielectric material, and the second dielectric spacer layer 1604 is made of a dielectric material different from that of the first dielectric spacer layer 1602 and the third dielectric spacer layer 1606. In some examples, the first dielectric spacer layer 1602 and the third dielectric spacer layer 1606 are made of silicon oxide (e.g., TEOS oxide), and the second dielectric spacer layer 1604 is made of silicon nitride. The dielectric spacers 1602 to 1606 can be deposited by CVD. In other examples, other dielectric materials and / or other deposition processes can be used.

[0053] refer to Figure 17A and 17BDielectric spacers 1602 to 1606 are etched to form a first emitter opening 1702 in the BJT region 104, passing through the first dielectric spacer 1602a, the second dielectric spacer 1604a, and the third dielectric spacer 1606a. The single-crystal base layer 1502a (of the base layer 1502) is exposed through the first emitter opening 1702. The dielectric spacers 1602 to 1606 can be patterned using appropriate photolithography and etching (e.g., RIE) processes.

[0054] refer to Figure 18A and 18B An emitter dielectric spacer layer 1802 is conventionally formed above the third dielectric spacer layer 1606a and the first emitter opening 1702. In some instances, the emitter dielectric spacer layer 1802 is silicon oxide (e.g., TEOS oxide) deposited by CVD, but in other instances, other dielectric materials and / or other deposition processes may be used.

[0055] refer to Figure 19A and 19B The emitter dielectric spacer layer 1802 is anisotropically etched to form an emitter dielectric spacer 1802a along the sidewalls defining the first emitter opening 1702 of the dielectric spacers 1602a, 1604a, and 1606a. The emitter dielectric spacer 1802a contracts the first emitter opening 1702 to form a second emitter opening 1902. Additionally, residual dielectric spacers 1802b may be retained on a corresponding vertical surface, such as the vertical surface at the sidewall 904 of the gate layer 802a in the first transition region 106. For example, the anisotropic etching may be a RIE (Regional Etching).

[0056] refer to Figure 20A and 20B An emitter layer 2002 is formed above the base layer 1502 (e.g., on a single-crystal base layer 1502a). The emitter layer 2002 comprises a single-crystal emitter layer 2002a and a polycrystalline emitter layer 2002b. The single-crystal emitter layer 2002a and the polycrystalline emitter layer 2002b are formed together to form the emitter layer 2002. In some examples, the emitter layer 2002 is or comprises a semiconductor layer doped with an n-type dopant (e.g., a dopant type opposite to that of the base layer 1502). In some examples, the emitter layer 2002 is or comprises silicon. In some examples, the emitter layer 2002 is doped with a concentration of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3The emitter layer 2002 is doped with an n-type dopant within the specified range. The emitter layer 2002 can be epitaxially grown on the base layer 1502 (e.g., a single-crystal base layer 1502a), emitter dielectric spacer 1802a, third dielectric spacer layer 1606a, and residual dielectric spacer 1802b, which are exposed through the second emitter opening 1902. In some instances, the emitter layer 2002 can be epitaxially grown using a non-selective epitaxial growth process. This non-selective epitaxial growth process grows a single-crystal emitter layer 2002a from the single-crystal base layer 1502a and a polycrystalline emitter layer 2002b on other amorphous or polycrystalline surfaces (such as emitter dielectric spacer 1802a, third dielectric spacer layer 1606a, and residual dielectric spacer 1802b). The single-crystal emitter layer 2002a may meet the polycrystalline emitter layer 2002b at a facet not specifically described. Emitter layer 2002 is formed conformally by non-selective deposition. Emitter layer 2002 can be in-situ doped during the epitaxial growth process. The epitaxial growth process can be a CVD process, such as LPCVD, RPCVD, MOCVD, etc. Other materials, dopant types, dopant concentrations, and / or deposition processes can be implemented.

[0057] refer to Figure 21A and 21B An emitter dielectric capping layer 2102 is conformally formed above the emitter layer 2002. In some instances, the emitter dielectric capping layer 2102 is silicon oxide (e.g., TEOS oxide) deposited by CVD, but in other instances, other dielectric materials and / or other deposition processes may be used.

[0058] refer to Figure 22A and 22B The emitter dielectric capping layer 2102, the polycrystalline emitter layer 2002b, and the third dielectric spacer layer 1606a are patterned to form the emitter dielectric capping layer 2102a, the polycrystalline emitter layer 2002c, and the third dielectric spacer layer 1606b in the BJT region 104. In the illustrated example, layers 2102, 2002b, and 1606a are patterned using appropriate photolithography and etching (e.g., anisotropic etching, such as RIE) processes. Residual polycrystalline emitter layer 2002d and residual third dielectric spacer layer 1606c are retained at the sidewall 904 of the gate layer 802a in the first transition region 106, attributable to the etching process (e.g., anisotropic etching).

[0059] refer to Figure 23A and 23BIn the BJT region 104, an emitter dielectric protection spacer layer 2302 is conformally formed above the emitter dielectric capping layer 2102a and the second dielectric spacer layer 1604a, and along the sidewalls of the emitter dielectric capping layer 2102a, the polycrystalline emitter layer 2002c, and the third dielectric spacer 1606b. Additionally, in the first transition region 106, the emitter dielectric protection spacer layer 2302 is conformally formed above the residual polycrystalline emitter layer 2002d, along the sidewalls of the residual polycrystalline emitter layer 2002d and the residual third dielectric spacer layer 1606c, and above the second dielectric spacer layer 1604a in the first transition region 106. The emitter dielectric protection spacer layer 2302 is formed in the pFET region 110 and the nFET region 112 above the second dielectric spacer layer 1604a. In some instances, the emitter dielectric protective spacer 2302 is silicon oxide (e.g., TEOS oxide) deposited by CVD, but in other instances, other dielectric materials and / or other deposition processes may be used.

[0060] refer to Figure 24A and 24B The emitter dielectric protective spacer layer 2302 is anisotropically etched to form the emitter dielectric protective spacer 2302a along the sidewalls of the emitter dielectric capping layer 2102a, the polycrystalline emitter layer 2002c, and the third dielectric spacer 1606b. The emitter dielectric protective spacer 2302a protects the sidewalls of the polycrystalline emitter layer 2002c. Additionally, residual dielectric spacers 2302b may be retained on vertical surfaces, such as the vertical surfaces of the residual polycrystalline emitter layer 2002d and the residual third dielectric spacer layer 1606c in the first transition region 106. For example, the anisotropic etching may be a re-etching process (RIE).

[0061] refer to Figure 25A and 25B The second dielectric spacer layer 1604a is etched. The etching removes the exposed portion of the second dielectric spacer layer 1604a and, laterally away from the single-crystal emitter layer 2002a, undercuts the emitter dielectric protection spacer 2302a and the third dielectric spacer 1606b, thereby creating a second dielectric spacer 1604b below the third dielectric spacer 1606b. The etching may also undercut any one of the residual dielectric spacers 2302b in the first transition region 106, further forming a residual second dielectric spacer layer 1604c. The etching may be a selective wet or dry etching of the material of the second dielectric spacer layer 1604a, and the etching is also isotropic. For example, when the second dielectric spacer layer 1604a is silicon nitride, the etching process may include or incorporate the use of phosphoric acid.

[0062] refer to Figure 26A and 26BThe first dielectric spacer layer 1602a is etched. Etching the first dielectric spacer layer 1602a may involve removing an exposed portion of the first dielectric spacer layer 1602a from the single-crystal base layer 1502a. The etching may be a selective wet etching of the first dielectric spacer layer 1602a. Wet etching may remove the first dielectric spacer layer 1602a beneath the emitter dielectric protection spacer 2302a and the second dielectric spacer 1604b. For example, when the first dielectric spacer layer 1602a is silicon oxide, diluted hydrofluoric acid (dHF) etching may be used to etch the first dielectric spacer layer 1602a. Removal of the first dielectric spacer layer 1602a opens (e.g., exposes) a region on the base layer 1502 adjacent to the single-crystal emitter layer 2002a on which a raised base layer may be formed. Furthermore, when the emitter dielectric capping layer 2102a, emitter dielectric protection spacer 2302a, and third dielectric spacer 1606b are made of the same material as the first dielectric spacer layer 1602a, wet etching can further etch those layers and spacers, thereby reducing the corresponding thickness of those layers and spacers, resulting in the emitter dielectric capping layer 2102c, emitter dielectric protection spacer 2302c, and third dielectric spacer 1606d, as explained. The remaining first dielectric spacer layer 1602b remains below the remaining second dielectric spacer layer 1604c in the first transition region 106. Additionally, in the first transition region 106, when the remaining dielectric spacer 2302b is made of the same material as the first dielectric spacer layer 1602a, wet etching can further etch those spacers, reducing the number of spacers, thereby resulting in the remaining dielectric spacer 2302d, as explained.

[0063] refer to Figure 27A and 27B A raised base layer 2702 is formed above the base layer 1502. The raised base layer 2702 comprises at least one polycrystalline raised base layer on the polycrystalline base layer 1502b. The raised base layer 2702 may comprise a single-crystal raised base layer. If the single-crystal base layer 1502a is exposed by etching the first dielectric spacer layer 1602a, the raised base layer 2702 may comprise a single-crystal portion on the single-crystal base layer 1502a. In some examples, the raised base layer 2702 is or comprises a semiconductor layer doped with a p-type dopant (e.g., the same type of dopant as the base layer 1502). In some examples, the raised base layer 2702 is or comprises silicon. In some examples, the raised base layer 2702 is doped with a concentration of 1×10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3The p-type dopant is used for doping within the specified range. The raised base layer 2702 can be epitaxially grown on the base layer 1502. In some instances, the raised base layer 2702 can be epitaxially grown using a selective epitaxial growth process. The selective deposition of the raised base layer 2702 conformally forms the raised base layer 2702 on a crystalline (e.g., polycrystalline and single-crystal) surface, said crystalline surface including the exposed portion of the base layer 1502 (e.g., polycrystalline base layer 1502b). Furthermore, the raised base layer 2702 can be in-situ doped during the epitaxial growth process (e.g., a selective epitaxial growth process). The epitaxial growth process can be a CVD process, such as LPCVD, RPCVD, MOCVD, etc. Other materials, dopant types, dopant concentrations, and / or deposition processes can be implemented.

[0064] refer to Figure 28A and 28B A dielectric protective layer 2802 is conformally formed over and along the emitter dielectric capping layer 2102c, emitter dielectric protective spacer 2302c, and raised base layer 2702 in the BJT region 104. The dielectric protective layer 2802 is further conformally formed over and along the raised base layer 2702 and the residual dielectric spacer 2302d in the first transition region 106, and is also conformally formed over the raised base layer 2702 in the pFET region 110 and nFET region 112. In some instances, the dielectric protective layer 2802 is silicon oxide (e.g., TEOS oxide) deposited by CVD, but in other instances, other dielectric materials and / or other deposition processes may be used.

[0065] refer to Figure 29A and 29BIn the BJT region 104, a dielectric protective layer 2802, a raised base layer 2702, a base layer 1502 (e.g., a polycrystalline base layer 1502b), and a fourth pedestal oxide sublayer 304f are patterned. The dielectric protective layer 2802, the raised base layer 2702, the polycrystalline base layer 1502b, and the fourth pedestal oxide sublayer 304f are patterned to remain in the BJT region 104 as a dielectric protective layer 2802a, a raised base layer 2702a, a polycrystalline base layer 1502c, and a fourth pedestal oxide sublayer 304g, respectively. Furthermore, a third pedestal oxide sublayer 302d is thinned in the region where the dielectric protective layer 2802, the raised base layer 2702, the polycrystalline base layer 1502b, and the fourth pedestal oxide sublayer 304f have been removed, thus creating a third pedestal oxide sublayer 302e. Patterning the fourth pedestal oxide sublayer 304f and thinning the third pedestal oxide sublayer 302d creates sidewalls 2902 and 2904 of the fourth pedestal oxide sublayer 304g and the third pedestal oxide sublayer 302e, which are aligned with the corresponding sidewalls of the polycrystalline base layer 1502c and further protruding base layer 2702a. Layers 2802, 2702, 1502b, 304f, and 302d can be patterned or thinned using appropriate photolithography and etching (e.g., RIE) processes.

[0066] As described, etching the dielectric protective layer 2802, the raised base layer 2702, and the polycrystalline base layer 1502b removes the dielectric protective layer 2802, residual dielectric spacer 2302d, raised base layer 2702, and residual polycrystalline emitter layer 2002d from the first transition region 106. Subsequently, etching the fourth base oxide sublayer 304f and the third base oxide sublayer 302d removes any remaining residual dielectric spacer 2302d, residual dielectric spacer 1802b, residual third dielectric spacer layer 1606c, and dielectric protective layer 804a in the first transition region 106. Etching the fourth base oxide sublayer 304f leaves a residual fourth base oxide sublayer 304h in the first transition region 106. The residual polycrystalline base layer 1502d remains in the first transition region 106 along the sidewall 904 of the gate layer 802a and above the residual oxide layer 304h. Various etching processes can also reduce the residual dielectric spacer layers 1604c and 1602b, leaving the residual dielectric spacer layers 1604d and 1602c above the residual polycrystalline base layer 1502d. Furthermore, various etching processes remove the dielectric protective layer 2802, the raised base layer 2702, the polycrystalline base layer 1502b, and the dielectric protective layer 804a from the pFET region 110 and the nFET region 112.

[0067] refer to Figure 30A and 30BA hard mask layer 3002 is conformally formed over the semiconductor substrate 102. More specifically, in the BJT region 104, the hard mask layer 3002 is conformally formed over the third pedestal oxide sublayer 302e and the dielectric protection layer 2802a, and along the sidewalls of the dielectric protection layer 2802a, the raised base layer 2702a, the polycrystalline base layer 1502c, and the fourth pedestal oxide sublayer 304g and the third pedestal oxide sublayer 302e. The hard mask layer 3002 is conformally formed over the gate layer 802a in the first transition region 106, the pFET region 110, and the nFET region 112, and is conformally formed over the residual fourth pedestal oxide sublayer 304h, the residual polycrystalline base layer 1502d, and the residual dielectric spacer layers 1602c and 1604d in the first transition region 106, and along the respective sidewalls of the layers. In some instances, the hard mask layer 3002 is or contains silicon nitride deposited by CVD, but in other instances, other hard mask (e.g., dielectric) materials and / or other deposition processes may be used.

[0068] refer to Figure 31A and 31B Hard mask layer 3002, gate layer 802a, and gate oxide layers 702 and 502a are patterned into hard mask layers 3002a and 3002b, gate electrodes 802b and 802c, and gate oxide layers 702a and 502b, respectively, in pFET region 110 and nFET region 112. Gate electrode 802b is located above gate oxide layer 702a in pFET region 110 (e.g., above), and gate electrode 802c is located above gate oxide layer 502b in nFET region 112 (e.g., above). Hard mask layers 3002a and 3002b remain above gate electrodes 802b and 802c, respectively (e.g., above). The hard mask layers 3002, gate layer 802a, and gate oxide layers 702 and 502a can be patterned using appropriate photolithography and etching (e.g., RIE) processes. The patterned hard mask layer 3002 is such that the hard mask layer 3002c is retained in the BJT region and transition regions 108, 106. The residual gate layer 802d (with sidewalls 904) is retained in the first transition region 106 along the sidewalls of the residual fourth pedestal oxide sublayer 304h and the third pedestal oxide sublayer 302e and additionally above said layers.

[0069] Re-oxidation layers 3102a and 3102b are formed along the sidewalls of gate electrodes 802b and 802c and the exposed portions of the upper surface 120 of the semiconductor substrate 102. Re-oxidation layer 3102a is formed in the pFET region 110 along the sidewalls of gate electrode 802b and the exposed portions of the upper surface 120, and re-oxidation layer 3102b is formed in the nFET region 112 along the sidewalls of gate electrode 802c and the exposed portions of the upper surface 120. Re-oxidation layers 3102a and 3102b can be formed by an oxidation process (such as by ISSG oxidation). The formation of re-oxidation layers 3102a and 3102b can remove damage to the sidewalls and / or upper surface 120 of gate electrodes 802b and 802c formed by an etching process that patterns the gate electrodes 802b and 802c, the damage of which may be plasma-induced. The formation of re-oxidation layers 3102a and 3102b can reduce gate-induced drain leakage current in the FET to be formed (which includes gate electrodes 802b and 802c). Additionally, in some instances, the oxidation process for forming re-oxidation layers 3102a and 3102b forms a residual re-oxidation layer 3102c in the first transition region 106 on the exposed portion of the upper surface 120 and on the sidewalls (opposite to sidewall 904) of the residual gate layer 802d.

[0070] refer to Figure 32A and 32BThe hard mask layer 3002c, the third pedestal oxide sublayer 302e, and the second pedestal oxide sublayer 124d are patterned into hard mask layers 3002d, 3002e, the third pedestal oxide sublayer 302f, a residual third pedestal oxide sublayer 302g, a second pedestal oxide sublayer 124e, and a residual second pedestal oxide sublayer 124f. The hard mask layer 3002d, the third pedestal oxide sublayer 302f, and the second pedestal oxide sublayer 124e are located in the BJT region 104. Specifically, the hard mask layer 3002d is located above the dielectric protection layer 2802a and the third pedestal oxide sublayer 302f, along the sidewalls of the dielectric protection layer 2802a, the raised base layer 2702a, and the polycrystalline base layer 1502c, and along the sidewalls 2902 and 2904 of the fourth pedestal oxide sublayer 304g and the third pedestal oxide sublayer 302f. The hard mask layer 3002d extends laterally above the third pedestal oxide sublayer 302f, away from the polycrystalline base layer 1502c and the sidewalls 2902 and 2904 of the fourth pedestal oxide sublayer 304g and the third pedestal oxide sublayer 302f. The third pedestal oxide sublayer 302g and the second pedestal oxide sublayer 124e extend laterally together with the hard mask layer 3002d. The patterned third pedestal oxide sublayer 302e and the second pedestal oxide sublayer 124d form the third pedestal oxide sublayer 302f and the second pedestal oxide sublayer 124e with sidewalls 3202, and form the third pedestal oxide sublayer 302f with sidewalls 3204. The sidewalls 3202 and 3204 are laterally away from the corresponding sidewalls 2902 and 2904 of the fourth pedestal oxide sublayer 304g and the third pedestal oxide sublayer 302e. The sidewalls 3202 of the third pedestal oxide sublayer 302e and the second pedestal oxide sublayer 124e are located above the upper surface 120 of the semiconductor substrate 102 and the n-type doped sub-collector diffusion region 204. The sidewalls 3204 of the third pedestal oxide sublayer 302e are located above the first portion 132a of the isolation structure 132. The hard mask layer 3002c and portions of the third pedestal oxide sublayer 302e and the second pedestal oxide sublayer 124d are removed from at least a portion of the n-type doped sub-collector diffusion region 204 and the p-type doped well 206. The hard mask layer 3002c and portions of the third pedestal oxide sublayer 302e and the second pedestal oxide sublayer 124d can be patterned using appropriate photolithography and etching (e.g., RIE) processes. Although patterning is described and depicted as passing through the second pedestal oxide sublayer 124d, patterning may enter (e.g., not pass through) the second pedestal oxide sublayer 124d, or may pass through the second pedestal oxide sublayer 124d and enter the first pedestal oxide sublayer 122d.

[0071] The hard mask layer 3002e, the residual third pedestal oxide sublayer 302g, and the residual second pedestal oxide sublayer 124f are located in the first transition region 106. The residual third pedestal oxide sublayer 302g is located above the residual second pedestal oxide sublayer 124f and the first portion 134a of the isolation structure 134, and below the residual fourth pedestal oxide sublayer 304h.

[0072] refer to Figure 33A and 33B The first gate dielectric spacers 3302a and 3302b are formed along the sidewalls of the gate electrodes 802b and 802c (e.g., on the re-oxidation layers 3102a and 3102b). The first gate dielectric spacers 3302a and 3302b can be formed by conformally depositing a material layer of the first gate dielectric spacers 3302a and 3302b over the semiconductor substrate 102 and anisotropically etching (e.g., by RIE) the layers so that the first gate dielectric spacers 3302a and 3302b are retained. The material of the first gate dielectric spacers 3302a and 3302b can be any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. The layers can be deposited by CVD, PECVD, ALD, etc. The formation of the first gate dielectric spacers 3302a and 3302b may further form residual dielectric spacers 3302c on vertical surfaces (such as the vertical surfaces of hard mask layers 3002d, 3002e, etc.) in the BJT region 104 and the first transition region 106.

[0073] A p-type lightly doped drain region (LDD) 3312 and an n-type LDD 3314 are formed in the semiconductor substrate 102 in the pFET region 110 and the nFET region 112, respectively. In some embodiments, the p-type LDD 3312 and the n-type LDD 3314 may be formed before the formation of the first gate dielectric spacers 3302a and 3302b, and in some embodiments, the p-type LDD 3312 and the n-type LDD 3314 may be formed after the formation of the first gate dielectric spacers 3302a and 3302b. The p-type LDD 3312 is located on the laterally opposite side of the gate electrode 802b in the semiconductor substrate 102, and the n-type LDD 3314 is located on the laterally opposite side of the gate electrode 802c in the semiconductor substrate 102. A p-type LDD 3312 can be formed by masking (e.g., using photolithography through a photoresist) the BJT regions 104, transition regions 106, 108, and nFET region 112 and embedding a p-type dopant into the semiconductor substrate 102 in the pFET region 110. An n-type LDD 3314 can be formed by masking (e.g., using photolithography through a photoresist) the BJT regions 104, transition regions 106, 108, and pFET region 110 and embedding an n-type dopant into the semiconductor substrate 102 in the nFET region 112. The concentration of the p-type dopant in the p-type LDD 3312 is greater than the concentration of the n-type dopant in the n-type doped well 202, and the concentration of the n-type dopant in the n-type LDD 3314 is greater than the concentration of the p-type dopant in the p-type doped well 208. In some examples, the p-type LDD 3312 uses a concentration of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 The p-type dopant is used within the range of n-type LDD 3314, and the concentration is 1×10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 Doping with n-type dopant within the range. Other doping concentrations can be implemented. Activation annealing can be performed after one or more implantations to form p-type LDD 3312 and n-type LDD 3314.

[0074] refer to Figure 34A and 34BAn embedded stress source 3402 is formed in the semiconductor substrate 102 within the pFET region 110. To form the embedded stress source 3402, a corresponding groove is formed in the semiconductor substrate 102. To form the groove, a conformal hard mask layer (not shown) is formed over the semiconductor substrate 102 in the BJT regions 104, transition regions 106, 108, and nFET region 112. The conformal hard mask layer may be or contain silicon nitride, silicon oxynitride, the like, or a combination thereof. The conformal hard mask layer can be formed by conformally depositing and patterning the conformal hard mask layer. The conformal hard mask layer can be deposited using CVD, PECVD, ALD, etc. The conformal hard mask layer can be patterned using photolithography and etching (e.g., RIE) processes. Next, a stress source groove is formed in the semiconductor substrate 102 within the pFET region 110. A stress source trench is etched in the semiconductor substrate 102 to form an embedded stress source, which patterns the reoxide layer 3102a into a reoxide layer 3102d located beneath the corresponding first gate dielectric spacer 3302a. Any suitable etching process can be used to form the stress source trench; the etching process can be a wet or dry etching process. The etching process can be anisotropic and selective (e.g., preferential etching) to the crystal planes of the semiconductor substrate 102. An embedded stress source 3402 is then formed in the stress source trench. The embedded stress source 3402 can be formed using a selective epitaxial growth process. MOCVD, molecular beam epitaxy (MBE), LPCVD, or another epitaxial process can be used to form the embedded stress source 3402. In some instances, the embedded stress source 3402 is a semiconductor material that induces compressive stress in the channel region beneath the gate electrode 802b in the semiconductor substrate 102. For example, when the semiconductor substrate 102 is silicon, the embedded stress source 3402 can be or comprise silicon germanium.

[0075] refer to Figure 35A and 35BThe conformal hard mask layer, dielectric spacers 3302a, 3302b, 3302c, and hard mask layers 3002a, 3002b, 3002d, 3002e used to form the embedded stress source 3402 are removed. These layers and spacers can be removed by an etching process selectively etching the materials of the respective layers and spacers; the etching process can be a wet or dry etching process and can be isotropic. For example, when the conformal hard mask layer, dielectric spacers 3302a, 3302b, 3302c, and hard mask layers 3002a, 3002b, 3002d, 3002e are silicon nitride, a wet etching process containing phosphoric acid can be performed. Furthermore, after removing the dielectric spacers 3302a, 3302b, 3302c and the hard mask layers 3002a, 3002b, 3002d, 3002e, the cleaning process can remove the re-oxidized layers 3102b, 3102c, 3102d, as explained. Although not explained, the cleaning process can thin the first substrate oxide sublayer 122d.

[0076] refer to Figure 36A and 36B Second gate dielectric spacers 3602a and 3602b are formed along the sidewalls of gate electrodes 802b and 802c, respectively. The second gate dielectric spacers 3602a and 3602b can be formed by conformally depositing a material layer of the second gate dielectric spacers 3602a and 3602b over the semiconductor substrate 102 and anisotropically etching (e.g., by RIE) the layer to retain the second gate dielectric spacers 3602a and 3602b. The material of the second gate dielectric spacers 3602a and 3602b can be any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. The layers can be deposited by CVD, PECVD, ALD, etc. The formation of the second gate dielectric spacers 3602a and 3602b may further form residual dielectric spacers (e.g., residual dielectric spacer 3602c) on the sidewalls of the components in the BJT region 104 and / or the first transition region 106.

[0077] Stress memory technology can be implemented, for example, in nFET region 112. A stress source dielectric layer is formed in nFET region 112 over semiconductor substrate 102, gate electrode 802c, and second gate dielectric spacer 3602b. The stress source dielectric layer may be or contain silicon nitride, the like, or a combination thereof. The stress source dielectric layer can be formed by conformally depositing and patterning it. The stress source dielectric layer can be deposited by CVD, PECVD, ALD, etc. The stress source dielectric layer can be patterned using photolithography and etching processes. An annealing process is performed on the stress source dielectric layer in nFET region 112. The annealing process allows the lattice structure of semiconductor substrate 102 to conform due to the stress induced by the stress source dielectric layer. After the annealing process, the stress source dielectric layer is removed. The stress source dielectric layer can be removed by an etching process selectively etching the material of the stress source dielectric layer, said etching process being either a wet or dry etching process.

[0078] An n-type collector contact region 3612, an n-type source / drain (NSD) region 3614, a p-type source / drain (PSD) region, and a p-type guard ring contact region 3616 are formed in a semiconductor substrate 102. The n-type collector contact region 3612 is formed in a BJT region 104 within an n-type doped sub-collector diffusion region 204 in the semiconductor substrate 102. The n-type collector contact region 3612 is laterally located between the sidewalls 3202 of the third base oxide sublayer 302f and the second base oxide sublayer 124e and the second portion 132b of the isolation structure 132. The NSD region 3614 is formed in an nFET region 112 within a p-type doped well 208 in the semiconductor substrate 102. The NSD region 3614 is located on the opposite lateral side of the gate electrode 802c, and an n-type LDD 3314 is present between the NSD region and the gate electrode. A PSD region is formed in the pFET region 110 and may be formed in the embedded stress source 3402, and / or may further extend below the embedded stress source 3402 into the n-type doped well 202 in the semiconductor substrate 102. The PSD region is located on the opposite lateral side of the gate electrode 802b, and a p-type LDD 3312 is present between the PSD region and the gate electrode. A p-type guard ring contact region 3616 is formed in the BJT region 104 within the p-type doped well 206 in the semiconductor substrate 102. The p-type guard ring contact region 3616 is laterally located between the isolation structures 132 and 134.

[0079] Implantation is performed to form an n-type collector contact region 3612 and an NSD region 3614. The n-type collector contact region 3612 and NSD region 3614 can be formed by masking (e.g., using photolithography through a photoresist) the base layer 1502, the raised base layer 2702a, and the emitter layer 2002 in the pFET region 110 and the BJT region 104, and by implanting n-type dopant into the semiconductor substrate 102 in the nFET region 112 and the exposed portion of the BJT region 104. Implantation is performed to form a PSD region and a p-type guard ring contact region 3616. The PSD region and p-type guard ring contact region 3616 can be formed by masking (e.g., using photolithography through a photoresist) the BJT region 104 (except for the p-type doped well 206) and the nFET region 112, and by implanting p-type dopant into the semiconductor substrate 102 in the pFET region 110 and the p-type doped well 206. Simultaneously with the implantation of the PSD region and the p-type guard ring contact region 3616, a raised base layer 2702a and / or a base layer 1502 may be implanted. During the implantation of the PSD region and the p-type guard ring contact region 3616, a region of the raised base layer 2702a may be exposed through a mask so that p-type dopants can also be implanted into the raised base layer 2702a and / or the base layer 1502.

[0080] The concentration of n-type dopant in the n-type collector contact region 3612 is greater than the concentration of n-type dopant in the n-type doped sub-collector diffusion region 204. The concentration of n-type dopant in the NSD region 3614 is greater than the concentration of n-type dopant in the n-type LDD 3314 and the concentration of p-type dopant in the p-type doped well 208. The concentration of p-type dopant in the PSD region is greater than the concentration of p-type dopant in the p-type LDD 3312 and the concentration of n-type dopant in the n-type doped well 202. The concentration of p-type guard ring contact region 3616 is greater than the concentration of p-type dopant in the p-type doped well 206. In some examples, the n-type collector contact region 3612 and the NSD region 3614 are used with a concentration of 1×10⁻⁶. 20 cm -3 Up to 1×10 21 cm -3 The n-type dopant is used within the range of 1×10⁻⁶, and the PSD region and the p-type guard ring contact region are doped with 3616 at a concentration of 1×10⁻⁶. 20 cm -3 Up to 1×10 21 cm -3 P-type dopant within the range. Other doping concentrations can be implemented. Activation annealing can be performed after implantation to form the n-type collector contact region 3612, NSD region 3614, PSD region, and p-type guard ring contact region 3616.

[0081] refer to Figure 37A and 37BMetal-semiconductor compounds 3702, 3704, 3706, 3708, 3710, 3712, 3714, 3716, and 3718 are formed. Metal-semiconductor compound 3702 is located on emitter layer 2002 (e.g., polycrystalline emitter layer 2002c and / or monocrystalline emitter layer 2002a). Metal-semiconductor compound 3704 is located on raised base layer 2702a. Metal-semiconductor compound 3706 is located on the upper surface 120 of semiconductor substrate 102 at n-type collector contact region 3612. Metal-semiconductor compound 3708 is located on the upper surface 120 of semiconductor substrate 102 at p-type guard ring contact region 3616. Metal-semiconductor compound 3710 is located on any exposed upper surface of the semiconductor material in the first transition region 106, such as on the upper surface 120 of the semiconductor substrate 102 and the upper surfaces of the residual gate layer 802d and the residual polycrystalline base layer 1502d. Metal-semiconductor compound 3712 is located on the embedded stress source 3402. Metal-semiconductor compound 3714 is located on the NSD region 3614 in the semiconductor substrate 102. Metal-semiconductor compounds 3716 and 3718 are located on the gate electrodes 802b and 802c, respectively. Metal-semiconductor compounds 3702 to 3718 may be silicides (e.g., NiSix, TiSix, CoSix, PtSix), germanides, etc.

[0082] To form the metal-semiconductor compounds 3702 to 3718, any retained dielectric material on the surfaces where the metal-semiconductor compounds 3702 to 3718 will be formed is removed. For example, if any of the exposed portions of the dielectric protective layer 2802a, the emitter dielectric capping layer 2102c, and the first base oxide sublayer 122d are retained after the formation of the second gate dielectric spacers 3602a, 3602b, those layers or their exposed portions can be removed by etching and / or cleaning processes. For example, when layers 2802a, 2102c, 122d are silicon oxide, diluted hydrofluoric acid (dHF) can be used. The portion of the first base oxide sublayer 122d not below the second base oxide sublayers 124e, 124f is removed, thereby patterning the first base oxide sublayers 122e, 122f below the second base oxide sublayers 124e, 124f, respectively. Other layers and / or spacers can be reduced through etching and / or cleaning processes. For example, emitter dielectric protection spacer 2302c can be reduced to emitter dielectric protection spacer 2302e, and the exposed portion of the third base oxide sublayer 302f is thinned to form the third base oxide sublayer 302h. More specifically, the exposed portions of the third base oxide sublayer 302f between sidewalls 2902, 3202 and between sidewalls 2904, 3204 are thinned.

[0083] The metal-semiconductor compounds 3702 to 3718 can then be formed by depositing a metal (e.g., Ni, Ti, Co, Pt) over the semiconductor substrate 102 (e.g., by physical vapor deposition (PVD), CVD, etc.). The metal reacts with a semiconductor material, such as the semiconductor material of the emitter layer 2002 (e.g., a polycrystalline emitter layer 2002c and / or a single-crystal emitter layer 2002a), the semiconductor material of the raised base layer 2702a, the semiconductor material of the semiconductor substrate 102, the semiconductor material of the embedded stress source 3402, and the semiconductor material of the gate electrodes 802b, 802c (e.g., silicon, such as polycrystalline silicon). An annealing process can be used to react the metal with the semiconductor material.

[0084] After forming the metal-semiconductor compounds 3702 to 3718, in some instances, the second gate dielectric spacers 3602a, 3602b and the residual dielectric spacer 3602c are removed. Suitable etching processes (such as wet or dry etching, and / or isotropic etching) can be performed to remove the second gate dielectric spacers 3602a, 3602b and the residual dielectric spacer 3602c. In some instances, the removal of the second gate dielectric spacers 3602a, 3602b and the residual dielectric spacer 3602c can be omitted. Furthermore, in some instances, the second gate dielectric spacers 3602a, 3602b can be retained while the residual dielectric spacer 3602c is removed. In such cases, masking (e.g., by photoresist) can allow the removal of the residual dielectric spacer 3602c while retaining the second gate dielectric spacers 3602a, 3602b.

[0085] A dielectric layer 3722 is formed above a semiconductor substrate 102, and contacts 3732, 3734, 3736, 3742, and 3744 are formed to penetrate the dielectric layer 3722. The dielectric layer 3722 may comprise one or more dielectric layers. For example, the dielectric layer 3722 may comprise a conformal first dielectric layer located above the semiconductor substrate 102 and a second dielectric layer located above the first dielectric layer. The conformal first dielectric layer may be a stress source layer, an etch stop layer, etc., and may be or comprise silicon nitride, silicon oxynitride, the like, or combinations thereof. The second dielectric layer may be or comprise silicon oxide, silicon nitride, etc. The dielectric layer 3722 may be or comprise a pre-metal dielectric (PMD), an interlayer dielectric (ILD), etc. The dielectric layer 3722 may be deposited using CVD, PECVD, ALD, etc. The dielectric layer 3722 may be planarized, for example, by CMP.

[0086] Contacts 3732, 3734, 3736, 3742, and 3744 extend through dielectric layer 3722 and contact corresponding metal-semiconductor compounds 3702, 3704, 3706, 3712, and 3714. Contacts 3732, 3734, 3736, 3742, and 3744 may each comprise one or more barrier layers and / or adhesive layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), the like, or combinations thereof) conformally located in corresponding openings through dielectric layer 3722, and filler metal (e.g., tungsten (W), copper (Cu), aluminum (Al), the like, or combinations thereof) located above and / or on one or more barrier layers and / or adhesive layers.

[0087] To form contacts 3732, 3734, 3736, 3742, and 3744, appropriate photolithography and etching processes can be used to form corresponding openings through the dielectric layer 3722 to the metal-semiconductor compounds 3702, 3704, 3706, 3712, and 3714. One or more metals of contacts 3732, 3734, 3736, 3742, and 3744 are deposited in the openings through the dielectric layer 3722. One or more metals can be deposited using one or more appropriate deposition processes (such as CVD, PVD, etc.). Any excess of one or more metals can be removed, for example by CMP and / or by patterning using photolithography and etching processes.

[0088] Figure 38A and 38B arrive Figure 44A and 44B These are corresponding cross-sectional views of semiconductor devices at intermediate manufacturing stages, based on some examples. The methods illustrated in these figures are formed... Figure 44A and 44B The semiconductor device 4400. Processing is as described above regarding... Figure 1A and 1B arrive Figure 15A and 15B The process described continues.

[0089] refer to Figure 38A and 38B A first dielectric spacer layer 3802 is conformally formed over the base layer 1502, and a second dielectric spacer layer 3804 is conformally formed over the first dielectric spacer layer 3802. In some examples, the dielectric material of the second dielectric spacer layer 3804 is different from the dielectric material of the first dielectric spacer layer 3802. In some examples, the first dielectric spacer layer 3802 is silicon oxide (e.g., TEOS oxide), and the second dielectric spacer layer 3804 is silicon nitride. The dielectric spacers 3802 and 3804 can be deposited by CVD. In other examples, other dielectric materials and / or other deposition processes can be used.

[0090] refer to Figure 39A and 39B Dielectric spacers 3802 and 3804 are etched to form an emitter opening 3902 in the BJT region 104, passing through the first dielectric spacer 3802a and the second dielectric spacer 3804a. The single-crystal base layer 1502a (of the base layer 1502) is exposed through the emitter opening 3902. The dielectric spacers 3802 and 3804 can be patterned using appropriate photolithography and etching (e.g., RIE) processes.

[0091] refer to Figure 40A and 40B , such as regarding Figure 20A and 20B As described, an emitter layer 2002 is formed above the base layer 1502 (e.g., on a single-crystal base layer 1502a). The emitter layer 2002 can be epitaxially grown on the base layer 1502 (e.g., the single-crystal base layer 1502a) exposed through the emitter opening 3902 and on the second dielectric spacer layer 3804a. (Reference) Figure 41A and 41B , such as regarding Figure 21A and 21B As described, an emitter dielectric capping layer 2102 is conformally formed above the emitter layer 2002.

[0092] refer to Figure 42A and 42B The emitter dielectric capping layer 2102, the polycrystalline emitter layer 2002b, and the second dielectric spacer layer 3804a are patterned to form the emitter dielectric capping layer 2102a, the polycrystalline emitter layer 2002c, and the second dielectric spacer layer 3804b. Layers 2102, 2002b, and 3804a can be patterned using appropriate photolithography and etching (e.g., RIE) processes. As illustrated, residual emitter dielectric capping layer 2102b, residual polycrystalline emitter layer 2002d, and residual second dielectric spacer layer 3804c may be retained in the first transition region 106.

[0093] refer to Figure 43A and 43BIn the BJT region 104, a first dielectric spacer layer 3802a, a base layer 1502 (e.g., a polycrystalline base layer 1502b), and a fourth pedestal oxide sublayer 304f are patterned. The first dielectric spacer layer 3802a, the polycrystalline base layer 1502b, and the fourth pedestal oxide sublayer 304f are patterned to remain in the BJT region 104 as the first dielectric spacer layer 3802b, the polycrystalline base layer 1502c, and the fourth pedestal oxide sublayer 304g, respectively. Furthermore, a third pedestal oxide sublayer 302d is thinned in the region where the first dielectric spacer layer 3802a, the polycrystalline base layer 1502b, and the fourth pedestal oxide sublayer 304f have been removed, thus creating a third pedestal oxide sublayer 302e. Patterning the fourth pedestal oxide sublayer 304f and thinning the third pedestal oxide sublayer 302d produces sidewalls 2902, 2904 of the fourth pedestal oxide sublayer 304g and the third pedestal oxide sublayer 302e that are aligned with the corresponding sidewalls of the polycrystalline base layer. Layers 3802a, 1502b, 304f, and 302d can be patterned or thinned using appropriate photolithography and etching (e.g., RIE) processes.

[0094] As described, etching the first dielectric spacer layer 3802a and the polycrystalline base layer 1502b removes residual dielectric spacer 2102b, dielectric protective layer 804a, and residual polycrystalline emitter layer 2002d from the first transition region 106. Subsequently, etching the fourth base oxide sublayer 304f and the third base oxide sublayer 302d removes any remaining residual dielectric spacer 2102b and dielectric protective layer 804a in the first transition region 106. Etching the fourth base oxide sublayer 304f leaves a residual fourth base oxide sublayer 304h in the first transition region 106. The residual polycrystalline base layer 1502d remains in the first transition region 106 along the sidewall 904 of the gate layer 802a and above the residual oxide layer 304h. Various etchings also reduce the residual second dielectric spacer layer 3804c, leaving the residual second dielectric spacer layer 3804d above the residual polycrystalline base layer 1502d. In addition, various etching processes remove the first dielectric spacer layer 3802a, the polycrystalline base layer 1502b, and the dielectric protection layer 804a from the pFET region 110 and the nFET region 112.

[0095] Subsequently, the above-mentioned matters were handled. Figure 30A and 30B arrive Figure 37A and 37B The process described continues. Figure 44A and 44B Corresponding to through about Figure 37A and 37B The described process involves the processing performed. Regarding the above... Figure 37A and 37BThe formation of the described metal-semiconductor compound, metal-semiconductor compound 3704 in Figure 44A and 44B The first dielectric spacer 3802d is located on the base layer 1502 (e.g., a polycrystalline base layer 1502c). The semiconductor material of the base layer 1502 (e.g., a polycrystalline base layer 1502c) reacts with the deposited metal. In the process of forming the metal-semiconductor compound, the first dielectric spacer 3802b, which is not below the second dielectric spacer 3804b, can be removed, for example, by cleaning or etching processes, leaving the first dielectric spacer 3802d below the second dielectric spacer 3804b.

[0096] Figure 37A and 37B Explain semiconductor device 3700, and Figure 44A and 44B Semiconductor device 4400 is described. Each of the described semiconductor devices 3700 and 4400 includes a BJT in the BJT region 104. The BJT includes a collector layer 1302, a base layer 1502 (e.g., a monocrystalline base layer 1502a and a polycrystalline base layer 1502c), and an emitter layer 2002 (e.g., a monocrystalline emitter layer 2002a and a polycrystalline emitter layer 2002b). Figure 37A and 37B The BJT of the semiconductor device 3700 also includes a raised base layer 2702a located on the base layer 1502 (e.g., on the polycrystalline base layer 1502c).

[0097] The collector layer 1302 is located above (e.g., on) the upper surface 120 of the semiconductor substrate 102 and extends through an opening in the substrate dielectric stack located above the upper surface of the semiconductor substrate 102. The substrate dielectric stack (e.g., a substrate oxide stack) includes a first substrate oxide sublayer 122e above the upper surface 120, a second substrate oxide sublayer 124e above the first substrate oxide sublayer 122e, a third substrate oxide sublayer 302h above the second substrate oxide sublayer 124e, and a fourth substrate oxide sublayer 304g above the third substrate oxide sublayer 302h. The opening through the substrate dielectric stack in which the collector layer 1302 is formed is at least partially defined by the reverse sidewall 1202. The collector layer 1302 is located on the n-type doped sub-collector diffusion region 204 in the semiconductor substrate 102. The base layer 1502 (e.g., a single-crystal base layer 1502a) is located above the collector layer 1302 (e.g., on top), and the base layer 1502 (e.g., a polycrystalline base layer 1502c) is located above the upper surface of the fourth base oxide sublayer 304g (e.g., on top).

[0098] A substrate dielectric stack is located in the BJT region 104 and beneath the base layer 1502. The portion of the substrate dielectric stack directly beneath the base layer 1502 (e.g., comprising substrate oxide sublayers 304g, 302h, 124e, 122e) has a first thickness. The substrate dielectric stack (e.g., a fourth substrate oxide sublayer 304g and a third substrate oxide sublayer 302h) has sidewalls 2902, 2904 aligned with corresponding sidewalls of the base layer 1502. The substrate dielectric stack has a first thickness laterally located between the sidewalls 2902, 2904. The substrate dielectric stack (e.g., a third substrate oxide sublayer 302h, a second substrate oxide sublayer 124e, and a first substrate oxide sublayer 122e) extends laterally from the base layer 1502 (e.g., a polycrystalline base layer 1502c). For example, a substrate dielectric stack extends over the upper surface 120 of the semiconductor substrate 102 above the n-type doped sub-collector diffusion region 204, and laterally away from the corresponding sidewall of the polycrystalline base layer 1502c (and the aligned sidewall 2902 of the substrate dielectric stack) to reach the sidewall 3202 near the n-type collector contact region 3612. Additionally, a substrate dielectric stack (e.g., a third substrate oxide sublayer 302g) extends laterally over the first portion 132a of the isolation structure 132, away from the corresponding sidewall of the polycrystalline base layer 1502c (and the aligned sidewall 2904 of the substrate dielectric stack) to reach the sidewall 3204 above the first portion 132a of the isolation structure 132. The substrate dielectric stack has a second thickness laterally located between the sidewalls 2902 and 3202, and a third thickness laterally located between the sidewalls 2904 and 3204. The second and third thicknesses of the base dielectric stack are each less than the first thickness of the base dielectric stack.

[0099] In some instances, the substrate dielectric stack (e.g., a substrate oxide stack) may contain nitrogen in the sublayers and at the interfaces between said sublayers and other sublayers. For example, as described above, if the fourth substrate sacrificial nitride sublayer 304a fails to pass through... Figure 5A and 5B as well as Figure 7A and 7B If the oxidation process is complete, then the fourth base oxide sublayer 304g may contain nitrogen at the interface between the fourth base oxide sublayer 304g and the third base oxide sublayer 302h.

[0100] Emitter layer 2002 (e.g., monocrystalline emitter layer 2002a) is located above (e.g., on top of) base layer 1502 (e.g., monocrystalline base layer 1502a) and passes through an opening defined by the spacer structure, and emitter layer 2002 (e.g., polycrystalline emitter layer 2002c) is located above (e.g., on top of) the spacer structure. Figure 37A and 37BIn the semiconductor device 3700, the spacer structure includes a second dielectric spacer 1604b, a third dielectric spacer 1606d, and an emitter dielectric spacer 1802a. Figure 44A and 44B In the semiconductor device 4400, the spacer structure includes a first dielectric spacer 3802d and a second dielectric spacer 3804b.

[0101] Metal-semiconductor compound 3702 is located on emitter layer 2002 (e.g., polycrystalline emitter layer 2002c and / or monocrystalline emitter layer 2002a). Metal-semiconductor compound 3706 is located on the upper surface 120 of semiconductor substrate 102 on n-type collector contact region 3612. Figure 37A and 37B In the semiconductor device 3700, a metal-semiconductor compound 3704 is located on the raised base layer 2702a. Figure 44A and 44B In the semiconductor device 4400, the metal-semiconductor compound 3704 is located on the base layer 1502 (e.g., the polycrystalline base layer 1502c).

[0102] In some instances, the BJT may be a heterojunction BJT. As previously indicated, in some instances, the collector layer 1302 and emitter layer 2002 may be silicon, and the base layer 1502 may comprise silicon germanium. Therefore, in some instances, the base layer 1502 may comprise a semiconductor material dissimilar to the corresponding semiconductor materials of the collector layer 1302 and emitter layer 2002. These dissimilar semiconductor materials may form one or more heterojunctions in the BJT, and thus, the BJT may be a heterojunction BJT.

[0103] Each of the illustrated semiconductor devices 3700 and 4400 includes a pFET in pFET region 110 and an nFET in nFET region 112. pFET region 110 and nFET region 112 are located within a CFET region. The pFET includes a gate electrode 802b, a gate oxide layer 702a, an embedded stress source 3402, a PSD region, a p-type LDD 3312, and a channel region in the semiconductor substrate 102 below the gate electrode 802b. The gate electrode 802b is located above (e.g., on) the gate oxide layer 702a, and the gate oxide layer 702a is located above (e.g., on) the upper surface 120 of the semiconductor substrate 102. The p-type LDD 3312 is located on the laterally opposite side of the gate electrode 802b and within the semiconductor substrate 102. The channel region is laterally located between the p-type LDDs 3312. An embedded stress source 3402 and a PSD region are located on laterally opposite sides of the gate electrode 802b, with a p-type LDD 3312 and a channel region between the embedded stress source and the PSD region. Similarly, an nFET includes a gate electrode 802c, a gate oxide layer 502b, an NSD region 3614, an n-type LDD 3314, and a channel region in the semiconductor substrate 102 below the gate electrode 802c. The gate electrode 802c is located above (e.g., on) the gate oxide layer 502b, and the gate oxide layer 502b is located above (e.g., on) the upper surface 120 of the semiconductor substrate 102. The n-type LDD 3314 is located on the laterally opposite sides of the gate electrode 802c and in the semiconductor substrate 102. The channel region is laterally located between the n-type LDDs 3314. The NSD region 3614 is located on the laterally opposite sides of the gate electrode 802c, with an n-type LDD 3314 and a channel region between the NSD regions. pFET and nFET can be complementary devices (e.g., complementary metal-oxide-semiconductor (CMOS) devices). In some instances, pFET can be a p-type metal-oxide-semiconductor (PMOS) transistor, and nFET can be an n-type metal-oxide-semiconductor (NMOS) transistor.

[0104] The first transition region 106 is located between the BJT region 104 and the CFET region (e.g., in the illustrated example, the CFET region has the boundary of the pFET region 110). The second transition region 108 extends from the boundary of the BJT region 104 (e.g., opposite the first transition region 106). A composite structure may be retained in the first transition region 106 and / or the second transition region 108. The composite structure may include corresponding residues of various layers or materials formed during semiconductor processing and / or may be one or more processed articles. Figure 37A and 44AAs described above, the composite structure includes a residual gate layer 802d and a residual polycrystalline base layer 1502d located on the sidewall 904 of the residual gate layer 802d. The composite structure also includes a residual substrate dielectric stack comprising residual substrate oxide sublayers 304h, 302g, 124f, and 122f. In some instances, the residual substrate dielectric stack may contain nitrogen as described above, wherein the substrate dielectric stack is formed from BJTs in the BJT region 104. For example, the residual fourth substrate oxide sublayer 304h may contain nitrogen at the interface between the residual fourth substrate oxide sublayer 304h and the residual third substrate oxide sublayer 302g. Furthermore, in some instances, the composite structure may include a residual polycrystalline emitter spacer. The composite structure may include one or more other residual dielectric spacers. In other instances, the composite structure including such residual spacers or residual layers may not be formed in the first transition region 106 and / or the second transition region 108.

[0105] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations may be made therein without departing from the scope defined by the appended claims.

Claims

1. A semiconductor device comprising: Semiconductor substrate; A substrate dielectric stack is located above the semiconductor substrate. The substrate dielectric stack contains nitrogen at the interface between a first sublayer and a second sublayer of the substrate dielectric stack. An opening extends through the substrate dielectric stack to the semiconductor substrate. The opening is at least partially defined by a retrograde sidewall that extends retrogradely into the substrate dielectric stack from away from the semiconductor substrate to near the semiconductor substrate. and A bipolar junction transistor (BJT) is located on the semiconductor substrate, with at least a first portion of the BJT located on the upper surface of the semiconductor substrate and in the opening through the base dielectric stack, and at least a second portion of the BJT further located above the base dielectric stack.

2. The semiconductor device of claim 1, wherein the retrograde sidewall comprises a sidewall portion having an upper overhang portion and a lower retrograde portion, a first dimension orthogonal to the upper surface of the semiconductor substrate between the upper overhang portion and the lower retrograde portion, a second dimension parallel to the upper surface of the semiconductor substrate between the upper overhang portion and the lower retrograde portion, and the ratio of the first dimension to the second dimension being equal to or less than 1.

376.

3. The semiconductor device of claim 1, wherein the base dielectric stack comprises: A first substrate oxide sublayer is located above the semiconductor substrate; and A second base oxide sublayer is located above the first base oxide sublayer, the second base oxide sublayer containing the nitrogen, and the interface is located between the first base oxide sublayer and the second base oxide sublayer.

4. The semiconductor device according to claim 1, wherein: The BJT includes: A collector layer is located on the semiconductor substrate, and the collector layer is located in the opening through the base dielectric stack; A base layer, which is located on the collector layer, and the base layer is located above the base dielectric stack; and An emitter layer is located on the base layer.

5. A method comprising: Forming a dielectric stack, comprising: A first oxide sublayer is formed above the semiconductor substrate; A sacrificial nitride sublayer is deposited above the first oxide sublayer; and The sacrificial nitride sublayer is oxidized, wherein the oxidation of the sacrificial nitride sublayer forms a second oxide sublayer above the first oxide sublayer; and The dielectric stack is etched with an etchant to form an opening through the dielectric stack to the semiconductor substrate, the opening being at least partially defined by a retrograde sidewall.

6. The method of claim 5, wherein the etchant etches the first oxide sublayer laterally at a rate greater than the etchant etches the second oxide sublayer laterally.

7. The method of claim 5, wherein the retrograde sidewall comprises a sidewall portion having an upper overhang portion and a lower retrograde portion, a first dimension orthogonal to the upper surface of the semiconductor substrate between the upper overhang portion and the lower retrograde portion, a second dimension parallel to the upper surface of the semiconductor substrate between the upper overhang portion and the lower retrograde portion, and the ratio of the first dimension to the second dimension being equal to or less than 1.

376.

8. The method of claim 5, further comprising epitaxially growing a semiconductor material on the semiconductor substrate and in the opening.

9. The method of claim 5, wherein oxidizing the sacrificial nitride sublayer further forms a gate oxide layer of a field-effect transistor on the semiconductor substrate.

10. The method of claim 9, further comprising epitaxially growing the collector layer of the bipolar junction transistor on the semiconductor substrate and in the opening.

11. The method according to claim 5, wherein: Forming the first oxide sublayer comprises: An oxidation process is performed on the semiconductor substrate to form the first oxide sublayer; and Dopant is implanted into the semiconductor substrate through the first oxide sublayer; implanting the dopant will damage the first oxide sublayer. Forming the dielectric stack further includes depositing a third oxide sublayer over the first oxide sublayer, wherein the sacrificial nitride sublayer is deposited over the third oxide sublayer; and During the etching of the dielectric stack with the etchant, the lateral etching rate of the first oxide sublayer to the etchant is greater than the lateral etching rate of the third oxide sublayer to the etchant, and the lateral etching rate of the third oxide sublayer to the etchant is greater than the lateral etching rate of the second oxide sublayer to the etchant.

12. A method comprising: Forming a dielectric stack, comprising: A first dielectric layer is formed above the semiconductor substrate; A second dielectric layer is deposited above the first dielectric layer, the second dielectric layer comprising nitrogen; and The second dielectric layer is processed such that the lateral etching rate of the second dielectric layer on the etchant is less than the lateral etching rate of the first dielectric layer on the etchant. and Forming an opening through the dielectric stack involves etching the dielectric stack using the etchant.

13. The method of claim 12, wherein the opening is at least partially defined by a retrograde sidewall.

14. The method of claim 13, wherein the retrograde sidewall comprises a sidewall portion having an upper overhang portion and a lower retrograde portion, a first dimension orthogonal to the upper surface of the semiconductor substrate between the upper overhang portion and the lower retrograde portion, a second dimension parallel to the upper surface of the semiconductor substrate between the upper overhang portion and the lower retrograde portion, and the ratio of the first dimension to the second dimension being equal to or less than 1.

376.

15. The method of claim 12, wherein processing the second dielectric layer comprises performing an oxidation process.

16. The method of claim 15, wherein the oxidation process further forms a gate oxide layer of a field-effect transistor on the semiconductor substrate.

17. The method of claim 16, further comprising epitaxially growing the collector layer of the bipolar junction transistor on the semiconductor substrate and in the opening.

18. The method of claim 12, wherein processing the second dielectric layer degasses at least some of the nitrogen.

19. The method according to claim 12, wherein: The first dielectric layer is an oxide layer; The deposited second dielectric layer is a nitride layer; and Processing the second dielectric layer will oxidize the second dielectric layer.

20. The method of claim 19, wherein: Forming the first mesonoelectronic layer includes: An oxidation process is performed on the semiconductor substrate to form the first dielectric layer; and Dopant is implanted into the semiconductor substrate through the first dielectric layer; implanting the dopant will damage the first dielectric layer. The formation of the dielectric stack further includes depositing a third dielectric layer, which is an oxide layer, over the first dielectric layer, and depositing the second dielectric layer over the third dielectric layer; and After processing the second dielectric layer, the lateral etching rate of the second dielectric layer on the etchant is less than the lateral etching rate of the third dielectric layer on the etchant, and the lateral etching rate of the third dielectric layer on the etchant is less than the lateral etching rate of the first dielectric layer on the etchant.

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