P-type nitride-based transistor

Abstract

The invention relates to a p-type nitride-based transistor. A semiconductor device (500) includes a first semiconductor material (510, 515), which in turn includes a bipolar junction transistor (BJT) (504); and a second semiconductor material (550, 555, 560) on the first semiconductor material (510, 515). The second semiconductor material includes a field effect transistor (FET) (502). The BJT (504) and the FET (502) are coupled to each other such that a drain (585) current of the FET is boosted and supplied at an emitter (540) terminal of the BJT.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more particularly to p-type nitride-based transistors. Background Technology

[0002] High electron mobility transistors (HEMTs) may include heterojunctions, with channels formed near the heterojunctions. Heterojunctions can be formed using different semiconductor materials. The channels can be turned on or off by applying an appropriate voltage to the gate structure. Gallium nitride (GaN)-based HEMT devices typically exhibit high breakdown electric field, high electron mobility, low resistance, high current, faster switching speed, high thermal conductivity, and excellent reverse recovery performance, making them suitable for applications requiring low loss and high efficiency, such as power electronic devices (e.g., power switches), radio frequency (RF) circuits, and so on. Summary of the Invention

[0003] The present invention is provided to illustrate the disclosed concepts in a simplified form, and these examples will be further described in the detailed description below (including the provided drawings).

[0004] According to certain aspects, a semiconductor device may include: a first semiconductor material that includes a bipolar junction transistor (BJT); and a second semiconductor material located on the first semiconductor material and including a high electron mobility transistor.

[0005] According to some aspects, a method of manufacturing a semiconductor device includes forming a first semiconductor material having a bipolar junction transistor (BJT); and forming a second semiconductor material having a high electron mobility transistor on the first semiconductor material.

[0006] The foregoing summary provides a fairly broad overview of various features of the examples disclosed herein in order to better understand the following detailed description. Additional features and advantages of such examples will be described below. The described examples can be readily used as a basis for modifying or designing other examples within the scope of the appended claims.

[0007] This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used alone to define the scope of the claimed subject matter. The subject matter should be understood with reference to the appropriate portions of the entire specification, any or all drawings, and each claim. The foregoing, together with other features and examples, will be described in more detail below in the description, claims, and accompanying drawings. This summary is provided to present examples of the disclosed concepts in a simplified form, which will be further described in the detailed description below (including the provided drawings). Attached Figure Description

[0008] The following description of illustrative examples is based on the diagrams provided below.

[0009] Figure 1 These are cross-sectional views of high electron mobility transistors (HEMTs) based on some examples.

[0010] Figure 2A This is a cross-sectional view of a semiconductor device including a p-type enhancement-mode field-effect transistor (FET) and an enhancement-mode HEMT, based on some examples.

[0011] Figure 2B These are cross-sectional views of semiconductor devices including p-type depletion mode FETs and depletion mode HEMTs, based on some examples.

[0012] Figure 3 This is a circuit diagram of a p-type FET and HEMT configured as a half-bridge based on some examples.

[0013] Figure 4 These are circuit diagrams of p-type FETs and HEMTs configured as inverters based on some examples.

[0014] Figure 5A These are cross-sectional views of semiconductor devices including p-type FETs and bipolar junction transistors (BJTs) based on some examples.

[0015] Figure 5B It is based on some examples Figure 5A A circuit diagram of a semiconductor device, the semiconductor device including an electrical connection between a p-type FET and a BJT.

[0016] Figure 6 , 7 And 8 is based on some examples. Figure 5A A cross-sectional view of a semiconductor device, the semiconductor device including an electrical connection between a p-type FET and a BJT.

[0017] Figure 9 It is a plan view of the connection between a p-type FET and a BJT contained in a semiconductor device, based on some examples.

[0018] Figure 10A The diagram shows a cross-sectional view of a semiconductor device according to some examples, the semiconductor device including a p-type FET, an npn BJT and a plurality of pn junctions suitable for forming a Zener diode.

[0019] Figure 10B Based on some examples Figure 10A The circuit diagram of the semiconductor device shown in the figure.

[0020] Figure 10CThe cross-sectional view of a semiconductor device according to some examples includes a p-type FET, an npn BJT, and a plurality of pn junctions suitable for forming a Zener diode.

[0021] Figure 11A This is a cross-sectional view of a semiconductor device including a HEMT and multiple Zener diodes, based on some examples.

[0022] Figure 11B It is based on some examples Figure 11A The circuit diagram of the semiconductor device shown in the figure.

[0023] Figure 11C This is a cross-sectional view of a semiconductor device including a HEMT and multiple Zener diodes, based on some examples.

[0024] Figure 12 and 13 These are cross-sectional views of vertically stacked semiconductor devices, including p-type FETs and BJTs, in various operations of the manufacturing process, based on some examples.

[0025] Figure 14 and 15 This explains based on some examples. Figure 12 and 13 The flowchart of the manufacturing process described herein.

[0026] The drawings and accompanying detailed description are provided to understand the features of various examples and do not limit the scope of the appended claims. Examples illustrated in the drawings and described in the accompanying detailed description can be readily used as the basis for modifications or designs of other examples within the scope of the appended claims. Those skilled in the art will readily recognize from the following description that alternative embodiments of the illustrated structures and methods may be employed without departing from the principles of this disclosure or the benefits proclaimed. Where possible, the same reference numerals may be used to refer to the same elements shared between the drawings. The drawings are drawn to clearly illustrate relevant elements or features and are not necessarily drawn to scale. Detailed Implementation

[0027] This disclosure relates to semiconductor devices. In one example, the semiconductor device includes a p-type field-effect transistor (FET) and a bipolar junction transistor (BJT), the BJT being located below the p-type FET and configured to increase the drain current of the p-type FET. In one example, the BJT is an np-nBJT located below the p-type FET and contained in a first semiconductor material, and the p-type FET is contained in a second semiconductor material different from the first material. The BJT and p-type FET are configured such that the drain current of the p-type FET is boosted and supplied by the emitter terminal of the BJT. The increased current of the p-type FET makes it suitable for a variety of applications. For example, the p-type FET can be used with an n-type HEMT to form a half-bridge, inverter, etc. The semiconductor device may advantageously include multiple pn junctions configured as one or more Zener diodes to protect the gates of the p-type FET and HEMT from high voltage and current. The p-type FET and HEMT may be GaN-based field-effect transistors.

[0028] For example, a GaN-based HEMT (Heated Metal-Oxide-Transistor) GaN-based field-effect transistor may comprise a heterojunction formed of a channel layer (e.g., a GaN layer) and a barrier layer (e.g., an aluminum gallium nitride (AlGaN) layer). A high-density two-dimensional electron gas (2DEG) region can be formed at the heterojunction as the transistor channel. For example, the 2DEG layer may have a density greater than approximately 1.0 × 10⁻⁶. 13 cm -2 GaN-based HEMTs exhibit high sheet charge density and therefore low static on-state resistance. Due to their high breakdown field, high electron mobility, low static resistance, and high thermal conductivity, GaN-based HEMTs are suitable for high-frequency and high-power applications. However, the relatively low current of p-type GaN-based HEMTs limits their potential applications. Embodiments of this disclosure overcome these drawbacks of p-type GaN-based HEMTs by integrating a BJT transistor configured to enhance the drain current of the HEMT within a semiconductor structure containing the p-type GaN-based HEMT.

[0029] Various features are described below with reference to the figures. The illustrated examples may not possess all the aspects or advantages shown. The aspects or advantages described in connection with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so stated or explicitly described. Furthermore, the methods described herein may be described with a specific order of operations, but other methods according to other examples may be implemented with various other orders of operations (e.g., different serial or parallel executions involving various operations).

[0030] Various examples are described herein. While specific examples may illustrate various aspects of the features generally described above, examples may be incorporated into any combination of features generally described above (which are described in more detail in the examples below). For ease of reference, the three-dimensional xyz axes are illustrated in some figures. Some cross-sectional views of various semiconductor devices in this document serve as general depictions for illustrating various aspects or concepts of such semiconductor devices. More specifically, some drain contact structures illustrated in the cross-sectional views may not necessarily accurately depict the structure of such drain contact points beyond what is described herein. The illustration of these drain contact structures is intended to illustrate various aspects or concepts of those drain contact structures.

[0031] Various examples are described in the context of HEMTs. Some examples may be implemented in enhancement-mode side-facing HEMTs for high-voltage (e.g., about 650 V to about 1,200 V) or low-to-medium-voltage (e.g., about 10 V to about 100 V, or about 10 V to about 200 V) applications. In other examples, the semiconductor device may comprise a bidirectional field-effect transistor (FET), a gated Schottky barrier diode (e.g., a gate-to-drain shorted structure or a gate-to-source shorted structure), or similar devices. Some examples may be implemented with any epitaxial structure, any field plate and / or ohmic contact structure, planar or three-dimensional structure (e.g., fin structure), and / or various other modifications.

[0032] For the purposes of illustration, some of the examples disclosed herein may focus on group III nitride-based devices, such as GaN-based HEMTs. However, this disclosure is not limited to GaN-based HEMTs and can be applied to other devices comprising heterostructures formed of other semiconductor materials (e.g., other group III nitrides or other III-V semiconductor materials), wherein the heterostructures can sense 2DEG at the heterojunction interface.

[0033] In the following description, specific details are set forth for illustrative purposes to provide a thorough understanding of examples of this disclosure. However, it will be apparent, however, that various embodiments may be practiced without these specific details. For example, apparatuses, systems, structures, assemblies, integrated circuits, and other components may be shown as components in block diagram form to avoid obscuring examples with unnecessary details. In other instances, well-known apparatuses, processes, systems, structures, and techniques may be shown without the need for necessary details to avoid obscuring examples. The drawings and descriptions are not intended to be limiting. The terminology and expressions used in this disclosure are used as descriptive rather than limiting terms, and their use is not intended to exclude any equivalents of the features or portions thereof shown and described. The word “example” is used herein to mean “serving as an example, illustration, or description.” Any embodiment or design described herein as an “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0034] GaN-based HEMTs incorporate heterostructures that can induce a two-dimensional electron gas (2DEG) at the interface between two GaN-based materials with different band gaps. In one example, the heterostructure may consist of a GaN layer and an Al layer. x Ga (1-x) An N-layer is formed, where x is the concentration of aluminum. The GaN layer can have higher aluminum content than Al. x Ga (1-x) N layers with narrow band gaps, the Al x Ga (1-x) The N-layer, due to its relatively wide bandgap, can be called a barrier layer. Due to the bandgap mismatch, large conduction band shift, and spontaneous and piezoelectric polarization properties of the group III nitride layer, a high-mobility 2DEG can be generated in the GaN layer near the heterostructure interface, forming a conductive channel (hence the name "channel layer"). Compared to silicon-based transistors, GaN-based transistors typically exhibit high breakdown electric field, high electron mobility, low on-state resistance, high current, faster switching speed, high thermal conductivity, and excellent reverse recovery performance, making them more suitable for applications where low loss and high efficiency are expected, such as power electronic devices (e.g., power switches).

[0035] GaN-based transistors may include a gate structure located between a source structure and a drain structure. The drain structure may include metal contacts that are directly or indirectly (e.g., via tunneling) coupled to the channel layer and may form an ohmic contact with the channel layer. The source structure may include metal contacts that are directly or indirectly coupled to the channel layer and may form an ohmic contact with the channel layer. Depending on the architecture of the gate structure, GaN-based transistors may be enhancement-mode high electron mobility transistors (e-HEMTs) or depletion-mode high electron mobility transistors (d-HEMTs). For example, the gate structure of an e-HEMT may include a p-GaN layer formed above a barrier layer and gate electrical contacts (metal electrodes) formed on the p-GaN layer, which together form the p-GaN gate structure. The p-GaN layer of the gate structure may be doped with, for example, magnesium (Mg), which is a acceptor that allows the GaN layer to be p-type or p-doped. When no gate drive voltage is applied to the gate contacts, the p-GaN layer can deplete electrons in the 2DEG channel beneath the p-GaN gate structure, disabling the conductive path between the source and drain, and thus turning off the e-HEMT. When a positive voltage above the gate threshold voltage is applied to the gate contacts, the gate structure attracts electrons, allowing the 2DEG beneath the gate structure to fill with electrons, thereby turning on the e-HEMT. In contrast, the gate structure of a d-HEMT may include an insulating layer (e.g., a dielectric layer) above a barrier layer and gate contacts (e.g., metal electrodes) on the insulating layer. When no voltage signal is applied to the gate contacts, the 2DEG beneath the gate structure may not be depleted, allowing the conductive path in the channel layer between the drain and source structures to be enabled even without a positive gate voltage. A negative gate voltage can be applied to the gate contacts to turn off the d-HEMT, depleting electrons from the 2DEG beneath the gate structure. In some applications, such as switch-mode power supply applications (e.g., power switches), e-HEMT can be used instead of d-HEMT, for example, to reduce leakage current, reduce power loss, simplify driver circuitry, and / or improve device stability.

[0036] Figure 1 This is a cross-sectional view of an example of a high electron mobility transistor (HEMT) 100. In the illustrated example, the HEMT 100 is an e-mode GaN-based transistor, comprising a substrate 110, a channel layer 120, a barrier layer 130, a gate structure, a source structure, and a drain structure. The substrate 110 may comprise, for example, a silicon substrate, a silicon carbide substrate, a semiconductor-on-insulator (SOI) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, or an engineered GaN substrate (Qromis). TMThe substrate 110 may be a QST (Quick Substrate Technology) substrate, a substrate comprising another semiconductor material with a bandgap wider than that of silicon, or any other suitable substrate. In one example, substrate 110 may comprise a bulk silicon substrate and may also comprise one or more transition or buffer layers of suitable material to accommodate lattice mismatch between substrate 110 and channel layer 120 (e.g., to reduce or minimize the generation and / or propagation of lattice defects in channel layer 120). For example, the transition or buffer layer may have a gradient concentration of one or more elements in the surface normal direction (e.g., the z-direction) of substrate 110 to gradually change the lattice constant.

[0037] The channel layer 120 and barrier layer 130 can be epitaxially grown on the substrate 110 to form a heterostructure. Because the band structures of the channel layer 120 and barrier layer 130 are different, the heterostructure can induce a 2DEG 122 layer near the interface between the channel layer 120 and barrier layer 130. The 2DEG 112 can conduct current in a two-dimensional plane (e.g., the xy plane). In some instances, the channel layer 120 may be part of the substrate 110. The channel layer 120 may comprise, for example, a GaN layer, an AlGaN layer, or an InAlN layer. In some instances, the material of the channel layer 120 may comprise an unintentionally doped material, such as a material doped by diffusion from a dopant from another layer, or a material containing intrinsic material. The barrier layer 130 may comprise, for example, an AlGaN layer. Other materials may also be used for the channel layer 120 and barrier layer 130. For example, the channel layer 120 may comprise indium aluminum gallium nitride (InAlGaN). i Al j Ga 1-i-j N) (where 0≤i≤1, 0≤j≤1 and 0≤i+j≤1), and the barrier layer 130 may contain indium aluminum gallium nitride (In k Al l Ga 1-k-l N) (where 0≤k≤1, 0≤l≤1 and 0≤k+l≤1).

[0038] The gate structure of HEMT 100 may include a gate semiconductor layer 140 located above the upper surface of the barrier layer 130. In some instances, the gate semiconductor layer 140 may include a p-doped semiconductor layer. For example, the gate semiconductor layer 140 may include a GaN layer, or more generally, an In... m Al n Ga 1-m-nAn N-layer (where 0 ≤ m < 1, 0 ≤ n < 1, and 0 ≤ m + n ≤ 1). The p-type dopant used to dope the gate semiconductor layer 140 may include magnesium (Mg), carbon (C), zinc (Zn), etc., or combinations thereof. In examples where the gate semiconductor layer 140 comprises GaN doped with a p-type dopant, the gate semiconductor layer 140 may be referred to as a p-GaN layer. In some examples, the concentration of the electrically activated dopant in the gate semiconductor layer 140 may be equal to or greater than about 1 × 10⁻⁶. 17 cm -3 In some instances, the concentration may be equal to or greater than approximately 1 × 10⁻⁶. 18 cm -3 Other materials, dopants, and / or concentrations may be used in other instances. The gate semiconductor layer 140 may be formed by epitaxial growth using an etch mask and selective etching, or by selective region growth using a growth mask. The etch mask or growth mask defines the shape and size of the gate semiconductor layer 140. The doping density and thickness of the p-doped gate semiconductor layer 140, as well as the thickness of the barrier layer 130 beneath the gate semiconductor layer 140, may be selected such that the p-doped gate semiconductor layer 140 depletes the 2DEG 122 beneath the gate semiconductor layer 140, thereby turning off the HEMT 100 without a positive gate voltage and turning it on by applying a positive voltage to the gate structure.

[0039] A gate electrical contact 142 may be formed on the gate semiconductor layer 140 to apply a gate voltage to the gate semiconductor layer 140. The gate electrical contact 142 may be electrically coupled to a gate driver circuit via electrical interconnects such as conductive traces and / or vias (not shown). In some embodiments, the gate electrical contact 142 may extend laterally beyond the gate semiconductor layer 140 to form a gate field plate, for example to reduce current breakdown and dynamic on-state resistance and increase breakdown voltage. The gate electrical contact 142 may comprise one or more metals and / or metal alloys having high conductivity.

[0040] At the source region of the HEMT 100, a source contact 144 may extend through the barrier layer 130 and contact the source region of the channel layer 120. The source contact 144 may comprise a metal or metal alloy and may form a low-barrier metal-semiconductor contact (e.g., an ohmic contact) with the channel layer 120. In some embodiments, the source contact 144 may not extend through the barrier layer 130 and may be electrically coupled to the source region of the channel layer 120 via, for example, tunneling effects. In some embodiments, one or more source field plates may be formed and coupled to the source contact 144. The source field plates may be used to reduce current breakdown and dynamic on-state resistance and / or increase the breakdown voltage of the HEMT 100.

[0041] At the drain region of HEMT 100, drain contact 146 may extend through barrier layer 130 and contact the drain region of channel layer 120. Drain contact 146 may comprise metal or a metal alloy and may form a low-barrier metal-semiconductor contact (e.g., an ohmic contact) with channel layer 120. In some embodiments, drain contact 146 may not extend through barrier layer 130 and may be electrically coupled to source region of channel layer 120 via, for example, tunneling effects.

[0042] Each of the gate contact 142, source contact 144, and drain contact 146 may comprise, for example, titanium (Ti), tungsten titanate (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), alloys, or combinations thereof. In some instances, the alloy may comprise, for example, aluminum tungsten titanate (TiWAl) or aluminum tungsten titanate (TiAlN), or combinations thereof.

[0043] In some instances, HEMT 100 may contain one or more dielectric layers. Figure 1 (Not shown in the image), the dielectric layer isolates and protects the gate structure, drain structure, and source structure. One or more dielectric layers may contain the same or different dielectric materials deposited in one or more deposition processes. For example, one or more dielectric layers may contain oxide-based or nitride-based materials, such as silicon oxide (e.g., phosphosilicate glass (PSG)), aluminum oxide, silicon nitride, etc. In some instances, one or more dielectric layers may further include one or more etch stop layers, such as silicon nitride (SiN), for controlling the etch depth of the etching process (e.g., for patterning the dielectric or metal layers).

[0044] In some instances, the electrical contacts or other metallic electrical interconnects in the HEMT 100 may each comprise one or more metal barrier layers and / or one or more adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) between a metallic material (e.g., Al, Cu, W, etc., or combinations thereof) and one or more dielectric layers. The metal barrier layers prevent metal atoms from diffusing into the dielectric layers. The adhesion layers can be used to improve the adhesion of the metallic material to the dielectric material of the one or more dielectric layers, thereby reducing or avoiding defects and reliability issues, such as interface delamination.

[0045] Figure 2A This is a cross-sectional view of semiconductor device 200, which includes a p-type enhancement-mode field-effect transistor (FET) (alternately referred to herein as a p-type e-mode FET) 270 and an enhancement-mode HEMT (alternately referred to herein as an e-mode HEMT) 280. Semiconductor device 200 is shown having a vertically stacked layer (e.g., along...). Figure 2AThe vertical layer stack (z-axis stack) partially includes a substrate (referred to herein as semiconductor material) 210, a buffer layer 220 on the substrate 210, a barrier layer 230 on the buffer layer 220, and a semiconductor layer 240 on the barrier layer 230.

[0046] The p-type e-mode FET 270 is also shown to partially include a source structure 272 and a drain structure 276, both formed on the semiconductor layer 240. The p-type e-mode FET 270 is further shown to include a gate structure 274 partially located in a recess 275. The recess 275 is formed in the semiconductor layer 240 and partially includes a dielectric layer 250 adapted to insulate the gate structure 274 from the semiconductor layer 240. The e-mode HEMT 280 is shown to partially include a source structure 282 and a drain structure 286, both formed on the barrier layer 230. The e-mode HEMT 280 is also shown to partially include a gate structure 284 located on the semiconductor layer 285. Semiconductor layers 240 and 285 may be formed during the same semiconductor manufacturing process, but they are different and not physically in contact with each other.

[0047] Figure 2B This is a cross-sectional view of semiconductor device 215, which includes a p-type depletion-mode FET (alternatively referred to herein as a p-type d-mode FET) 260 and a depletion-mode HEMT (alternatively referred to herein as a d-mode HEMT) 290. Semiconductor device 215 is shown having a vertical stack of layers, which partially includes a substrate (alternatively referred to herein as a semiconductor material) 210, a buffer layer 220 above the substrate 210, a barrier layer 230 above the buffer layer 220, and a semiconductor layer 240 above the barrier layer 230. The p-type d-mode FET 260 is shown partially including a source structure 262 and a drain structure 266, both formed above the semiconductor layer 240. The p-type d-mode FET 260 is further shown including a dielectric layer 250 above the semiconductor layer 240 and a gate structure 264 above the dielectric layer 250. The d-mode HEMT 290 is shown to partially include a source structure 292 and a drain structure 296, both formed on a barrier layer 230. The d-mode HEMT 290 is also shown to partially include a dielectric layer 275 located on the barrier layer 230, and a gate structure 294 located on the dielectric layer 275. Figure 2BIn the p-type d-mode FET 260, the thickness of the semiconductor layer 240 beneath the gate structure 264 is greater than the thickness of the semiconductor layer 240 beneath the gate structure 274 of the p-type e-mode FET 270. This increased thickness further isolates the gate structure 264 from the semiconductor layer 240 and reduces charge depletion in the semiconductor layer 240, allowing the FET 260 to become a d-mode device with a negative threshold voltage.

[0048] refer to Figure 2A and 2B In various examples, substrate 210 may comprise a silicon substrate, a silicon carbide substrate, an SOI substrate, a sapphire substrate, a GaN substrate, a GaAs substrate, an engineered GaN substrate (QST substrate), a substrate comprising another semiconductor material with a bandgap wider than that of silicon, or any other suitable substrate. In some examples, dielectric layers 250 and 275 are formed of the same dielectric material, such as silicon dioxide, etc. In some examples, buffer layer 220 comprises GaN; barrier layer 230 comprises AlGaN; and semiconductor layer 240 comprises p-type GaN (p-GaN) or other p-type nitride-based semiconductor materials. In some instances, gate structures 274, 284, 264, 294, source structures 272, 282, 262, 292, and drain structures 276, 286, 266, and 296 may comprise titanium (Ti), tungsten titanate (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), alloys, or any combination thereof. In some instances, the alloy may comprise, for example, aluminum tungsten titanate (TiWAl), aluminum nitride (TiAlN), or combinations thereof.

[0049] Figure 3 A p-type FET 305 and an n-type HEMT 310 configured as a half-bridge to perform voltage conversion (e.g., operating as a buck converter) are shown. Figure 3 In this configuration, the p-type FET 305 is configured as a high-side switch, and the n-type HEMT 310 is configured as a low-side switch. A load 320 coupled to the drain terminals of the p-type FET 305 and HEMT 310 is shown as including an inductor 322, a capacitor 324, and a resistor 326. The gate terminals of the p-type FET 305 and HEMT 310 are driven by a gate driver circuit 330. When the gate driver circuit 330 causes the p-type FET 305 to turn on and the HEMT 310 to turn off, a voltage VIN is coupled to the switch terminals (…). Figure 3The gate driver circuit 330 turns on HEMT 310 and turns off p-type FET 305, thereby charging the SW terminal. Similarly, when the gate driver circuit 330 causes HEMT 310 to turn on and p-type FET 305 to turn off, the reference voltage Vref. may be at ground potential, coupled to node A, thereby discharging the SW terminal. By controlling the relative on-time of transistors 305 and 310, the voltage at output node OUT can be set to a specified value. In one example, p-type FET 305 and HEMT 310 are enhancement-mode transistors, for example... Figure 2A The transistors shown in the image. In another example, the p-type FET 305 and HEMT 310 are depletion-mode transistors, for example... Figure 2B The transistors shown in the image. The advantage of using a p-type FET 305 as a high-side driver is that the gate voltage of the FET 305 does not need to exceed VIN (and the SW terminal voltage, which can reach VIN) to turn on the FET 305. In contrast, if the FET 305 were an n-type transistor, the driver circuitry for the FET 305 might require a bootstrap capacitor and a charging circuitry system to allow the driver circuitry to provide a gate voltage higher than VIN to turn on the FET 305. Therefore, using a p-type FET 305 as a high-side driver simplifies the FET 305 driver circuitry.

[0050] Figure 4 A p-type FET 410 and an n-type HEMT 420 configured as inverters 400 are shown. The source terminals of the p-type FET 410 and the n-type HEMT 420 are coupled to a supply voltage Vcc and a ground potential, respectively, and the input voltage V0 and the output voltage V1 can have opposite logic states. Inverter 400 can be an example of digital logic circuitry, which can be used with other GaN semiconductor devices / systems (e.g., Figure 3 The half-bridge or high-speed GaN device system (e.g., for radio frequency (RF) applications) is integrated as part of the control circuitry system on the same substrate (e.g., substrate 210). This reduces interconnect parasitics between the control circuitry system and the GaN semiconductor device / system, reduces the overall device size, and reduces fabrication complexity and cost.

[0051] Figure 5A This is a cross-sectional view of a semiconductor device 500 based on some examples. The semiconductor device 500 is shown as including a p-type e-mode FET transistor and an npn bipolar junction transistor (BJT) configured to increase the drain current of the FET transistor, as further described below.

[0052] Semiconductor device 500 is shown to include vertically stacked layers (e.g., in...) Figure 5AThe vertical stack of layers (stacked along the z-axis) partially comprises a p-type semiconductor material 510 and an n-type semiconductor material 515 formed on the p-type semiconductor material 510. In one example, the n-type semiconductor material 515 is an epitaxial layer grown over the p-type semiconductor material 510 (alternatively referred to herein as an n-epitaxial layer). In some examples, the p-type semiconductor material 510 may be referred to as a semiconductor substrate. In other examples, the p-type semiconductor material 510 and the n-epitaxial layer 515 may be referred to together as a semiconductor substrate.

[0053] The semiconductor device 500 is also shown to partially include: an n-type semiconductor material 510 disposed between the n-type epitaxial layer 515. + Buried layer (referred to herein as region) 520, formed in the n-th epitaxial layer 515 and extending to a depth n of buried layer 520. + Settlement layer 525, p-type layer 535 formed in n-elongation layer 515, in deep n + n formed in the settlement layer 525 + Layer 530 and n formed in p layer 535 + Layer 540. As further described below, layers 530, 535 and 540 form the collector, base and emitter regions of the BJT transistor 504, respectively.

[0054] The semiconductor device 500 is also shown to partially include a buffer layer 550 on the n-epitaxial layer 515, a barrier layer 555 on the buffer layer 550, and a semiconductor layer 560 on the barrier layer 555. The semiconductor device 500 is also shown to partially include an insulating layer 565 on the semiconductor layer 560. The insulating layer 565 also covers the sidewalls and bottom of a recess 580 formed in the semiconductor layer 560. A gate structure 575 is located on the insulating layer 565 in the recess 585, and the gate structure extends partially on the insulating layer 565. The semiconductor device 500 is also shown to partially include a source structure 570 and a drain structure 585 on the semiconductor layer 560.

[0055] The gate structure 575, source structure 570, and drain structure 585 can respectively form the gate, source, and drain terminals of a p-type FET 502, which can be used as... Figure 2A Examples of p-type e-mode FET 270, such as Figure 5A As shown in the diagram. In some instances, the gate structure 575, drain structure 585, source structure 570, and semiconductor layer 560 can be part of a p-type d-mode FET, for example... Figure 2B The p-type d-mode FET 270. Therefore, the semiconductor device 500 includes a vertical stack of p-type FET 504 and BJT 502 (e.g., along...). Figure 5A (z-axis stacking).

[0056] As further described below, the following electrical connections can be established: (i) between the collector of BJT 504 and the source of p-type FET 502; (ii) between the base of BJT 504 and the drain of p-type FET 502; and (iii) between the emitter of BJT 504 and the gate of p-type FET 502 to form various circuit systems and achieve various purposes.

[0057] In some instances, buffer layer 550 comprises a GaN layer, and semiconductor layer 560 comprises a p-GaN layer or other p-type nitride-based semiconductor layer. In some instances, barrier layer 555 comprises an AlGaN layer or an indium aluminum gallium nitride layer. (See also...) Figure 5A As illustrated in the example, the BJT transistor is formed in a first semiconductor material (e.g., substrate 510 and epitaxial layer 515), which is different from the second semiconductor material (e.g., semiconductor layer 560, barrier layer 565, and buffer layer 550) forming the p-type FET. Furthermore, the second semiconductor material is located on the first semiconductor material. As will be described below, forming the p-type FET 502 on the BJT 504 as a vertical stack reduces fabrication complexity.

[0058] Figure 5B It is based on some examples Figure 5A A circuit diagram showing the electrical connection between the p-type FET 502 and the BJT 504. (See diagram below.) Figure 5B As shown, FET 502 and BJT 504 can be connected together to form transistor 582. Transistor 582 has a current terminal 582a coupled to the source structure 570 of the p-type FET 502 and the collector 530 of the BJT 504, a gate 582b coupled to the gate structure 575 of the p-type FET 502, and a current terminal 582c coupled to the emitter 540 of the BJT 504. The drain structure 585 of the p-type FET 502 is coupled to the base 535 of the BJT 504. With this arrangement, the current conducted from current terminal 582a to current terminal 582b in transistor 582 can be controlled by the voltage at gate 582b and boosted by the BJT 504, allowing transistor 582 to be used in high power / current density applications, such as… Figure 3 Examples include the high-side switching of a half-bridge circuit, or its use in high-speed applications, such as... Figure 4 Logic circuits (e.g., inverters).

[0059] Figure 6 The image shows a cross-sectional view of a semiconductor device 500, illustrating the electrical connection between a p-type FET 502 and a BJT 504. Figure 6In the examples shown, vias 602, 604, and 606 filled with one or more conductive materials are used for vertical electrical connections. Via 602 extends vertically through semiconductor layer 560, barrier layer 555, and buffer layer 550, and is shown to couple the source structure 570 of a p-type FET 502 to the collector 530 of a BJT 504. Via 604 is also shown to extend vertically through semiconductor layer 560, barrier layer 555, and buffer layer 550, providing a connection to the emitter 540 of the BJT at the emitter substructure 590 located on semiconductor layer 560. Via 606 also extends through semiconductor layer 560, barrier layer 555, and buffer layer 550, and is shown to couple the drain structure 585 of a p-type FET 502 to the base 535 of the BJT 504. The direct electrical connection between the terminals of the p-type FET 502 and the BJT 504 is made through a vertical through-hole. Figure 6 The arrangement can reduce the parasitic relationship between the metal interconnects and the p-type FET 502 and BJT 504.

[0060] Figure 7 Showing Figure 6 The semiconductor device 500 has been further processed to include optional isolation regions 710 and 720, which are adapted to isolate the drain region of a p-type FET 502 from the source region of the p-type FET 502. Isolation region 710 is an insulating-filled trench extending from semiconductor layer 560 to between epitaxial layer 515, buried layer 525, and base layer 535. Isolation region 720 is also an insulating-filled trench extending from semiconductor layer 560 through base layer 535 to epitaxial layer 515. In this example, isolation regions 710 and 720 are shown terminating on buried layer 520. The insulating material filling isolation regions 710 and 720 may comprise any insulating or dielectric material, such as silicon oxide or silicon nitride. For example, isolation regions 710 and 720 can be advantageous when vias 602 and 606, respectively associated with the source and drain regions of the p-type FET 502, are located in the active region of the p-type FET 502, wherein current can flow between the source and drain of the p-type FET 502. Isolation regions 710 and 720 prevent short circuits from occurring between the source structure 570 and drain structure 580 of the p-type FET 502, which would otherwise occur through the semiconductor layer 560 (which may be a p-GaN layer) due to the presence of metal in vias 602, 604, and 606.

[0061] Figure 8 This is a cross-sectional view of a semiconductor device 800 based on some examples. Semiconductor device 800 and... Figure 6 Similar to the semiconductor device 500 shown, except that in the semiconductor device 800, a buried layer 520 partially defines the layer associated with the BJT 504, and a deep n+ The deposition layer 525 and p-layer 535 are positioned laterally away from the p-type FET 502, which is partially defined by the gate structure 575, source structure 570, and drain structure 585. Therefore, the p-type FET 502 and BJT 504 of the semiconductor device 800 are not vertically aligned, and the electrical connection between the terminals of the p-type FET 502 and BJT 504 can use lateral metal interconnects (e.g., metal interconnects extending laterally along the x / y axis) and... Figure 8 A higher semiconductor processing layer, not shown in the diagram, is formed. In the semiconductor device 800, the collector structure / terminal 802 is coupled to the collector region 530 of the BJT 504 using a via 602, the emitter structure / terminal 804 is coupled to the emitter region 540 of the BJT 504 using a via 604, and the base structure / terminal 806 is coupled to the base region 535 of the BJT 504 using a via 606. The collector structure 802, emitter structure 804, base structure 806, source structure 570, gate structure 575, and drain structure 585 are all conductive and provide ohmic contacts. Figure 8 In this example, since the active region of the p-type FET 502 does not overlap with the vias 602, 604, and 606, isolation regions 710 and 720 can be omitted. Because the vias 602, 604, and 606 are positioned laterally away from the active region of the p-type FET 502, isolation regions are not required in the semiconductor device 800.

[0062] Figure 9 This is a plan view of a semiconductor device 900 including a p-type FET 502 and a BJT 504, based on some examples. The semiconductor device 900 may correspond to... Figure 8 In semiconductor device 800, the associated p-type FET 502 and BJT 504 are not vertically aligned. Therefore, in semiconductor device 900, the base structure 535, emitter structure 540, and collector structure 530 are coupled to their respective base, emitter, and collector regions using their respective vias, for example... Figure 8 As shown in the image.

[0063] The p-type FET 502 is shown as including a drain structure 585, a gate structure 575, and a source structure 570. In order to... Figure 5BThe p-type FET 502 is connected to the BJT 504 in the manner shown to increase the drain current of the p-type FET 502. A drain structure 585 is coupled to a base structure 535 using a metal interconnect 950. A collector structure 530 is coupled to a source structure 570 using a metal interconnect 952. A gate structure 575 is coupled to a metal interconnect 954, and an emitter structure 540 is coupled to a metal interconnect 956. Therefore, the device structure 900 is operated by controlling the relative voltages applied to the device terminals defined by metal interconnects 952, 954, and 956.

[0064] In some instances, the base-emitter junction of the BJT in a semiconductor device, as described herein, can be configured as a Zener diode to protect the p-type FET or HEMT of the semiconductor device from high voltage and / or high current. When configured in this way, the base of the BJT forms the anode of the Zener diode, and the emitter of the BJT forms the cathode of the Zener diode.

[0065] Figure 10A This is a cross-sectional view of a semiconductor device 1000 including a p-type FET and an npn BJT. The semiconductor device 1000 is similar to... Figure 5A The semiconductor device 500 shown includes additional p-type regions 1010 and 1020 formed within the n-type region 515, in addition to semiconductor device 1000 being partially included in the n-type region 515. The p-type region 1010 includes n-type regions suitable for forming a first pair of back-to-back Zener diodes. + Regions 1012 and 1014, and p-type region 1020 contains n-type diodes suitable for forming a second pair of back-to-back Zener diodes. + Regions 1022 and 1024. To protect the gate 575 of the p-type FET 502 from high voltage and high current, in some instances, the gate structure 575 of the p-type FET 502 is coupled to the n-type FET 502. + Regions 1012 and 1022; the source structure 570 of the p-type FET 502 is coupled to the n-type FET. + Region 1014; and the emitter region 540 of the BJT 502 is coupled to n + Region 1024. p-type region 1010 further includes p for contact with it. + Region 1015. Similarly, p-type region 1020 further includes p for contact with it. + Area 1025. Figure 10A The connections between the various terminals of the p-type FET 502, BJT 504 and Zener diode are not shown, but can be achieved using a variety of techniques, such as conductive filled vias and / or metal interconnects, as described in detail above.

[0066] Figure 10B yes Figure 10AA schematic diagram of the semiconductor device 1000 is shown below. References are also made below. Figure 10A and 10B Zener diode 1060 represents Figure 10A The diode between the n+ region 1012 and the p region 1010, its cathode terminal ( Figure 10A The n+ region 1012 is coupled to the gate terminal of the p-type FET 502, and the anode terminal ( Figure 10A The P-region 1010 is coupled to the anode terminal of the Zener diode 1062. The Zener diode 1062 represents... Figure 10A The diode between the n+ region 1014 and the p region 1010, its cathode terminal ( Figure 10A The n+ region (1014) is coupled to the source terminal of the p-type FET 502. The Zener diode 1070 represents... Figure 10A The diode between the n+ region 1022 and the p region 1020, its cathode terminal ( Figure 10A The n+ region 1022) is coupled to the gate terminal of the p-type FET 502, and the anode terminal ( Figure 10A The p-region 1020 is coupled to the anode terminal of the Zener diode 1072. The Zener diode 1072 represents... Figure 10A The diode between the n+ region 1024 and the p region 1020, its cathode terminal ( Figure 10A The n+ region 1024 is coupled to the emitter of the BJT 504 of the semiconductor device 1000.

[0067] Figure 10C This is a cross-sectional view of a semiconductor device 1050 including a p-type FET 502 and an npn BJT 504. Semiconductor device 1050 and... Figure 10A Similar to the semiconductor device 1000 shown, except that in semiconductor device 1050, the p-type region 1010 and the n+ region 1012 together form a first Zener diode, and the p-type region 1020 and the n+ region 1022 together form a second Zener diode. The two Zener diodes are biased to form back-to-back Zener diodes, as shown, for example, in… Figure 10B This is shown between the gate and source regions of a p-type FET502. The p-type FET formed therein... + Region 1015 is used to create contact with p-type region 1010, and the p formed therein is used. + Use region 1025 to create contact with the p-type region.

[0068] Figure 11AThis is a cross-sectional view of a semiconductor device 1100 comprising an e-mode HEMT 1120 and multiple Zener diodes, based on some examples. The semiconductor device 1100 is shown to partially comprise a p-type substrate 1110, an epitaxial layer 1115, a buffer layer 1150, and a barrier layer 1155. The semiconductor device 1100 is also shown to partially comprise a semiconductor layer 1160 on which the gate structure 1175 of the HEMT 1120 is formed. The source structure 1170 and drain structure 185 of the HEMT 1120 are shown to be formed on the barrier layer 1155.

[0069] Semiconductor device 1100 is also shown as partially comprising p-type regions 1130 and 1140 formed within an n-type region 1115. The p-type region 1130 includes n+ regions 1132 and 1134 adapted to form a first pair of back-to-back Zener diodes. The p-type region 1140 includes n+ regions 1142 and 1144 adapted to form a second pair of back-to-back Zener diodes. To protect the gate structure 1175 of the HEMT 1120 from high voltage and high current, in some embodiments, the gate structure 1175 of the HEMT 1120 is coupled to n+ regions 1132 and 1142, the source structure 1170 of the HEMT 1120 is coupled to n+ region 1144, and the drain structure 1185 of the HEMT 1120 is coupled to n+ region 1134. The p-type region 1130 further includes p-type regions for contact with it. + Region 1135. Similarly, p-type region 1140 further includes p for contacting therewith. + Area 1145. Figure 11A The connections between the various terminals of the HEMT 1120 and Zener diodes are not shown, but can be achieved using a variety of techniques, such as conductive filled vias and / or metal interconnects, as described in detail above.

[0070] Figure 11B yes Figure 11A A schematic diagram of the semiconductor device 1100 is shown below. References are also made below. Figure 11A and 11B Zener diode 1160 represents Figure 11A The diode between the n+ region 1132 and the p region 1130, its cathode terminal ( Figure 11A The n+ region 1132) is coupled to the gate terminal of the HEMT 1120 of the semiconductor device 1100, and the anode terminal ( Figure 11A The p-region 1130) is coupled to the anode terminal of the Zener diode 1162. The Zener diode 1162 represents... Figure 11A The diode between the n+ region 1134 and the p region 1130, its cathode terminal ( Figure 11AThe n+ region 1134) is coupled to the drain terminal of the HEMT 1120. The Zener diode 1170 represents... Figure 11A The diode between the n+ region 1142 and the p region 1140, its cathode terminal ( Figure 11A The n+ region 1142) is coupled to the gate terminal of the HEMT 1120, and the anode terminal ( Figure 11A The p-region 1140) is coupled to the anode terminal of the Zener diode 1172. The Zener diode 1172 represents... Figure 11A The diode between the n+ region 1144 and the p region 1140, its cathode terminal ( Figure 11A The n+ region 1144) is coupled to the source end of the HEMT 1120 of the semiconductor device 1100.

[0071] Figure 11C This is a cross-sectional view of a semiconductor device 1150 including an e-mode HEMT 1120 and multiple Zener diodes, based on some examples. Semiconductor device 1150 and... Figure 11A Similar to the semiconductor device 1100 shown, except that in semiconductor device 1150, the p-type region 1130 and the n+ region 1132 together form a first Zener diode, and the p-type region 1140 and the n+ region 1142 together form a second Zener diode. The two Zener diodes are biased to form back-to-back Zener diodes, as shown, for example, between the gate and source regions of HEMT 1120. Figure 11B As shown in [the document]. Using the p formed therein + Region 1135 is used to create contact with p-type region 1130, and the p formed therein is used. + Use region 1145 to create contact with p-type region 1140.

[0072] According to some examples, a method of manufacturing a semiconductor device may include forming a first semiconductor material having a BJT, and forming a second semiconductor material having a FET on the first semiconductor material. Figure 12 This is a cross-sectional view of the np-nBJT semiconductor structure 1200 formed through multiple processing steps. To fabricate the semiconductor structure 1200, a p-type semiconductor substrate 1210 with relatively high resistivity is selected as the first semiconductor material in this example. Then, n-type BJTs are formed in the substrate. + A buried layer 1220 is formed, followed by the growth of an n-type epitaxial layer 1230. Subsequently, a deep n-type epitaxial layer is formed within the epitaxial layer. + Settling region 1240 is established to connect with the buried layer. Next, an ion implantation step is used to form a p-type base layer 1250 in the epitaxial layer. Subsequently, another ion implantation step is used to form n-type base layers 1250 and 1240, respectively. +Layers 1260 and 1270. Layers 1260, 1250 and 1270 represent the emitter, base and collector of the BJT 1204 contained in the semiconductor structure 1200, respectively.

[0073] Figure 13 This demonstrates the application of some examples in the context of... Figure 12 A semiconductor structure 1300 is formed after further processing of the semiconductor structure 1200 to include a p-type FET 1302. A buffer layer 1310 is grown (e.g., by epitaxial growth) on the semiconductor structure 1200. Next, a barrier layer 1320 is grown (e.g., by epitaxial growth) on the buffer layer 1310, and a semiconductor layer 1330 is grown (e.g., by epitaxial growth) on the barrier layer 1320. In one example, the buffer layer 1310 contains GaN, the barrier layer 1320 contains AlGaN, and the semiconductor layer 1330 contains a p-type GaN (p-GaN) layer epitaxially grown on the barrier layer 1320. A source structure 1350 providing an ohmic contact is then formed on the semiconductor layer 1330. Figure 12 and 13 In this configuration, a buffer layer 1310, a barrier layer 1320, and a semiconductor layer 1330 can be grown on the semiconductor structure 1200 and then patterned to form a p-type FET 1302. This arrangement reduces the need for wafer bonding and epitaxial regeneration processes, and reduces fabrication complexity and cost.

[0074] A recess 1380 is then formed in the semiconductor layer 1330, followed by the deposition of a gate dielectric 1340 into the recess. Next, a gate metal layer is deposited and patterned to form a gate structure 1360. Although Figure 13 Not shown in the text, but it can form isolation trenches and conductive filled vias, such as in the reference. Figure 6 and 7 As shown, an ohmic contact is formed with the emitter 1260, base 1250, and collector 1270 of the BJT 1204. Metallization is used. Figure 13 (Not shown in the text) The collector 1270 of BJT 1204 is coupled to the source 1340 of p-type FET 1302, and the base 1250 of BJT 1204 is coupled to the drain 1385 of p-type FET 1302, as described in detail above.

[0075] Figure 14 Flowchart 1400 illustrates an example of a process for fabricating a semiconductor device comprising a p-type FET and a BJT as described herein. At 1402, a first semiconductor material having a BJT is formed, for example... Figure 12 and 13The BJT 1204 is shown in the image. At 1404, a second semiconductor material with a FET is formed on the first semiconductor material, for example... Figure 13 The FET 1302 shown in the image.

[0076] Figure 15 Flowchart 1500 illustrates an example of a process for forming a second semiconductor material on a first semiconductor material, as described in flowchart 1400. At 1502, on a substrate (e.g., Figure 13 A second semiconductor material GaN buffer layer (e.g., layer 1230) is grown on the layer 1230. Figure 13 Layer 1310 shown serves as the first epitaxial layer. In some instances, the substrate may be a first semiconductor material with a BJT. At 1504, a barrier layer of a second semiconductor material (e.g., ...) is grown on the GaN buffer layer. Figure 13 Layer 1320 is shown in the diagram. At 1506, a p-GaN layer of a second semiconductor material (e.g., [missing information]) is grown on the barrier layer. Figure 13 Layer 1330 shown in the diagram serves as the second epitaxial layer. The p-GaN layer is then patterned to form a gate structure. In instances where the substrate is not the first semiconductor material, the second semiconductor material can be removed from the substrate and bonded to the first semiconductor material.

[0077] In this description, the term "coupled" may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, if intermediate component C does not alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C such that device B is controlled by control signals generated by device A.

[0078] Furthermore, in this specification, the expression "based on" means "at least partially based on". Therefore, if X is based on Y, then X may vary with Y and any number of other factors.

[0079] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) to perform a function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform a function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components, and through the interconnection of the device or a combination thereof.

[0080] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0081] The circuits or devices described herein as containing certain components may be practically adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more power sources (e.g., voltage and / or current sources) may alternatively contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some passive elements and / or sources to form the described structure, for example, by an end user and / or a third party at or after manufacturing.

[0082] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little change to the rest of the circuit system. For example, field-effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, e.g., NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0083] The claims may refer to the control input terminal and its current terminals of the transistor. In the context of a FET, the control input terminal is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input terminal is the base, and the current terminals are the collector and emitter.

[0084] In this article, "FET on" or "enabled" means that a conductive channel exists in the FET and drain current can flow through it. "FET off" or "disabled" means that no conductive channel exists, and therefore drain current does not flow through the FET. However, a "disabled" FET can have current flowing through the body diode of the transistor.

[0085] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0086] While some elements in the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Furthermore, some or all of the features described as external to the integrated circuit may be contained within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0087] The use of the phrase “grounding” in the preceding description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, or any other form of grounding connection that is applicable to or suitable for the teachings of this description.

[0088] In this specification, unless otherwise stated, “about,” “approximately,” or “generally” preceding a parameter means within + / -10% of the parameter, or, if the parameter is zero, within a reasonable range of values ​​approximately zero.

[0089] As used herein, the terms “and” and “or” can have a variety of meanings, which are expected to depend at least in part on the context in which they are used. Generally, “or” used to relate, for example, a list of A, B, or C, is intended to mean A, B, and C (used herein in an inclusive sense), and A, B, or C (used herein in an exclusive sense). Additionally, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in the singular or to describe a combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Furthermore, the term “at least one of” used to relate, for example, a list of A, B, or C, can be interpreted as meaning A, B, C, or a combination of A, B, and / or C, such as AB, AC, BC, AA, ABC, AAB, ACC, AABBCCC, etc.

[0090] Although various examples have been described in detail, it should be understood that various changes, substitutions, and modifications can be made therein without departing from the scope defined by the appended claims. The apparatus, structure, material, and process discussed above are examples. Various procedures or components may be omitted, substituted, or added where appropriate in various examples. Furthermore, features described with respect to certain examples may be combined in various other examples. Different aspects and elements of examples may be combined in a similar manner. Moreover, technological evolution, and therefore numerous elements, do not limit the scope of this disclosure to examples of those particular examples.

[0091] Specific details are given in the description to provide a thorough understanding of the examples. However, the examples may be practiced without these specific details. For example, well-known circuits, processes, systems, structures, and techniques may be shown without unnecessary details to avoid obscuring the examples. This description is merely illustrative and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the foregoing description of the examples will provide a illustrative description for those skilled in the art to implement various examples. Various changes can be made to the function and arrangement of the elements without departing from the spirit and scope of this disclosure. Modifications may be made to the described examples within the scope of the claims, and other examples are possible.

Claims

1. A semiconductor device comprising: The first semiconductor material includes a bipolar junction transistor (BJT); and A second semiconductor material is located on the first semiconductor material and includes a field-effect transistor (FET).

2. The semiconductor device of claim 1, wherein the source of the FET is coupled to the collector of the BJT at a first current terminal, the drain of the FET is coupled to the base of the BJT, and the emitter of the BJT is coupled to a second current terminal.

3. The semiconductor device of claim 2, wherein the source is at least partially electrically coupled to the collector and the first current terminal through a first via, the drain is at least partially electrically coupled to the base through a second via, and the emitter is at least partially electrically coupled to the second current terminal through a third via.

4. The semiconductor device according to claim 2, further comprising: A first metal interconnect is located on the second semiconductor material and coupled to the source, the collector and the first current terminal; A second metal interconnect is located on the second semiconductor material and coupled to the drain and the base; and A third metal interconnect is located on the second semiconductor material and coupled to the emitter and the second current terminal.

5. The semiconductor device of claim 3, further comprising a first isolation region located between the third via and the first via, and a second isolation region located between the third via and the second via.

6. The semiconductor device of claim 2, wherein the FET is a p-type FET, and wherein the second semiconductor material further comprises a high electron mobility transistor (HEMT).

7. The semiconductor device of claim 6, wherein the p-type FET and the HEMT are configured as a half-bridge, wherein the first current terminal is coupled to a power input terminal, the second current terminal is coupled to the drain of the HEMT, the source of the HEMT is coupled to a reference voltage, and the gates of the p-type FET and the HEMT are coupled to a gate driver circuit.

8. The semiconductor device of claim 6, wherein the p-type FET and the HEMT are configured as inverters.

9. The semiconductor device of claim 1, wherein the base and emitter of the BJT are configured as Zener diodes, and wherein the gate of the FET is coupled to the cathode of the Zener diode.

10. The semiconductor device of claim 1, wherein the first semiconductor material comprises: A first N-type region is configured as the collector of the BJT; a P-type region is configured as the base of the BJT. and a second N-type region, which is located in the P-type region and configured as the emitter of the BJT.

11. The semiconductor device of claim 10, wherein the first semiconductor material is an N-type epitaxial layer located on a P-type semiconductor substrate.

12. The semiconductor device of claim 1, wherein the first semiconductor material is a semiconductor substrate comprising at least one of silicon or silicon carbide.

13. The semiconductor device of claim 1, wherein the second semiconductor material comprises p-type gallium nitride (pGaN).

14. The semiconductor device of claim 11, further comprising: A third semiconductor material is located between the epitaxial layer and the second semiconductor material, and includes a GaN buffer layer; and A barrier layer is located between the second semiconductor material and the third semiconductor material.

15. The semiconductor device of claim 1, wherein the FET is a p-type FET, and wherein the gate of the p-type FET is partially located in a recess of the second semiconductor material.

16. A semiconductor device comprising: A silicon-based semiconductor material, comprising a first N-type region, a P-type region, and a second N-type region surrounded by the P-type region; The first p-type gallium nitride (p-GaN) layer is located on the silicon-based semiconductor material; A dielectric layer is located on top of the first p-GaN layer; A first terminal is located on the first p-GaN layer and configured as the source of a p-GaN transistor having a channel region partially located in the first p-GaN layer, wherein the first terminal penetrates the dielectric layer. A second terminal is located on the first p-GaN layer and configured as the drain of the p-GaN transistor, wherein the second terminal penetrates the dielectric layer; and A third terminal is located on the dielectric layer and configured as the gate of the p-GaN transistor, wherein the third terminal is laterally located between the first terminal and the second terminal.

17. The semiconductor device of claim 16, wherein the first N-type region is configured as the collector of a bipolar junction transistor (BJT), the P-type region is configured as the base of the BJT, and the second N-type region is configured as the emitter of the BJT.

18. The semiconductor device of claim 17, wherein the source is electrically coupled to the collector and the drain is electrically coupled to the base.

19. The semiconductor device of claim 16, further comprising: The second p-GaN layer is different from the first p-GaN layer and is located on the silicon-based semiconductor material; A GaN buffer layer is located below the second p-GaN layer; The fourth terminal is located on the second p-GaN layer and is configured as the gate of an n-GaN transistor; The fifth terminal, located on the GaN buffer layer and configured as the drain of the n-GaN transistor; and The sixth terminal is located on the GaN buffer layer and is configured as the source of the n-GaN transistor.

20. The semiconductor device of claim 19, wherein the n-GaN transistor and the p-GaN transistor are configured as a half-bridge, wherein the first terminal is coupled to a power input terminal, the second terminal is coupled to the fifth terminal, the sixth terminal is coupled to a reference voltage, and the third terminal and the fourth terminal are coupled to a gate driver circuit.

21. The semiconductor device of claim 19, wherein the n-GaN transistor and the p-GaN transistor are configured as inverters.

22. The semiconductor device of claim 17, wherein the base and emitter of the BJT are configured as Zener diodes, and wherein the gate of the p-GaN is coupled to the cathode of the Zener diode.

23. The semiconductor device of claim 16, wherein the silicon-based semiconductor material is an N-type epitaxial layer located on a P-type semiconductor substrate.

24. A method of manufacturing a semiconductor device, the method comprising: A first semiconductor material for forming a bipolar junction transistor (BJT); and A second semiconductor material having a field-effect transistor (FET) is formed on the first semiconductor material.

25. The method of claim 24, wherein forming the second semiconductor material on the first semiconductor material comprises: A GaN buffer layer of the second semiconductor material is grown on the first semiconductor material having the BJT as a first epitaxial layer; A barrier layer of the second semiconductor material is grown on the GaN buffer layer; and A p-GaN layer of the second semiconductor material is grown on the barrier layer as a second epitaxial layer.

26. The method of claim 24, wherein forming the second semiconductor material on the first semiconductor material comprises: A GaN buffer layer of the second semiconductor material is grown on the substrate as the first epitaxial layer; A barrier layer of the second semiconductor material is grown on the GaN buffer layer; A pGaN layer of the second semiconductor material is grown on the barrier layer as a second epitaxial layer; Remove the second semiconductor material having the GaN buffer layer, the barrier layer and the pGaN layer from the substrate; and The second semiconductor material having the GaN buffer layer, the barrier layer and the pGaN layer is bonded to the first semiconductor material having the BJT.

27. The method of claim 25, further comprising: The p-GaN layer is patterned to form a first p-GaN region and a second p-GaN region, and a portion of the barrier layer is exposed. A p-type transistor is formed by forming a first source electrode, a first drain electrode, and a first gate electrode on the first pGaN region. and An n-type transistor is formed by forming a second gate electrode on the second pGaN region and forming a second drain electrode and a second source electrode on the exposed portion of the barrier layer and on both sides of the second gate electrode.

28. The method of claim 24, further comprising: The source of the FET is coupled to the collector of the BJT at the first current terminal; The drain of the FET is coupled to the base of the BJT; and The emitter of the BJT is coupled to the second current terminal.

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