Semiconductor device

Abstract

A semiconductor device includes: a substrate including first and second active patterns spaced apart from each other in a first direction parallel to a top surface of the substrate; a first source / drain pattern on the first active pattern; a second source / drain pattern on the second active pattern; a first active contact on the first source / drain pattern; a second active contact on the second source / drain pattern; and a cutting pattern between the first active contact and the second active contact, where the cutting pattern may include: a first cutting pattern between the first active contact and the second active contact, the first cutting pattern extending toward the substrate; and a second cut pattern on at least one side surface of the first cut pattern and a bottom surface of the first cut pattern, the second cut pattern exposing at least a portion of the at least one side surface of the first cut pattern.

Description

semiconductor devices Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same, and more specifically, to semiconductor devices including field-effect transistors and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices can include integrated circuits, which include metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices continue to shrink, the size of MOSFETs is also shrinking. This miniaturization of MOSFETs can degrade the operating characteristics of semiconductor devices. Therefore, various studies have been conducted to develop methods for manufacturing semiconductor devices with superior performance while overcoming the limitations caused by the high integration density of semiconductor devices.

[0003] The information disclosed in this background section was already known or derived by the inventors before or during the implementation of the embodiments of this application, or it is technical information acquired during the implementation of the embodiments. Therefore, it may contain information that does not form prior art known to the public. Summary of the Invention

[0004] One or more example embodiments provide semiconductor devices with enhanced electrical performance.

[0005] One or more example embodiments provide a method for manufacturing a semiconductor device with enhanced reliability.

[0006] According to one aspect of an example embodiment, a semiconductor device may include: a substrate including a first active pattern and a second active pattern spaced apart from each other in a first direction parallel to a top surface of the substrate; a first source / drain pattern located on the first active pattern; a second source / drain pattern located on the second active pattern; a first active contact located on the first source / drain pattern; a second active contact located on the second source / drain pattern; and a dicing pattern located between the first active contact and the second active contact, wherein the dicing pattern may include: a first dicing pattern located between the first active contact and the second active contact and extending toward the substrate; and a second dicing pattern located on at least one side surface and a bottom surface of the first dicing pattern and exposing at least a portion of the at least one side surface of the first dicing pattern.

[0007] According to one aspect of an example embodiment, a semiconductor device may include: a substrate including a first active pattern and a second active pattern; a first source / drain pattern located on the first active pattern; a second source / drain pattern located on the second active pattern; a first active contact located on the first source / drain pattern; a second active contact located on the second source / drain pattern; and a dicing pattern located between the first active contact and the second active contact, wherein the dicing pattern may include: a first dicing pattern located between the first active contact and the second active contact. The first cutting pattern includes: a contact between the first active contact and extending toward the substrate; and a second cutting pattern located on at least one side surface and a bottom surface of the first cutting pattern, wherein the first cutting pattern may include: a first side surface facing the first active contact; and a second side surface intersecting the first side surface, wherein the second cutting pattern may include: a first cutting portion located on a first side surface of the first cutting pattern and having a first thickness; and a second cutting portion located on a second side surface of the first cutting pattern and having a second thickness, wherein the first thickness is different from the second thickness.

[0008] According to one aspect of an example embodiment, a semiconductor device may include: a substrate including a first active pattern and a second active pattern; a device isolation layer located between the first active pattern and the second active pattern; a first source / drain pattern located on the first active pattern; a first channel pattern located on the first active pattern; a second source / drain pattern located on the second active pattern; a second channel pattern located on the second active pattern; and a gate electrode extending across the first channel pattern and the second channel pattern. An active contact, the first active contact being located on the first source / drain pattern; a second active contact being located on the second source / drain pattern; and a dicing pattern being located between the first active contact and the second active contact, wherein the dicing pattern may include: a first dicing pattern being located between the first active contact and the second active contact and extending toward the substrate; and a second dicing pattern being located on at least one side surface of the first dicing pattern and on the bottom surface of the first dicing pattern, and exposing at least a portion of the at least one side surface of the first dicing pattern. Attached Figure Description

[0009] The above and other aspects, features, and advantages of specific exemplary embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which: Figures 1 to 3 are diagrams illustrating logic cells of a semiconductor device according to one or more embodiments; Figure 4 is a plan view illustrating a semiconductor device according to one or more embodiments; Figures 5A to 5E are cross-sectional views illustrating a semiconductor device according to one or more embodiments; Figure 5F is an enlarged view of portion M of Figure 4 according to one or more embodiments; Figure 5G is an enlarged view of portion N of Figure 5C according to one or more embodiments; and Figure 5H is an enlarged view of portion O of Figure 5D according to one or more embodiments. Figures 6A to 17H are diagrams illustrating methods of manufacturing a semiconductor device according to one or more embodiments; Figure 18 is a plan view illustrating a semiconductor device according to one or more embodiments; Figures 19A to 19E are cross-sectional views illustrating a semiconductor device according to one or more embodiments; Figure 19F is an enlarged view illustrating portion M of Figure 18 according to one or more embodiments; Figure 19G is an enlarged view illustrating portion N of Figure 19C according to one or more embodiments; Figure 19H is an enlarged view illustrating portion O of Figure 19D according to one or more embodiments; Figures 20 to 21H are diagrams illustrating methods of manufacturing a semiconductor device according to one or more embodiments. Detailed Implementation

[0010] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms.

[0011] As used in this article, expressions such as "at least one of..." modify the entire list of elements when they follow a list of elements, not individual elements within the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0012] It will be understood that when an element or layer is described as being "above," "on top of," "above," "below," "below," "connected to," or "combined with" another element or layer, it can be directly above, above, above, below, below, or directly connected to the other element or layer, or there can be intermediate elements or layers. In contrast, when an element is described as being directly "above," "above," "above," "below," "below," "directly connected to," or "directly combined with" another element or layer, there are no intermediate elements or layers.

[0013] Figures 1 to 3 are diagrams illustrating logic units of a semiconductor device according to one or more embodiments.

[0014] Referring to Figure 1, a single-height cell SHC can be provided. For example, a first power line M1_R1 and a second power line M1_R2 can be provided on substrate 100. The first power line M1_R1 can be a path for providing the drain voltage VDD (e.g., a power supply voltage). The second power line M1_R2 can be a path for providing the source voltage VSS (e.g., a ground voltage).

[0015] A single-height cell SHC can be defined between a first power line M1_R1 and a second power line M1_R2. A single-height cell SHC may include a p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (MOSFET) (PMOSFET) region PR and an n-type MOSFET (NMOSFET) region NR. For example, a single-height cell SHC may have a complementary metal-oxide-semiconductor (CMOS) structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0016] Each of the PMOSFET region PR and the NMOSFET region NR may have a first width W1 in the first direction D1. The first height HE1 may be defined as the length of a single-height cell SHC in the first direction D1. The first height HE1 may be substantially the same as the distance (e.g., pitch) between the first electric field line M1_R1 and the second electric field line M1_R2.

[0017] A single-height SHC can constitute a logic unit. In this specification, a logic unit can refer to a logic device that performs a specific function, such as an AND, OR, XOR, XNOR, or inverter. For example, a logic unit may include transistors for constituting a logic device, and may also include wiring connecting the transistors to each other.

[0018] Referring to Figure 2, a dual-height cell DHC can be provided. For example, a first electric field line M1_R1, a second electric field line M1_R2, and a third electric field line M1_R3 can be provided on the substrate 100. The first electric field line M1_R1 can be disposed between the second electric field line M1_R2 and the third electric field line M1_R3. The third electric field line M1_R3 can be a path used to provide the source voltage VSS.

[0019] The dual-height cell (DHC) can be defined between the second electric field line M1_R2 and the third electric field line M1_R3. The dual-height cell (DHC) may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0020] The first NMOSFET region NR1 can be adjacent to the second electric field line M1_R2. The second NMOSFET region NR2 can be adjacent to the third electric field line M1_R3. The first PMOSFET region PR1 and the second PMOSFET region PR2 can be adjacent to the first electric field line M1_R1. In the plan view, the first electric field line M1_R1 can be located between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0021] The second height HE2 can be defined as the length of the dual-height cell DHC in the first direction D1. The second height HE2 can be approximately twice the length of the first height HE1 in Figure 1. The first PMOSFET region PR1 and the second PMOSFET region PR2 of the dual-height cell DHC can work together as a single PMOSFET region.

[0022] Therefore, a dual-height cell DHC can have a PMOS transistor with a channel size larger than that of the PMOS transistor included in the single-height cell SHC discussed above in Figure 1. For example, the channel size of the PMOS transistor included in the dual-height cell DHC can be approximately twice the channel size of the PMOS transistor included in the single-height cell SHC. A dual-height cell DHC can operate at a higher speed than a single-height cell SHC. The dual-height cell DHC shown in Figure 2 can be defined as a multi-height cell. A multi-height cell can include a three-height cell with a cell height approximately three times that of a single-height cell SHC.

[0023] Referring to Figure 3, a first single-height cell SHC1, a second single-height cell SHC2, and a double-height cell DHC can be provided on the substrate 100 in a two-dimensional configuration. The first single-height cell SHC1 can be disposed between the first electric field line M1_R1 and the second electric field line M1_R2. The second single-height cell SHC2 can be disposed between the first electric field line M1_R1 and the third electric field line M1_R3. The second single-height cell SHC2 can be adjacent to the first single-height cell SHC1 in the first direction D1.

[0024] The dual-height unit DHC can be located between the second power line M1_R2 and the third power line M1_R3. The dual-height unit DHC can be adjacent to the first single-height unit SHC1 and the second single-height unit SHC2 in the second direction D2.

[0025] A separation structure DB can be provided between the first single-height unit SHC1 and the dual-height unit DHC, and between the second single-height unit SHC2 and the dual-height unit DHC. The separation structure DB can electrically isolate the active region of the dual-height unit DHC from the active regions of each of the first single-height unit SHC1 and the second single-height unit SHC2.

[0026] Figure 4 is a plan view illustrating a semiconductor device according to one or more embodiments. Figures 5A to 5E are cross-sectional views illustrating a semiconductor device according to one or more embodiments. Figure 5A shows a cross-sectional view taken along line A-A' of Figure 4. Figure 5B shows a cross-sectional view taken along line B-B' of Figure 4. Figure 5C shows a cross-sectional view taken along line C-C' of Figure 4. Figure 5D shows a cross-sectional view taken along line D-D' of Figure 4. Figure 5E shows a cross-sectional view taken along line E-E' of Figure 4. Figure 5F is an enlarged view showing portion M of Figure 4 according to one or more embodiments. Figure 5G is an enlarged view showing portion N of Figure 5C according to one or more embodiments. Figure 5H is an enlarged view showing portion O of Figure 5D according to one or more embodiments. Descriptions of aspects identical or similar to those described above may be omitted.

[0027] Referring to Figures 4 and 5A through 5E, a first single-height cell SHC1 and a second single-height cell SHC2 may be provided on substrate 100. Each of the first single-height cell SHC1 and the second single-height cell SHC2 may include a logic transistor included in a logic circuit. Substrate 100 may be a compound semiconductor substrate or a semiconductor substrate comprising silicon, germanium, or silicon-germanium.

[0028] The substrate 100 may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. Each of the first PMOSFET region PR1 and the second PMOSFET region PR2 may be an active region, and each of the first NMOSFET region NR1 and the second NMOSFET region NR2 may also be an active region. Each of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may extend in a second direction D2 that is parallel to the top surface of the substrate 100 and intersects with the first direction D1.

[0029] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed on the upper part of the substrate 100. The first active pattern AP1 may be disposed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 may be disposed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be portions of the substrate 100 that protrude from the top surface of the substrate 100 in a third direction D3 perpendicular to the top surface of the substrate 100.

[0030] The device isolation layer ST can fill the trench TR. The device isolation layer ST can include a silicon oxide layer. The device isolation layer ST can be disposed between the first active pattern AP1 and the second active pattern AP2.

[0031] A first source / drain pattern SD1 can be provided on a first PMOSFET region PR1 and a second PMOSFET region PR2. The first source / drain pattern SD1 can be disposed on a first active pattern AP1. The first source / drain pattern SD1 can be an impurity region of a first conductivity type (e.g., p-type). A first channel pattern CH1 can be located between a pair of adjacent first source / drain patterns SD1 in a second direction D2 and can be disposed on the first active pattern AP1. The first channel pattern CH1 can include semiconductor patterns SP1, SP2, and SP3 spaced apart from each other in a third direction D3 on the first active pattern AP1. A pair of first source / drain patterns SD1 can be connected to the semiconductor patterns SP1, SP2, and SP3 of the first channel pattern CH1.

[0032] A second source / drain pattern SD2 can be provided on the first NMOSFET region NR1 and the second NMOSFET region NR2. The second source / drain pattern SD2 can be disposed on the second active pattern AP2. The second source / drain pattern SD2 can be an impurity region of a second conductivity type (e.g., n-type) different from the first conductivity type. A second channel pattern CH2 can be located between a pair of adjacent second source / drain patterns SD2 in the second direction D2 and can be disposed on the second active pattern AP2. The second channel pattern CH2 can include semiconductor patterns SP1, SP2, and SP3 spaced apart from each other in the third direction D3 on the second active pattern AP2. A pair of second source / drain patterns SD2 can be connected to the semiconductor patterns SP1, SP2, and SP3 of the second channel pattern CH2.

[0033] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by selective epitaxial growth. For example, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be coplanar with the top surfaces of the first channel pattern CH1 and the second channel pattern CH2. Alternatively, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be higher than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2.

[0034] The first source / drain pattern SD1 may include a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the first channel pattern CH1. Therefore, a pair of first source / drain patterns SD1 can provide compressive stress to the first channel pattern CH1 between them. For example, the second source / drain pattern SD2 may include a semiconductor material (e.g., Si or SiC) with a lattice constant that is the same as or less than that of the second channel pattern CH2. When the second source / drain pattern SD2 includes a semiconductor material with a lattice constant less than that of the second channel pattern CH2, a pair of second source / drain patterns SD2 can provide tensile stress to the second channel pattern CH2 between them.

[0035] A gate electrode GE may be provided, extending in a first direction D1 and simultaneously across a first active pattern AP1 and a second active pattern AP2. The gate electrode GE may overlap with the first channel pattern CH1 and the second channel pattern CH2 in a vertical direction. Each gate electrode GE may surround the top surface and opposite sidewall of each of the first channel pattern CH1 and the second channel pattern CH2.

[0036] The first single-height unit SHC1 may have a first boundary BD1 and a second boundary BD2 that are opposite to each other in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The first single-height unit SHC1 may have a third boundary BD3 and a fourth boundary BD4 that are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0037] The gate cleaving pattern CT can be disposed on the third boundary BD3 and the fourth boundary BD4 of the first single-height cell SHC1. The gate cleaving pattern CT can be disposed on the boundary of each of the first single-height cell SHC1 and the second single-height cell SHC2 in the second direction D2. In a plan view, the gate cleaving pattern CT located on the third boundary BD3 and the fourth boundary BD4 can be configured to overlap with the gate electrode GE accordingly. The gate cleaving pattern CT may include a dielectric material, such as a silicon oxide layer or a silicon nitride layer.

[0038] The gate dicing pattern CT can separate the gate electrode GE located on the first single-height cell SHC1 from the gate electrode GE located on the second single-height cell SHC2. The gate dicing pattern CT can be located between the gate electrodes GE located on the first single-height cell SHC1 and the gate electrodes GE located on the second single-height cell SHC2 that are aligned with each other in the first direction D1. For example, the gate dicing pattern CT can divide the gate electrode GE extending along the first direction D1 into multiple gate electrodes GE.

[0039] The gate electrode GE may extend in the first direction D1, and simultaneously extend across the first channel pattern CH1 and the second channel pattern CH2. The gate electrode GE may overlap with the first channel pattern CH1 and the second channel pattern CH2 in the vertical direction. The gate electrode GE may include a first portion PO1 between the first semiconductor pattern SP1 and the active pattern AP1 or AP2, a second portion PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 located on the third semiconductor pattern SP3.

[0040] Referring to Figure 5E, the gate electrode GE can be disposed on the top surface TS, bottom surface BS, and opposite sidewall SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For example, the transistor according to one or more embodiments can be a three-dimensional field-effect transistor (e.g., a multi-bridge FET (MBCFET) or a gate-all-around FET (GAAFET)) in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH2.

[0041] A pair of gate spacers GS may be disposed on opposite sidewalls of the fourth portion PO4 of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE in a first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar with the top surface of the first interlayer dielectric layer 110, which will be described below. For example, the gate spacers GS may comprise at least one of SiCN, SiCON, and SiN. For example, the gate spacers GS may each comprise a multilayer formed of at least two selected from SiCN, SiCON, and SiN.

[0042] A gate cover pattern GP may be provided on the gate electrode GE. The gate cover pattern GP may extend along the gate electrode GE in a first direction D1. The gate cover pattern GP may include a material that has etch selectivity relative to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, which will be discussed below. For example, the gate cover pattern GP may include at least one selected from SiON, SiCN, SiCON, and SiN.

[0043] The gate dielectric layer GI may be located between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate dielectric layer GI may cover the top surface TS, bottom surface BS, and opposite sidewall SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate dielectric layer GI may cover the top surface of the device isolation layer ST located below the gate electrode GE.

[0044] On the first NMOSFET region NR1 and the second NMOSFET region NR2, the dielectric pattern IP can be positioned between the gate dielectric layer GI and the second source / drain pattern SD2. The gate dielectric layer GI and the dielectric pattern IP can separate the gate electrode GE from the second source / drain pattern SD2. In contrast, the dielectric pattern IP may not be provided on the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0045] The gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern may be disposed on the gate dielectric layer GI and adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The thickness and composition of the first metal pattern can be adjusted to achieve the desired threshold voltage of the transistor. For example, the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE may be formed by the first metal pattern. The first metal pattern and the second metal pattern may have different work functions than each other.

[0046] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). Additionally, the first metal pattern may also include carbon (C). The first metal pattern may include multiple stacked metal layers.

[0047] The second metal pattern may include a metal with a resistance less than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion PO4 of the gate electrode GE may include the first metal pattern and the second metal pattern located on the first metal pattern.

[0048] A first interlayer dielectric layer 110 may be provided on substrate 100. The first interlayer dielectric layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The top surface of the first interlayer dielectric layer 110 may be substantially coplanar with the top surface of the gate overlay pattern GP and the top surface of the gate spacer GS.

[0049] A second interlayer dielectric layer 120 may be disposed on the first interlayer dielectric layer 110 to cover the gate cover pattern GP. A third interlayer dielectric layer 130 may be provided on the second interlayer dielectric layer 120. A fourth interlayer dielectric layer 140 may be provided on the third interlayer dielectric layer 130. For example, the first interlayer dielectric layer 110 to the fourth interlayer dielectric layer 140 may comprise silicon oxide layers.

[0050] Each of the first single-height unit SHC1 and the second single-height unit SHC2 may have a pair of partition structures DB facing each other in a second direction D2 on its opposite sides. For example, the pair of partition structures DB may be correspondingly disposed on the first boundary BD1 and the second boundary BD2 of the first single-height unit SHC1. The partition structures DB may extend in a first direction D1 parallel to the gate electrode GE.

[0051] The separator structure DB can penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to extend into the first active pattern AP1 and the second active pattern AP2. The separator structure DB can penetrate the upper portion of each of the first active pattern AP1 and the second active pattern AP2. The separator structure DB can electrically isolate the active region of each of the first single-height cell SHC1 and the second single-height cell SHC2 from the active region of the other cell.

[0052] An active contact AC can be provided that penetrates the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to electrically connect to the first source / drain pattern SD1 and the second source / drain pattern SD2. The first active contact AC1 can be electrically connected to the first source / drain pattern SD1 of the first PMOSFET region PR1. The second active contact AC2 can be electrically connected to the second source / drain pattern SD2 of the first NMOSFET region NR1. The third active contact AC3 can be electrically connected to the first source / drain pattern SD1 of the second PMOSFET region PR2.

[0053] Each active contact AC can be disposed between a pair of gate electrodes GE. In a plan view, each active contact AC can have a strip or line extending in a first direction D1.

[0054] The active contact AC can be a self-aligned contact. For example, a gate cover pattern GP and a gate spacer GS can be used to form the active contact AC in a self-aligned manner. For example, each active contact AC can cover at least a portion of the sidewall of the gate spacer GS. Each active contact AC can cover a portion of the top surface of the gate cover pattern GP.

[0055] Each active contact AC may include a conductive pattern FM and a barrier pattern BM. The conductive pattern FM may include a metal with low resistance. The barrier pattern BM may conformally cover the conductive pattern FM. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one of titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, nickel nitride (NiN) layer, cobalt nitride (CoN) layer, and platinum nitride (PtN) layer.

[0056] The silicide pattern SC can be correspondingly positioned between the active contact AC and the first source / drain pattern SD1 and the second source / drain pattern SD2. The active contact AC can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 via the silicide pattern SC. The silicide pattern SC can include a metal silicide, such as at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0057] Referring further to Figures 4 and 5F to 5H, the active cutting pattern ACP can be disposed between the active contacts AC. The first active cutting pattern ACP1 can be disposed between the first active contact AC1 and the second active contact AC2. The second active cutting pattern ACP2 can be disposed between the first active contact AC1 and the third active contact AC3.

[0058] At least a portion of each active diced pattern ACP may overlap with the gate electrode GE in the vertical direction. The active diced pattern ACP may include a dielectric material. A first active diced pattern ACP1 may electrically insulate the first active contact AC1 and the second active contact AC2 from each other. A second active diced pattern ACP2 may electrically insulate the first active contact AC1 and the third active contact AC3 from each other. The lowest surface of each active diced pattern ACP may be located at a horizontal height lower than the horizontal height of the lowest surface of each active contact AC.

[0059] Each active diced pattern ACP may include a first diced pattern CP1 extending toward the substrate 100 and a second diced pattern CP2 located on the side and bottom surfaces of the first diced pattern CP1. The second diced pattern CP2 may expose at least a portion of the side surface of the first diced pattern CP1.

[0060] The first cutting pattern CP1 may have a first side surface S1 and a third side surface S3 that are opposite to each other in the first direction D1. The first side surface S1 and the third side surface S3 may face the active contact AC respectively.

[0061] The first cutting pattern CP1 may have a fourth side surface S4 and a second side surface S2 intersecting the first side surface S1. The second side surface S2 and the fourth side surface S4 may be opposite each other in the second direction D2.

[0062] The first side surface S1 and the third side surface S3 of the first cutting pattern CP1 can respectively contact the active contact AC. The first side surface S1 and the third side surface S3 of the first cutting pattern CP1 can be the side surfaces exposed by the second cutting pattern CP2.

[0063] For example, the first side surface S1 of the first active dicing pattern ACP1 can contact the first active contact AC1. The third side surface S3 of the first active dicing pattern ACP1 can contact the second active contact AC2. The first side surface S1 of the second active dicing pattern ACP2 can contact the third active contact AC3. The third side surface S3 of the second active dicing pattern ACP2 can contact the first active contact AC1.

[0064] The first diced pattern CP1 and the second diced pattern CP2 may contain materials different from each other. The dielectric constant of the first diced pattern CP1 may be greater than that of the second diced pattern CP2. The first diced pattern CP1 may contain silicon nitride, such as SiN.

[0065] The second cut pattern CP2 may cover the side and bottom surfaces of the first cut pattern CP1. The second cut pattern CP2 may expose at least a portion of the side surface of the first cut pattern CP1. The thickness CP2_W of the second cut pattern CP2 may be in the range of, for example, about 3 nm to about 5 nm. The thickness CP2_W of the second cut pattern CP2 may be measured along the second direction D2 on the side surface of the first cut pattern CP1.

[0066] The second diced pattern CP2 may include a carbon-containing dielectric material. The amount of carbon in the second diced pattern CP2 may range from approximately 5 mol% to approximately 20 mol% relative to 100 mol% of the dielectric material. The second diced pattern CP2 may include silicon carbide, such as SiOC.

[0067] The second cutting pattern CP2 may include a first cutting portion P1 that covers the bottom surface and side surfaces of the first cutting pattern CP1. The first cutting portion P1 may cover the bottom surface of the first cutting pattern CP1, and may also cover the lower part of the first side surface S1, the second side surface S2, the third side surface S3 and the fourth side surface S4 of the first cutting pattern CP1.

[0068] The top surface P1_U of the first cut portion P1 can be located at a lower horizontal height than the top surface CP1_U of the first cut pattern CP1. The top surface P1_U of the first cut portion P1 can contact each active contact AC (see Figures 5C and 5G).

[0069] The bottom surface P1_L of the first cutting portion P1 can be located at a horizontal height lower than the horizontal height of the bottom surface CP1_L of the first cutting pattern CP1. The bottom surface P1_L of the first cutting portion P1 can be referred to as the bottom surface of the second cutting pattern CP2, and can also be referred to as the lowest surface of each active cutting pattern ACP.

[0070] The second cutting pattern CP2 may include a second cutting portion P2 extending from the first cutting portion P1 toward the third direction D3. The second cutting portion P2 may correspondingly extend onto the upper portions of the second side surface S2 and the fourth side surface S4 of the first cutting pattern CP1. The second cutting portion P2 may correspondingly expose the upper portions of the first side surface S1 and the third side surface S3 of the first cutting pattern CP1 (i.e., the upper portions of the first side surface S1 and the third side surface S3 of the first cutting pattern CP1 can be exposed through the second cutting portion P2). The second cutting pattern CP2 may expose portions of the first side surface S1 and the third side surface S3 of the first cutting pattern CP1 on which the second cutting portion P2 is not disposed (i.e., portions of the first side surface S1 and the third side surface S3 of the first cutting pattern CP1 on which the second cutting portion P2 is not disposed can be exposed through the second cutting portion P2).

[0071] The second cut portions P2 can be spaced apart from each other by a first distance P2_D1 in the second direction D2. The first distance P2_D1 can be greater than the width AC_W of each active contact AC in the second direction D2. Each uppermost surface P2_U of the second cut portion P2 can be coplanar with the top surface CP1_U of the first cut pattern CP1. Each uppermost surface P2_U of the second cut portion P2 can be located at a horizontal height higher than the horizontal height of the top surface P1_U of the first cut portion P1.

[0072] According to one or more embodiments, the second dicing pattern CP2 may expose at least a portion of the side surface of the first dicing pattern CP1 (i.e., a portion of the side surface of the first dicing pattern CP1 may be exposed by the second dicing pattern CP2). Therefore, each active dicing pattern ACP may have a reduced size (e.g., width in the first direction D1). Each active contact AC has an increased area, thus improving the electrical performance of the semiconductor device.

[0073] Furthermore, the second dicing pattern CP2 can have a smaller dielectric constant than the first dicing pattern CP1. Therefore, the capacitance between adjacent active contacts AC can be improved. Thus, a semiconductor device with improved electrical performance can be provided.

[0074] Referring back to Figures 4 and 5A through 5E, a gate contact GC can be provided to penetrate the second interlayer dielectric layer 120 and the gate overlay pattern GP for electrical connection to the gate electrode GE. Each active contact AC can have an upper portion adjacent to the gate contact GC, and an upper dielectric pattern UIP can fill the upper portion of the active contact AC. The bottom surface of the upper dielectric pattern UIP can be lower than the bottom surface of the gate contact GC. For example, the upper dielectric pattern UIP can cause the active contact AC adjacent to the gate contact GC to have a top surface lower than the bottom surface of the gate contact GC. Therefore, short circuits caused by contact between the gate contact GC and its adjacent active contact AC can be prevented. The gate contact GC can include at least one metal selected from, for example, aluminum, copper, tungsten, molybdenum, and cobalt.

[0075] The gate contact GC may include a conductive pattern FM and a barrier pattern BM. The conductive pattern FM may include a low-resistance metal. The barrier pattern BM may conformally cover the conductive pattern FM.

[0076] A first metal layer M1 may be provided in the third interlayer dielectric layer 130. For example, the first metal layer M1 may include a first power line M1_R1, a second power line M1_R2, a third power line M1_R3, and a first wiring M1_I. The lines M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1 may extend parallel to each other in the second direction D2.

[0077] For example, the first power line M1_R1 and the second power line M1_R2 can be correspondingly arranged on the third boundary BD3 and the fourth boundary BD4 of the first single-height unit SHC1. The first power line M1_R1 can extend along the third boundary BD3 in the second direction D2. The second power line M1_R2 can extend along the fourth boundary BD4 in the second direction D2.

[0078] The first metal layer M1 may further include a first path VI1. The first path VI1 may be correspondingly disposed below lines M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1. The active contact AC can be electrically connected to the wiring of the first metal layer M1 through the first path VI1. The gate contact GC can be electrically connected to the wiring of the first metal layer M1 through the first path VI1.

[0079] A second metal layer M2 may be provided in the fourth interlayer dielectric layer 140. The second metal layer M2 may include multiple second wirings M2_I. The second wirings M2_I of the second metal layer M2 may all be linear or strip-shaped extending in the first direction D1. For example, the second wirings M2_I may extend parallel to each other in the first direction D1.

[0080] The second metal layer M2 may further include a second path VI2 correspondingly disposed below the second wiring M2_I. A specific line of the first metal layer M1 can be electrically connected to a corresponding line of the second metal layer M2 through the second path VI2.

[0081] The wiring of the first metal layer M1 and the second metal layer M2 may include the same or different conductive materials. For example, the wiring of the first metal layer M1 and the second metal layer M2 may include at least one metallic material selected from aluminum, copper, tungsten, molybdenum, and cobalt. Other metal layers (e.g., M3, M4, M5, etc.) may be additionally stacked on the fourth interlayer dielectric layer 140. Each stacked metal layer may include lines for routing between cells.

[0082] Figures 6A to 17H are diagrams illustrating methods of manufacturing a semiconductor device according to one or more embodiments. Figures 6A to 11A show cross-sectional views taken along line A-A' of Figure 4. Figures 6B to 11B show cross-sectional views taken along line B-B' of Figure 4. Figures 6C to 11C show cross-sectional views taken along line C-C' of Figure 4. Figures 6D to 11D show cross-sectional views taken along line D-D' of Figure 4. Figures 6E to 11E show cross-sectional views taken along line E-E' of Figure 4. Figures 12, 14, and 16 show plan views illustrating semiconductor devices according to one or more embodiments. Figures 13A, 15A, and 17A show cross-sectional views taken along line A-A' of Figure 16. Figures 13B, 15B, and 17B show cross-sectional views taken along line B-B' of Figure 16. Figures 13C, 15C, and 17C show cross-sectional views taken along line C-C' of Figure 16. Figures 13D, 15D, and 17D show cross-sectional views taken along line D-D' of Figure 16. Figures 13E, 15E, and 17E show cross-sectional views taken along line E-E' of Figures 12, 14, and 16. Figure 13F shows an enlarged view of portion M shown in Figure 12. Figure 15F shows an enlarged view of portion M shown in Figure 14. Figure 17F shows an enlarged view of portion M shown in Figure 16. Figure 17G shows an enlarged view of portion N shown in Figure 17C. Figure 17H ​​shows an enlarged view of portion O shown in Figure 17D. Descriptions of aspects that are the same as or similar to those described above may be omitted.

[0083] Referring to Figures 6A to 6E, a substrate 100 may be provided comprising a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. The first NMOSFET region NR1 and the first PMOSFET region PR1 may define a first single-height cell SHC1, and the second NMOSFET region NR2 and the second PMOSFET region PR2 may define a second single-height cell SHC2.

[0084] The substrate 100 can be patterned to form a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 can be formed on a first PMOSFET region PR1 and a second PMOSFET region PR2. The second active pattern AP2 can be formed on a first NMOSFET region NR1 and a second NMOSFET region NR2.

[0085] The formation of the first active pattern AP1 and the second active pattern AP2 may include, for example, forming a mask pattern on the substrate 100 and using the mask pattern as an etching mask to etch the substrate 100. The etching process may form trenches TR that define the first active pattern AP1 and the second active pattern AP2.

[0086] The substrate 100 may have a first sacrificial layer SAL and an active layer ACL alternately stacked on its top surface in a third direction D3 perpendicular to the top surface of the substrate 100. Therefore, multiple stacked patterns STP can be formed, each stacked pattern STP including alternately stacked first sacrificial layers SAL and active layers ACL. The first sacrificial layer SAL may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the active layer ACL may include another of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the first sacrificial layer SAL may include silicon-germanium (SiGe) or germanium (Ge), and the active layer ACL may include silicon (Si).

[0087] A device isolation layer ST can be formed to fill the trench TR. For example, a dielectric layer can be formed on the front surface of the substrate 100 to cover the first active pattern AP1 and the second active pattern AP2 and the stacked pattern STP. The dielectric layer can be recessed until the stacked pattern STP is exposed to form the device isolation layer ST.

[0088] Referring to Figures 7A to 7E, a sacrificial pattern PP spanning the stacked pattern STP can be formed on the substrate 100. Each sacrificial pattern PP can be formed as a line or strip extending in a first direction D1.

[0089] For example, forming a sacrificial pattern PP may include forming a sacrificial layer on the front surface of the substrate 100, forming a first hard mask pattern MP on the sacrificial layer, and using the first hard mask pattern MP as an etch mask to pattern the sacrificial layer. The sacrificial layer may include polysilicon.

[0090] A pair of gate spacers GS can be formed on opposite sidewalls of each sacrificial pattern PP. The formation of the gate spacers GS may include conformally forming a gate spacer layer on the front surface of the substrate 100 and anisotropically etching the gate spacer layer.

[0091] Referring to Figures 8A to 8D, a first recess RS1 can be formed in a stacked pattern STP located on a first active pattern AP1. A second recess RS2 can be formed in a stacked pattern STP located on a second active pattern AP2. The formation of the first recess RS1 and the second recess RS2 can also cause the device isolation layer ST on the opposite side of each of the first active pattern AP1 and the second active pattern AP2 to be recessed.

[0092] For example, the first hard mask pattern MP and the gate spacer GS can be used as an etching mask to etch the stacked pattern STP located on the first active pattern AP1, thereby forming a first recess RS1. The first recess RS1 can be formed between a pair of sacrificial patterns PP. A second recess RS2 located in the stacked pattern STP on the second active pattern AP2 can be formed by the same method used to form the first recess RS1.

[0093] The active layer ACL can be formed by sequentially stacking a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 between adjacent first recesses RS1. The active layer ACL can also be formed by sequentially stacking a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 between adjacent second recesses RS2. The first channel pattern CH1 can be formed by the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 between adjacent first recesses RS1. The second channel pattern CH2 can be formed by the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 between adjacent second recesses RS2.

[0094] Referring to Figures 9A to 9E, a first source / drain pattern SD1 can be correspondingly formed in the first recess RS1. For example, a first selective epitaxial growth (SEG) process can be performed, in which the inner wall of the first recess RS1 is used as a seed layer to form the first source / drain pattern SD1. The first SEG process may include chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).

[0095] The first source / drain pattern SD1 may comprise a semiconductor element (e.g., SiGe) with a lattice constant greater than that of the substrate 100. Impurities may be implanted in situ during the first SEG process. Optionally, impurities may be implanted into the first source / drain pattern SD1 after its formation. The first source / drain pattern SD1 may be doped to have a first conductivity type (e.g., p-type).

[0096] A second source / drain pattern SD2 can be correspondingly formed in the second recess RS2. For example, a second SEG process can be performed in which the inner wall of the second recess RS2 is used as a seed layer to form the second source / drain pattern SD2. For example, the second source / drain pattern SD2 may include the same semiconductor element as the semiconductor element of the substrate 100 (e.g., Si). The second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type). A dielectric pattern IP can be formed between the second source / drain pattern SD2 and the first sacrificial layer SAL.

[0097] A first interlayer dielectric layer 110 can be formed to cover a first source / drain pattern SD1, a second source / drain pattern SD2, a first hard mask pattern MP, and a gate spacer GS. The first interlayer dielectric layer 110 can be planarized until the top surface of the sacrificial pattern PP is exposed. The first interlayer dielectric layer 110 can be planarized using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, the first hard mask pattern MP can be completely removed.

[0098] Exposed sacrificial patterns (PP) can be selectively removed. Removal of the sacrificial patterns (PP) can form external regions (ORG) exposing the first channel pattern (CH1) and the second channel pattern (CH2). Removal of the sacrificial patterns (PP) can include performing a wet etching process using an etchant that selectively etches polysilicon.

[0099] The first sacrificial layer SAL, exposed through the external region ORG, can be selectively removed to form the internal region IRG. For example, an etching process that selectively etches the first sacrificial layer SAL can be performed, such that only the first sacrificial layer SAL is removed, leaving the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For silicon-germanium with a relatively high germanium concentration, the etching process can have a high etching rate.

[0100] The etching process can remove the first sacrificial layer SAL located on the first active pattern AP1 and the second active pattern AP2. The etching process can be a wet etching process. The etching material used in the etching process can rapidly etch the first sacrificial layer SAL, which has a relatively high germanium concentration.

[0101] With the selective removal of the first sacrificial layer SAL, only the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can remain on each of the first active pattern AP1 and the second active pattern AP2. The removal of the first sacrificial layer SAL can form the first internal region IRG1, the second internal region IRG2, and the third internal region IRG3.

[0102] A gate dielectric layer GI can be formed on the exposed first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate dielectric layer GI can be formed around each of the first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3.

[0103] Referring to Figures 10A to 10E, the gate electrode GE may include a first portion PO1, a second portion PO2, and a third portion PO3 respectively formed in the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3, and may also include a fourth portion PO4 formed in the outer region ORG. The gate electrode GE may be recessed to have a reduced height. A gate overlay pattern GP may be formed on the recessed gate electrode GE. A gate dicing pattern CT may be provided on the boundary parallel to the second direction D2 of each of the first single-height unit SHC1 and the second single-height unit SHC2.

[0104] Referring to Figures 11A to 11E, a second interlayer dielectric layer 120 can be formed on the first interlayer dielectric layer 110. The second interlayer dielectric layer 120 can be formed on the gate overlay pattern GP.

[0105] Cut trenches (APTs) can be formed to penetrate the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110. Each cut trench APT can be formed between the gate electrodes GE. At least a portion of each cut trench APT can overlap perpendicularly with the gate electrode GE.

[0106] A first diced trench APT1 can be formed between the first source / drain pattern SD1 of the first PMOSFET region PR1 and the second source / drain pattern SD2 of the first NMOSFET region NR1. A second diced trench APT2 can be formed between the first source / drain pattern SD1 of the first PMOSFET region PR1 and the first source / drain pattern SD1 of the second PMOSFET region PR2.

[0107] The formation of the cut trench APT may include, for example, forming a first mask pattern on the second interlayer dielectric layer 120 and using the first mask pattern as an etching mask to etch the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110.

[0108] Referring to Figures 12 and 13A to 13E, the active cut pattern ACP can fill the cut groove APT. At least a portion of each active cut pattern ACP can overlap with the gate electrode GE in the vertical direction.

[0109] A first active dicing pattern ACP1 can be formed between the first source / drain pattern SD1 of the first PMOSFET region PR1 and the second source / drain pattern SD2 of the first NMOSFET region NR1. A second active dicing pattern ACP2 can be formed between the first source / drain pattern SD1 of the first PMOSFET region PR1 and the first source / drain pattern SD1 of the second PMOSFET region PR2.

[0110] Each active cutting pattern ACP may include a first cutting pattern CP1 and a preliminary cutting pattern PCP covering the side and bottom surfaces of the first cutting pattern CP1. The first cutting pattern CP1 and the preliminary cutting pattern PCP may be made of different materials.

[0111] The dielectric constant of the first diced pattern CP1 can be greater than that of the preliminary diced pattern PCP. The first diced pattern CP1 may include silicon nitride, such as SiN. The preliminary diced pattern PCP may include a carbon-containing dielectric material. The amount of carbon in the preliminary diced pattern PCP may range from approximately 5 mol% to approximately 20 mol% relative to 100 mol% of the dielectric material. The preliminary diced pattern PCP may include silicon carbide, such as SiOC.

[0112] The first cutting pattern CP1 may have a first side surface S1 and a third side surface S3 that are opposite to each other. The first side surface S1 and the third side surface S3 may face the first source / drain pattern SD1 and the second source / drain pattern SD2. The first side surface S1 and the third side surface S3 may be opposite to each other in the first direction D1.

[0113] For example, the first side surface S1 of the first active diced pattern ACP1 can face the first source / drain pattern SD1 of the first PMOSFET region PR1. The third side surface S3 of the first active diced pattern ACP1 can face the second source / drain pattern SD2 of the first NMOSFET region NR1.

[0114] The first side surface S1 of the second active diced pattern ACP2 can face the first source / drain pattern SD1 of the second PMOSFET region PR2. The third side surface S3 of the second active diced pattern ACP2 can face the first source / drain pattern SD1 of the first PMOSFET region PR1.

[0115] The first cutting pattern CP1 may have a second side surface S2 intersecting the first side surface S1, and may also have a fourth side surface S4 opposite to the second side surface S2. The second side surface S2 and the fourth side surface S4 may be opposite to each other in the second direction D2.

[0116] The preliminary cut pattern PCP can cover the side and bottom surfaces of the first cut pattern CP1. The preliminary cut pattern PCP can cover all the first side surfaces S1, second side surfaces S2, third side surfaces S3, and fourth side surfaces S4 of the first cut pattern CP1. The bottom surface PCP_L of the preliminary cut pattern PCP can be located at a horizontal height lower than the horizontal height of the bottom surface CP1_L of the first cut pattern CP1. The thickness PCP_W of the preliminary cut pattern PCP can be, for example, in the range of approximately 3 nm to approximately 5 nm. The thickness PCP_W of the preliminary cut pattern PCP can be measured along the second direction D2 on the side surface of the first cut pattern CP1.

[0117] The formation of an active cut pattern ACP may include, for example, forming a preliminary cut pattern PCP in a cut trench APT, forming a first cut pattern CP1 on the preliminary cut pattern PCP to fill each cut trench APT, and performing a planarization process until the second interlayer dielectric layer 120 is exposed. The planarization process makes the top surface CP1_U of the first cut pattern CP1 coplanar with the top surface 120U of the second interlayer dielectric layer 120.

[0118] Referring to Figures 14 and 15A to 15E, an active trench ACT can be formed to penetrate the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110.

[0119] A first active trench ACT1 can be formed on the first source / drain pattern SD1 in the first PMOSFET region PR1. The first active trench ACT1 can expose the top surface of the first source / drain pattern SD1. A second active trench ACT2 can be formed on the second source / drain pattern SD2 in the first NMOSFET region NR1. The second active trench ACT2 can expose the top surface of the second source / drain pattern SD2. A third active trench ACT3 can be formed on the first source / drain pattern SD1 in the second PMOSFET region PR2. The third active trench ACT3 can expose the top surface of the first source / drain pattern SD1.

[0120] Referring again to Figures 15C, 15D, and 15F, the first active dicing pattern ACP1 can be located between the first active trench ACT1 and the second active trench ACT2. The first active trench ACT1 and the second active trench ACT2 can expose the side surfaces of the first active dicing pattern ACP1. The preliminary dicing pattern PCP disposed on the first side surface S1 and the third side surface S3 of the first active dicing pattern ACP1 can be exposed.

[0121] The second active cutting pattern ACP2 can be located between the first active trench ACT1 and the third active trench ACT3. The first active trench ACT1 and the third active trench ACT3 can expose the side surfaces of the second active cutting pattern ACP2. The preliminary cutting pattern PCP disposed on the first side surface S1 and the third side surface S3 of the second active cutting pattern ACP2 can be exposed.

[0122] The formation of the active trench (ACT) may include, for example, forming a second mask pattern on the second interlayer dielectric layer 120 and using the second mask pattern as an etching mask to etch the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110.

[0123] According to one or more embodiments, each of the first active cutting pattern ACP1 and the second active cutting pattern ACP2 may include a preliminary cutting pattern PCP. Therefore, the distance between the first active cutting pattern ACP1 and the second active cutting pattern ACP2 (e.g., the distance in the first direction D1) can be reduced.

[0124] This distance can be reduced, thereby reducing the number of failures that are not exposed during the etching process on the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2. Therefore, a method for manufacturing semiconductor devices with improved reliability can be provided.

[0125] Referring to Figures 16 and 17A through 17H, ashing and wet etching processes can be performed to remove impurities. These processes remove impurities generated during the etching process used to form the active trench (ACT).

[0126] Ashing and wet etching processes can remove exposed pre-cut pattern PCP. Ashing reduces the carbon content of the exposed pre-cut pattern PCP. Wet etching removes exposed pre-cut pattern PCP.

[0127] For example, the carbon content of a pre-cut patterned PCP can range from approximately 5 mol% to approximately 20 mol% relative to 100 mol% of dielectric material. An ashing process can reduce the carbon content of the exposed pre-cut patterned PCP. The carbon content of the exposed pre-cut patterned PCP can then range from approximately 0.01 mol% to approximately 3 mol% relative to 100 mol% of dielectric material.

[0128] Therefore, the exposed preliminary cut pattern PCP and the initial cut pattern PCP can have different etching selectivity. A wet etching process can etch the exposed preliminary cut pattern PCP.

[0129] Therefore, the first side surface S1 and the third side surface S3 of the first cutting pattern CP1 can be exposed. The first active trench ACT1 and the second active trench ACT2 can expose the first side surface S1 and the third side surface S3 of the first active cutting pattern ACP1. The first active trench ACT1 and the third active trench ACT3 can expose the first side surface S1 and the third side surface S3 of the second active cutting pattern ACP2.

[0130] Referring again to Figures 17F, 17G, and 17H, a wet etching process can form a second cut pattern CP2. The second cut pattern CP2 can refer to the residue of the initial cut pattern PCP retained after the wet etching process. The second cut pattern CP2 can cover the side and bottom surfaces of the first cut pattern CP1. The second cut pattern CP2 can expose a portion of the side surface of the first cut pattern CP1.

[0131] The second cutting pattern CP2 may include a first cutting portion P1 covering the bottom and side surfaces of the first cutting pattern CP1. The first cutting portion P1 may cover the bottom surface of the first cutting pattern CP1, and may also cover the lower portions of the first side surfaces S1, S2, S3, and S4 of the first cutting pattern CP1. Each active trench ACT may expose the top surface P1_U of the first cutting portion P1. The top surface P1_U of the first cutting portion P1 may be located at a horizontal height lower than the horizontal height of the top surface CP1_U of the first cutting pattern CP1. The bottom surface P1_L of the first cutting portion P1 may be located at a horizontal height lower than the horizontal height of the bottom surface CP1_L of the first cutting pattern CP1. The bottom surface P1_L of the first cutting portion P1 may be referred to as the bottom surface of the second cutting pattern CP2.

[0132] The second cutting pattern CP2 may include a second cutting portion P2 extending from the first cutting portion P1 in a third direction D3. The second cutting portion P2 may extend onto the upper portion of the second side surface S2 and the fourth side surface S4 of the first cutting pattern CP1. The second cutting portions P2 may be spaced apart from each other in the second direction D2. The first distance P2_D1 between the second cutting portions P2 in the second direction D2 may be greater than the width ACT_W of each active trench ACT in the second direction D2. The second cutting portions P2 may partially cover the second side surface S2 and the fourth side surface S4 of the first cutting pattern CP1. Each uppermost surface P2_U of the second cutting portion P2 may be coplanar with the top surface CP1_U of the first cutting pattern CP1. Each uppermost surface P2_U of the second cutting portion P2 may be located at a horizontal height higher than the horizontal height of the top surface P1_U of the first cutting portion P1.

[0133] Referring back to Figures 4 to 5G, an active contact AC can be formed to fill the active trench ACT. The first active contact AC1 can fill the first active trench ACT1. The first active contact AC1 can contact the first side surface S1 of the first active dicing pattern ACP1, and can also contact the third side surface S3 of the second active dicing pattern ACP2.

[0134] The second active contact AC2 can fill the second active trench ACT2. The second active contact AC2 can contact the third side surface S3 of the first active dicing pattern ACP1.

[0135] The third active contact AC3 can fill the third active trench ACT3. The third active contact AC3 can contact the first side surface S1 of the second active cut pattern ACP2.

[0136] According to one or more embodiments, active contacts AC can be formed after removing the exposed initial dicing pattern PCP. Therefore, each active contact AC can have an increased area. Consequently, a semiconductor device with improved electrical performance can be provided.

[0137] A gate contact GC can be formed to penetrate the second interlayer dielectric layer 120 and the gate cover pattern GP to be electrically connected to the gate electrode GE.

[0138] The formation of the gate contact GC and each active contact AC may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be formed conformally and may include a metal layer and a metal nitride layer. The conductive pattern FM may include a metal with low resistance.

[0139] A separator structure DB can be formed. The separator structure DB can extend from the second interlayer dielectric layer 120 through the gate electrode GE into the active pattern AP1 or AP2. The separator structure DB may include a dielectric material, such as a silicon oxide layer or a silicon nitride layer.

[0140] A third interlayer dielectric layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer dielectric layer 130. A fourth interlayer dielectric layer 140 may be formed on the third interlayer dielectric layer 130. A second metal layer M2 may be formed in the fourth interlayer dielectric layer 140.

[0141] Figure 18 is a plan view illustrating a semiconductor device according to one or more embodiments. Figures 19A to 19E are cross-sectional views illustrating a semiconductor device according to one or more embodiments. Figure 19F is an enlarged view illustrating portion M of Figure 18 according to one or more embodiments. Figure 19G is an enlarged view illustrating portion N of Figure 19C according to one or more embodiments. Figure 19H is an enlarged view illustrating portion O of Figure 19D according to one or more embodiments. Descriptions of aspects that are the same as or similar to those described above may be omitted.

[0142] Referring to Figures 18 and 19A to 19E, an active cut pattern ACP can be provided between active contacts AC. For example, a first active cut pattern ACP1 can be provided between the first active contact AC1 and the second active contact AC2. A second active cut pattern ACP2 can be provided between the first active contact AC1 and the third active contact AC3.

[0143] At least a portion of each active diced pattern ACP may overlap with the gate electrode GE in the vertical direction. The active diced pattern ACP may include a dielectric material. A first active diced pattern ACP1 may electrically insulate the first active contact AC1 and the second active contact AC2 from each other. A second active diced pattern ACP2 may electrically insulate the first active contact AC1 and the third active contact AC3 from each other. The lowest surface of each active diced pattern ACP may be located at a horizontal height lower than the horizontal height of the lowest surface of each active contact AC.

[0144] Referring further to Figures 19G and 19H, each active dicing pattern ACP may include a first dicing pattern CP1 extending toward the substrate 100 and a second dicing pattern CP2 located on the side surface and bottom surface of the first dicing pattern CP1.

[0145] The first cutting pattern CP1 may have a first side surface S1 and a third side surface S3 that are opposite to each other. The first side surface S1 and the third side surface S3 may face the active contact AC. The first side surface S1 and the third side surface S3 may be opposite to each other in a first direction D1.

[0146] The first cutting pattern CP1 may have a second side surface S2 intersecting the first side surface S1, and may also have a fourth side surface S4 opposite to the second side surface S2. The second side surface S2 and the fourth side surface S4 may be spaced apart from each other in the second direction D2.

[0147] The first diced pattern CP1 and the second diced pattern CP2 may contain materials different from each other. The dielectric constant of the first diced pattern CP1 may be greater than that of the second diced pattern CP2. The first diced pattern CP1 may contain silicon nitride, such as SiN.

[0148] The second dicing pattern CP2 may surround the side and bottom surfaces of the first dicing pattern CP1. The second dicing pattern CP2 may include silicon carbide, such as SiOC.

[0149] The second cutting pattern CP2 may include a first cutting portion P1 covering the bottom and side surfaces of the first cutting pattern CP1. The first cutting portion P1 may cover the lower parts of the first side surfaces S1, S2, S3, and S4 of the first cutting pattern CP1. The top surface P1_U of the first cutting portion P1 may be located at a horizontal height lower than the horizontal height of the top surface CP1_U of the first cutting pattern CP1. The bottom surface P1_L of the first cutting portion P1 may be located at a horizontal height lower than the horizontal height of the bottom surface CP1_L of the first cutting pattern CP1. The bottom surface P1_L of the first cutting portion P1 may be referred to as the bottom surface of the second cutting pattern CP2, and may also be referred to as the lowest surface of each active cutting pattern ACP.

[0150] The second cutting pattern CP2 may include a second cutting portion P2 extending from the first cutting portion P1 in a third direction D3. The second cutting portion P2 may extend onto the upper part of the second side surface S2 and the fourth side surface S4 of the first cutting pattern CP1. Each uppermost surface P2_U of the second cutting portion P2 may be coplanar with the top surface CP1_U of the first cutting pattern CP1. Each uppermost surface P2_U of the second cutting portion P2 may be located at a horizontal height higher than the horizontal height of the top surface P1_U of the first cutting portion P1.

[0151] The first cut portion P1 and the second cut portion P2 may include a first dielectric material containing carbon. The carbon content of the first cut portion P1 may be in the range of approximately 5 mol% to approximately 20 mol% relative to 100 mol% of the first dielectric material. The carbon content of the second cut portion P2 may be in the range of approximately 5 mol% to approximately 20 mol% relative to 100 mol% of the first dielectric material.

[0152] The second cutting pattern CP2 may include a third cutting portion P3 extending from the first cutting portion P1 in the third direction D3. The third cutting portion P3 may extend to the upper part of the first side surface S1 and the third side surface S3 of the first cutting pattern CP1. The width P3_D of each third cutting portion P3 in the second direction D2 may be greater than the width AC_W of each active contact AC in the second direction D2.

[0153] The thickness P3_W of each third cut portion P3 may differ from the thickness P2_W of each second cut portion P2. The thickness P3_W of each third cut portion P3 may represent the thickness measured along the first direction D1 on the side surface of the first cut pattern CP1. The thickness P2_W of each second cut portion P2 may represent the thickness measured along the second direction D2 on the side surface of the first cut pattern CP1. The thickness P3_W of each third cut portion P3 may be less than the thickness P2_W of each second cut portion P2. The thickness P3_W of each third cut portion P3 may be in the range of, for example, approximately 0.01 nm to approximately 0.1 nm. The thickness P2_W of each second cut portion P2 may be in the range of, for example, approximately 3 nm to approximately 5 nm.

[0154] The third cut portion P3 may include a carbon-containing second dielectric material. The carbon content of the third cut portion P3 may be less than the carbon content of the first cut portion P1. The carbon content of the third cut portion P3 may be less than the carbon content of the second cut portion P2. The carbon content of the third cut portion P3 relative to 100 mol% of the second dielectric material may be in the range of, for example, about 0.01 mol% to about 3 mol%.

[0155] The third cut portion P3 may have etching selectivity relative to at least one of the first cut portion P1, the second cut portion P2, and the first cut pattern CP1. Since the third cut portion P3 has a reduced carbon content, the third cut portion P3 may have etching selectivity different from that of the first cut portion P1, the second cut portion P2, and the first cut pattern CP1.

[0156] The third cut portion P3 can contact the active contact AC. For example, the third cut portion P3 of the first active cut pattern ACP1 can contact the first active contact AC1 and the second active contact AC2. The third cut portion P3 of the second active cut pattern ACP2 can contact the third active contact AC3 and the first active contact AC1.

[0157] Each uppermost surface P3_U of the third cutting portion P3 can be coplanar with the top surface P1_U of the first cutting portion P1. Each uppermost surface P3_U of the third cutting portion P3 can be coplanar with the top surface CP1_U of the first cutting pattern CP1.

[0158] According to one or more embodiments, the third cut portion P3 of the second cut pattern CP2 can all have a very small thickness. Therefore, the active cut pattern ACP can all have a reduced size (e.g., width in the first direction D1). Thus, since each active contact AC has an increased area, the semiconductor device can improve its electrical performance.

[0159] Furthermore, the second diced pattern CP2 can have a smaller dielectric constant than the first diced pattern CP1. Therefore, improved capacitance can be provided between adjacent active contacts AC. Consequently, the electrical performance of the semiconductor device can be improved.

[0160] Other configurations can be the same as those discussed in Figures 4 to 5G.

[0161] Figures 20 to 21H are diagrams illustrating methods of manufacturing a semiconductor device according to one or more embodiments. Figure 20 is a plan view showing a semiconductor device according to one or more embodiments. Figure 21A shows a cross-sectional view taken along line A-A' of Figure 20. Figure 21B shows a cross-sectional view taken along line B-B' of Figure 20. Figure 21C shows a cross-sectional view taken along line C-C' of Figure 20. Figure 21D shows a cross-sectional view taken along line D-D' of Figure 20. Figure 21E shows a cross-sectional view taken along line E-E' of Figure 20. Figure 21F shows an enlarged view showing portion M of Figure 20. Figure 21G shows an enlarged view showing portion N of Figure 21C. Figure 21H shows an enlarged view showing portion O of Figure 21D. Descriptions of aspects that are the same as or similar to those described above may be omitted.

[0162] Referring back to Figures 11A to 11E, a diced trench APT can be formed to penetrate the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110. A first diced trench APT1 can be formed between the first source / drain pattern SD1 of the first PMOSFET region PR1 and the second source / drain pattern SD2 of the first NMOSFET region NR1. A second diced trench APT2 can be formed between the first source / drain pattern SD1 of the first PMOSFET region PR1 and the first source / drain pattern SD1 of the second PMOSFET region PR2.

[0163] Referring back to Figures 12 and 13A through 13F, the active cut pattern ACP can fill the cut groove APT. At least a portion of each active cut pattern ACP can overlap perpendicularly with the gate electrode GE.

[0164] A first active dicing pattern ACP1 can be formed between the first source / drain pattern SD1 of the first PMOSFET region PR1 and the second source / drain pattern SD2 of the first NMOSFET region NR1. A second active dicing pattern ACP2 can be formed between the first source / drain pattern SD1 of the first PMOSFET region PR1 and the first source / drain pattern SD1 of the second PMOSFET region PR2.

[0165] Each active diced pattern (ACP) may include a first diced pattern (CP1) and a preliminary diced pattern (PCP) covering the side and bottom surfaces of the first diced pattern (CP1). The first diced pattern (CP1) and the preliminary diced pattern (PCP) may include different materials from each other. The dielectric constant of the first diced pattern (CP1) may be greater than that of the preliminary diced pattern (PCP). The first diced pattern (CP1) may include silicon nitride, such as SiN. The carbon content in the preliminary diced pattern (PCP) may range from about 5 mol% to about 20 mol% relative to 100 mol% of dielectric material. The preliminary diced pattern (PCP) may include silicon carbide, such as SiOC.

[0166] The first cutting pattern CP1 may have a first side surface S1 and a third side surface S3 that are opposite to each other. The first side surface S1 and the third side surface S3 may face the first source / drain pattern SD1 and the second source / drain pattern SD2. The first side surface S1 and the third side surface S3 may be opposite to each other in the first direction D1.

[0167] For example, the first side surface S1 of the first active diced pattern ACP1 can face the first source / drain pattern SD1 of the first PMOSFET region PR1. The third side surface S3 of the first active diced pattern ACP1 can face the second source / drain pattern SD2 of the first NMOSFET region NR1.

[0168] The first side surface S1 of the second active diced pattern ACP2 can face the first source / drain pattern SD1 of the second PMOSFET region PR2. The third side surface S3 of the second active diced pattern ACP2 can face the first source / drain pattern SD1 of the first PMOSFET region PR1.

[0169] The first cutting pattern CP1 may have a second side surface S2 intersecting the first side surface S1, and may also have a fourth side surface S4 opposite to the second side surface S2. The second side surface S2 and the fourth side surface S4 may be opposite to each other in the second direction D2.

[0170] The preliminary cut pattern PCP can cover the side and bottom surfaces of the first cut pattern CP1. The preliminary cut pattern PCP can cover all the first side surfaces S1, second side surfaces S2, third side surfaces S3, and fourth side surfaces S4 of the first cut pattern CP1. The thickness PCP_W of the preliminary cut pattern PCP can be in the range of, for example, approximately 3 nm to approximately 5 nm.

[0171] Referring back to Figures 14 and 15A to 15E, an active trench ACT can be formed to penetrate the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110.

[0172] A first active trench ACT1 can be formed on the first source / drain pattern SD1 in the first PMOSFET region PR1. The first active trench ACT1 can expose the top surface of the first source / drain pattern SD1. A second active trench ACT2 can be formed on the second source / drain pattern SD2 in the first NMOSFET region NR1. The second active trench ACT2 can expose the top surface of the second source / drain pattern SD2. A third active trench ACT3 can be formed on the first source / drain pattern SD1 in the second PMOSFET region PR2. The third active trench ACT3 can expose the top surface of the first source / drain pattern SD1.

[0173] Referring to Figures 15C, 15D, and 15F, a first active dicing pattern ACP1 can be located between a first active trench ACT1 and a second active trench ACT2. The first active trench ACT1 and the second active trench ACT2 can expose the side surfaces of the first active dicing pattern ACP1. A preliminary dicing pattern PCP can be exposed on the first side surface S1 and the third side surface S3 of the first active dicing pattern ACP1.

[0174] The second active cutting pattern ACP2 can be located between the first active trench ACT1 and the third active trench ACT3. The first active trench ACT1 and the third active trench ACT3 can expose the side surfaces of the second active cutting pattern ACP2. The preliminary cutting pattern PCP disposed on the first side surface S1 and the third side surface S3 of the second active cutting pattern ACP2 can be exposed.

[0175] According to one or more embodiments, each of the first active dicing pattern ACP1 and the second active dicing pattern ACP2 may include a preliminary dicing pattern PCP. Therefore, a reduced distance can be provided between the first active dicing pattern ACP1 and the second active dicing pattern ACP2.

[0176] This distance can be reduced, thereby reducing the undesirable situation where the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 are not exposed. Therefore, a method for manufacturing semiconductor devices with improved reliability can be provided.

[0177] Referring to Figures 20 and 21A through 21E, ashing and wet etching processes can be performed to remove impurities. These processes remove impurities generated during the etching process used to form the active trench (ACT).

[0178] Ashing and wet etching processes can remove a portion of the exposed pre-cut pattern PCP. Ashing can reduce the carbon content of the exposed pre-cut pattern PCP.

[0179] For example, the preliminary diced patterned PCP may include a carbon-containing dielectric material. The carbon content of the preliminary diced patterned PCP may range from about 5 mol% to about 20 mol% relative to 100 mol% dielectric material.

[0180] The ashing process can reduce the carbon content of exposed pre-cut patterned PCP. The carbon content of exposed pre-cut patterned PCP can range from about 0.01 mol% to about 3 mol% relative to 100 mol% of dielectric material.

[0181] Therefore, the exposed preliminary cut pattern PCP and the preliminary cut pattern PCP can have different etching selectivity. In a wet etching process, the exposed preliminary cut pattern PCP can be partially etched, but the preliminary cut pattern PCP can be left unetched.

[0182] Referring again to Figures 21F to 21H, a wet etching process can form a second dicing pattern CP2. The second dicing pattern CP2 can refer to the residue of the initial dicing pattern PCP retained after the wet etching process. The second dicing pattern CP2 can cover the side and bottom surfaces of the first dicing pattern CP1. The second dicing pattern CP2 can include silicon carbide, such as SiOC.

[0183] The second cutting pattern CP2 may include a first cutting portion P1 covering the bottom surface and side surfaces of the first cutting pattern CP1. The first cutting portion P1 may cover the bottom surface of the first cutting pattern CP1, and may also cover the lower portions of the first side surfaces S1, S2, S3, and S4 of the first cutting pattern CP1. The top surface P1_U of the first cutting portion P1 may be located at a horizontal height lower than the horizontal height of the top surface CP1_U of the first cutting pattern CP1. The bottom surface P1_L of the first cutting portion P1 may be located at a horizontal height lower than the horizontal height of the bottom surface CP1_L of the first cutting pattern CP1.

[0184] The second cutting pattern CP2 may include a second cutting portion P2 extending from the first cutting portion P1 in a third direction D3. The second cutting portion P2 may extend onto the upper part of the second side surface S2 and the fourth side surface S4 of the first cutting pattern CP1. Each uppermost surface P2_U of the second cutting portion P2 may be coplanar with the top surface CP1_U of the first cutting pattern CP1. Each uppermost surface P2_U of the second cutting portion P2 may be located at a horizontal height higher than the horizontal height of the top surface P1_U of the first cutting portion P1.

[0185] The first cut portion P1 and the second cut portion P2 may include a first dielectric material containing carbon. The carbon content of the first cut portion P1 may be in the range of approximately 5 mol% to approximately 20 mol% relative to 100 mol% of the first dielectric material. The carbon content of the second cut portion P2 may be in the range of approximately 5 mol% to approximately 20 mol% relative to 100 mol% of the first dielectric material.

[0186] The second cutting pattern CP2 may include a third cutting portion P3 extending from the first cutting portion P1 in the third direction D3. The third cutting portion P3 may extend to the upper part of the first side surface S1 and the third side surface S3 of the first cutting pattern CP1. The width P3_D of each third cutting portion P3 in the second direction D2 may be greater than the width ACT_W of each active trench ACT in the second direction D2.

[0187] The thickness P3_W of each third cut portion P3 may differ from the thickness P2_W of each second cut portion P2. The thickness P3_W of each third cut portion P3 may be measured along a first direction D1 on the side surface of the first cut pattern CP1. The thickness P2_W of each second cut portion P2 may be measured along a second direction D2 on the side surface of the first cut pattern CP1.

[0188] The thickness P3_W of each third cut portion P3 can be less than the thickness P2_W of each second cut portion P2. The thickness P3_W of each third cut portion P3 can be in the range of, for example, about 0.01 nm to about 0.1 nm. The thickness P2_W of each second cut portion P2 can be in the range of, for example, about 3 nm to about 5 nm.

[0189] Each uppermost surface P3_U of the third cutting portion P3 can be coplanar with the top surface P1_U of the first cutting portion P1. Each uppermost surface P3_U of the third cutting portion P3 can be coplanar with the top surface CP1_U of the first cutting pattern CP1.

[0190] According to one or more embodiments, the third cut portion P3 of the second cut pattern CP2 can all have a very small thickness. Therefore, the active cut pattern ACP can have a reduced size (e.g., width in the first direction D1). Therefore, the active contacts AC can all have an increased area, and thus the electrical performance of the semiconductor device can be improved.

[0191] Furthermore, the second dicing pattern CP2 can have a smaller dielectric constant than the first dicing pattern CP1. Therefore, improved capacitance can be provided between adjacent active contacts AC. Consequently, the electrical performance of the semiconductor device can be improved.

[0192] Apart from the methods discussed above, the methods for manufacturing semiconductor devices can be the same as those discussed with reference to Figures 6A to 17H.

[0193] Semiconductor devices according to some embodiments of the present invention may include diced patterns, the dicing patterns comprising a first diced pattern and a second diced pattern. The second diced pattern may be partially removed during the fabrication of the active contact. Therefore, the active contact can have an increased area, and thus the electrical performance of the semiconductor device can be improved.

[0194] Furthermore, the second diced pattern can include a material with a low dielectric constant. Therefore, improved capacitance can be provided between adjacent active patterns. Consequently, the electrical performance of the semiconductor device can be improved.

[0195] Furthermore, the second diced pattern can be formed with increased thickness. Therefore, a reduced distance can be provided between adjacent diced patterns. Since the source / drain patterns can be sufficiently etched even in the etching process used to fabricate active contacts, a method for manufacturing semiconductor devices with improved reliability can be provided.

[0196] Each embodiment described above is not excluded from being associated with one or more features of another example or embodiment that are also provided herein or not provided herein but are consistent with this disclosure.

[0197] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate, the substrate comprising a first active pattern and a second active pattern spaced apart from each other in a first direction parallel to the top surface of the substrate; The first source / drain pattern is located on the first active pattern; The second source / drain pattern is located on the second active pattern; The first active contact is located on the first source / drain pattern; The second active contact is located on the second source / drain pattern; The dicing pattern is located between the first active contact and the second active contact, wherein the dicing pattern includes: a first dicing pattern located between the first active contact and the second active contact and extending toward the substrate; and a second dicing pattern located on at least one side surface of the first dicing pattern and on the bottom surface of the first dicing pattern, and exposing at least a portion of the at least one side surface of the first dicing pattern.

2. The semiconductor device according to claim 1, wherein, The first cutting pattern includes a material different from that of the second cutting pattern.

3. The semiconductor device according to claim 1, wherein, The dielectric constant of the second cut pattern is less than that of the first cut pattern.

4. The semiconductor device according to claim 1, wherein, The first dicing pattern comprises silicon nitride, and the second dicing pattern comprises silicon oxide.

5. The semiconductor device according to claim 1, further comprising: The first channel pattern is located on the first active pattern; The second channel pattern is located on the second active pattern; And a gate electrode extending across the first channel pattern and the second channel pattern, wherein at least a portion of the second diced pattern overlaps the gate electrode in a second direction perpendicular to the top surface of the substrate.

6. The semiconductor device according to claim 1, wherein, The first side surface of the first cut pattern contacts the first active contact, and the first side surface of the first cut pattern is exposed by the second cut pattern.

7. The semiconductor device according to claim 1, wherein, The thickness of the second cutting pattern is 3nm to 5nm.

8. The semiconductor device according to claim 1, wherein, The bottom surface of the second cutting pattern is located at a lower horizontal level than the bottom surface of the first cutting pattern.

9. The semiconductor device according to claim 1, wherein, The first cutting pattern has a first side surface and a second side surface that are opposite to each other in a second direction that is parallel to the top surface of the substrate and intersects the first direction, wherein the second cutting pattern includes a plurality of first cutting portions spaced apart from each other in the second direction, and wherein the plurality of first cutting portions at least partially cover the first side surface and the second side surface of the first cutting pattern.

10. The semiconductor device according to claim 9, wherein, The plurality of first cut portions are spaced apart from each other by a first distance in the second direction, wherein the first distance between the plurality of first cut portions in the second direction is greater than the width of the first active contact in the second direction.

11. A semiconductor device, the semiconductor device comprising: A substrate, the substrate comprising a first active pattern and a second active pattern; The first source / drain pattern is located on the first active pattern; The second source / drain pattern is located on the second active pattern; The first active contact is located on the first source / drain pattern; The second active contact is located on the second source / drain pattern; The dicing pattern is located between the first active contact and the second active contact, wherein the dicing pattern includes: a first dicing pattern located between the first active contact and the second active contact and extending toward the substrate; and a second dicing pattern located on at least one side surface and a bottom surface of the first dicing pattern, wherein the first dicing pattern includes: a first side surface facing the first active contact; and a second side surface intersecting the first side surface, wherein the second dicing pattern includes: a first dicing portion located on the first side surface of the first dicing pattern and having a first thickness; and a second dicing portion located on the second side surface of the first dicing pattern and having a second thickness, wherein the first thickness is different from the second thickness.

12. The semiconductor device according to claim 11, wherein, The first thickness of the first cut portion is less than the second thickness of the second cut portion.

13. The semiconductor device according to claim 11, wherein, The second thickness of the second cut portion is 3nm to 5nm.

14. The semiconductor device of claim 11, wherein, The first cut portion includes a first dielectric material containing carbon, wherein the second cut portion includes a second dielectric material containing carbon, and wherein the carbon content of the first cut portion is less than the carbon content of the second cut portion.

15. The semiconductor device according to claim 14, wherein, The carbon content of the first cut portion is 0.01 mol% to 3 mol% relative to 100 mol% of the first dielectric material, and the carbon content of the second cut portion is 5 mol% to 20 mol% relative to 100 mol% of the second dielectric material.

16. The semiconductor device according to claim 11, wherein, The first cutting pattern has an etching selectivity that is different from the etching selectivity of the first cutting portion of the second cutting pattern.

17. The semiconductor device according to claim 11, wherein, The first cutting pattern includes a material different from that of the second cutting pattern.

18. The semiconductor device according to claim 11, wherein, The first cut portion contacts the first active contact.

19. A semiconductor device, the semiconductor device comprising: A substrate, the substrate comprising a first active pattern and a second active pattern; Device isolation layer, the device isolation layer being located between the first active pattern and the second active pattern; first source / drain pattern, the first source / drain pattern being located on the first active pattern; first channel pattern, the first channel pattern being located on the first active pattern; The second source / drain pattern is located on the second active pattern; The second channel pattern is located on the second active pattern; A gate electrode that extends across the first channel pattern and the second channel pattern; The first active contact is located on the first source / drain pattern; The second active contact is located on the second source / drain pattern; The dicing pattern is located between the first active contact and the second active contact, wherein the dicing pattern includes: a first dicing pattern located between the first active contact and the second active contact and extending toward the substrate; and a second dicing pattern located on at least one side surface of the first dicing pattern and on the bottom surface of the first dicing pattern, and exposing at least a portion of the at least one side surface of the first dicing pattern.

20. The semiconductor device according to claim 19, wherein, The first dicing pattern comprises silicon nitride, and the second dicing pattern comprises silicon oxide.

Images