Display device

Abstract

An embodiment of the present disclosure relates to a display device, and more particularly, to a display device capable of improving brightness uniformity in an optical region and enhancing light transmittance in the optical region by connecting a first signal line electrically connected to a voltage line in a region adjacent to the optical region to a second signal line.

Description

Display device

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0149973, filed on October 29, 2024, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] This invention relates to a display device. Background Technology

[0004] With technological advancements, display devices can now offer not only image display capabilities but also a variety of other functions such as image capture and sensing. To achieve this, display devices require optoelectronic devices (also known as light receivers or sensors) such as cameras and sensing sensors.

[0005] Because optoelectronic devices need to receive light from the front of the display device, they must be positioned to facilitate light reception. Therefore, conventional display devices must expose the camera (camera lens) and sensing sensors at the front. As a result, the bezels of the display panel become wider, or notches or physical holes are formed in the display area to accommodate the optoelectronic devices.

[0006] In other words, as optoelectronic devices (such as cameras and sensing sensors) that receive forward-facing light and perform specific functions are included in the display device, the bezel of the display device may become larger, or design constraints may arise for the front (or front-facing) design of the display device. Furthermore, when a display device includes optoelectronic devices, unexpected image quality degradation may occur due to the structure housing the optoelectronic devices. Summary of the Invention

[0007] Embodiments of this disclosure may provide a display device in which optoelectronic devices are not exposed at the front of the display device, while still allowing optoelectronic devices disposed below the display panel of the display device to properly receive light through a light-transmitting structure.

[0008] Embodiments of this disclosure may provide a display device that improves brightness uniformity and enhances transmittance within an optical region by connecting multiple signal lines (e.g., DC signal lines, also known as DC signal lines) in a mesh structure in a region adjacent to the optical region.

[0009] Embodiments of this disclosure may provide a display device that ensures brightness uniformity in the optical region, thereby improving optical characteristics and output while achieving low-power operation.

[0010] Embodiments of this disclosure may provide a display device comprising: a display panel including (or containing) an optical region having a plurality of transmissive regions and a plurality of first emitting regions, and a general region (also referred to as a common area) disposed outside the optical region and having a plurality of second emitting regions. The display device may further include optoelectronic devices disposed below the display panel and overlapping the optical region. The general area may include a plurality of signal lines connected in a mesh structure in a region adjacent to the optical region.

[0011] The plurality of signal lines may include a plurality of first signal lines extending in a first direction and at least one second signal line extending in a second direction intersecting the first direction. The second signal line may be electrically connected in a region adjacent to the optical region to at least two of the plurality of first signal lines that are electrically connected to the same voltage line.

[0012] Embodiments of this disclosure may provide a display device comprising: a display panel including a normal area and an optical area overlapping with optoelectronic devices disposed below the display panel; the display panel comprising: a substrate; a transistor layer disposed on the substrate and including at least one transistor and a passivation layer disposed on the at least one transistor; a first signal line disposed on the passivation layer in the normal area and electrically connected to a voltage line; a plurality of planarization layers disposed on the transistor layer and the first signal line; a second signal line disposed on any one of the plurality of planarization layers in the normal area and electrically connected to the first signal line in a region adjacent to the optical area; and a light-emitting device layer disposed on the plurality of planarization layers and including a plurality of light-emitting devices corresponding to each of the optical area and the normal area.

[0013] According to embodiments of the present disclosure, a display device may be provided in which optoelectronic devices are not exposed at the front of the display device, while still allowing optoelectronic devices disposed below the display panel of the display device to properly receive light through a light transmission structure.

[0014] According to embodiments of this disclosure, by connecting signal lines (e.g., DC signal lines, hereinafter referred to as DC signal lines) in a mesh structure in a region adjacent to the optical region, the brightness variation in the optical region can be improved, and the transmittance in the optical region can be enhanced.

[0015] According to embodiments of this disclosure, brightness uniformity in the optical region can be ensured, thereby improving optical characteristics and output while enabling low-power operation. Attached Figure Description

[0016] Figures 1A to 1E are graphics illustrating a display device according to an embodiment of the present disclosure.

[0017] Figure 2 is a diagram illustrating the system configuration of a display device according to an embodiment of the present disclosure.

[0018] Figure 3 is a graphic illustrating an example of a sub-pixel according to an embodiment of the present disclosure.

[0019] Figure 4 is a graphic illustrating another example of a sub-pixel according to an embodiment of the present disclosure.

[0020] Figure 5 is a diagram illustrating the arrangement of subpixels in the normal area and the optical area according to an embodiment of the present disclosure.

[0021] Figure 6 is a graphic illustrating an example of a signal line connection structure in a display panel according to an embodiment of the present disclosure.

[0022] Figure 7 is a graphic illustrating another example of a signal line connection structure in a display panel according to an embodiment of the present disclosure.

[0023] Figures 8 and 9 are diagrams further illustrating the signal line connection structure in a display panel according to an embodiment of the present disclosure.

[0024] Figures 10 and 11 are diagrams illustrating implementation examples of a display device according to embodiments of the present disclosure. Detailed Implementation

[0025] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and in which the same reference numerals and symbols may be used to denote the same or similar components, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that the description may make the subject matter of some embodiments of the invention considerably unclear. Terms such as “comprising (or including),” “having,” “containing,” “constituting,” “composed of,” and “formed by” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0026] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements (or components) of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is merely used to distinguish the corresponding element from other elements.

[0027] When referring to the first element and the second element as "connected or coupled," "in contact or overlapping," etc., it should be interpreted as meaning that not only can the first element be "directly connected or coupled" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact or overlapping," etc., with each other.

[0028] When time-relative terms such as “after,” “following,” “next,” or “before” are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a non-continuous or non-sequential process or operation, unless the terms “directly” or “immediately” are used together.

[0029] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical or corresponding information of the component or feature (e.g., level, range, etc.) includes tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0030] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Figures 1A to 1E are graphics of a display device 100 according to an embodiment of the present disclosure.

[0032] Referring to Figures 1A to 1E, a display device 100 according to an embodiment of the present disclosure may include (or contain) a display panel 110 for displaying images and at least one optoelectronic device (e.g., a first optoelectronic device 11 and a second optoelectronic device 12).

[0033] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images.

[0034] In the display area DA, multiple sub-pixels can be arranged, and various signal lines for driving the multiple sub-pixels can be set.

[0035] The non-display area NDA can be the outer area of ​​the display area DA. Various signal lines can be arranged in the non-display area NDA, and various driving circuits can be connected to it. The non-display area NDA can be bent so that it is not visible from the front (or front surface), or it can be covered by a housing (not shown). The non-display area NDA is also referred to as the bezel or bezel area.

[0036] Referring to Figures 1A to 1D, in a display device 100 according to an embodiment of the present disclosure, the at least one optoelectronic device (e.g., a first optoelectronic device 11 and a second optoelectronic device 12) may be an electronic component located below the display panel 110 (i.e., on the opposite side of the viewing surface).

[0037] External light can enter through the front surface (viewing surface) of the display panel 110, pass through the display panel 110, and be transmitted to the at least one optoelectronic device (e.g., the first optoelectronic device 11 and the second optoelectronic device 12) located below the display panel 110.

[0038] The at least one optoelectronic device (e.g., the first optoelectronic device 11 and the second optoelectronic device 12) can receive external light transmitted through the display panel 110 and perform a predetermined function based on the received external light. For example, the at least one optoelectronic device (e.g., the first optoelectronic device 11 and the second optoelectronic device 12) may include at least one of an imaging device (or imaging apparatus) such as a camera (image sensor) and a sensing sensor such as a proximity sensor or an ambient light sensor.

[0039] Referring to Figures 1A to 1E, in a display panel 110 according to an embodiment of the present disclosure, the display area DA may include a normal area NA and at least one optical area (e.g., a first optical area OA1 and a second optical area OA2).

[0040] The at least one optical region (e.g., the first optical region OA1 and the second optical region OA2) may be a region that overlaps with at least one optoelectronic device (e.g., the first optoelectronic device 11 and the second optoelectronic device 12).

[0041] According to the example in Figure 1A, the display area DA may include a general area NA and a first optical area OA1. Here, at least a portion of the first optical area OA1 may overlap with the first optoelectronic device 11.

[0042] In FIG1A, the first optical region OA1 is shown as having a circular shape; however, the shape of the first optical region OA1 according to embodiments of the present disclosure is not limited thereto.

[0043] For example, as shown in Figure 1B, the first optical region OA1 can have an octagonal shape, and it can also have various polygonal shapes.

[0044] According to the example in Figure 1C, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of Figure 1C, the general area NA can be arranged between the first optical area OA1 and the second optical area OA2 (that is, the first optical area OA1 and the second optical area OA2 may not be in contact with each other). Here, at least a portion of the first optical area OA1 may overlap with the first optoelectronic device 11, and at least a portion of the second optical area OA2 may overlap with the second optoelectronic device 12.

[0045] According to the example in Figure 1D, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of Figure 1D, the general area NA may not be placed between the first optical area OA1 and the second optical area OA2. That is, the first optical area OA1 and the second optical area OA2 may be in contact with each other. Here, at least a portion of the first optical area OA1 may overlap with the first optoelectronic device 11, and at least a portion of the second optical area OA2 may overlap with the second optoelectronic device 12.

[0046] According to the example in Figure 1E, the display panel 110 also includes an aperture region H, in which a second optoelectronic device 12 is disposed, and the aperture region H is surrounded by a normal region NA. In the aperture region H, the second optoelectronic device 12 can be positioned above the display panel 110. However, embodiments of this disclosure are not limited thereto, and the aperture region H can be a second optical region OA2, in which the second optoelectronic device 12 is positioned below the display panel 110 within the display region DA.

[0047] The display area DA on the display panel 110 may include a first optical area OA1 and a normal area NA.

[0048] According to the example in Figure 1E, a normal area NA is provided between the first optical area OA1 and the aperture area H, and the aperture area H is located on an imaginary center line that vertically divides the display panel 110. The first optical area OA1 may be spaced apart from the aperture area H to the left or right relative to the imaginary center line.

[0049] In Figure 1E, the first optical region OA1 and the aperture region H are shown to have the same size; however, embodiments of this disclosure are not limited thereto. For example, the sizes of the first optical region OA1 and the aperture region H may be different. For example, the size of the first optical region OA1 may be smaller than the size of the aperture region H.

[0050] According to an embodiment of the present disclosure, the display device 100 can improve the transmittance of at least one optical zone (e.g., the first optical zone OA1 and the second optical zone OA2) by removing signal lines (e.g., DC signal lines) from the at least one optical zone (e.g., the first optical zone OA1 and the second optical zone OA2). In this case, if the at least one optical zone (e.g., the first optical zone OA1 and the second optical zone OA2) is located on one side of the display panel 110, that is, on the left or right side relative to an imaginary center line, as shown in the example of FIG1E, an RC load difference may occur in the common power lines (such as DC signal lines) provided in the left non-display area NDA and the right non-display area NDA of the display panel 110. Therefore, left / right brightness variations may occur within the at least one optical zone (e.g., the first optical zone OA1 and the second optical zone OA2).

[0051] Therefore, the display device 100 according to embodiments of this disclosure can improve the left / right brightness deviation within at least one optical zone (e.g., the first optical zone OA1 and the second optical zone OA2) caused by differences in RC load by using data dummy lines (also called data virtual lines) to connect at least one signal line (e.g., a DC signal line) in a mesh structure. Additionally, it can enhance the transmittance of said at least one optical zone (e.g., the first optical zone OA1 and the second optical zone OA2).

[0052] For example, a DC signal line may include at least one of an initialization voltage line providing an initialization voltage Vini, a reset voltage line providing a reset voltage VAR, and a bias voltage line applying a bias voltage VOBS.

[0053] The at least one optical region (e.g., the first optical region OA1 and the second optical region OA2) may include both an image display structure and a light transmission structure. That is, since the at least one optical region (e.g., the first optical region OA1 and the second optical region OA2) is part of the display area DA, sub-pixels for image display must be arranged within the at least one optical region (e.g., the first optical region OA1 and the second optical region OA2). Furthermore, the at least one optical region (e.g., the first optical region OA1 and the second optical region OA2) must include a light-transmitting structure to allow light to pass through and reach the at least one optoelectronic device (e.g., the first optoelectronic device 11 and the second optoelectronic device 12).

[0054] In the following text, the image display structure may be referred to as the emission region, and the light transmission structure may be referred to as the transmission region.

[0055] The at least one optoelectronic device (e.g., the first optoelectronic device 11 and the second optoelectronic device 12) is a device that needs to receive light; however, it is positioned below the display panel 110 (on the opposite side of the viewing surface) and can receive light transmitted through the display panel 110.

[0056] At least one optoelectronic device (e.g., first optoelectronic device 11 and second optoelectronic device 12) is not exposed on the front surface (viewing surface) of the display panel 110. Therefore, optoelectronic devices 11 and 12 may not be visible when the user views the front of the display device 100.

[0057] For example, the first optoelectronic device 11 can be a sensing sensor such as a proximity sensor or an ambient light sensor, while the second optoelectronic device 12 can be a camera. The sensing sensor can be, for example, an infrared sensor that detects infrared light.

[0058] Conversely, the first optoelectronic device 11 can be a camera, and the second optoelectronic device 12 can be a sensing sensor.

[0059] In the following text, for ease of explanation, an example will be described in which the first optoelectronic device 11 is a sensing sensor and the second optoelectronic device 12 is a camera. Here, "camera" can refer to a camera lens or an image sensor.

[0060] When the second optoelectronic device 12 is a camera, the camera is positioned below the display panel 110, but it can be a front-facing camera that captures images in the direction of the front of the display panel 110. Therefore, the user can use the camera to take pictures, and the camera is not visible on the viewing surface when viewing the display panel 110.

[0061] The ordinary area NA and the at least one optical area (e.g., the first optical area OA1 and the second optical area OA2) are display areas DA capable of displaying images. However, the ordinary area NA is an area where a light transmission structure does not need to be formed, while the at least one optical area (e.g., the first optical area OA1 and the second optical area OA2) is an area where a light transmission structure must be formed.

[0062] Therefore, the at least one optical region (e.g., the first optical region OA1 and the second optical region OA2) needs to have a transmittance higher than a certain level, while the ordinary region NA may have no transmittance or may have a low transmittance lower than a certain level.

[0063] For example, the at least one optical region (e.g., the first optical region OA1 and the second optical region OA2) and the ordinary region NA) may differ in terms of resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line (or wiring) structure, electrode arrangement structure, or line (or wiring) arrangement structure.

[0064] For example, the number of subpixels per unit area in the at least one optical region (e.g., the first optical region OA1 and the second optical region OA2) can be less than the number of subpixels per unit area in the ordinary region NA. That is, the resolution of the at least one optical region (e.g., the first optical region OA1 and the second optical region OA2) can be lower than the resolution of the ordinary region NA. Here, the number of subpixels per unit area is a unit used to measure resolution and can also be referred to as PPI (pixels per inch), which indicates the number of pixels per inch.

[0065] For example, the number of subpixels per unit area in the first optical region OA1 can be less than the number of subpixels per unit area in the ordinary region NA. The number of subpixels per unit area in the second optical region OA2 can be equal to or greater than the number of subpixels per unit area in the first optical region OA1.

[0066] Each of the first optical region OA1 and the second optical region OA2 can have various shapes, such as circular, elliptical, rectangular, hexagonal, or octagonal. The first optical region OA1 and the second optical region OA2 can have the same or different shapes.

[0067] Referring to Figure 1D, when the first optical region OA1 and the second optical region OA2 are in contact with each other, the entire optical region including the first optical region OA1 and the second optical region OA2 can also have various shapes, such as circles, ellipses, rectangles, hexagons or octagons.

[0068] In the following text, for ease of explanation, an example in which each of the first optical region OA1 and the second optical region OA2 is circular will be described.

[0069] Since the display device 100 according to the embodiments of the present disclosure does not require a notch or hole in the display panel 110 for exposing a camera or sensing sensor, the area of ​​the display area DA may not be reduced.

[0070] Therefore, since the display panel 110 does not require a notch or camera hole for exposing the camera or sensing sensor, the size of the bezel area can be reduced, and design constraints can be eliminated, thereby increasing design freedom.

[0071] Although the at least one optoelectronic device (e.g., the first optoelectronic device 11 and the second optoelectronic device 12) is positioned behind (or below) the display panel 110 in the display device 100 according to an embodiment of the present disclosure, the at least one optoelectronic device (e.g., the first optoelectronic device 11 and the second optoelectronic device 12) must be able to properly receive light and perform its designated function correctly.

[0072] Furthermore, in the display device 100 according to the embodiments of the present disclosure, although at least one optoelectronic device (e.g., the first optoelectronic device 11 and the second optoelectronic device 12) is hidden behind the display panel 110 and overlaps with the display area DA, normal image display must also be possible in at least one optical area OA1 and OA2 that overlaps with the at least one optoelectronic device (e.g., the first optoelectronic device 11 and the second optoelectronic device 12) in the display area DA.

[0073] Figure 2 is a diagram illustrating the system configuration of a display device 100 according to an embodiment of the present disclosure.

[0074] Referring to FIG2, the display device 100 may include a display panel 110 and a display driving circuit as a component for displaying images.

[0075] The display driving circuit is a circuit used to drive the display panel 110, and may include a data driving circuit 220, a gate driving circuit 230, and a controller 240.

[0076] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images. The non-display area NDA may be an outer area of ​​the display area DA and may also be referred to as a border area. All or part of the non-display area NDA may be visible from the front of the display device 100, or it may be bent so that it is not visible from the front of the display device 100.

[0077] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. Additionally, the display panel 110 may also include various types of signal lines for driving the plurality of sub-pixels SP.

[0078] The display device 100 according to embodiments of the present disclosure may be a liquid crystal display (or a liquid crystal display device) or a self-emissive display (or self-emissive display device) in which the display panel 110 emits its own light. If the display device 100 is a self-emissive display, each of the plurality of sub-pixels SP may include a light-emitting device.

[0079] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting device is implemented as an organic light-emitting diode (OLED). In another example, the display device 100 may be an inorganic light-emitting display device in which the light-emitting device is implemented as an inorganic-based light-emitting diode. In yet another example, the display device 100 may be a quantum dot display device in which the light-emitting device is implemented as a quantum dot, which is a self-emissive semiconductor crystal.

[0080] The structure of each of the plurality of sub-pixels SP can vary depending on the type of display device 100. For example, if the display device 100 is a self-emissive display in which the sub-pixels SP emit their own light, then each sub-pixel SP may include a self-emissive light-emitting device, at least one transistor, and at least one capacitor.

[0081] For example, various types of signal lines may include multiple data lines DL that transmit data signals (also known as data voltages or image signals) and multiple gate lines GL that transmit gate signals (also known as scan signals and / or transmit control signals).

[0082] The plurality of data lines DL and the plurality of gate lines GL may intersect each other. Each of the plurality of gate lines GL may be configured to extend in a first direction, and each of the plurality of data lines DL may be configured to extend in a second direction.

[0083] Here, the first direction can be horizontal (row), and the second direction can be vertical (column). Alternatively, the first direction can be vertical, and the second direction can be horizontal.

[0084] The data driving circuit 220 is used to drive the multiple data lines DL and can output data signals to the multiple data lines DL. The gate driving circuit 230 is used to drive the multiple gate lines GL and can output gate signals to the multiple gate lines GL.

[0085] The controller 240 is a device for controlling the data driving circuit 220 and the gate driving circuit 230, and can control the driving timing of the multiple data lines DL and the multiple gate lines GL.

[0086] The controller 240 can supply a data drive control signal DCS to the data drive circuit 220 to control the data drive circuit 220, and can supply a gate drive control signal GCS to the gate drive circuit 230 to control the gate drive circuit 230.

[0087] The controller 240 can receive input image data from the host system 250 and supply image data DATA to the data drive circuit 220 based on the input image data.

[0088] The data driving circuit 220 can supply data signals to the multiple data lines DL according to the driving timing control of the controller 240.

[0089] The data driving circuit 220 can receive digital image data DATA from the controller 240, convert the received image data DATA into an analog data signal, and output the analog data signal to the multiple data lines DL.

[0090] The gate drive circuit 230 can supply gate signals to the plurality of gate lines GL according to the timing control of the controller 240. The gate drive circuit 230 can receive a first gate voltage corresponding to the on-level voltage and a second gate voltage corresponding to the off-level voltage, as well as various gate drive control signals GCS, generate gate signals, and supply the generated gate signals to the plurality of gate lines GL.

[0091] For example, the data drive circuit 220 can be connected to the display panel 110 using a tape auto-bonding (TAB) method, or it can be connected to the pads of the display panel 110 using a chip-on-glass (COG) method or a chip-on-panel (COP) method. Alternatively, it can be implemented and connected to the display panel 110 using a chip-on-film (COF) method.

[0092] The gate driving circuit 230 can be connected to the display panel 110 using a tap-on-buck (TAB) method, or it can be connected to the pads of the display panel 110 using a chip-on-glass (COG) method or a chip-on-panel (COP) method. Alternatively, it can be connected to the display panel 110 using a chip-on-film (COF) method. Furthermore, the gate driving circuit 230 can be formed as a gate-on-panel (GIP) type in the non-display area NDA of the display panel 110. The gate driving circuit 230 can be disposed on or connected to the substrate. Specifically, when the gate driving circuit 230 is of the GIP type, it can be disposed in the non-display area NDA of the display panel 110 (or the substrate). When the gate driving circuit 230 is of the chip-on-glass (COG) type or the chip-on-film (COF) type, it can be connected to the substrate.

[0093] Meanwhile, at least one of the data driving circuit 220 and the gate driving circuit 230 can be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 can be configured not to overlap with the sub-pixel SP, or can be configured to partially or completely overlap with the sub-pixel SP.

[0094] The data driving circuit 220 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method or panel design method, the data driving circuit 220 can be connected to both sides of the display panel 110 (e.g., the top and bottom sides) or two or more of the four sides of the display panel 110.

[0095] The gate drive circuit 230 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving method or panel design method, the gate drive circuit 230 can be connected to both sides of the display panel 110 (e.g., the left and right sides) or two or more of the four sides of the display panel 110.

[0096] The controller 240 can be implemented as a component separate from the data drive circuit 220, or it can be integrated with the data drive circuit 220 and implemented as an integrated circuit.

[0097] The controller 240 may be a timing controller commonly used in display technology, a control device that includes a timing controller and performs additional control functions, or a control device separate from the timing controller. Alternatively, it may be circuitry within a control device. The controller 240 may be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0098] The controller 240 can be mounted on a printed circuit board or flexible printed circuit and is electrically connected to the data drive circuit 220 and the gate drive circuit 230 via the printed circuit board or flexible printed circuit.

[0099] The controller 240 can send signals to and receive signals from the data drive circuit 220 according to at least one predefined interface. For example, the interface may include Low Voltage Differential Signaling (LVDS), Embedded Clock Point-to-Point Interface (EPI), or Serial Peripheral Interface (SPI).

[0100] The display device 100 according to an embodiment of the present disclosure may further include a touch sensor and a touch sensing circuit, the touch sensing circuit sensing the touch sensor to detect whether a touch object (such as a finger or pen) has been touched, or to detect the touch position, so as to provide not only image display function, but also touch sensing function.

[0101] The touch sensing circuit may include: a touch driving circuit 260 that drives and senses the touch sensor to generate and output touch sensing data; and a touch controller 270 that detects a touch occurrence or determines the touch location based on the touch sensing data.

[0102] The touch sensor may include multiple touch electrodes. Additionally, the touch sensor may include multiple touch lines to electrically connect the multiple touch electrodes to the touch driving circuit 260.

[0103] The touch sensor can exist externally in the form of a touch panel, or it can be located inside the display panel 110. When the touch sensor is externally presented as a touch panel, it is referred to as an external type. If the touch sensor is an external type touch sensor, the touch panel and the display panel 110 are manufactured separately and can be combined during the assembly process. An external type touch panel may include a touch panel substrate and a plurality of touch electrodes located on the touch panel substrate.

[0104] When the touch sensor is located inside the display panel 110, the touch sensor can be formed on the substrate SUB together with the signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0105] The touch driving circuit 260 can supply touch driving signals to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0106] Touch sensing circuits can use self-capacitance sensing or mutual capacitance sensing to perform touch sensing.

[0107] When a touch sensing circuit performs touch sensing using a self-capacitance sensing method, it can detect a touch based on the capacitance between each touch electrode and the touch object (e.g., a finger or a pen).

[0108] In the self-capacitance sensing method, each of the plurality of touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive and sense all or some of the plurality of touch electrodes.

[0109] When a touch sensing circuit uses a mutual capacitance sensing method to perform touch sensing, it can detect touch based on the capacitance between the touch electrodes.

[0110] In the mutual capacitance sensing method, the plurality of touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0111] The touch driver circuit 260 and touch controller 270 included in the touch sensing circuit can be implemented as separate devices or as a single integrated device. Additionally, the touch driver circuit 260 and data driver circuit 220 can also be implemented as separate devices or as a single integrated device.

[0112] The display device 100 may also include a power supply circuit that supplies various power sources to the display driving circuit and / or touch sensing circuit.

[0113] The display device 100 according to embodiments of the present disclosure may be a mobile terminal such as a smartphone or tablet computer, or a monitor or television (TV) of various sizes. However, the display device 100 is not limited to these and may encompass various types and sizes of displays capable of displaying information or images.

[0114] As described above, the display area DA in the display panel 110 may include a normal area NA and at least one optical area (e.g., a first optical area OA1 and a second optical area OA2).

[0115] The ordinary region NA and the at least one optical region (e.g., the first optical region OA1 and the second optical region OA2) are areas capable of displaying an image. However, the ordinary region NA does not require a light transmission structure, while the at least one optical region (e.g., the first optical region OA1 and the second optical region OA2) must have a light transmission structure.

[0116] Figure 3 is a graphic illustrating an example of a sub-pixel SP according to an embodiment of the present disclosure.

[0117] Referring to Figure 3, each of the plurality of sub-pixels SP disposed in the ordinary area NA, the first optical area OA1, and the second optical area OA2 of the display area DA included in the display panel 110 can be disposed on the substrate SUB. Each sub-pixel SP may include a light-emitting device ED disposed in the emitting area (or light-emitting area), a driving transistor DRT for driving the light-emitting device ED, a scanning transistor SCT for transmitting the data voltage VDATA to the first node N1 of the driving transistor DRT, and a storage capacitor Cst for maintaining a specific voltage within a frame period.

[0118] The driving transistor DRT may include a first node N1 to which a data voltage is applied, a second node N2 electrically connected to a light-emitting device ED, and a third node N3 to which a driving voltage ELVDD is applied from the driving voltage line DVL.

[0119] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT, and can be electrically connected to the source node or drain node of the scanning transistor SCT.

[0120] The second node N2 of the driving transistor DRT can be the source node or the drain node of the driving transistor DRT, and can be electrically connected to the pixel electrode PE of the light-emitting device ED.

[0121] The third node N3 of the driving transistor DRT can be either the drain node or the source node of the driving transistor DRT.

[0122] A storage capacitor Cst can be connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst is charged with a charge corresponding to the voltage difference between its two ends and is used to maintain the voltage difference within a predetermined frame period. Therefore, the corresponding sub-pixel SP can emit light during the predetermined frame period.

[0123] The scanning transistor SCT can be controlled by a gate signal and can be connected between the first node N1 of the driving transistor DRT and the data line DL.

[0124] The scanning transistor SCT can be turned on by a gate signal of the turn-on level voltage supplied from the gate line GL, thereby transmitting the data voltage VDATA supplied from the data line DL to the first node N1 of the driving transistor DRT.

[0125] The scanning transistor SCT and the driving transistor DRT can be either n-type or p-type transistors.

[0126] If the scanning transistor SCT is an n-type transistor, the gate signal turn-on voltage can be a high level voltage. If the scanning transistor SCT is a p-type transistor, the gate signal turn-on voltage can be a low level voltage.

[0127] The light-emitting device (ED) may include a pixel electrode (PE), a light-emitting layer (EL), and a common electrode (CE). A reference voltage may be applied to the common electrode (CE).

[0128] For example, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode. Conversely, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode. In the following text, for ease of explanation, it will be assumed that the pixel electrode PE is an anode electrode and the common electrode CE is a cathode electrode.

[0129] For example, the light-emitting device (ED) can be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting device. In this case, if the ED is an OLED, the light-emitting layer (EL) in the ED can include an organic light-emitting layer containing organic materials.

[0130] The storage capacitor Cst is not an internal capacitor (e.g., a parasitic capacitor such as Cgs or Cgd) existing between the gate node and source node (or drain node) of the driving transistor DRT. Instead, the storage capacitor Cst can be an external capacitor intentionally designed to be outside the driving transistor DRT.

[0131] Since the circuit elements (especially the light-emitting devices, EDs) in each sub-pixel SP are susceptible to external moisture and oxygen, an encapsulation layer ENCAP can be provided in the display panel to prevent moisture or oxygen from penetrating into the circuit elements (especially the light-emitting devices, EDs). The encapsulation layer ENCAP can be configured to cover the light-emitting devices, EDs.

[0132] The structure of the sub-pixel SP shown in Figure 3 is only an example and can be modified in various ways to include one or more additional transistors or one or more additional capacitors.

[0133] For example, a sub-pixel SP may also include a plurality of transistors electrically connected to each of a DC signal line such as an initialization voltage line, a reset voltage line, and a bias voltage line. The structure of the sub-pixel SP electrically connected to the DC signal lines will now be described with reference to the embodiment shown in FIG4.

[0134] Figure 4 is a graphic illustrating another example of a sub-pixel SP according to an embodiment of the present disclosure.

[0135] Referring to Figure 4, each of the multiple sub-pixels SP can be connected to the data line DL supplying the data voltage VDATA, the first scan line SCL1 supplying the first scan signal SC1, the second scan line SCL2 supplying the second scan signal SC2, the third scan line SCL3 supplying the third scan signal SC3, the fourth scan line SCL4 supplying the fourth scan signal SC4, and the transmit control signal line EML supplying the transmit control signal EM.

[0136] The gate drive circuit 230 can output each of the first scan signal SC1 to the fourth scan signal SC4 and the transmit control signal EM to the first scan line SCL1 to the fourth scan line SCL4 and the transmit control signal line EML, respectively. To achieve this, the gate drive circuit 230 may include a first scan driver to a fourth scan driver that respectively generates the first scan signal SC1 to the fourth scan signal SC4, and an transmit control driver that generates the transmit control signal EM. However, embodiments of this disclosure are not limited thereto.

[0137] Referring to Figure 4, the sub-pixel SP may include a driving transistor DRT, a first transistor T1 to a seventh transistor T7, a storage capacitor Cst, and a light-emitting device ED.

[0138] Each transistor (e.g., the driver transistor DRT and the first transistors T1 through the seventh transistor T7) may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0139] Each transistor (e.g., the driving transistor DRT and the first transistors T1 through T7) can be a p-type transistor or an n-type transistor. In the example of FIG4, the first transistor T1 and the seventh transistor T7 are n-type transistors, while the remaining transistors (e.g., the driving transistor DRT and the second transistors T2 through T6) are p-type transistors. However, embodiments of the present invention are not limited thereto, and all or some of the transistors (e.g., the driving transistor DRT and the first transistors T1 through T7) can be p-type or n-type transistors. Furthermore, the n-type transistor can be an oxide thin-film transistor (TFT) or a polycrystalline silicon TFT, while the p-type transistor can be a polycrystalline silicon TFT or an oxide TFT.

[0140] In the following description, it will be provided under the assumption that the first transistor T1 and the seventh transistor T7 are n-type transistors and the remaining transistors (e.g., the drive transistor DRT and the second transistors T2 through the sixth transistor T6) are p-type transistors. Therefore, when a high-level voltage is applied to their gate nodes, the first transistor T1 and the seventh transistor T7 can be turned on, and when a low-level voltage is applied to their gate nodes, the remaining transistors (e.g., the drive transistor DRT and the second transistors T2 through the sixth transistor T6) can be turned on.

[0141] The first transistor T1 can be used as a compensation transistor, the second transistor T2 can be used as a data supply transistor, the third transistor T3 and the fourth transistor T4 can be used as emitter control transistors, the fifth transistor T5 can be used as a bias transistor, and the sixth transistor T6 and the seventh transistor T7 can be used as initialization transistors.

[0142] The light-emitting device (ED) may include a pixel electrode (e.g., an anode electrode) and a common electrode (e.g., a cathode electrode). The pixel electrode of the ED may be connected to a fifth node N5, and a reference voltage may be applied to the common electrode.

[0143] The driving transistor DRT may include a first electrode connected to a second node N2, a second electrode connected to a third node N3, and a gate electrode connected to a first node N1. The driving transistor DRT can supply driving current to the light-emitting device ED based on the voltage at the first node N1 (or the data voltage stored in the storage capacitor Cst).

[0144] The first transistor T1 may include a first electrode connected to a first node N1, a second electrode connected to a third node N3, and a gate electrode for receiving a first scan signal SC1. The first transistor T1 can be turned on in response to the first scan signal SC1. When the first transistor T1 is turned on, the first node N1 and the third node N3 are electrically connected, causing the driving transistor DRT to be in a diode-connected state, thereby allowing sampling of its threshold voltage Vth. In this sense, the first transistor T1 can be referred to as a compensation transistor.

[0145] The storage capacitor Cst can be connected or formed between the first node N1 and the fourth node N4. The storage capacitor Cst can store or maintain the drive voltage ELVDD.

[0146] The second transistor T2 may include a first electrode that receives data voltage VDATA via data line DL, a second electrode connected to the second node N2, and a gate electrode that receives the second scan signal SC2.

[0147] The second transistor T2 can be turned on in response to the second scan signal SC2, thereby transmitting the data voltage VDATA to the second node N2. In this sense, the second transistor T2 can be referred to as the data supply transistor.

[0148] The third transistor T3 can be connected between the fourth node N4 and the second node N2, while the fourth transistor T4 can be connected between the third node N3 and the fifth node N5. These transistors can form a current flow path through which the driving current flows. Here, the third transistor T3 and the fourth transistor T4 can also be referred to as the first emitter control transistor and the second emitter control transistor, respectively.

[0149] The third transistor T3 may include: a first electrode connected to a fourth node N4, wherein a drive voltage EVDD is applied to the fourth node N4; a second electrode connected to a second node N2; and a gate electrode that receives a transmit control signal EM.

[0150] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5, and a gate electrode for receiving the transmit control signal EM. Here, the fifth node N5 may electrically correspond to the anode electrode of the light-emitting device ED.

[0151] The third transistor T3 and the fourth transistor T4 can be simultaneously turned on in response to the emission control signal EM(n). When the third transistor T3 and the fourth transistor T4 are turned on, a drive current can be supplied to the light-emitting device ED. The light-emitting device ED can emit light with a brightness corresponding to the drive current.

[0152] The fifth transistor T5 may include a first electrode to which a bias voltage VOBS is applied via a bias voltage line, a second electrode connected to the second node N2, and a gate electrode to which a third scan signal SC3 is applied. The fifth transistor T5 may also be referred to as a bias transistor.

[0153] The sixth transistor T6 may include a first electrode to which a reset voltage VAR is applied via a reset voltage line, a second electrode connected to the fifth node N5, and a gate electrode to which a third scan signal SC3 is applied.

[0154] The sixth transistor T6 can be turned on in response to the third scan signal SC3 before (or after) the light-emitting device ED emits light. Therefore, the reset voltage VAR can be applied to the fifth node N5 to initialize the anode electrode (or pixel electrode) of the light-emitting device ED.

[0155] A light-emitting device (ED) may have a parasitic capacitor formed between its anode and cathode electrodes. When the ED emits light, the parasitic capacitor can be charged, resulting in a specific voltage at the anode electrode of the ED. Therefore, by applying a reset voltage VAR to the anode electrode of the ED via a sixth transistor T6, the charge accumulated in the ED can be reset.

[0156] According to the example in Figure 4, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 can be configured to jointly receive the third scan signal SC3. However, embodiments of this disclosure are not limited thereto, and the fifth transistor T5 and the sixth transistor T6 can be configured to receive different scan signals, so that they can be controlled independently.

[0157] The seventh transistor T7 may include a first electrode to which an initialization voltage Vini is applied via an initialization voltage line, a second electrode connected to the first node N1, and a gate electrode to which a fourth scan signal SC4 is applied.

[0158] The seventh transistor T7 can be turned on in response to the fourth scan signal SC4. Therefore, the initialization voltage Vini can be applied to the first node N1, which corresponds to the gate electrode of the driving transistor DRT. Thus, the gate electrode of the driving transistor DRT can be initialized.

[0159] Unwanted charge may remain in the gate electrode of the driving transistor DRT due to the driving voltage EVDD stored in the capacitor Cst. Therefore, the residual charge can be reset by applying the initialization voltage Vini to the gate electrode of the driving transistor DRT via the seventh transistor T7.

[0160] Figure 5 is a diagram illustrating the arrangement of sub-pixels SP in the general area NA, the first optical area OA1, and the second optical area OA2 according to an embodiment of the present disclosure.

[0161] Referring to Figure 5, multiple sub-pixels SP can be arranged in each of the ordinary area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA.

[0162] For example, the plurality of sub-pixels SP may include a red sub-pixel Red SP that emits red light, a green sub-pixel Green SP that emits green light, and a blue sub-pixel Blue SP that emits blue light.

[0163] Therefore, each of the ordinary area NA, the first optical area OA1, and the second optical area OA2 may include multiple emission areas EA corresponding to the red sub-pixel Red SP, multiple emission areas EA corresponding to the green sub-pixel Green SP, and multiple emission areas EA corresponding to the blue sub-pixel Blue SP.

[0164] In the following text, for ease of description, the emission area EA included in the first optical region OA1 and the second optical region OA2 may be referred to as the first emission area, and the emission area EA included in the ordinary region NA may be referred to as the second emission area.

[0165] Referring to Figure 5, the ordinary region NA may not contain a transmissive region (i.e., a light-transmitting structure), but may contain multiple emitting regions EA.

[0166] However, the first optical region OA1 and the second optical region OA2 may include not only multiple emission regions EA, but also multiple transmission regions.

[0167] In other words, the first optical region OA1 may include multiple emission regions EA and multiple first transmission regions TA1, and the second optical region OA2 may include multiple emission regions EA and multiple second transmission regions TA2.

[0168] The plurality of emission regions EA, the plurality of first transmission regions TA1, and the plurality of second transmission regions TA2 can be distinguished based on whether they allow light transmission. Specifically, the plurality of emission regions EA can be regions where light transmission is blocked, while the plurality of first transmission regions TA1 and the plurality of second transmission regions TA2 can be regions where light transmission is permitted.

[0169] Furthermore, the plurality of emission regions EA, the plurality of first transmission regions TA1, and the plurality of second transmission regions TA2 can be distinguished based on the presence or absence of a specific metal layer. For example, a common electrode CE can be formed in the plurality of emission regions EA, but may not be formed in the plurality of first transmission regions TA1 and the plurality of second transmission regions TA2. A light-shielding layer can be formed in the plurality of emission regions EA, but may not be formed in the plurality of first transmission regions TA1 and the plurality of second transmission regions TA2.

[0170] Since the first optical region OA1 contains multiple first transmission regions TA1 and the second optical region OA2 also contains multiple second transmission regions TA2, the first optical region OA1 and the second optical region OA2 can be defined as regions that can transmit light (e.g., external light).

[0171] The transmittance (transparency) of the first optical region OA1 and the transmittance (transparency) of the second optical region OA2 can be the same.

[0172] In this case, the first transmission area TA1 of the first optical region OA1 and the second transmission area TA2 of the second optical region OA2 can have the same shape or size. Alternatively, even if the first transmission area TA1 and the second transmission area TA2 of the first optical region OA1 and the second optical region OA2 have different shapes or sizes, the ratio of the first transmission area TA1 in the first optical region OA1 and the ratio of the second transmission area TA2 in the second optical region OA2 can also be the same.

[0173] Conversely, the transmittance (transparency) of the first optical region OA1 and the transmittance (transparency) of the second optical region OA2 can be different.

[0174] In this case, the first transmission area TA1 of the first optical region OA1 and the second transmission area TA2 of the second optical region OA2 can have different shapes or sizes. Alternatively, even if the first transmission area TA1 and the second transmission area TA2 have the same shape or size, the ratio of the first transmission area TA1 within the first optical region OA1 and the ratio of the second transmission area TA2 within the second optical region OA2 can be different.

[0175] For example, if the first optoelectronic device 11 overlapping with the first optical region OA1 is a camera, and the second optoelectronic device 12 overlapping with the second optical region OA2 is a sensor, then the camera may require a larger amount of light than the sensor.

[0176] Therefore, the transmittance (transparency) of the first optical region OA1 can be higher than that of the second optical region OA2.

[0177] In this case, the first transmission area TA1 of the first optical region OA1 can be larger than the second transmission area TA2 of the second optical region OA2. Alternatively, even if the first transmission area TA1 and the second transmission area TA2 have the same size, the ratio of the first transmission area TA1 within the first optical region OA1 can be greater than the ratio of the second transmission area TA2 within the second optical region OA2.

[0178] As shown in Figure 5, in the embodiments of this disclosure, the first transmission region TA1 and the second transmission region TA2 can also be referred to as transparent regions, and the transmittance can also be referred to as transparency.

[0179] Additionally, as shown in FIG5, in the embodiments of this disclosure, it is assumed that the first optical area OA1 and the second optical area OA2 are positioned at the top of the display area DA of the display panel 110 (in other words, at the upper part) and arranged side by side.

[0180] Referring to Figure 5, a horizontal display area with a first optical area OA1 and a second optical area OA2 can be defined as a first horizontal display area HA1, and a horizontal display area without a first optical area OA1 and a second optical area OA2 can be defined as a second horizontal display area HA2.

[0181] Referring to Figure 5, the first horizontal display area HA1 may include the ordinary area NA, the first optical area OA1, and the second optical area OA2. The second horizontal display area HA2 may only include the ordinary area NA.

[0182] In the following text, for ease of description, at least one of the first optical region OA1 and the second optical region OA2 may be referred to as optical region OA, and at least one of the plurality of first transmission regions TA1 in the first optical region OA1 and the plurality of second transmission regions TA2 in the second optical region OA2 may be referred to as transmission region TA.

[0183] Figure 6 is a graphic illustrating an example of the connection structure of signal lines in a display panel 110 according to an embodiment of the present disclosure.

[0184] Referring to FIG6, the display panel 110 according to an embodiment of the present disclosure may include in the normal area NA a plurality of first signal lines extending in a first direction (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) and at least one second signal line extending in a second direction intersecting the first direction (e.g., second-1 signal line DSL_V1 and second-2 signal line DSL_V2).

[0185] According to the example in Figure 6, the first direction can be horizontal (i.e., row) and the second direction can be vertical (i.e., column). However, embodiments of this disclosure are not limited thereto.

[0186] Each of the first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) can be electrically connected to a voltage line.

[0187] Here, the voltage lines electrically connected to the multiple first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) can be DC signal lines, which may include at least one of initialization voltage lines, reset voltage lines, and bias voltage lines.

[0188] In the region adjacent to the optical zone OA, the second signal line (e.g., the second-1 signal line DSL_V1 and the second-2 signal line DSL_V2) can electrically connect to each of at least two of the multiple first signal lines (e.g., the first-1 signal line DSL_H1 and the first-2 signal line DSL_H2) at the same voltage line.

[0189] Each of the first signal line (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) and the second signal line (e.g., second-1 signal line DSL_V1 and second-2 signal line DSL_V2) can be a data dummy line.

[0190] According to the example in Figure 6, at least one of the multiple first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) extending toward the optical region OA can be disconnected at the edge portion OA_E of the optical region OA.

[0191] In Figure 6, the edge portion OA_E of the optical region OA is illustrated as the boundary line between the optical region OA and the ordinary region NA (the dashed line defining the optical region OA in Figure 6). However, embodiments of this disclosure are not limited to this, and based on the boundary line, the edge portion OA_E of the optical region OA may include a region that partially overlaps with the optical region OA and a region that partially overlaps with the ordinary region NA.

[0192] In other words, the display device 100 according to embodiments of the present disclosure can electrically connect signal lines (e.g., DC signal lines) in a region adjacent to the optical region OA using horizontal and vertical data dummy lines. This configuration can improve the transmittance in the optical region OA while ensuring brightness uniformity in the optical region OA at minimal cost.

[0193] According to the example in Figure 6, the first signal line (e.g., the first-1 signal line DSL_H1 and the first-2 signal line DSL_H2) can be electrically connected to the corresponding second signal line (e.g., the second-1 signal line DSL_V1 and the second-2 signal line DSL_V2) in at least one of the first connection area A1, which is spaced at a predetermined distance from the first side (e.g., the left side) of the optical area OA, and the second connection area A2, which is spaced at a predetermined distance from the second side (e.g., the right side) of the optical area OA.

[0194] According to the example in Figure 6, the first signal line (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) may include multiple first-1 signal lines DSL_H1 and multiple first-2 signal lines DSL_H2.

[0195] Additionally, the second signal line (e.g., second-1 signal line DSL_V1 and second-2 signal line DSL_V2) may include second-1 signal line DSL_V1 and second-2 signal line DSL_V2, wherein the second-1 signal line DSL_V1 is electrically connected to each of the plurality of first-1 signal lines DSL_H1 in the first connection area A1 and / or the second connection area A2, and the second-2 signal line DSL_V2 is electrically connected to each of the plurality of first-2 signal lines DSL_H2 in the first connection area A1 and / or the second connection area A2.

[0196] For example, the plurality of first-1 signal lines DSL_H1 can be lines connected to any one of the initialization voltage line, reset voltage line, and bias voltage line, respectively, while the plurality of first-2 signal lines DSL_H2 can be lines connected to one of the initialization voltage line, reset voltage line, and bias voltage line (excluding the voltage lines connected to the first-1 signal lines DSL_H1).

[0197] However, the display device 100 according to embodiments of this disclosure is not limited thereto. It may further include a plurality of first-3 signal lines extending in a first direction and respectively connected to the remaining voltage lines among the initialization voltage line, reset voltage line, and bias voltage line that are not connected to the first-1 signal line DSL_H1 or the first-2 signal line DSL_H2. Additionally, it may include second-3 signal lines extending in a second direction and electrically connected to each of the plurality of first-3 signal lines in the first connection area A1 and / or the second connection area A2.

[0198] The plurality of first-1 signal lines DSL_H1 and the plurality of first-2 signal lines DSL_H2 may be arranged alternately along a second direction in at least a portion of the display panel 110. For example, the at least a portion of the display panel 110 may be an area that at least partially overlaps with the optical area OA.

[0199] According to the example in Figure 6, in a portion of the display panel 110, the plurality of first-1 signal lines DSL_H1 can be arranged in an odd number of rows, and the plurality of first-2 signal lines DSL_H2 can be arranged in an even number of rows. However, embodiments of this disclosure are not limited thereto, and the plurality of first-1 signal lines DSL_H1 can be arranged in an even number of rows, while the plurality of first-2 signal lines DSL_H2 can be arranged in an odd number of rows.

[0200] Each of the different voltage lines can be directly connected to the corresponding first signal line (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2).

[0201] In other words, each of the different voltage lines can be designed so that they do not overlap, thus preventing short circuits between the voltage lines. This allows them to be connected to each of the corresponding first signal lines (e.g., first-1 and first-2 signal lines DSL_H1 and DSL_H2) without jumping connections.

[0202] Meanwhile, if at least one of the first voltage lines overlaps with at least one second voltage line in at least one overlapping region on the same plane (i.e., the same layer), the at least one first voltage line can be hopped across the at least one overlapping region to connect to each of the corresponding first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2).

[0203] For example, at least one first voltage line may have a lower line resistance than at least one second voltage line.

[0204] More specifically, if the reset voltage line and bias voltage line in the initialization voltage line, reset voltage line, and bias voltage line are arranged on the same layer and overlap each other, and if the line resistance of the reset voltage line is lower than the line resistance of the bias voltage line, then the reset voltage line can be connected to a jumper line arranged on a different plane (i.e., a different layer) from the reset voltage line and bias voltage line in the overlapping area. This prevents short circuits between the reset voltage line and bias voltage line in the overlapping area.

[0205] The first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) and the second signal lines (e.g., second-1 signal line DSL_V1 and second-2 signal line DSL_V2) can be formed of different materials on different planes. Each of the first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) can be formed of the same material on the same plane, and each of the second signal lines (e.g., second-1 signal line DSL_V1 and second-2 signal line DSL_V2) can be formed of the same material on the same plane.

[0206] The first signal line (e.g., first signal line DSL_H1 and first signal line DSL_H2) and the second signal line corresponding to the first signal line (e.g., second signal line DSL_V1 and second signal line DSL_V2) can be electrically connected via a connection pattern CP in the overlapping area.

[0207] For example, the connection pattern CP can be formed of the same material as the second signal lines (e.g., second signal line DSL_1 and second signal line DSL_2). However, embodiments of this disclosure are not limited thereto, and the connection pattern CP and the second signal lines (e.g., second signal line DSL_1 and second signal line DSL_2) can be formed of different materials.

[0208] Figure 7 is a graphic illustrating another example of the connection structure of signal lines in a display panel 110 according to an embodiment of the present disclosure.

[0209] Referring to FIG7, the display panel 110 according to an embodiment of the present disclosure may include: a first auxiliary connection line SCL1, which is electrically connected at the edge portion OA_E of the optical region OA to a pair of adjacent first-1 signal lines DSL_H1 among the plurality of first-1 signal lines DSL_H1; and a second auxiliary connection line SCL2, which is electrically connected at the edge portion OA_E of the optical region OA to a pair of adjacent first-2 signal lines DSL_H2 among the plurality of first-2 signal lines DSL_H2.

[0210] According to the example in Figure 7, the display device 100 can group the first-1 signal lines DSL_H1 corresponding to the position of the optical area OA in pairs in the second direction, and use the first auxiliary connection line SCL1 to connect the two first-1 signal lines grouped in the same group at the edge portion OA_E of the optical area OA.

[0211] In addition, the display device 100 can group the first-2 signal lines DSL_H2 corresponding to the position of the optical area OA in pairs in the second direction, and use the second auxiliary connection line SCL2 to connect the two first-2 signal lines grouped in the same group at the edge portion OA_E of the optical area OA.

[0212] In other words, the display device 100 according to embodiments of this disclosure can electrically connect each of the first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) and the second signal lines (e.g., second-1 signal line DSL_V1 and second-2 signal line DSL_V2) not only in the first connection area A1 and / or the second connection area A2, but also at the edge portion OA_E of the optical area OA_E. In this way, the brightness uniformity in the optical area OA can be further improved by reducing brightness variations.

[0213] Figures 8 and 9 are diagrams used to further explain the connection structure of the signal lines in the display panel 110 according to an embodiment of the present disclosure.

[0214] Specifically, Figure 8 shows an enlarged plan view of the region corresponding to reference numeral 600 in Figure 6, and Figure 9 shows a cross-sectional view of the region corresponding to line AA′ in Figure 8.

[0215] Referring to FIG8, the display panel 110 according to an embodiment of the present disclosure may include a plurality of first ground voltage lines VSSL_H and a plurality of first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) extending in a first direction.

[0216] For example, each of the plurality of first ground voltage lines VSSL_H and the plurality of first signal lines (or, for example, first-1 signal line DSL_H1 and first-2 signal line DSL_H2) may be a data dummy line; however, embodiments of this disclosure are not limited thereto.

[0217] Each of the plurality of first ground voltage lines VSSL_H can be connected to the main ground voltage line arranged in the non-display area NDA of the display panel 110, and can receive the ground voltage ELVSS. Each of the plurality of first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) can be connected to any one of the initialization voltage line, reset voltage line, and bias voltage line arranged in the non-display area NDA of the display panel 110, and can receive the corresponding voltage among the initialization voltage Vini, reset voltage VAR, and bias voltage VOBS.

[0218] The display panel 110 according to an embodiment of the present disclosure may include a plurality of driving voltage lines (e.g., a first driving voltage line VDDL1 and a second driving voltage line VDDL2) extending in a second direction, a plurality of data lines (e.g., first data lines to fourth data lines DL1, DL2, DL3, DL4), a plurality of second signal lines (e.g., a second-1 signal line DSL_V1 and a second-2 signal line DSL_V2), and a plurality of second ground voltage lines (e.g., a second-1 ground voltage line VSSL_V1 and a second-2 ground voltage line VSSL_V2).

[0219] For example, each of the plurality of second ground voltage lines (e.g., second-1 ground voltage line VSSL_V1 and second-2 ground voltage line VSSL_V2) and the plurality of second signal lines (second-1 signal line DSL_V1 and second-2 signal line DSL_V2) may be a data dummy line; however, embodiments of this disclosure are not limited thereto.

[0220] The multiple drive voltage lines (e.g., the first drive voltage line VDDL1 and the second drive voltage line VDDL2) can be lines that receive the drive voltage ELVDD. Considering power loss and stability, they can be configured to have a relatively larger linewidth than other lines (e.g., the first -1 signal line DSL_H1 and the first -2 signal line DSL_H2, the second -1 signal line DSL_V1 and the second -2 signal line DSL_V2, and the first to fourth data lines DL1, DL2, DL3, and DL4).

[0221] The plurality of second ground voltage lines (e.g., second-1 ground voltage line VSSL_V1 and second-2 ground voltage line VSSL_V2) can be connected to the main ground voltage line arranged in the non-display area NDA of the display panel 110, and can receive the ground voltage ELVSS.

[0222] The multiple data lines (e.g., the first to fourth data lines DL1, DL2, DL3 and DL4) can supply data voltage VDATA to the corresponding sub-pixel SP among the multiple sub-pixels.

[0223] According to the example in Figure 8, among the plurality of data lines (e.g., first to fourth data lines DL1, DL2, DL3, and DL4), the first data line DL1 and the third data line DL3 may be lines that supply data voltage VDATA to the adjacent green sub-pixel SP_G. The second data line DL2 and the fourth data line DL4 may be lines that supply data voltage VDATA to the adjacent red sub-pixel SP_R and blue sub-pixel SP_B. However, embodiments of this disclosure are not limited thereto.

[0224] According to the example in Figure 8, the green sub-pixel SP_G, red sub-pixel SP_R, and blue sub-pixel SP_B can represent the emission area. That is, in Figure 8, the green sub-pixel SP_G, red sub-pixel SP_R, and blue sub-pixel SP_B can represent the light-emitting device (ED). In the following text, for ease of explanation, the green sub-pixel SP_G, red sub-pixel SP_R, and blue sub-pixel SP_B are referred to as the light-emitting device ED or the emission area formed by the light-emitting device ED.

[0225] Referring to Figure 8, two green sub-pixels SP_G, one red sub-pixel SP_R, and one blue sub-pixel SP_B arranged (or aligned) along a first or second direction can constitute a unit pixel. In other words, the display panel 110 may include multiple unit pixels, and each of the multiple unit pixels may include two green sub-pixels SP_G, one red sub-pixel SP_R, and one blue sub-pixel SP_B.

[0226] Referring to Figure 8, the green sub-pixel SP_G can be arranged in the first direction (i.e., the horizontal direction) and the second direction (i.e., the vertical direction). The red sub-pixel SP_R and the blue sub-pixel SP_B can be arranged alternately one after another in the first direction and the second direction.

[0227] At least two of the green subpixel SP_G, red subpixel SP_R, and blue subpixel SP_B may have the same or different shapes and sizes.

[0228] According to the example in Figure 8, considering the lifetime and luminous efficiency of the emitting material for each color, the blue sub-pixel SP_B can be formed with a larger area than the green sub-pixel SP_G and the red sub-pixel SP_R. However, the embodiments of this disclosure are not limited thereto.

[0229] Each of the plurality of first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) can be connected to the second-1 signal line DSL_V1 by means of a connection pattern CP in the region overlapping with the second-1 signal line DSL_V1.

[0230] Each of the plurality of first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) can be connected to the second-2 signal line DSL_V2 via a connection pattern CP in the region overlapping with the second-2 signal line DSL_V2.

[0231] Each of the plurality of first ground voltage lines VSSL_H may be electrically connected to the second-1 ground voltage line VSSL_V1 in an overlapping region that overlaps with the second-1 ground voltage line VSSL_V1 among the plurality of second ground voltage lines (e.g., second-1 ground voltage line VSSL_V1 and second-2 ground voltage line VSSL_V2), or may not be connected depending on the embodiment.

[0232] Referring to Figure 9, the first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) and the second signal lines (e.g., second-1 signal line DSL_V1 and second-2 signal line DSL_V2) can be arranged on different planes. Each of the first signal lines (e.g., first-1 signal line DSL_H1 and first-2 signal line DSL_H2) can be electrically connected to the corresponding second signal line (e.g., second-1 signal line DSL_V1 or second-2 signal line DSL_V2) through a connection pattern CP in the overlapping area.

[0233] According to the example in Figure 9, the first -2 signal line DSL_H2 can be disposed on the passivation layer PAS0, and the second -2 signal line DSL_V2 can be disposed on the first planarization layer PLN1 among a plurality of planarization layers (e.g., the first planarization layer PLN1 and the second planarization layer PLN2), wherein the plurality of planarization layers are disposed on the passivation layer PAS0.

[0234] In the overlapping area of ​​the first-2 signal line DSL_H2 and the second-2 signal line DSL_V2, a contact hole can be formed in the first planarization layer PLN1, and the first-2 signal line DSL_H2 and the second-2 signal line DSL_V2 can be electrically connected by a connection pattern CP provided in the contact hole.

[0235] Figures 10 and 11 are diagrams illustrating an embodiment of the display device 100 according to an embodiment of the present disclosure.

[0236] Specifically, FIG10 shows a cross-sectional view of the non-transmissive region NTA in the ordinary region NA of the display device 100 according to an embodiment of the present disclosure. FIG11 shows a cross-sectional view of the transmissive region TA in the optical region OA of the display device 100 according to an embodiment of the present disclosure.

[0237] Referring to Figures 10 and 11, a display device 100 according to an embodiment of the present disclosure may include a nontransmissive region NTA in a normal region NA, a nontransmissive region NTA in an optical region OA, and a transmissive region TA in an optical region OA.

[0238] The non-transmissive region NTA of the optical region OA may include a first emission region, and the non-transmissive region NTA of the normal region NA may include a second emission region. Figure 10 shows an example of the non-transmissive region NTA in the normal region NA.

[0239] For ease of explanation, Figure 11 shows an example where the transmission region TA of the optical region OA overlaps with the first optoelectronic device 11. However, the transmission region TA of the optical region OA can also overlap with the second optoelectronic device 12.

[0240] Additionally, in Figures 10 and 11, the first optoelectronic device 11 is shown overlapping with the transmissive region TA. However, the first optoelectronic device 11 may also overlap with at least a portion of the non-transmissive region NTA included in the optical region OA.

[0241] The non-transmissive region NTA in the normal region NA, the non-transmissive region NTA in the optical region OA, and the transmissive region TA in the optical region OA may include a substrate SUB, a transistor layer TRL, a planarization layer PLN, a light-emitting device layer EDL, a packaging layer ENCAP, a touch sensor layer TSL, and a protective layer PAC.

[0242] First, referring to Figure 10, the stacking structure of the nontransmissive region NTA in the optical region OA and the normal region NA will be described.

[0243] The substrate SUB may include a first substrate SUB1, an intermediate insulating film IPD, and a second substrate SUB2. The intermediate insulating film IPD may be positioned between the first substrate SUB1 and the second substrate SUB2. By utilizing the first substrate SUB1, the intermediate insulating film IPD, and the second substrate SUB2 to configure the substrate SUB, moisture penetration can be prevented. For example, the first substrate SUB1 and the second substrate SUB2 may be polyimide (PI) substrates.

[0244] The intermediate insulating film (IPD) may include inorganic materials. For example, the intermediate insulating film (IPD) may include silicon nitride (SiNx) or silicon oxide (SiOx).

[0245] The transistor layer TRL may include various patterns (ACT, SD1, GATE) for forming transistors such as driving transistors DRT, various insulating films (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0) and various metal patterns (TM, GM, ML1, ML2).

[0246] Depending on the embodiment, at least one additional insulating film may be disposed between the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2 and / or between the second interlayer insulating film ILD2 and the passivation layer PAS0.

[0247] The stacking structure of the transistor layer (TRL) will now be described in more detail.

[0248] The multi-buffer layer MBUF can be disposed on the second substrate SUB2, and the first active buffer layer ABUF1 can be disposed on the multi-buffer layer MBUF.

[0249] The first metal layer ML1 and the second metal layer ML2 can be disposed on the first active buffer layer ABUF1. The first metal layer ML1 and the second metal layer ML2 can be used as light-shielding elements.

[0250] The second active buffer layer ABUF2 can be disposed on the first metal layer ML1 and the second metal layer ML2. The active layer ACT for driving the transistor DRT can be disposed on the second active buffer layer ABUF2.

[0251] The gate insulating layer GI can be disposed on the second active buffer layer ABUF2, while covering the active layer ACT.

[0252] The gate electrode (GATE) of the driving transistor (DRT) can be disposed on the gate insulating layer (GI). In this case, at a location different from where the driving transistor (DRT) is formed, the gate material layer (GM) can be disposed on the gate insulating layer (GI) together with the gate electrode (GATE) of the driving transistor (DRT).

[0253] The first interlayer insulating layer ILD1 can be disposed on the gate insulating layer GI, simultaneously covering the gate electrode GATE and the gate material layer GM. A metal pattern TM can be disposed on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 can be disposed on the first interlayer insulating layer ILD1, simultaneously covering the metal pattern TM.

[0254] Two first source-drain electrode patterns SD1 can be disposed on the second interlayer insulating layer ILD2. Of the two first source-drain electrode patterns SD1, one can be the source node (or drain node) of the driving transistor DRT, and the other can be the drain node (or source node) of the driving transistor DRT.

[0255] Two first source-drain electrode patterns SD1 can be connected to one side and the other side of the active layer ACT through contact holes in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI. The portion of the active layer ACT that overlaps with the gate electrode GATE can be a channel region. Of the two first source-drain electrode patterns SD1, one can be connected to one side of the channel region in the active layer ACT, and the other can be connected to the other side of the channel region in the active layer ACT.

[0256] The passivation layer PAS0 can be disposed on the second interlayer insulating layer ILD2, while simultaneously covering the two first source-drain electrode patterns SD1.

[0257] In the non-transmissive region NTA of the normal region NA, the first signal line DSL_H can be disposed on the passivation layer PAS0, wherein the first signal line DSL_H can include at least one of the first-1 signal line DSL_H1 and the first-2 signal line DSL_H2.

[0258] The first signal line DSL_H may be formed of the same material as the first source-drain electrode pattern SD1; however, embodiments of this disclosure are not limited thereto.

[0259] According to one embodiment, the first signal line DSL_H can be disposed on the same plane as the first source-drain electrode pattern SD1 (i.e., the second interlayer insulating layer ILD2).

[0260] The planarization layer PLN can be disposed on the transistor layer TRL. The planarization layer PLN may include a first planarization layer PLN1 and a second planarization layer PLN2.

[0261] The first planarization layer PLN1 can be disposed on the passivation layer PAS0. The second source-drain electrode pattern SD2 can be disposed on the first planarization layer PLN1. The second source-drain electrode pattern SD2 can be connected to one of the two first source-drain electrode patterns SD1 (corresponding to node N2 in Figure 4) through the contact hole in the first planarization layer PLN1.

[0262] In the non-transmissive region NTA of the normal region NA, the second signal line DSL_V can be disposed on the first planarization layer PLN1, wherein the second signal line DSL_V can include at least one of the first-2 signal line DSL_V1 and the second-2 signal line DSL_V2.

[0263] In the non-transmissive region NTA of the normal region NA, contact holes can be formed in the area where the first signal line DSL_H and the second signal line DSL_V of the first planarization layer PLN1 are vertically (or vertically) overlapping. A connection pattern CP can be provided in the contact holes of the first planarization layer PLN1 to electrically connect the first signal line DSL_H and the second signal line DSL_V.

[0264] For example, the connection pattern CP can be set in at least one of the first connection area A1 and the second connection area A2 adjacent (or near) the optical area OA (see, for example, Figures 6 and 7).

[0265] The second planarization layer PLN2 can be disposed on the first planarization layer PLN1, simultaneously covering the second source-drain electrode pattern SD2 and the second signal line DSL_V in the non-transmissive region NTA of the normal region NA. The second planarization layer PLN2 can be disposed on the first planarization layer PLN1, simultaneously covering the second source-drain electrode pattern SD2 in the non-transmissive region NTA of the optical region NA. The light-emitting device layer EDL can be positioned (or disposed) on the second planarization layer PLN2.

[0266] The light-emitting device layer (EDL) may include a light-emitting device (ED) formed by a pixel electrode (PE), a light-emitting layer (EL), and a common electrode (CE). The light-emitting layer (EL) may include an organic film.

[0267] The pixel electrode PE can be disposed on the second planarization layer PLN2, and the pixel electrode PE can be electrically connected to the second source-drain electrode pattern SD2 through the contact holes in the second planarization layer PLN2.

[0268] A dam can be disposed on the second planarization layer PLN2, simultaneously covering the pixel electrode PE. The dam can have an opening corresponding to the emission region of the sub-pixel SP. A portion of the pixel electrode PE can be exposed through the opening portion (or opening) of the dam. A light-emitting layer EL can be disposed within and surrounding the opening portion of the dam. Therefore, the light-emitting layer EL can be disposed on the pixel electrode PE exposed through the opening portion of the dam.

[0269] The common electrode CE can be disposed on the light-emitting layer EL. For example, the common electrode CE can be a cathode electrode.

[0270] The encapsulation layer can be disposed on the aforementioned light-emitting device layer (EDL).

[0271] The encapsulation layer can have a single-layer or multi-layer structure. For example, the encapsulation layer PAS1 may include a lower encapsulation layer PAS1, a middle encapsulation layer PCL, and a top encapsulation layer PAS2.

[0272] However, the display device 100 according to the embodiments of this disclosure is not limited thereto, and may include only the intermediate encapsulation layer PCL.

[0273] The lower encapsulation layer PAS1 and the upper encapsulation layer PAS2 are inorganic films, while the intermediate encapsulation layer PCL can be either an organic or inorganic film. The intermediate encapsulation layer PCL can be used as a planarization layer.

[0274] The lower encapsulation layer PAS1 is disposed on the common electrode CE and can be positioned closest to the light-emitting device ED. The lower encapsulation layer PAS1 can be formed from an inorganic insulating material capable of low-temperature deposition. For example, the lower encapsulation layer PAS1 can be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Because the lower encapsulation layer PAS1 is deposited in a low-temperature environment, damage to the light-emitting layer EL, which contains organic materials susceptible to high temperatures during the deposition process, can be prevented.

[0275] The intermediate encapsulation layer (PCL) acts as a buffer, reducing interlayer stress caused by bending of the display device 100 and enhancing planarization performance. For example, the PCL can be formed from organic insulating materials such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbide (SiOC). The PCL can be formed using an inkjet printing method.

[0276] The display device 100 (particularly the display panel 110) may include at least one dam at or near the end of the slope of the encapsulation layer ENCAP to prevent the ENCAP from collapsing. The at least one dam may be located at or near the boundary between the display area DA and the non-display area NDA.

[0277] The intermediate encapsulation layer (PCL) containing organic material may be located only on the inner side of the main dam section. In other words, the intermediate encapsulation layer (PCL) may not be present at the top of all dam sections. Alternatively, the intermediate encapsulation layer (PCL) may be located at the top of at least the main dam section or the secondary dam section. That is, the intermediate encapsulation layer (PCL) may extend only to the top of the main dam section. Or, the intermediate encapsulation layer (PCL) may extend beyond the top of the main dam section to the top of the secondary dam section.

[0278] The upper encapsulation layer PAS2 can be formed on a substrate SUB on which the intermediate encapsulation layer PCL is formed, and covers the upper and side surfaces of both the intermediate encapsulation layer PCL and the lower encapsulation layer PAS1. The upper encapsulation layer PAS2 can minimize or block the penetration of external moisture and oxygen into the lower encapsulation layer PAS1 and the intermediate encapsulation layer PCL. For example, the upper encapsulation layer PAS2 can be formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0279] The touch sensor layer (TSL) can be placed on the encapsulation layer (ENCAP).

[0280] The touch buffer layer T-BUF can be disposed on the encapsulation layer ENCAP, and the touch sensor TS can be disposed on the touch buffer layer T-BUF. The touch sensor TS may include a touch sensor metal TSM and a bridging metal BRG located on different layers. The touch interlayer insulating film T-ILD can be disposed between the touch sensor metal TSM and the bridging metal BRG.

[0281] For example, a touch sensor metal TSM may include a first touch sensor metal, a second touch sensor metal, and a third touch sensor metal arranged adjacent to each other. The first and second touch sensor metals need to be electrically connected. However, if a third touch sensor metal is present between them, the first and second touch sensor metals can be electrically connected via a bridging metal BRG located on different layers. The bridging metal BRG can be insulated from the third touch sensor metal via a touch interlayer insulating film (T-ILD).

[0282] During the formation of the touch sensor layer (TSL), chemical solutions (such as developers or etchants) used in the formation process or external moisture may be generated. By arranging a touch buffer layer (T-BUF) and then forming the touch sensor layer (TSL) on top of the T-BUF, these chemical solutions or moisture can be prevented from penetrating into the light-emitting layer (EL) containing organic materials during the fabrication process of the touch sensor layer (TSL). Therefore, the touch buffer layer (T-BUF) can protect the light-emitting layer (EL), which is susceptible to chemical solutions or moisture, from damage.

[0283] To prevent damage to the light-emitting layer EL, which contains organic materials susceptible to high temperatures, the touch buffer layer T-BUF is formed of an organic insulating material that can be deposited at low temperatures (e.g., 100°C or lower) and has a low dielectric constant of about 1 to 3. For example, the touch buffer layer T-BUF can be formed of acrylic, epoxy, or siloxane-based materials. Typically, when the display device 100 is bent, the encapsulation layer ENCAP may be damaged, and the touch sensor metal of the touch sensor TS located on the touch buffer layer T-BUF may crack. However, according to embodiments of this disclosure, even if the display device 100 is bent, the touch buffer layer T-BUF, due to its organic insulating material, has planarization properties that prevent damage to the encapsulation layer ENCAP and / or cracking of the touch sensor metal TSM and bridging metal BRG forming the touch sensor TS.

[0284] The protective layer PAC can be placed above the touch sensor TS. The protective layer PAC can be an organic insulating film.

[0285] The following describes the laminated structure of the transmission region TA within the optical region OA with reference to FIG11.

[0286] Referring to Figure 11, the substrate SUB and insulating layers (e.g., MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0, PLN1, PLN2, BANK and ENCAP, PAS1, PCL1, PCL2, PAS2, PAC) arranged in the non-transmittent region NTA can be similarly arranged in the transmittent region TA within the optical region OA.

[0287] However, apart from the insulating material in the non-transmissive region NTA, material layers with electrical properties (or electrical performance) (e.g., metal material layers, semiconductor layers, etc.) may not be provided in the transmissive region TA.

[0288] For example, the semiconductor layer ACT associated with the transistor and the metal material layers (e.g., ML1, ML2, GATE, GM, TM, SD1, and SD2) may not be located in the transmissive region TA. Additionally, the pixel electrode PE and common electrode CE included in the light-emitting device ED may not be located in the transmissive region TA. The light-emitting layer EL may or may not be located in the transmissive region TA. The touch sensor metal TSM and bridging metal BRG included in the touch sensor TS may not be located in the transmissive region TA.

[0289] The embodiments of this disclosure described above are summarized below.

[0290] The display device according to embodiments of the present disclosure may include a display panel, the display panel including an optical region having a plurality of transmissive regions and a plurality of first emitting regions, and a general region disposed outside the optical region and having a plurality of second emitting regions. The display device may further include optoelectronic devices disposed below the display panel and overlapping the optical region.

[0291] The ordinary area may include multiple signal lines connected in a mesh structure in the area adjacent to the optical area.

[0292] The plurality of signal lines may include a plurality of first signal lines extending in a first direction and at least one second signal line extending in a second direction intersecting the first direction, wherein the at least one second signal line is electrically connected in a region adjacent to the optical region to each of at least two of the plurality of first signal lines that are electrically connected to the same voltage line.

[0293] Each of the plurality of first signal lines and at least one second signal line may be a data dummy line.

[0294] At least two of the first signal lines may be electrically connected to at least one second signal line in at least one connection area spaced at a predetermined distance from the first side of the optical area or in a second connection area spaced at a predetermined distance from the second side of the optical area.

[0295] Voltage lines may include at least one of initialization voltage lines, reset voltage lines, and bias voltage lines.

[0296] At least one of the multiple first signal lines extending in the direction of the optical region may be broken at the edge portion of the optical region.

[0297] At least two of the first signal lines may include multiple first-1 signal lines electrically connected to the first voltage line and multiple first-2 signal lines electrically connected to the second voltage line.

[0298] At least one second signal line may include a second-1 signal line electrically connected to each of the plurality of first-1 signal lines and a second-2 signal line electrically connected to each of the plurality of first-2 signal lines.

[0299] Multiple first-1 signal lines and multiple first-2 signal lines can be arranged alternately in a second direction in at least a portion of the display panel.

[0300] At least a portion of the display panel may be an area that at least partially overlaps with the optical area.

[0301] Each of the plurality of first-1 signal lines can be connected to the second-1 signal line by a connection pattern in the area overlapping with the second-1 signal line, and each of the plurality of first-2 signal lines can be connected to the second-2 signal line by a connection pattern in the area overlapping with the second-2 signal line.

[0302] The connection pattern can be set in at least one of the first connection area and the second connection area adjacent to the optical area.

[0303] The display device may further include a first auxiliary connection line electrically connecting adjacent pairs of a plurality of first-1 signal lines at the edge portion of the optical region and a second auxiliary connection line electrically connecting adjacent pairs of a plurality of first-2 signal lines at the edge portion of the optical region.

[0304] If at least one of the first voltage lines overlaps with at least one of the second voltage lines in at least one overlapping region on the same plane, then at least one of the first voltage lines may be connected by skipping over the at least one overlapping region.

[0305] At least one first voltage line may have a lower line resistance than at least one second voltage line.

[0306] Multiple first signal lines and at least one second signal line can be formed from different materials on different planes.

[0307] The display device may also include a connection pattern that electrically connects each of a plurality of first signal lines to at least one second signal line.

[0308] Each of the multiple first signal lines can be formed from the same material on the same plane.

[0309] The display panel of the display device may further include a substrate, a transistor layer disposed on the substrate and including at least one transistor and a passivation layer disposed on the at least one transistor, and a plurality of planarization layers disposed on the transistor layer.

[0310] Multiple first signal lines can be disposed on the passivation layer, and at least one second signal line can be disposed on any one of the multiple planarization layers.

[0311] The display device may further include a connection pattern disposed in each contact hole in a region of each of the plurality of first signal lines overlapping with at least one second signal line, which electrically connects each of the plurality of first signal lines to at least one second signal line.

[0312] The connection pattern can be formed from the same material as at least one second signal line.

[0313] There may be no material layer with electrical properties in the plurality of transmission regions.

[0314] The display device according to embodiments of the present disclosure may include: a display panel including a normal area and an optical area overlapping with optoelectronic devices disposed below the display panel, wherein the display panel may include: a substrate; a transistor layer disposed on the substrate and including at least one transistor and a passivation layer disposed on the at least one transistor; a first signal line disposed on the passivation layer in the normal area and electrically connected to a voltage line; a plurality of planarization layers disposed on the transistor layer and the first signal line; a second signal line disposed on any one of the plurality of planarization layers in the normal area and electrically connected to the first signal line in a region adjacent to the optical area; and a light-emitting device layer disposed on the plurality of planarization layers and including a plurality of light-emitting devices corresponding to each of the optical area and the normal area.

[0315] The multiple planarization layers may include a first planarization layer disposed on the passivation layer and the first signal line, and a second planarization layer disposed on the first planarization layer, wherein the second signal line may be disposed on the second planarization layer.

[0316] The display device may further include a connection pattern disposed in a contact hole formed in the first planarization layer, which electrically connects the first signal line and the second signal line.

[0317] The substrate may include a first substrate, an intermediate insulating layer disposed on the first substrate, and a second substrate disposed on the intermediate insulating layer.

[0318] The optical region may include the transmission region, and the transmission region may overlap with the light-emitting layer in the light-emitting device in the transmission region.

[0319] The above description has been presented to enable any person skilled in the art to make and use the technical concept of the invention, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings provide examples of the technical concept of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the invention.

Claims

1. A display device comprising: The display panel includes an optical area having multiple transmissive areas and multiple first emitting areas, and a general area disposed outside the optical area and having multiple second emitting areas; And optoelectronic devices disposed below the display panel and overlapping the optical area, wherein the ordinary area includes multiple signal lines connected in a mesh structure in a region adjacent to the optical area.

2. The display device according to claim 1, wherein, The plurality of signal lines includes: a plurality of first signal lines extending in a first direction, each of the plurality of first signal lines being electrically connected to a voltage line; and at least one second signal line extending in a second direction intersecting the first direction, and electrically connected in a region adjacent to the optical region to each of at least two of the plurality of first signal lines that are electrically connected to the same voltage line.

3. The display device according to claim 2, wherein, Each of the plurality of first signal lines and the at least one second signal line is a data dummy line.

4. The display device according to claim 2, wherein, The at least two first signal lines are electrically connected to the at least one second signal line in at least one of a first connection area spaced apart from the first side of the optical area by a predetermined distance and a second connection area spaced apart from the second side of the optical area by the predetermined distance.

5. The display device according to claim 2, wherein, The voltage line includes at least one of an initialization voltage line, a reset voltage line, and a bias voltage line.

6. The display device according to claim 2, wherein, At least one of the plurality of first signal lines extending toward the optical region is broken at the edge portion of the optical region.

7. The display device according to claim 2, wherein, The at least two first signal lines include multiple first-1 signal lines electrically connected to the first voltage line and multiple first-2 signal lines electrically connected to the second voltage line.

8. The display device according to claim 7, wherein, The at least one second signal line includes a second-1 signal line electrically connected to each of the plurality of first-1 signal lines and a second-2 signal line electrically connected to each of the plurality of first-2 signal lines.

9. The display device according to claim 7, wherein, The plurality of first-1 signal lines and the plurality of first-2 signal lines are arranged alternately along the second direction in at least a portion of the display panel.

10. The display device according to claim 9, wherein, The at least portion of the display panel is an area that at least partially overlaps with the optical area.

11. The display device according to claim 8, wherein, Each of the plurality of first-1 signal lines is connected to the second-1 signal line by a connection pattern in the region overlapping with the second-1 signal line, and each of the plurality of first-2 signal lines is connected to the second-2 signal line by a connection pattern in the region overlapping with the second-2 signal line.

12. The display device according to claim 11, wherein, The connection pattern is disposed in at least one of the first connection area and the second connection area adjacent to the optical area.

13. The display device according to claim 7, further comprising: At the edge portion of the optical region, an auxiliary connection line is electrically connected to an adjacent pair of the plurality of first-1 signal lines; And a second auxiliary connection line electrically connecting adjacent pairs of the plurality of first-2 signal lines at the edge portion of the optical region.

14. The display device as claimed in claim 2, wherein, When at least one first voltage line among different voltage lines overlaps with at least one second voltage line among different voltage lines in at least one overlapping region on the same plane, the at least one first voltage line is connected by skipping over in the at least one overlapping region.

15. The display device according to claim 14, wherein, The at least one first voltage line has a lower line resistance than the at least one second voltage line.

16. The display device according to claim 2, wherein: The plurality of first signal lines and the at least one second signal line are formed of different materials on different planes; and the display device further includes a connection pattern that electrically connects each of the plurality of first signal lines to the at least one second signal line.

17. The display device according to claim 2, wherein, Each of the plurality of first signal lines is formed of the same material on the same plane.

18. The display device according to claim 2, wherein, The display panel includes: a substrate; a transistor layer disposed on the substrate and including at least one transistor and a passivation layer disposed on the at least one transistor; and a plurality of planarization layers disposed on the transistor layer, wherein the plurality of first signal lines are disposed on the passivation layers, and the at least one second signal line is disposed on any one of the plurality of planarization layers.

19. The display device of claim 18, further comprising a connection pattern disposed in each contact hole in an overlap area of ​​each of the plurality of first signal lines with the at least one second signal line, and electrically connecting each of the plurality of first signal lines to the at least one second signal line.

20. The display device according to claim 19, wherein, The connection pattern is formed of the same material as the at least one second signal line.

21. The display device according to claim 1, wherein, There is no material layer with electrical properties in the plurality of transmission regions.

22. A display device comprising: A display panel includes a normal area and an optical area overlapping with optoelectronic devices disposed below the display panel. The display panel includes: a substrate; a transistor layer disposed on the substrate and including at least one transistor and a passivation layer disposed on the at least one transistor; a first signal line disposed on the passivation layer in the normal area and electrically connected to a voltage line; a plurality of planarization layers disposed on the transistor layer and the first signal line; a second signal line disposed on any one of the plurality of planarization layers in the normal area and electrically connected to the first signal line in a region adjacent to the optical area; and a light-emitting device layer disposed on the plurality of planarization layers and including a plurality of light-emitting devices corresponding to each of the optical area and the normal area.

23. The display device according to claim 22, wherein, The plurality of planarization layers include a first planarization layer disposed on the passivation layer and the first signal line, and a second planarization layer disposed on the first planarization layer, wherein the second signal line is disposed on the second planarization layer.

24. The display device of claim 23 further includes a connection pattern disposed in a contact hole formed in the first planarization layer and electrically connecting the first signal line and the second signal line.

25. The display device according to claim 22, wherein, The substrate includes a first substrate, an intermediate insulating layer disposed on the first substrate, and a second substrate disposed on the intermediate insulating layer.

26. The display device according to claim 22, wherein, The optical region includes a transmission region, and the light-emitting device layer overlaps with the emission layer in the light-emitting device within the transmission region.

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