Device with piezoelectric film on semiconductor substrate
By separately fabricating piezoelectric films on a semiconductor substrate and using bonding layers and caps to form air gaps, the problems of piezoelectric film contamination and manufacturing environment incompatibility were solved, enabling the fabrication and simplified alignment of high-frequency, high-Q resonators and improving resonator performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2025-10-21
- Publication Date
- 2026-05-01
AI Technical Summary
Forming piezoelectric films on semiconductor substrates presents challenges such as contamination and incompatibility with manufacturing environments, resulting in poor quality piezoelectric films that are difficult to operate at high frequencies.
The piezoelectric film is fabricated separately from the integrated circuit. An air gap is formed using a bonding layer and a cap to simplify alignment. The piezoelectric film is excited by electrodes to generate standing waves, avoiding degradation caused by bonding line inductance.
The fabrication of a high-frequency, high-Q resonator was realized, simplifying the alignment process, improving the quality of the piezoelectric film and the performance of the resonator, and making it suitable for high-frequency operation.
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Figure CN121969007A_ABST
Abstract
Description
Device with a piezoelectric film on a semiconductor substrate Technical Field
[0001] This application relates to a device having a piezoelectric film on a semiconductor substrate. Background Technology
[0002] A resonator is a device or system that oscillates naturally at a frequency called the resonant frequency. Resonators can be, for example, crystal resonators (also called quartz resonators), inductor-capacitor (LC) resonators, or microelectromechanical systems (MEMS) resonators. Resonators are typically passive devices, combined with active circuit systems to form oscillators. Oscillators generate periodic signals at their resonant frequency. For example, a crystal oscillator is an electronic circuit that uses the mechanical resonance of a vibrating crystal to generate an electrical signal with a very precise frequency. Crystal oscillators can be used to generate frequencies to track time or to generate clock signals for digital integrated circuits. MEMS resonators can be used instead of crystal resonators to track time and generate stable clock signals for analog and digital integrated circuits. Summary of the Invention
[0003] In one example, the device includes a die, a bonding layer, and a film. The die includes a semiconductor substrate, a metallization structure on the semiconductor substrate, and a dielectric material surrounding at least a portion of the metallization structure. The bonding layer is located on the metallization structure. The film is attached to the bonding layer. The film contains a piezoelectric material.
[0004] In another example, the method includes forming a bonding layer on at least one of a metallized structure of a bare die or a film. The method also includes attaching the film to the metallized structure via the bonding layer. Attached Figure Description
[0005] Figure 1 is a cross-sectional view of an example circuit containing a piezoelectric crystal layer attached to an integrated circuit.
[0006] Figure 2 is a partial cross-sectional view of the circuit in Figure 1, showing the electric field flux between the electrodes of the integrated circuit.
[0007] Figure 3 is a graph of admittance versus frequency in an example of the circuit in Figure 1.
[0008] Figure 4 is a cross-sectional view of another example circuit containing a piezoelectric crystal layer attached to an integrated circuit.
[0009] Figure 5 is a cross-sectional view of an example circuit, which includes multiple resonators formed by piezoelectric crystal layers attached to an integrated circuit.
[0010] Figure 6 is a block diagram of an example bandpass filter that includes multiple resonators of the circuit in Figure 5.
[0011] Figure 7 is a graph of admittance versus frequency in an example resonator of the circuit in Figure 5.
[0012] Figure 8 is a graph showing the performance of an example of the bandpass filter in Figure 6.
[0013] Figure 9 is a schematic diagram of an example RF receiver circuit that includes the bandpass filter of Figure 6.
[0014] Figure 10 is a block diagram of an example oscillator circuit, which includes an example of using a resonator with a piezoelectric crystal layer attached to an integrated circuit.
[0015] Figure 11 is a flowchart of an example method for fabricating a circuit that includes a piezoelectric crystal layer attached to an integrated circuit.
[0016] Figures 12A to 12K are cross-sectional views of various fabrication steps of the method in Figure 11.
[0017] Figures 13A and 13B are perspective views of an example alignment of a piezoelectric crystal layer with an integrated circuit. Detailed Implementation
[0018] Figure 1 is a cross-sectional view of an example circuit 100, which includes a resonator 103 attached to an integrated circuit 101. The integrated circuit 101 includes a semiconductor substrate 102 and a metallization structure 104 located on the semiconductor substrate 102. The semiconductor substrate 102 may include complementary metal-oxide-semiconductor (CMOS) circuitry or circuitry using another technology, and may include transistors and / or other electronic components that interact with the resonator 103 to provide desired functionality. The metallization structure 104 includes an insulating material 106 (e.g., silicon dioxide) and one or more metal layers within the insulating material 106. The metal layers may include copper, aluminum, or other suitable metals. The metal layers may interconnect components of the semiconductor substrate 102 and connect the integrated circuit 101 to the resonator 103, as well as to input / output terminals providing connectivity to external circuitry. The metallization structure 104 includes electrodes disposed within the metal layers that couple the integrated circuit 101 to the resonator 103. Electrodes 116, 118, and 120 are shown in Figure 1. Electrodes 116, 118 and 120 are laterally adjacent to each other and can be either positive or negative electrodes.
[0019] Resonator 103 includes a piezoelectric film 110, a bonding layer 108, and a cap 112. The piezoelectric film 110 is located between the bonding layer 108 and the cap 112. The piezoelectric film 110 may comprise various piezoelectric materials, such as lithium niobate, aluminum nitride, or other materials. Certain piezoelectric film materials, such as lithium niobate, have fewer defects and provide improved piezoelectric properties and electromechanical coupling effects, which allows resonator 103 to operate at high frequencies. However, forming the piezoelectric film 110 on the semiconductor substrate 102 in the environment in which it is fabricated can be challenging. For example, the material used to fabricate the piezoelectric film 110 may contaminate the silicon and introduce defects in electronic devices formed in silicon, or the manufacturing environment (e.g., temperature) required to produce the material of the piezoelectric film 110 may be incompatible with integrated circuit processing. Therefore, as will be described herein, the material of the piezoelectric film 110 can be fabricated separately from the integrated circuit 101, which, compared to using a process compatible with the integrated circuit 101 and the materials used to fabricate the integrated circuit, allows for improved quality of the piezoelectric film 110.
[0020] Bonding layer 108 bonds integrated circuit 101 and resonator 103 such that piezoelectric film 110 overlaps with electrodes 116, 118, and 120. Bonding layer 108 is disposed on a first side of piezoelectric film 110. Bonding layer 108 may comprise bonding materials such as polymers, or other materials suitable for bonding integrated circuit 101 and resonator 103. Suitable polymers may include parylene (e.g., parylene N or parylene C), polydimethylsiloxane (PDMS), etc. Other suitable bonding materials may also be used. In various examples, the thickness of bonding layer 108 may be from about 50 nanometers (nm) to 100 nm. Other bonding layer thicknesses may also be used. In some examples of circuit 100, bonding layer 108 may be provided as part of integrated circuit 101.
[0021] A cap 112 is disposed on the second side of the piezoelectric film 110. The cap 112 may be silicon or other suitable material. A portion of the cap 112 is thinned to provide an air gap 114 between the piezoelectric film 110 and the cap 112. The air gap 114 improves acoustic transduction in the circuit 100. In some instances, the height of the air gap 114 may be about 10 nm or higher.
[0022] A circuit system disposed on semiconductor substrate 102 is coupled to electrodes 116, 118, and 120, and a drive signal generated by the circuit system is provided at electrodes 116, 118, and 120. The drive signal excites an electric field in piezoelectric film 110 through the electrodes to generate a standing wave in piezoelectric film 110. Figure 2 is a cross-sectional view of a portion of circuit 100, showing the electric field flux between electrodes 116, 118, and 120. The electric field is confined within the region of piezoelectric film 110 between electrodes 116, 118, and 120.
[0023] Figure 3 is a graph of admittance versus frequency in an example of circuit 100, illustrating the electrostatic excitation of the piezoelectric film 110, where the coupling coefficient (k... 2 The piezoelectric film 110 may be lithium niobate, and the bonding layer 108 may be 100 μm thick PDMS.
[0024] Figure 4 is a cross-sectional view of an example circuit 200 including an integrated circuit 101 attached to a resonator 103. Circuit 200 includes the integrated circuit 101 as described with reference to Figure 1. The example resonator 103 used in circuit 200 includes a bonding layer 108, a piezoelectric film 110, and a cap 112, with an opening in the bonding layer 108 to form an air gap 402. Electrodes 116, 118, and 120 are spaced apart from the piezoelectric film 110 via the air gap 402. The piezoelectric film 110 is suspended in the air gap between the electrodes 116, 118, and 120 and the cap 112, which improves the quality factor and coupling coefficient of the resonator.
[0025] The dimensions of air gaps 114 and 402 can be designed such that the air gaps can be aligned with electrodes 116, 118, and 120 with relatively large tolerances. Therefore, the alignment of integrated circuit 101 with resonator 103 can be significantly simplified and can be performed in environments where high-precision alignment tools may be lacking (e.g., in packaging facilities). Air gaps 114 and 402 can be filled with air or any suitable gas.
[0026] In some instances, the materials and construction of circuits 100 and 200 can produce high-Q resonators with resonant frequencies of 50 GHz or higher. Degradation due to junction line inductance is avoided by electrostatically exciting the piezoelectric film 110 using electrodes. The piezoelectric film 110 may comprise high-Q materials, such as lithium niobate, which, as mentioned above, are difficult to handle in integrated circuit fabrication.
[0027] While Figures 1, 2, and 4 illustrate examples of a single resonator unit cell, circuits 100 and 200 may contain any number of resonator unit cells. Figure 5 is a cross-sectional view of an example circuit containing multiple resonator unit cells. In Figure 5, the metallization structure 104 includes resonator unit cells 502, 504, and 506. Resonator unit cell 502 includes electrodes 116, 118, and 120. Resonator unit cell 504 includes electrodes 508, 510, and 512. Resonator unit cell 506 includes electrodes 514, 516, and 518. As shown in Figure 2, the electric field flux is confined within the piezoelectric film 110 region between the electrodes of each of the resonator unit cells 502, 504, and 506.
[0028] The metallization structure 104 may include metal conductors connecting various resonator unit cells to form a circuit or provide the desired function. Figure 6 is a block diagram of an example bandpass filter 600 including multiple resonators. The bandpass filter 600 includes resonators 602, 604, 606, 608, and 610, each of which may be a resonator unit cell as shown in Figure 5, coupled via metal conductors of the metallization structure 104. Resonators 602, 604, and 606 are coupled in series via metal conductors 612 and 614. Resonators 608 and 610 are coupled as shunts via metal conductors 616 and 618. For example, the negative electrode of resonator 602 is coupled to the positive electrode of resonator 604 via metal conductor 612 and to the positive electrode of resonator 608 via metal conductor 616. The negative electrode of resonator 604 is coupled to the positive electrode of resonator 606 via metal conductor 614 and to the positive electrode of resonator 610 via metal conductor 618. The positive electrode of resonator 602 can be used as the signal input terminal of the filter, and the negative electrode of resonator 606 can be used as the signal output terminal of the filter. The negative electrodes of resonators 608 and 610 can be connected to a reference terminal, such as ground.
[0029] Figure 7 is a graph of admittance versus frequency in example resonators 602, 604, or 606 of the bandpass filter 600. These filters can be implemented as resonator unit cells 502, 504, and 506 of Figure 5. In Figure 7, the heights of air gaps 114 and 402 can be approximately 10 m, and the coupling coefficient (k) of the resonator... 2 The figure is approximately 28.6%.
[0030] Figure 8 is a graph showing the performance of an example of the bandpass filter from Figure 6. Figure 8 illustrates the reflection coefficient S of an example of bandpass filter 600. 11 and forward voltage gain S 21 In Figure 8, the center frequency of the bandpass filter 600 is approximately 9.125 GHz, the fractional bandwidth is approximately 19.2%, the out-of-band rejection is approximately 48 dB, the minimum input level is approximately 1 dB, and the passband ripple is approximately 1.5 dB.
[0031] Figure 9 is a schematic diagram of an example RF receiver circuit 900 including an example of a bandpass filter 600. The RF receiver circuit 900 also includes an antenna 902, an amplifier 904, and a processing circuit 906. The antenna 902 is coupled to the input of the amplifier 904, and the output of the amplifier 904 is coupled to the input of the bandpass filter 600 (e.g., the positive electrode of the resonator 602). The output of the bandpass filter 600 (e.g., the negative terminal of the resonator 606) is coupled to the input of the processing circuit 906. The bandpass filter 600 attenuates out-of-band frequencies in the RF signal received from the antenna. The processing circuit 906 processes (e.g., demodulates and decodes) the filtered RF signal to extract information. The amplifier 904 and / or the processing circuit 906 may be implemented in a semiconductor substrate 102.
[0032] Figure 10 is a block diagram of an example oscillator circuit 1000. The oscillator circuit 1000 includes a resonator 1002 and an active circuit 1004. The resonator 1002 is coupled to the active circuit 1004. For example, the positive and negative electrodes of the resonator 1002 are driven by the active circuit 1004. The active circuit 1004 has an output terminal at which a clock signal having a frequency derived from the resonant frequency of the resonator 1002 is provided. The resonator 1002 and the active circuit 1004 can be implemented as examples of circuit 100 or circuit 200. The active circuit 1004 can be implemented in a semiconductor substrate 102, and the resonator 1002 can be implemented in a resonator 103 and a metallization structure 104.
[0033] Figure 11 is a flowchart of an example method 1100 for fabricating a circuit comprising a piezoelectric crystal layer attached to an integrated circuit. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Additionally, some embodiments may perform only some of the shown actions. Method 1100 can be used to fabricate examples of circuit 100 or circuit 200. The operation of method 1100 is illustrated in Figures 12A to 12K and Figures 13A and 13B.
[0034] Prior to the operation of block 1102, semiconductor substrate 102 is prepared in an integrated circuit fabrication facility (e.g., a CMOS IC fabrication facility), and electronic components are fabricated on semiconductor substrate 102. Piezoelectric film 110 may be prepared in a facility separate from the integrated circuit fabrication facility. Piezoelectric film 110 may be prepared in a facility suitable for manufacturing piezoelectric materials (e.g., piezoelectric materials having a single-crystal structure), such as lithium niobate crystals.
[0035] In block 1102, a metallization structure 104 is fabricated on semiconductor substrate 102. The metallization structure 104 may be fabricated in a back-end processing (BEOL) performed as part of an integrated circuit package. The metallization structure 104 may include any number of dielectrics (e.g., silicon dioxide) and metal layers (e.g., copper or aluminum) as needed to interconnect components provided by semiconductor substrate 102 and provide external connection terminals.
[0036] In frame 1104, electrodes 116, 118, and 120 (and any other electrodes that can be used to drive the piezoelectric film 110) are fabricated in metallized structure 104. The metal structure (including the electrodes) of metallized structure 104 can be fabricated using an inlay process.
[0037] In frame 1106, a dielectric material, such as silicon dioxide, is formed on the metallized structure.
[0038] In frame 1108, a portion of the dielectric layer formed in frame 1106 is removed to expose electrodes 116, 118, and 120. Figure 12A shows an example of a metallization structure 104 fabricated on semiconductor substrate 102 after the electrodes have been exposed. Figure 13A shows a dielectric layer 1302 on the metallization structure, which is etched to form openings 1304, thereby exposing electrodes 116, 118, and 120.
[0039] In frame 1110, a piezoelectric film 110 is fabricated and bonded to an acoustic substrate 1202. The piezoelectric film 110 can be fabricated in a facility separate from the integrated circuit fabrication facility in which the semiconductor substrate 102 is fabricated. The piezoelectric film 110 can be lithium niobate, aluminum nitride, or any other piezoelectric material. The piezoelectric film 110 can have a single-crystal or polycrystalline structure. The single-crystal film can be configured with various wafer orientations to provide desired acoustic properties. Because the piezoelectric film 110 is fabricated separately from the semiconductor substrate 102 (e.g., in a different facility), the fabrication of the piezoelectric film 110 does not contaminate the semiconductor substrate 102 (e.g., the lithium used to fabricate the piezoelectric film 110 does not contaminate the silicon of the semiconductor substrate 102), and the piezoelectric film 110 can be fabricated at a higher quality than is possible in an integrated circuit fabrication facility. The material of the acoustic substrate 1202 can be selected based on the piezoelectric film 110. The material of the acoustic substrate 1202 can be quartz, lithium niobate, sapphire, silicon, aluminum nitride, or other materials. Figure 12B illustrates an example of a piezoelectric film 110 bonded to an acoustic substrate 1202. The example of the piezoelectric film 110 may comprise one or more layers of piezoelectric crystals, wherein the orientation of each crystal layer can be selected to generate a desired resonant frequency. Figure 12C illustrates an example of a piezoelectric film 110 comprising piezoelectric crystal layers 1201 and 1203. The crystals of piezoelectric crystal layer 1201 may have the same orientation as the crystals of piezoelectric crystal layer 1203, or have a different orientation, to provide the desired resonant frequency.
[0040] In frame 1112, a silicon cap wafer 1204 is fabricated and bonded to the piezoelectric film 110. The silicon cap wafer 1204 provides an air gap 114. Figure 12D shows an example of the silicon cap wafer 1204. The silicon cap wafer 1204 is bonded to the piezoelectric film 110. Figure 12E shows the silicon cap wafer 1204 bonded to the piezoelectric film 110. After the silicon cap wafer 1204 is bonded to the piezoelectric film 110, the acoustic substrate 1202 can be removed.
[0041] After the acoustic substrate 1202 has been removed, recesses can be formed in some instances of the piezoelectric film 110. The recesses can be positioned such that electrodes 116, 118, and 120 are each aligned with one of the recesses. The recesses can improve energy confinement in the piezoelectric film 110 and increase the quality factor of the resonator. Figure 12F shows a recess 1205 formed in the piezoelectric film 110 above the air gap 114. The recess 1205 can be formed by etching the piezoelectric film 110.
[0042] After the acoustic substrate has been removed, in frame 1114, a bonding layer 108 is formed on the piezoelectric film 110 in place of the acoustic substrate 1202. For example, as shown in FIG12E or FIG12F, the bonding layer 108 may be formed on the piezoelectric film 110. The bonding layer 108 may be a polymer, silicon dioxide, or other materials. In some examples, the bonding layer 108 may be formed on the metallized structure 104.
[0043] The silicon cap wafer 1204 can be subdivided (individualized) into individual instances of resonator 103 for bonding to integrated circuit 101. Figure 12G illustrates the silicon cap wafer 1204 and the lines from which resonator 103 can be individualized from the silicon cap wafer 1204. Figure 12H illustrates an instance of resonator 103 individualized from the silicon cap wafer 1204.
[0044] In frame 1116, a portion of the bonding layer 108 can be removed from the resonator 103 to form a void in some instances. The removed portion of the bonding layer 108 can be aligned with the air gap 114, forming an air gap 402 between the piezoelectric film 110 and the electrodes 116, 118, and 120. Figure 12I shows an example of the resonator 103 after the portion of the bonding layer 108 has been removed to form the air gap 402.
[0045] In frame 1118, resonator 103 is aligned with electrodes 116, 118, and 120. If resonator 103 includes recess 1205, then recess 1205 is aligned with electrodes 116, 118, and 120. If resonator 103 lacks recess 1205, the alignment of resonator 103 with electrodes 116, 118, and 120 can be relatively imprecise because the dimensions of air gaps 114 and 402 can be designed to allow for imprecise alignment of resonator 103 relative to electrodes 116, 118, and 120. For example, the only constraint on alignment could be that air gaps 114 and 402 are located above electrodes 116, 118, and 120. Furthermore, the misalignment of the silicon cap wafer 1204 with the piezoelectric film 110 creates a lateral air gap within the opening 1304 where it is laterally adjacent to the piezoelectric film 110 (and the resonator 103). This does not degrade the performance of the resonator 103, at least because the lateral air gap does not affect energy limiting. In Figure 13A, proper alignment of the resonator 103 with the electrodes 116, 118, and 120 can be achieved by placing the resonator 103 anywhere within the opening 1304.
[0046] In frame 1120, a piezoelectric film 110 is attached to the metallization structure 104 via a bonding layer 108. Figures 12J and 12K show cross-sectional views of examples of a resonator 103 attached to the metallization structure 104. Figure 12J shows the resonator 103 of Figure 12H attached to the metallization structure 104. Figure 12K shows the resonator 103 of Figure 12I attached to the metallization structure 104. Figure 13B shows a perspective view of a resonator 103 attached to an integrated circuit 101.
[0047] In this description, the term "coupled" may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, if intermediate component C does not alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C such that device B is controlled by control signals generated by device A.
[0048] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.
[0049] The circuits or devices described herein as containing certain components may be practically adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more power sources (e.g., voltage and / or current sources) may alternatively contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some passive elements and / or power sources to form the described structure, for example, by an end user and / or a third party at or after manufacturing.
[0050] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available before the component replacement.
[0051] While some elements of the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit may be contained within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.
[0052] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, or any other form of grounding connection applicable to or suited to the teachings herein. In this specification, unless otherwise stated, "about," "approximately," or "generally" preceding a parameter means within + / - 10% of said parameter, or, if the parameter is zero, within a reasonable range of approximately zero.
[0053] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are possible.
Claims
1. An apparatus comprising: A bare die comprising a semiconductor substrate, a metallization structure on the semiconductor substrate, and a dielectric material surrounding at least a portion of the metallization structure; A bonding layer located on the metallized structure; and a membrane, which is attached to the bonding layer, the membrane comprising a piezoelectric material.
2. The device according to claim 1, wherein the piezoelectric material comprises at least one of the following: aluminum nitride or lithium niobate.
3. The device of claim 1, wherein the bonding layer comprises a bonding material, and the bonding material comprises at least one of a polymer or a dielectric material.
4. The device of claim 3, wherein the bonding material comprises at least one of the following: parylene, PDMS, or silica.
5. The device according to claim 3, wherein the piezoelectric material has a single-crystal structure.
6. The device of claim 1, wherein the metallized structure comprises a positive electrode and a negative electrode, the positive electrode and the negative electrode being laterally adjacent to each other.
7. The device of claim 6, wherein the membrane overlaps with the positive electrode and the negative electrode.
8. The device of claim 6, further comprising a cap located on the membrane, wherein a portion of the cap located above the positive electrode and the negative electrode is separated from a portion of the membrane by a first gap.
9. The device of claim 8, wherein the portion of the membrane is further spaced apart from the positive electrode and the negative electrode by a second gap, wherein the second gap does not contain the bonding layer.
10. The device according to claim 7, wherein: The positive electrode is a first positive electrode, and the negative electrode is a first negative electrode; the metallization structure includes a second positive electrode, a second negative electrode, a third positive electrode, and a third negative electrode that are laterally adjacent to each other; the first positive electrode is coupled to a signal input terminal, and the third negative electrode is coupled to a signal output terminal; The first negative electrode is coupled to the second positive electrode and the third positive electrode; and the second negative electrode is coupled to the reference terminal.
11. The device of claim 7, wherein the film, the positive electrode, and the negative electrode are configured as piezoelectric resonators, and the semiconductor substrate includes a transistor electrically coupled to the piezoelectric resonator via a metal conductor of the metallization structure.
12. The device of claim 11, wherein the transistor comprises a first half-bridge having a first switching terminal and a second half-bridge having a second switching terminal, and the piezoelectric resonator is coupled between the first switching terminal and the second switching terminal.
13. A method comprising: exist An bonding layer is formed on at least one of the metallized structure of the bare die or the film; And attach the film to the metallized structure via the bonding layer.
14. The method of claim 13, further comprising forming a positive electrode and a negative electrode laterally adjacent to each other in the metallized structure.
15. The method of claim 14, further comprising forming a cap on the membrane, the cap providing an air gap between a portion of the cap and the membrane.
16. The method of claim 15, further comprising: A dielectric layer is formed on the metallized structure; A portion of the dielectric layer is removed to form an opening exposing the positive electrode and the negative electrode; The bonding layer, the membrane, and the cap are placed in the opening.
17. The method of claim 15, further comprising placing the bonding layer, the film, and the cap on the metallized structure.
18. The method of claim 17, wherein the membrane is located between the air gap and the positive electrode and the negative electrode.
19. The method of claim 17, further comprising removing a portion of the bonding layer to form a void in the bonding layer.
20. The method of claim 19, further comprising aligning the voids in the bonding layer with the positive electrode and the negative electrode.