Semiconductor device with hybrid memory layer

Abstract

The invention relates to a semiconductor device with a hybrid memory layer and a method of manufacturing the same. The semiconductor device includes a first interconnection line extending in a first direction; a second interconnection line extending along a second direction; and a memory cell disposed between the first interconnection line and the second interconnection line. The memory cell includes a first electrode; a first memory layer including a ferroelectric layer over the first electrode; a second electrode over the first memory layer; a second memory layer including a high-k dielectric layer over the second electrode; an oxygen storage layer over the second storage layer; and a third electrode over the oxygen storage layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0150974, filed with the Korean Intellectual Property Office on October 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Specifically, a semiconductor device having a hybrid memory layer and a method for manufacturing the semiconductor device having the hybrid memory layer are disclosed. Background Technology

[0004] Semiconductor devices with ferroelectric layers are under investigation. Ferroelectric layers have low power consumption due to their low on-current characteristics. However, hybrid memory layers can have very low on-current and low on / off current ratios. Therefore, hybrid memory layers are difficult to use in semiconductor devices. Summary of the Invention

[0005] Embodiments of this disclosure provide a semiconductor device having a hybrid memory layer.

[0006] Embodiments of this disclosure provide a semiconductor device having a ferroelectric storage layer and a variable resistance layer.

[0007] Embodiments of this disclosure provide a method for manufacturing a semiconductor device having a hybrid memory layer.

[0008] Embodiments of this disclosure provide a method for manufacturing a semiconductor device having a ferroelectric storage layer and a variable resistance layer.

[0009] According to one embodiment of this disclosure, a semiconductor device includes: a first interconnect extending along a first direction; a second interconnect extending along a second direction; and a memory cell disposed between the first interconnect and the second interconnect. The memory cell includes a first electrode; a first memory layer including a ferroelectric layer disposed above the first electrode; a second electrode disposed above the first memory layer; a second memory layer including a high-k dielectric layer disposed above the second electrode; an oxygen storage layer disposed above the second memory layer; and a third electrode disposed above the oxygen storage layer.

[0010] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming a first electrode material layer, forming an interface insulating material layer on the first electrode material layer, forming a first storage material layer on the interface insulating material layer, forming a second electrode material layer on the first storage material layer, forming a second storage layer on the second electrode material layer, forming a third electrode material layer on the second storage material layer, and performing a deoxygenation process to remove the interface insulating material layer, and forming a metal oxide layer between the second electrode material layer and the third electrode material layer.

[0011] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming a first electrode material layer, the first electrode material layer including a polycrystalline silicon layer; forming an interface insulating material layer by oxidizing the upper surface of the first electrode material layer; forming a first storage material layer including a ferroelectric layer on the interface insulating material layer; forming a lower deoxygenating metal layer on the first storage material layer; forming a second storage material layer including a high-k dielectric layer on the lower deoxygenating metal layer; forming an upper deoxygenating metal layer on the second storage layer; and performing a deoxygenation process to remove the interface insulating layer and form an oxygen storage layer between the second storage material layer and the upper deoxygenating metal layer. Attached Figure Description

[0012] Figure 1A and Figure 1B These are schematic circuit diagrams and perspective views illustrating a cell array structure of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 2A This is a circuit diagram schematically illustrating a cell array structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 2B It is a schematic longitudinal cross-sectional view of a unit cell of a semiconductor device.

[0015] Figure 3 This is a schematic longitudinal cross-sectional view illustrating the memory cell structure of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figures 4A to 4E This is a schematic longitudinal cross-sectional view illustrating a method of forming a memory cell according to an embodiment of the present disclosure. Detailed Implementation

[0017] The embodiments disclosed herein will be described in detail with reference to the accompanying drawings. The specific structural or functional descriptions provided in the embodiments are merely examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0018] All the crosshairs in the diagram represent corresponding or similar areas between the diagrams, rather than representing material related to those areas.

[0019] When one element is identified as “connected” or “coupled” to another element, the two elements can be directly connected or coupled, or they can be connected or coupled through one or more intermediate elements. When two elements are identified as “directly connected” or “directly coupled”, one element is directly connected or coupled to the other element without any intermediate elements.

[0020] When one element is identified as being "above", "on top of", "below", or "under" another element, the two elements may be in direct contact, or an intermediate element may be placed between the two elements.

[0021] Terms such as "vertical," "horizontal," "top," "bottom," "above," "below," "under," "below," "over," "side," "upper part," "topmost," "lowest part," "bottommost," "front," "back," "left," "right," "column," "row," "hierarchy," and other terms indicating relative spatial relationships or directions are used for ease of description or reference to the accompanying drawings only and are not intended to limit the scope. Within the scope of this disclosure, other spatial relationships or directions may exist that are not shown in the accompanying drawings or described in the specification.

[0022] Terms such as "first" and "second" are used to distinguish individual elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be referred to as the second element, while in another example, the second element may be referred to as the first element.

[0023] In the specification, when an element included in an embodiment is described in the singular, the element may be interpreted as including multiple elements that perform the same or similar functions.

[0024] The relevant concepts are disclosed below with reference to embodiments and examples. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The examples disclosed in this specification should be considered exemplary and not restrictive. Therefore, the scope of this disclosure is not limited to the following description. All changes within the equivalent meaning and scope of the claims are included within its scope.

[0025] Figure 1A and Figure 1B These are schematic circuit diagrams and perspective views illustrating a cell array structure of a semiconductor device according to an embodiment of the present disclosure. Reference Figure 1A and Figure 1BThe cell array structure CA1 may include a first interconnect 10, a second interconnect 90, and memory cells MC. The first interconnect 10 may extend parallel to each other in a first horizontal direction X. For example, the first interconnect 10 may be a word line. The second interconnect 90 may extend parallel to each other in a second horizontal direction Y. For example, the second interconnect 90 may be a bit line. In another embodiment, the first interconnect 10 may be a bit line, and the second interconnect 90 may be a word line. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other. From a plan view, memory cells MC may be disposed at the intersections between the first interconnect 10 and the second interconnect 90. Each memory cell MC may include a variable resistor element. Each memory cell MC may include two electrodes. For example, each memory cell MC may include a first electrode electrically connected to the first interconnect 10 and a second electrode electrically connected to the second interconnect 90.

[0026] Figure 2A For illustrative purposes, a circuit diagram illustrating a cell array structure of a semiconductor device according to an embodiment of the present disclosure is shown. Figure 2B This is a schematic longitudinal cross-sectional view of a unit cell in a semiconductor device. (Reference) Figure 2A and Figure 2B The cell array structure CA2 may include an active line 110, a word line 120, a source line 190, and a unit cell UC. The active line 110 and word line 120 may extend parallel to each other in a first horizontal direction X. The source line 190 may extend parallel to each other in a second horizontal direction Y. The unit cell UC may be disposed at the intersection between the active line 110 and the source line 190. Each unit cell UC may include a select transistor ST and a memory cell MC. The select transistor ST may include a gate electrode 121 disposed on a substrate 105, a drain electrode 122 formed in the substrate 105, and a source electrode 123. The gate electrode 121 of the select transistor ST may correspond to the word line 120. The drain electrode 122 of the select transistor ST may be electrically connected to the active line 110 via an active contact plug 115. The source electrode 123 of the select transistor ST may be electrically connected to a first electrode of the memory cell MC. The second electrode of the memory cell MC may be electrically connected to the source line 190. The substrate 105 may include a semiconductor layer, such as a silicon layer. The active contact plug 115 may include a conductor, such as doped polysilicon, a metal, a metal compound, a metal silicide, or a metal alloy. Reference numerals for the gate insulating layer, gate capping layer, and gate spacer layer of the select transistor ST are omitted in the figure.

[0027] Figure 3 It is along Figure 1B The longitudinal cross-sectional view taken by line I-I' schematically illustrates the memory cell structure of a semiconductor device according to an embodiment of the present disclosure. (See reference...) Figure 3The storage cell structure 100 may include a first interconnect 10, a second interconnect 90, and a storage cell MC between the first interconnect 10 and the second interconnect 90. The first interconnect 10 and the second interconnect 90 may each have a linear shape that intersects each other and extends in different horizontal directions when viewed in plan view. The storage cell MC may have a column shape extending vertically between the first interconnect 10 and the second interconnect 90. The storage cell structure 100 may also include a first contact plug 15 between the first interconnect 10 and the storage cell MC, and a second contact plug 95 between the storage cell MC and the second interconnect 90.

[0028] The first interconnect 10, the second interconnect 90, the first contact plug 15, and the second contact plug 95 may comprise conductors, such as metals, metal alloys, metal compounds, metal silicides, or doped silicon. In one embodiment, the first interconnect 10, the second interconnect 90, the first contact plug 15, and the second contact plug 95 may comprise multiple conductor layers. In one embodiment, reference... Figure 2A and Figure 2B The first interconnect 10 may correspond to the source electrode 123 in the substrate 105, and the second interconnect 90 may correspond to the source line 190.

[0029] The storage unit MC may include a lower electrode 30, a lower storage layer 40, an intermediate electrode 50, an upper storage layer 60, an oxygen storage layer 70, and an upper electrode 80.

[0030] The lower electrode 30 may include a polysilicon layer. For example, the lower electrode 30 may include an N-doped polysilicon layer doped with N-type ions such as phosphorus (P), arsenic (As), or antimony (Sb).

[0031] The lower storage layer 40 may include a ferroelectric layer. For example, the lower storage layer 40 may include at least one of a hafnium (Hf)-based compound layer, a zirconium (Zr)-based compound layer, or a hafnium-zirconium (HfZr)-based compound layer. The hafnium (Hf)-based compound layer may include a hafnium oxide (HfO)-based ferroelectric material layer, the zirconium (Zr)-based compound layer may include a zirconium oxide (ZrO)-based ferroelectric material layer, and the hafnium-zirconium (HfZr)-based compound layer may include a hafnium oxide-zirconium (HfZrO)-based ferroelectric material layer. In one embodiment, the lower storage layer 40 may include one of hafnium oxide (HfO2), zirconium oxide (ZrO2), or hafnium-zirconium oxide (HfZrO). In another embodiment, the lower storage layer 40 may include at least one of impurity-doped hafnium oxide (HfO2), impurity-doped zirconium oxide (ZrO2), or impurity-doped hafnium oxide (HZO). Impurities may include at least one of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), arsenic (As), tin (Sn), gadolinium (Gd), lanthanum (La), scandium (Sc), and strontium (Sr).

[0032] The intermediate electrode 50 may include a metal layer. The intermediate electrode 50 may include an oxygen-free metal layer. For example, the intermediate electrode 50 may include a titanium (Ti) layer. In one embodiment, the intermediate electrode 50 may include a titanium oxide (TiO) layer. For example, a portion of the intermediate electrode 50 may be a titanium oxide (TiO) layer. The intermediate electrode 50 may physically and materially isolate the upper storage layer 60 from the lower storage layer 40.

[0033] The upper storage layer 60 may include a high-k dielectric layer. The upper storage layer 60 may comprise a metal oxide. For example, the upper storage layer 60 may comprise at least one of the following materials: titanium oxide (TiO), vanadium oxide (VO), manganese oxide (MnO), iron oxide (FeO), cobalt oxide (CoO), zinc oxide (ZnO), yttrium oxide (YO), zirconium oxide (ZrO), niobium oxide (NbO), molybdenum oxide (MoO), ruthenium oxide (RuO), palladium oxide (PdO), barium oxide (BaO), lanthanum oxide (LaO), hafnium oxide (HfO), iridium oxide (IrO), or other transition metal oxides. In one embodiment, the upper storage layer 60 may be an amorphous material layer. For example, when the upper storage layer 60 is an amorphous material layer, the formation of conductive filaments under an electric field is easier than when the upper storage layer 60 is a crystalline material layer. Furthermore, the conductive filaments are more likely to annihilate or electrically disconnect due to physical degradation.

[0034] The oxygen storage layer 70 may include at least one of a metal layer or a metal oxide layer. For example, the oxygen storage layer 70 may include at least one of a tantalum (Ta) layer, a hafnium (Hf) layer, a titanium (Ti) layer, a tantalum oxide (TaO) layer, a hafnium oxide (HfO) layer, or a titanium oxide (TiO) layer. The oxygen storage layer 70 may absorb oxygen atoms from the upper storage layer 60 and / or supply oxygen atoms to the upper storage layer 60. When oxygen atoms are absorbed from the upper storage layer 60 into the oxygen storage layer 70, oxygen vacancies may be generated in the upper storage layer 60. Therefore, by the movement of oxygen vacancies, conductive pathways, such as conductive filaments, may be formed in the upper storage layer 60. When oxygen atoms are supplied from the oxygen storage layer 70 to the upper storage layer 60, the oxygen vacancies may dissipate. Therefore, the conductive filaments may dissipate. The intermediate electrode 50 may block and prevent oxygen vacancies from moving from the upper storage layer 60 to the lower storage layer 40.

[0035] The upper electrode 80 may include at least one of a metal layer, a metal compound layer, and a metal alloy layer. In one embodiment, the upper electrode 80 and the oxygen storage layer 70 may contain the same metal. For example, the upper electrode 80 may include at least one of a tantalum (Ta) layer, a titanium (Ti) layer, a titanium nitride (TiN) layer, a titanium aluminum nitride (TiAlN) layer, or other conductive layers containing titanium (Ti) or tantalum (Ta).

[0036] According to one embodiment of this disclosure, a memory cell MC may include two memory elements, such as a lower memory layer 40 and an upper memory layer 60. The lower memory layer 40 may be used as a ferroelectric memory element. Therefore, compared to a non-ferroelectric memory layer, the lower memory layer 40 has a lower turn-off current characteristic and operates stably at lower power. That is, compared to a memory cell using a non-ferroelectric memory layer, the memory cell MC can be used as a memory element layer to maintain faster and more stable data with lower power. The upper memory layer 60 may be used as a variable resistance element layer using a high-k dielectric layer. For example, the memory element layer may be used as a variable resistance memory element layer whose conductivity is changed by generating and dissipating conductive filaments according to the applied voltage or current. Therefore, the memory cell MC can be used as a hybrid memory element having a ferroelectric memory element layer and a variable resistance memory element layer, and may have a high on / off current ratio.

[0037] Figures 4A to 4E A longitudinal cross-sectional view illustrating a method for forming a memory cell MC according to an embodiment of the present disclosure is shown for illustrative purposes. (See reference...) Figure 4A The manufacturing method may include forming a lower electrode material layer 31, an interface material layer 36, a lower storage material layer 41, an intermediate electrode material layer 51, an upper storage material layer 61, and an upper electrode material layer 81.

[0038] The lower electrode material layer 31 may include a silicon layer. For example, forming the lower electrode material layer 31 may include forming a polycrystalline silicon layer using a deposition process. In one embodiment, the method may further include a process of providing a dopant to the lower electrode material layer 31. For example, the method may further include performing an ion implantation process or an ion diffusion process. In one embodiment, the dopant may be provided simultaneously during the deposition process of forming the lower electrode material layer 31.

[0039] The interface material layer 36 may include a silicon oxide (SiO2) layer. For example, forming the interface material layer 36 may include forming a native oxide film on the surface of the lower electrode material layer 31 using a native oxidation reaction. In one embodiment, forming the interface material layer 36 may include oxidizing the surface of the lower electrode material layer 31. In another embodiment, forming the interface material layer 36 may include forming a silicon oxide (SiO2) layer on the lower electrode material layer 31 by performing a deposition process. That is, the interface material layer 36 may include a silicon oxide layer or an oxidized silicon layer. The lower electrode material layer 31 and the interface material layer 36 may contain the same material. For example, both the lower electrode material layer 31 and the interface material layer 36 may contain silicon (Si).

[0040] The lower storage material layer 41 may include a ferroelectric material layer. In one embodiment, the lower storage material layer 41 may include HZO (HfZrO), specifically, it may include a crystalline hafnium zirconium oxide layer or a polycrystalline hafnium zirconium oxide layer. Forming the lower storage material layer 41 may include forming a hafnium zirconium oxide layer comprising hafnium (Hf), zirconium (Zr), and oxygen (O) on the interface material layer 36 using a deposition process. In one embodiment, the lower storage layer 40 may be a crystalline layer. For example, the lower storage layer 40 may include a crystalline hafnium zirconium oxide (HfZrO) layer.

[0041] The intermediate electrode material layer 51 may include a reactive metal layer, such as titanium (Ti). For example, forming the intermediate electrode material layer 51 may include forming a titanium (Ti)-containing metal layer on the lower storage material layer 41 by performing a deposition process. In one embodiment, the intermediate electrode material layer 51 may include a lower deoxygenating metal layer. In one embodiment, the lower deoxygenating metal layer may include a lower oxygen-absorbing layer. The lower deoxygenating metal layer or the lower oxygen-absorbing layer may include a titanium (Ti) layer.

[0042] The upper storage material layer 61 may include a high-k dielectric material layer. For example, the upper storage material layer 61 may include a hafnium oxide (HfO) layer. Forming the upper storage material layer 61 may include forming a hafnium oxide layer on the intermediate electrode material layer 51 by performing a deposition process. In one embodiment, the upper storage material layer 61 may include an amorphous hafnium oxide layer.

[0043] The upper electrode material layer 81 may include a reactive metal layer, such as titanium (Ti). For example, forming the upper electrode material layer 81 may include forming a titanium (Ti) layer on the upper storage material layer 61 by performing a deposition process. In one embodiment, the upper storage material layer 61 may be an upper oxygen-removing metal layer. In one embodiment, the upper oxygen-removing metal layer may include an upper oxygen-absorbing layer. The upper oxygen-removing metal layer or the upper oxygen-absorbing layer may include a titanium (Ti) layer.

[0044] refer to Figure 4B The method may further include performing a first deoxygenation process to remove oxygen atoms from the interface material layer 36 and move them to the intermediate electrode material layer 51. For example, the intermediate electrode material layer 51 may absorb oxygen atoms from the interface material layer 36. As the oxygen atoms are removed, the interface material layer 36 can be thinned. In one embodiment, the intermediate electrode material layer 51 may typically be slightly oxidized. In one embodiment, a portion of the intermediate electrode material layer 51 may be partially oxidized. For example, all or part of the intermediate electrode material layer 51 may be modified with a titanium oxide layer. The intermediate electrode material layer 51 may expand slightly. In one embodiment, when the lower storage material layer 41 is a crystalline material layer, the movement of oxygen atoms from the interface material layer 36 to the intermediate electrode material layer 51 is more stable than when the lower storage material layer 41 is an amorphous material layer. That is, oxygen atoms can be removed more easily.

[0045] refer to Figure 4C The method may further include performing a second deoxygenation process to continuously remove oxygen atoms from the interface material layer 36 and move them to the intermediate electrode material layer 51, and to remove oxygen atoms from the intermediate electrode material layer 51 and move them to the upper electrode material layer 81. For example, the intermediate electrode material layer 51 may continuously absorb oxygen atoms from the interface material layer 36, while the upper electrode material layer 81 may absorb oxygen atoms from the intermediate electrode material layer 51. As oxygen atoms are further removed, the interface material layer 36 may be further thinned. The oxygen atoms removed from the intermediate electrode material layer 51 may partially oxidize the lower portion of the upper electrode material layer 81. For example, the lower portion of the upper electrode material layer 81 may be partially oxidized, thereby being modified into an oxygen storage material layer 71. In one embodiment, the oxygen storage material layer 71 may include at least one of a tantalum (Ta) layer, a hafnium (Hf) layer, a titanium (Ti) layer, a tantalum oxide (TaO) layer, a hafnium oxide (HfO) layer, or a titanium oxide (TiO) layer. The intermediate electrode material layer 51 can absorb oxygen atoms from the interface material layer 36 and provide oxygen atoms to the upper electrode material layer 81.

[0046] refer to Figure 4D The method may further include: performing a third removal process to continuously remove oxygen atoms from the interface material layer 36 and move them to the intermediate electrode material layer 51, thereby eliminating the interface material layer 36; and continuously removing oxygen atoms from the intermediate electrode material layer 51 and moving them to the upper electrode material layer 81, thereby increasing the thickness of the oxygen storage material layer 71. The interface material layer 36 may disappear. For example, all oxygen atoms in the interface material layer 36 may be removed, thereby modifying the interface material layer 36 to the same material as the lower electrode material layer 31. The upper electrode material layer 81 may continuously absorb oxygen atoms from the intermediate electrode material layer 51. Therefore, the oxygen storage material layer 71 may be further thickened.

[0047] The first to third cleaning processes can be performed continuously without interrupting the vacuum. For example, the first to third cleaning processes can be essentially a single process. The first to third cleaning processes may include performing an annealing process. The annealing process may include heating at least one of the lower electrode material layer 31, interface material layer 36, lower storage material layer 41, intermediate electrode material layer 51, upper storage material layer 61, and upper electrode material layer 81 to about 300°C to 600°C.

[0048] refer to Figure 4EThe method may further include: patterning a lower electrode material layer 31, a lower storage material layer 41, an intermediate electrode material layer 51, an upper storage material layer 61, an oxygen storage material layer 71, and an upper electrode material layer 81 by performing a patterning process to form a memory cell MC. Through patterning, the lower electrode material layer 31, lower storage material layer 41, intermediate electrode material layer 51, upper storage material layer 61, oxygen storage material layer 71, and upper electrode material layer 81 can form a lower electrode 30, a lower storage layer 40, an intermediate electrode 50, an upper storage layer 60, an oxygen storage layer 70, and an upper electrode 80. Therefore, the memory cell MC may include a lower electrode 30, a lower storage layer 40, an intermediate electrode 50, an upper storage layer 60, an oxygen storage layer 70, and an upper electrode 80. In one embodiment, the method may further include conformally forming spacer layers on two sides and a top surface of the memory cell MC. The spacer layers may be oxygen-free insulating materials. For example, the spacer layers may include silicon nitride-based insulating layers.

[0049] According to embodiments of this disclosure, semiconductor devices with hybrid storage layers can operate at low operating voltages and can have a high on / off current ratio.

[0050] Although this disclosure has been described with respect to certain specific embodiments, those skilled in the art will understand that various changes and modifications may be made without departing from the spirit and scope of this disclosure as defined in the following claims.

Claims

1. A semiconductor device, comprising: A first interconnect line extends along a first direction; The second interconnect line extends along the second direction; and A storage unit disposed between the first interconnect and the second interconnect, wherein the storage unit comprises: First electrode; A first storage layer includes a ferroelectric layer disposed on the first electrode; The second electrode is disposed on top of the first storage layer; A second storage layer includes a high-k dielectric layer disposed above the second electrode; an oxygen storage layer disposed above the second storage layer; and... The third electrode is disposed on the oxygen storage layer.

2. The semiconductor device according to claim 1, in, The first electrode includes a polycrystalline silicon layer.

3. The semiconductor device according to claim 1, in, The first storage layer includes a crystalline hafnium zirconium oxide layer.

4. The semiconductor device according to claim 1, in, The second electrode comprises at least one of a titanium layer or a titanium nitride layer.

5. The semiconductor device according to claim 1, in, The second storage layer includes an amorphous hafnium oxide layer.

6. The semiconductor device according to claim 1, in, The second storage layer contains oxygen vacancies.

7. The semiconductor device according to claim 1, in, The oxygen storage layer includes at least one of a tantalum layer, a hafnium layer, a titanium layer, a tantalum oxide layer, a hafnium oxide layer, or a titanium oxide layer.

8. The semiconductor device according to claim 1, in, The third electrode includes at least one of a titanium layer or a titanium nitride layer.

9. The semiconductor device according to claim 1, further comprising: A first contact plug is located between the first interconnect and the memory cell.

10. The semiconductor device according to claim 9, further comprising: A second contact plug is located between the storage cell and the second interconnect.

11. The semiconductor device according to claim 1, in, The first direction and the second direction are perpendicular to each other.

12. A method for manufacturing a semiconductor device, comprising: Forming the first electrode material layer, An interface insulating material layer is formed on top of the first electrode material layer. A first storage material layer is formed on top of the interface insulating material layer. A second electrode material layer is formed on top of the first storage material layer. A second storage material layer is formed on top of the second electrode material layer. A third electrode material layer is formed on top of the second storage material layer, and A deoxygenation process is performed to remove the interface insulating material layer and to form a metal oxide layer between the second electrode material layer and the third electrode material layer.

13. The method according to claim 12, in, The first electrode material layer includes a polycrystalline silicon layer.

14. The method according to claim 12, in, The interface insulating material layer includes silicon oxide.

15. The method according to claim 14, in, Forming the interface insulating material layer includes: oxidizing the upper surface of the first electrode material layer.

16. The method according to claim 12, in, The first storage material layer includes a ferroelectric layer, and the ferroelectric layer includes a crystalline hafnium zirconium oxide layer.

17. The method according to claim 12, in, The second electrode material layer contains at least one of titanium or titanium oxide.

18. The method according to claim 12, in, The first storage material layer includes an amorphous hafnium oxide layer.

19. The method according to claim 12, in, The metal oxide layer includes a titanium oxide layer.

20. The method according to claim 12, in, The third electrode material layer includes at least one of a titanium layer or a titanium nitride layer.

21. The method of claim 12, further comprising: The first electrode material layer, the first storage material layer, the second electrode material layer, the second storage material layer, the metal oxide layer, and the third electrode material layer are patterned to form a storage cell including a first electrode, a first storage layer, a second electrode, a second storage layer, an oxygen storage layer, and a third electrode.

22. A method for manufacturing a semiconductor device, comprising: Forming a first electrode material layer including a polycrystalline silicon layer, An interface insulating layer is formed by oxidizing the upper surface of the first electrode material layer. A first storage material layer, including a ferroelectric layer, is formed on the interface insulating layer. A lower deoxygenated metal layer is formed on top of the first storage material layer. A second storage material layer, including a high-k dielectric layer, is formed on top of the lower deoxygenated metal layer. An oxygen-removing metal layer is formed on top of the second storage material layer, and A deoxygenation process is performed to remove the interface insulation layer and form an oxygen storage layer between the second storage material layer and the upper deoxygenated metal layer.

23. The method according to claim 22, in, The ferroelectric layer includes a hafnium zirconium oxide layer.

24. The method according to claim 22, in, The lower deoxygenating metal layer includes a titanium layer.

25. The method according to claim 22, in, The high-k dielectric layer includes a hafnium oxide layer.

26. The method according to claim 22, in, The oxygen-removing metal layer includes a titanium layer.

27. The method according to claim 22, in, The oxygen storage layer includes at least one of a tantalum layer, a hafnium layer, a titanium layer, a tantalum oxide layer, a hafnium oxide layer, or a titanium oxide layer.

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