Manufacturing process for dicing integrated circuit (IC) dies
The DBG manufacturing process, which involves plasma etching before back-side grinding, solves the problems of dicing and circuit damage, enabling a more reliable IC die separation process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2025-10-17
- Publication Date
- 2026-05-01
AI Technical Summary
In the current technology for cutting integrated circuit dies, conventional etching processes can easily lead to damage to the cutting tape and manufacturing process components, and photoresist may form bubbles during the adhesion process, resulting in circuit damage.
The DBG manufacturing process employs plasma etching before back-side grinding. First, the semiconductor wafer is plasma etched, then the photoresist is removed, followed by back-side grinding and bonding to the DAF. Then, a second plasma etching is performed to etch the DAF, and finally, the dicing tape is stretched to separate the IC die.
It reduces the breakage of the cutting strip and damage to the manufacturing circuit, avoids circuit damage caused by photoresist bubbles, and improves the reliability and efficiency of the cutting process.
Smart Images
Figure CN121969050A_ABST
Abstract
Description
Manufacturing processes used for dicing integrated circuit (IC) dies Technical Field
[0001] This specification generally relates to integrated circuit manufacturing systems, and more specifically, to manufacturing processes for dicing integrated circuit dies. Background Technology
[0002] Integrated circuit (IC) packaging has long been implemented in computer devices to provide increasingly compact circuitry in computer products. Some ICs can be formed as flip-chip devices and / or quad flat no-lead (QFN) packages, which may include conductive pillars of electrical contacts formed onto associated contact pads on a printed circuit board (PCB). The manufacture of integrated circuits typically involves etching semiconductor material in any of a variety of ways. One such example of etching is plasma etching. Plasma etching can be performed to cut IC dies by providing etching between each of the IC dies on a semiconductor wafer. Summary of the Invention
[0003] One example includes a method for dicing a semiconductor wafer comprising multiple integrated circuit (IC) dies. The method includes plasma etching of a portion of the thickness of the semiconductor wafer between fabricated circuits in a substrate, to provide an etched semiconductor wafer. The method also includes providing a flexible material on the fabricated circuits. The method further includes back-side grinding of the etched semiconductor wafer to separate the IC dies, thereby providing separated IC dies. Each of the separated IC dies may contain a corresponding one of the fabricated circuits. The method further includes disposing the separated IC dies on a die attachment film (DAF) and removing the flexible material.
[0004] Another example includes an IC dicing system. The system includes a plasma etching tool configured to provide a first plasma etching through a portion of the thickness between fabricated circuits on a semiconductor wafer, to provide an etched semiconductor wafer. The system also includes a back-grinding tool configured to back-grind the etched semiconductor wafer to separate IC dies, thereby providing separated IC dies. Each of the separated IC dies may contain a corresponding one of the fabricated circuits. The system further includes a wafer handling apparatus configured to attach the separated IC dies to a DAF disposed between the separated IC dies and a dicing tape. The plasma etching tool may be further configured to provide a second plasma etching through the DAF between the separated IC dies.
[0005] Another example described herein includes a method for dicing a semiconductor wafer comprising multiple IC dies. The method includes a first plasma etching that provides a portion of the thickness of the semiconductor wafer between fabricated circuits in a substrate of the semiconductor wafer to provide an etched semiconductor wafer. The method further includes back-side grinding of the etched semiconductor wafer to separate the IC dies, thereby providing separated IC dies. Each of the separated IC dies may contain a corresponding one of the fabricated circuits. The method further includes setting the separated IC dies on a DAF disposed between the separated IC dies and a dicing tape. The method further includes providing a second plasma etching on the separated IC dies to etch through the DAF between each of the separated IC dies, and stretching the dicing tape to cut individual separated IC dies.
[0006] Another example described herein includes an IC device. The device includes an IC die comprising fabricated circuitry formed on a substrate. The fabricated circuitry may include an oxide material layer on the exposed surfaces of the fabricated circuitry. The oxide material layer may exhibit degradation caused by plasma etching. The device further includes a package substantially surrounding the IC die. Attached Figure Description
[0007] Figure 1 is a block diagram of an example integrated circuit (IC) dicing system.
[0008] Figure 2 shows an example of a semiconductor wafer.
[0009] Figure 3 shows an example of the first manufacturing step in cutting a semiconductor wafer.
[0010] Figure 4 shows an example of the second manufacturing step in cutting a semiconductor wafer.
[0011] Figure 5 shows an example of the third manufacturing step in dicing a semiconductor wafer.
[0012] Figure 6 shows an example of the fourth manufacturing step in dicing a semiconductor wafer.
[0013] Figure 7 shows an example of the fifth manufacturing step in dicing a semiconductor wafer.
[0014] Figure 8 shows an example of the sixth manufacturing step in dicing a semiconductor wafer.
[0015] Figure 9 shows an example of the seventh manufacturing step in dicing a semiconductor wafer.
[0016] Figure 10 shows an example of the eighth manufacturing step in dicing a semiconductor wafer.
[0017] Figure 11 shows an example of the ninth manufacturing step in dicing a semiconductor wafer.
[0018] Figure 12 shows an example of the tenth manufacturing step in dicing a semiconductor wafer.
[0019] Figure 13 shows an example of the eleventh manufacturing step in cutting a semiconductor wafer.
[0020] Figure 14 shows an example of the twelfth manufacturing step in dicing a semiconductor wafer.
[0021] Figure 15 shows an example of an IC device.
[0022] Figure 16 shows an example of a method for cutting semiconductor wafers.
[0023] Figure 17 shows another example of a method for cutting semiconductor wafers. Detailed Implementation
[0024] This specification generally relates to integrated circuit manufacturing systems, and more specifically, to manufacturing processes for dicing integrated circuit dies. Manufacturing processes typically involve fabricating circuitry on a semiconductor wafer via any of a variety of integrated circuit (IC) manufacturing processes. Such processes typically involve dicing IC dies, which refers to separating IC dies from each other from the semiconductor wafer. Dicing can be performed in any of a variety of ways, including etching processes that can be performed similarly to etching during the fabrication of the circuitry therein. To perform the etching for dicing, the semiconductor material forming the semiconductor wafer is typically ground down in a back-side grinding process to remove a considerable thickness of semiconductor material.
[0025] Conventional manufacturing processes may include back-side polishing of semiconductor wafers. Back-side polishing processes typically involve providing a back-side polishing tape over the fabricated circuitry (e.g., on a surface opposite the back-side polishing surface) to manipulate the semiconductor wafer for the back-side polishing process. However, etching processes typically require a photoresist layer over the fabricated circuitry to facilitate etching of the semiconductor wafer without damaging the fabricated circuitry. Therefore, a back-side polishing tape can be applied after photoresist deposition and thus after the photoresist has been deposited on the fabricated circuitry.
[0026] Following back-side grinding in conventional manufacturing processes, the thinned semiconductor wafer can be attached to a dicing tape and / or a die attachment film (DAF), such as for a quad flat no-lead (QFN) package. In typical conventional manufacturing processes, after attaching the thinned semiconductor wafer, it can then be etched (e.g., plasma etching) to cut the fabricated circuitry, thereby providing discrete IC dies. However, in this conventional process, the etching (e.g., plasma etching) used to cut the fabricated circuitry can damage components essential to the manufacturing process.
[0027] As an example, etching a back-polished semiconductor wafer after it has been attached to a dicing tape can damage the dicing tape, for example, causing it to break when stretched for cutting single IC dies. As another example, to attach a semiconductor wafer to a DAF (e.g., on a 2:1 tape comprising the DAF and the dicing tape), the manufacturing process may include a heated environment to allow the DAF to adhere to the semiconductor wafer. However, as described above, the semiconductor wafer may have photoresist deposited over the fabricated circuitry and under the back-polished tape during this process. The heat generated by the semiconductor wafer attaching to the DAF can cause bubbles to form in the photoresist, thus potentially damaging the fabricated circuitry during subsequent dicing etching (e.g., plasma etching).
[0028] To mitigate breakage and / or damage to fabricated circuitry during dicing, the manufacturing process described herein incorporates a dicing-before-grinding (DBG) operation, in which the semiconductor wafer is plasma-etched prior to back-side grinding. In the manufacturing process described herein, photoresist is removed after plasma etching of the semiconductor wafer to dicing it into separate IC dies via back-side grinding of the etched wafer. The separated IC dies are then bonded to a DAF in a heated environment. Therefore, the absence of photoresist in the DAF bonding step mitigates damage to the fabricated circuitry due to the absence of photoresist that can form bubbles.
[0029] Furthermore, because the separated IC dies adhere to the DAF and dicing tape (e.g., 2:1 tape) after plasma etching, damage from plasma etching of the semiconductor wafer is prevented. The manufacturing process described herein may also perform a second plasma etching to etch through the DAF for dicing the separated IC dies. The manufacturing process can therefore implement a cover plate covering the DAF and dicing tape in a wafer exclusion zone to mitigate damage to the dicing tape. Consequently, damage from dicing tape breakage due to stretching is also mitigated.
[0030] Figure 1 is an example block diagram of an integrated circuit (IC) dicing system 100. The IC dicing system 100 can be implemented in any of a variety of manufacturing applications, for example, after an integrated circuit is fabricated on a semiconductor wafer (shown at 102). The semiconductor wafer 102 may include a semiconductor (e.g., silicon) substrate, on which circuitry can be fabricated on one or more layers above the substrate.
[0031] As described in more detail herein, the fabricated circuit may be contained in one or more oxide layers above and / or within one or more fabricated circuit layers. The IC dicing system 100 may be part of an overall manufacturing system for manufacturing IC devices, and in particular provides dicing of semiconductor wafers to provide individually separated IC dies. As described herein, the terms “manufacturing process” and “dicing process” refer to the portion of the overall manufacturing process provided by the IC dicing system 100, and are used interchangeably herein.
[0032] In the example of Figure 1, a semiconductor wafer 102 is provided to a dicing process system 104. The dicing process system 104 can be implemented to dic and dice the fabricated circuitry on the semiconductor wafer 102 into a plurality of IC dies 106. The diced IC dies 106 can then be packaged into IC chips for consumer distribution. As an example, the IC chip package may include attaching the IC dies to a lead frame (e.g., via a die attachment film (DAF)), placing the IC dies in a corresponding package, and filling the package with molding material.
[0033] The dicing process system 104 includes a plasma etching tool 108, a back-side grinding tool 110, and a wafer handling apparatus 112. The wafer handling apparatus 112 can refer to any of a variety of machines, devices, and apparatuses capable of moving, manipulating, and / or manipulating the semiconductor wafer 102. As described herein, the plasma etching tool 108 can be configured to perform a first plasma etching and a second plasma etching at different stages of the dicing process. The back-side grinding tool 110 is configured to perform back-side grinding of the semiconductor wafer 102. As described herein, the first plasma etching can be provided by the plasma etching tool 108 prior to back-side grinding provided by the back-side grinding tool 110. In this manner, the manufacturing process described herein implements a dicing before grinding (DBG) procedure.
[0034] In the DBG manufacturing process described herein, photoresist is applied to the fabricated circuitry of the semiconductor wafer 102 before a first plasma etching is performed via a plasma etching tool 108 to cleave the fabricated circuitry. The first plasma etching may be performed through a portion (less than all) of the thickness of the semiconductor wafer 102. The photoresist can then be removed, and a back-side polishing tool 110 may subsequently perform a back-side polishing process on the etched semiconductor wafer to provide separate IC dies, each containing one of the fabricated circuitry on the substrate. The separated IC dies are then attached to the DAF via a thermal application (e.g., via wafer handling equipment 112). Therefore, because the photoresist is removed after the plasma etching of the semiconductor wafer and before the separated IC dies are attached to the DAF, the formation of bubbles in the photoresist prior to etching can be prevented in the cleaving process described herein.
[0035] Furthermore, as described in more detail herein, damage to the dicing tape caused by plasma etching can be mitigated. For example, the manufacturing process described herein may also perform a second plasma etching via plasma etching tool 108 to etch the dicing tape through the DAF for separation of the IC die. The manufacturing process can thus implement a cover plate covering the DAF and the dicing tape in a wafer exclusion zone to mitigate damage to the dicing tape. Consequently, damage that could result from dicing tape breakage due to stretching is also mitigated.
[0036] Figure 2 is an example diagram of a semiconductor wafer 200. The semiconductor wafer 200 may correspond to the semiconductor wafer 102 in the example of Figure 1 and can therefore be provided to a dicing process system 104. The semiconductor wafer 200 can be implemented to manufacture any of a variety of IC circuit devices (e.g., in a quad flat no-lead (QFN) package). The semiconductor wafer 200 is shown in cross-sectional view in the example of Figure 2 to show the relative positions of the layers. The semiconductor wafer 200 is shown by way of example and is not intended to be drawn to scale.
[0037] Semiconductor wafer 200 includes a substrate 202 and a plurality of fabricated circuits 204 fabricated on the substrate 202. Each fabricated circuit 204 may correspond to a circuit that can be included in a corresponding IC device after the manufacturing process is completed. As an example, and as described in more detail herein, each fabricated circuit 204 may include one or more layers of oxide material formed on the exposed surface of the fabricated circuit 204.
[0038] Figures 3 to 14 illustrate the manufacturing steps for dicing a semiconductor wafer 200 in the examples described herein. Therefore, the same reference numerals as those provided in Figure 2 are used in the examples of Figures 3 to 14, and Figure 2 is referenced in the following examples of Figures 3 to 14. The manufacturing steps described in the examples of Figures 3 to 14 can be implemented, for example, by the dicing process system 104 in the example of Figure 1.
[0039] Figure 3 illustrates an example of the first manufacturing step 300. In the first manufacturing step 300, a photoresist layer 302 is formed over each of the manufacturing circuits 204. In the example of Figure 3, the photoresist layer 302 is shown as individual photoresist portions formed over each of the individual manufacturing circuits 204, such that the periphery of each portion of the photoresist layer 302 is substantially aligned with the periphery of the corresponding one in the manufacturing circuit 204.
[0040] Figure 4 illustrates an example of the second manufacturing step 400. In the second manufacturing step 400, a first plasma etching (e.g., via a plasma etching tool 108) is provided on the semiconductor wafer 200, typically manifested at 402. Specifically, the first plasma etching 402 is provided on the photoresist layer 302 and on the portion of the substrate 202 between each of the fabricated circuits 204. In the example of Figure 4, the first plasma etching 402 is manifested as a partial etching through the thickness of the substrate 202, and thus through a thickness less than the entire thickness of the substrate 202 / semiconductor wafer 200.
[0041] The second manufacturing step 400 thus involves cutting the manufactured circuit 204, which occurs prior to back-side grinding performed by the back-side grinding tool 110. Therefore, the manufacturing process described herein embodies DBG manufacturing technology.
[0042] Figure 5 illustrates an example of the third manufacturing step 500. In the third manufacturing step 500, the photoresist layer 302 is removed. At this step 500, because the photoresist material of the photoresist layer 302 has been removed, there is no subsequent plasma etching of the photoresist, which could cause damage to the fabricated circuit 204 beneath the photoresist layer 302. In other words, because the photoresist layer 302 is removed at the third manufacturing step 500 before the semiconductor wafer 200 is bonded to the DAF, bubbles cannot form in the photoresist material of the photoresist layer 302 in response to the heated environment that promotes the bonding of the semiconductor material to the DAF. Therefore, by implementing the DBG manufacturing technique in which the first plasma etching 402 of the second manufacturing step 402 occurs before the semiconductor wafer 200 is bonded to the DAF, damage to the fabricated circuit 204 can be mitigated.
[0043] Figure 6 illustrates an example of a fourth manufacturing step 600. In this step, a flexible material 602 is provided over the fabricated circuitry 204 (e.g., via wafer handling apparatus 112). The flexible material 602 may correspond to any of a variety of elastically deformable materials that can be disposed over the fabricated circuitry 204 and at least a portion of the depth of partial etching between the fabricated circuitry 204. As another example, the flexible material 602 may be non-adhesive so that it can be completely removed from the semiconductor wafer 200 without leaving residue on the substrate material of the fabricated circuitry 204 and / or the substrate 202. Examples of such flexible materials include back-side polishing tape, edge-gauge tape (EGT), or any of a variety of similar types of materials.
[0044] Figure 7 illustrates an example of the fifth manufacturing step 700. In the fifth manufacturing step 700, the semiconductor wafer 200 is back-ground using a back-ground polishing tool 110. As an example, the wafer handling apparatus 112 may be configured to manipulate / fix the semiconductor wafer 200 via a flexible material 602 to allow the back-ground polishing tool 110 to access the substrate 202 opposite to the flexible material 602 and the fabricated circuitry 204. Thus, the back-ground polishing tool 110 can completely back-ground a continuous portion of the substrate 202 to provide separated IC dies 702. Each separated IC die 702 includes one of the fabricated circuitry 204 formed on the substrate 704 corresponding to the remaining portion of the substrate 202. Fixing the semiconductor wafer 200 by the flexible material 602 allows the back-ground polishing tool 110 to separate the IC dies 702 while maintaining the position of the separated IC dies relative to each other.
[0045] Figure 8 illustrates an example of a sixth manufacturing step 800. In this step, the DAF 802 is bonded to the substrate 704 of the separated IC die 702. A flexible material 602 facilitates the bond of the substrate 704 of the separated IC die 702 to the DAF 802 in a controlled and coordinated manner. In the example of Figure 8, the DAF 802 may be provided as a 2:1 strip containing a dicing strip 804 coupled to the surface of the DAF 802 opposite to the substrate 704. However, alternatively, the DAF 802 and the dicing strip 804 may be provided separately. In the example of Figure 8, the DAF 802 and the dicing strip 804 (e.g., a 2:1 strip) are shown secured by a ring structure 806 (e.g., a stainless steel ring surrounding the periphery of the DAF 802 and the dicing strip 804). The area between the ring structure 806 and the separated IC die 702 at the edge of the array of IC dies 702 on the DAF 802 may correspond to the wafer exclusion zone 808, where the DAF 802 is exposed.
[0046] As described above, the substrate 704 can be bonded to the separated IC die 702 in a heated environment (e.g., approximately 50°C to approximately 70°C). However, because plasma etching is performed in the second manufacturing step 400 and the photoresist layer 302 is removed in the third manufacturing step 500, there is no possibility that bubbles formed in the photoresist material could adversely affect the fabricated circuit 204 during plasma etching, unlike the possibility in conventional dicing processes.
[0047] Figure 9 illustrates an example of the seventh manufacturing step 900. In the seventh manufacturing step 900, flexible material 602 is removed from the separated IC die 702. As described above, the flexible material 602 may be non-adhesive so that it can be completely removed from the separated IC die 702 without leaving any residue. Therefore, the separated IC die 702 can be further processed without difficult and / or expensive chemical cleaning processes to remove the flexible material 602.
[0048] Figure 10 illustrates an example of the eighth manufacturing step 1000. In the eighth manufacturing step 1000, a cover plate 1002 is provided over the wafer restricted area 808. The cover plate 1002 may thus correspond to the cover ring structure 806 and another ring of the wafer restricted area 808 (with circular, square, rectangular or other shaped holes), while exposing the portions of the separated IC die 702 and DAF 802 between the separated IC die 702.
[0049] Figure 11 illustrates an example of the ninth manufacturing step 1100. In the ninth manufacturing step 1100, a second plasma etching (e.g., via a plasma etching tool 108) is provided on the separated IC dies 702, typically present at 1102. Specifically, the second plasma etching 1102 is provided on the fabricated circuit 204 and on the exposed portions of the DAF 802 between the separated IC dies 702. The second plasma etching 1102 etches the exposed portions of the DAF 802 between the separated IC dies 702, thereby exposing the dicing strip 804 between the separated IC dies 702.
[0050] As described above, the cover plate 1002 covers the wafer restricted area 808 while exposing the portion of the separated IC die 702 and DAF 802 between the separated IC die 702. Therefore, the second plasma etching 1102 can etch the DAF 802 between the separated IC dies 702, leaving the portion of DAF 802 within the wafer restricted area 808 unetched and intact. Thus, the cover plate 1002 protects the dicing tape 804 beneath the portion of DAF 802 within the wafer restricted area 808 from damage. Therefore, when the dicing tape 804 is stretched, breakage of the dicing tape 804 can be mitigated.
[0051] Furthermore, as described above, each of the fabricated circuits 204 may comprise one or more layers of oxide material formed on the exposed surface of the fabricated circuit 204. The one or more oxide material layers may, for example, be part of a typical manufacturing process of the fabricated circuit 204. However, the second plasma etching 1102 may possess a plasma material having chemical properties that the one or more oxide layers can resist.
[0052] For example, the plasma material can be formed by a chemical process that significantly affects the difference in etch rate between DAF 802 and one or more oxide layers, where one or more oxide layers are etched significantly more slowly than DAF 802. Therefore, one or more oxide layers can act as a mask over fabricated circuit 204 to protect fabricated circuit 204 from damage caused by the second plasma etching 1102, while allowing exposed portions of DAF 802 to be etched away substantially completely. Therefore, the fabrication process described herein does not require the application of additional photoresist or a mask over fabricated circuit 204 to protect fabricated circuit 204 from the effects of the second plasma etching 1102.
[0053] Figure 12 shows an example of the tenth manufacturing step 1200. In the tenth manufacturing step 1200, the cover plate 1002 is removed. Thus, the portion of the DAF 802 in the wafer restricted area 808 and the ring structure 806, which had been protected by the cover plate 1002 from the effects of the second plasma etching 1102, are exposed again.
[0054] Figure 13 illustrates an example of the eleventh manufacturing step 1300. In the eleventh manufacturing step 1300, the dicing tape 804 is stretched to increase the spacing between the separated IC dies 702. Therefore, the separated IC dies 702 can be individually diced into individual IC dies 702 that can be mounted on a lead frame and packaged. As described above, the cover plate 1002 protects the dicing tape 804 from damage caused by the second plasma etching 1102. Therefore, the risk of breakage of the dicing tape 804 during stretching in the eleventh manufacturing step 1300 is mitigated.
[0055] Figure 14 illustrates an example of the twelfth and final manufacturing step 1400. In the twelfth manufacturing step 1400, the separated IC dies 702 are removed from the stretched dicing tape 804 and diced. As an example, because the portion of the DAF 802 in the wafer restricted area 808 is not etched by the second plasma etching 1102, the separated IC dies 702 at the edge of the array of IC dies 702 and therefore adjacent to the wafer restricted area 808 may not be able to be removed from the portion of the DAF 802 in the wafer restricted area 808. Therefore, the separated IC dies 702 at the edge of the array of IC dies 702 may be discarded based on the inability to diced the corresponding IC dies 702. Alternatively, instead of discarding the separated IC dies 702 at the edge of the array, they may be further processed to remove associated processing material. For example, additional die attachment film 802 extending from the side surface of IC die 702 and / or a cleaving strip 804 on the remaining die attachment film on the bottom surface of the separated IC die 702 at the edge of the array can be removed to further process the associated IC die 702.
[0056] Figure 15 illustrates an example of an IC device 1500. The IC device 1500 includes an IC die 1502, which may correspond to one of separate IC dies 702 provided from the manufacturing process described herein, and is therefore diced from a semiconductor wafer 200. The IC die 1502 thus includes fabricated circuitry 1504 on a substrate 1506. The IC die 1502 is coupled to a lead frame 1508 via a DAF 1510. As an example, the IC device 1500 may be arranged as a QFN device such that the lead frame 1508 includes conductive pads that are conductively coupled to contacts on a printed circuit board (PCB). The IC die 1502 (e.g., and the DAF 1510) may be surrounded by a package comprising a molding material 1512 having an outer surface 1514. Alternatively, the outer surface 1514 may be formed by a plastic outer sheath of the IC device 1500, in which case the molding material 1512 fills the internal volume of the plastic outer sheath 1514.
[0057] As described above, the fabricated circuit 1504 may include one or more layers of oxide material formed on the exposed surface of the fabricated circuit 1504. As also described above, the plasma material used for the second plasma etching 1102 may have chemical properties that are resistant to one or more oxide layers. Therefore, the fabricated circuit 1504 can be protected from the effects of the second plasma etching 1102 by one or more oxide material layers. However, the one or more oxide layers on the fabricated circuit 1504 may indicate the occurrence of the second plasma etching 1102 based on identifiable degradation of the oxide material.
[0058] In the example of Figure 15, the surface of one or more oxide layers (not shown) on fabricated circuit 1504 may exhibit signs of plasma etching, as shown in the magnified portion 1516 of fabricated circuit 1504. The surface of one or more oxide layers on fabricated circuit 1504 may appear to have a rough surface (for example), but the surface may actually exhibit any of a variety of other indications of degradation produced by the plasma etching process. This indication of plasma etching of one or more oxide layers on fabricated circuit 1504 (e.g., based on scanning electron microscopy (SEM) inspection) can provide an indication of whether IC device 1500 has been cut according to the manufacturing process described herein.
[0059] In view of the foregoing structural and functional features, the methods according to various aspects of the invention will be better understood with reference to Figures 16 and 17. Although the methods in Figures 16 and 17 are shown and described as being performed sequentially for simplicity of explanation, it should be understood and appreciated that the invention is not limited to the order in which they are described, as some aspects may occur in a different order and / or simultaneously with other aspects shown and described herein, according to the invention. Furthermore, not all of the described features may be necessary for implementing the methods according to one aspect of the invention.
[0060] Figure 16 illustrates another example of a method 1600 for dicing a semiconductor wafer (e.g., semiconductor wafer 102) comprising multiple fabricated circuits (e.g., fabricated circuit 204). At 1602, plasma etching (e.g., first plasma etching 402) is performed through a portion of the thickness of the substrate (e.g., substrate 202) between the fabricated circuits of the semiconductor wafer to provide an etched semiconductor wafer. At 1604, a flexible material (e.g., flexible material 602) is provided on the fabricated circuits. At 1606, the etched semiconductor wafer is back-side ground to separate the fabricated circuits, thereby providing separated IC dies (e.g., separated IC dies 702). Each of the separated IC dies may contain a corresponding one of the fabricated circuits. At 1608, the separated IC dies are placed on a DAF (e.g., DAF 802). At 1610, the flexible material is removed.
[0061] Figure 17 illustrates an example of a method 1700 for dicing a semiconductor wafer (e.g., semiconductor wafer 102) comprising multiple fabricated circuits (e.g., fabricated circuit 204). At 1702, a first plasma etching (e.g., first plasma etching 402) is performed through a portion of the thickness of the substrate (e.g., substrate 202) between the fabricated circuits of the semiconductor wafer to provide an etched semiconductor wafer. At 1704, the etched semiconductor wafer is back-side ground to separate the fabricated circuits, thereby providing separate IC dies (e.g., separate IC dies 702). Each of the separate IC dies may contain a corresponding one of the fabricated circuits. At 1706, the separate IC dies are disposed on a DAF (e.g., DAF 802) arranged between the separate IC dies and a dicing strip (e.g., dicing strip 804). At 1708, a second plasma etching (e.g., second plasma etching 1102) is performed on the separate IC dies to etch through the DAF between each of the separate IC dies. At 1710, the dicing tape is stretched to cut individual IC dies.
[0062] In this specification, the term "coupled" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is directly coupled to device B; or (b) in a second instance, if intermediate component C does not substantially alter the functional relationship between device A and device B, then device A is indirectly coupled to device B through intermediate component C, and therefore device B is controlled by device A via the control signal generated by device A.
[0063] Furthermore, in this specification, a device "configured" to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof. Additionally, circuits or devices described herein as containing certain components may actually be configured to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually contain only semiconductor elements within a single physical device (e.g., a semiconductor wafer and / or integrated circuit (IC) package) and may be configured to be coupled to at least some of the passive elements and / or sources during or after manufacturing, for example, by an end user and / or a third party, to form the described structure.
[0064] Modifications may be made to the described examples, and other examples may be made within the scope of the claims.
Claims
1. A method for dicing a semiconductor wafer comprising a plurality of fabricated circuits, the method comprising: Plasma etching is provided through a portion of the thickness of the substrate between the fabricated circuits of the semiconductor wafer to provide an etched semiconductor wafer; A flexible material is provided on the manufactured circuit; The etched semiconductor wafer is back-grinded to separate the fabricated circuitry, thereby providing separated integrated circuit (IC) dies, each of which includes a corresponding one of the fabricated circuitry. The separated IC die is placed on the die attachment film (DAF); and the flexible material is removed.
2. The method of claim 1, wherein providing the plasma etching comprises: A photoresist layer is formed over each of the manufactured circuits; The plasma etching is provided to remove semiconductor material from the substrate of the semiconductor wafer between each of the fabricated circuits to a depth less than the entire thickness of the substrate; And remove the photoresist layer.
3. The method of claim 1, wherein disposing the separate IC die on the DAF comprises coupling the separate IC die on the DAF to a first surface of the separate IC die, the first surface being opposite to a second surface of the separate IC die on which the flexible material is disposed.
4. The method of claim 3, wherein placing the separated IC die on the DAF further comprises placing the separated IC die on the DAF disposed between the first surface of the separated IC die and the dicing strip.
5. The method of claim 1, wherein the plasma etching is a first plasma etching, the method further comprising providing a second plasma etching on the separated IC dies after removing the flexible material to etch the DAF through the space between each of the separated IC dies.
6. The method of claim 5, wherein the fabricated circuit is fabricated from an oxide material over the fabricated circuit on the semiconductor wafer, wherein providing the second plasma etching comprises providing plasma material for the second plasma etching over the fabricated circuit and over the DAF located between each of the separated IC dies.
7. The method of claim 5, wherein providing the second plasma etching on the separated IC die comprises: A cover plate is provided above the wafer exclusion zone corresponding to the periphery of the DAF, the cover plate at least partially surrounding the separated IC die; The second plasma etching is performed on the separated IC die and the cover plate to protect the DAF in the wafer exclusion zone.
8. The method of claim 7, wherein the DAF is disposed on the cutting tape, the method further comprising: Remove the cover plate; And stretch the cutting strip to cut the separated IC die.
9. An integrated circuit (IC) dicing system, comprising: A plasma etching tool configured to provide a first plasma etching through a portion of the thickness of a substrate between fabricated circuits on a semiconductor wafer, to provide an etched semiconductor wafer; A back-side polishing tool configured to back-polish the etched semiconductor wafer to separate the manufactured circuitry, thereby providing separated IC dies, each of the separated IC dies including a corresponding one of the manufactured circuitry; and a wafer handling apparatus configured to attach the separated IC dies to a die attachment film (DAF) disposed between the separated IC dies and a dicing tape, the plasma etching tool further configured to provide a second plasma etching through the DAF between the separated IC dies.
10. The system of claim 9, wherein the wafer handling apparatus is further configured to form a photoresist layer over each of the fabricated circuits, such that the plasma etching tool provides the first plasma etching over the photoresist layer and an exposed portion of the semiconductor wafer located between the fabricated circuits of the semiconductor wafer, and is further configured to remove the photoresist layer after the first plasma etching.
11. The system of claim 9, wherein the wafer handling apparatus is further configured to stretch the dicing tape after the second plasma etching to cut the isolated IC die.
12. The system of claim 9, wherein the wafer handling apparatus is further configured to provide a flexible material on the manufactured circuit to secure the manufactured circuit, wherein the back-grinding tool is configured to back-grind the etched semiconductor wafer to separate the IC die, thereby providing the separated IC die while the manufactured circuit is secured by the flexible material.
13. The system of claim 12, wherein the wafer handling apparatus is further configured to attach the separated IC die on the DAF to a first surface of the separated IC die, the first surface being opposite to a second surface of the separated IC die to which the flexible material is applied.
14. The system of claim 9, wherein the fabricated circuit is fabricated from an oxide material over the fabricated circuit on the semiconductor wafer, wherein the plasma etching tool is configured to provide the second plasma etching over the fabricated circuit and over the DAF located between each of the separate IC dies.
15. The system of claim 9, wherein the wafer handling apparatus is configured to provide a cover plate over a wafer exclusion zone corresponding to the periphery of the DAF, the cover plate at least partially surrounding the separated IC die, wherein the plasma etching tool is configured to provide the second plasma etching on the separated IC die and the cover plate to protect the DAF in the wafer exclusion zone.
16. A method for dicing a semiconductor wafer comprising a plurality of fabricated circuits, the method comprising: A first plasma etching is provided through a portion of the thickness of the substrate between the fabricated circuits of the semiconductor wafer to provide an etched semiconductor wafer; The etched semiconductor wafer is back-grinded to separate the fabricated circuitry, thereby providing separated integrated circuit (IC) dies, each of which includes a corresponding one of the fabricated circuitry. The separated IC dies are disposed on a die attachment film (DAF) arranged between the separated IC dies and a dicing tape; a second plasma etching is performed on the separated IC dies to etch through the DAF between each of the separated IC dies; and the dicing tape is stretched to cut the separated IC dies individually.
17. The method of claim 16, wherein providing the first plasma etching comprises: A photoresist layer is formed over each of the manufactured circuits; The first plasma etching is provided to remove semiconductor material between each of the semiconductor wafers in the fabricated circuit to a depth less than the thickness of the semiconductor wafer; And remove the photoresist layer.
18. The method of claim 16, further comprising providing a flexible material on the fabricated circuit prior to back-grinding the etched semiconductor wafer, wherein disposing of the discrete IC die on the DAF comprises coupling the discrete IC die on the DAF to a first surface of the discrete IC die, the first surface being opposite a second surface of the discrete IC die to which the flexible material is disposed, wherein disposing of the discrete IC die on the DAF further comprises disposing the discrete IC die on the DAF disposed between the first surface of the discrete IC die and the dicing strip.
19. The method of claim 16, wherein the fabricated circuit is fabricated from an oxide material over the fabricated circuit on the semiconductor wafer, wherein providing the second plasma etching comprises providing plasma material for the second plasma etching over the fabricated circuit and over the DAF located between each of the separated IC dies.
20. The method of claim 16, wherein providing the second plasma etching on the separated IC die comprises: A cover plate is provided above the wafer exclusion zone corresponding to the periphery of the DAF, the cover plate at least partially surrounding the separated IC die; The second plasma etching is performed on the separated IC die and the cover plate to protect the DAF in the wafer exclusion zone.
21. An integrated circuit (IC) device, comprising: IC die, comprising fabricated circuitry formed on a substrate, the fabricated circuitry including an oxide material layer on an exposed surface of the fabricated circuitry, the oxide material layer exhibiting degradation caused by plasma etching; And the package, which essentially surrounds the IC die.
22. The IC device of claim 21, further comprising: A bare die attachment film (DAF) is coupled to a first surface of the substrate opposite to a second surface on which the fabricated circuit is formed. and lead frame, which is coupled to the DAF.