Semiconductor device and preparation method thereof
By introducing a high-melting-point penetration barrier layer beneath the ohmic metal layer, the penetration of components during high-temperature annealing is prevented, thus solving the problems of ohmic contact instability and reduced withstand voltage, and improving the stability and reliability of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUNAN SANAN SEMICON CO LTD
- Filing Date
- 2024-10-11
- Publication Date
- 2026-05-01
AI Technical Summary
In existing high-temperature annealing processes, when forming ohmic contacts, the components of the ohmic metal layer can easily penetrate into the dielectric layer and epitaxial layer, resulting in a shorter gate-source distance in semiconductor devices, reduced voltage withstand capability and reliability, and especially causing gate-source short circuit problems in small-sized devices.
A penetration barrier layer is introduced beneath the ohmic metal layer. The material is selected so that its melting point is higher than the annealing temperature to prevent the constituent components of the ohmic metal layer from penetrating into the dielectric layer. The ohmic contact area is defined by photolithography and the non-contact area is etched to form a stable ohmic contact.
It effectively prevents the infiltration of ohmic metal layer components, maintains the stability of the gate-source distance and gate-drain distance of the device, improves the stability and withstand voltage of ohmic contacts, avoids source-drain short circuits, and enhances the reliability and process stability of the device.
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Figure CN121969211A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology
[0002] With the rapid development of technology, semiconductor devices such as high electron mobility transistors (HEMTs) have been widely used in electronic devices such as mobile phones and tablets. Among them, HEMTs such as AlGaN / GaN are considered indispensable chip types for higher frequency and power communication systems and high-voltage, high-power-density power electronics. During the fabrication of semiconductor devices, non-rectified contacts, i.e., ohmic contacts, can be formed when the metal contacts the epitaxial layer.
[0003] Ohmic contacts are a key technology in semiconductor devices, and low-resistance, high-stability ohmic contacts are crucial for their performance and reliability. However, with the miniaturization of semiconductor devices, existing ohmic contact formation processes based on high-temperature annealing to reduce resistance are prone to gate-source short circuits, compromising the withstand voltage and reliability of semiconductor devices. Therefore, improving the performance of ohmic contacts has become an important research topic. Summary of the Invention
[0004] To address the existing technical problems, this application provides a semiconductor device with high ohmic contact stability and a method for manufacturing the same.
[0005] According to a first aspect of the embodiments of this application, a semiconductor device is provided, including an epitaxial layer, a dielectric layer, a penetration barrier layer, and an ohmic metal layer;
[0006] The epitaxial layer and the dielectric layer are stacked together. The penetration barrier layer is disposed on the ohmic contact region of the dielectric layer. The ohmic metal layer passes through the penetration barrier layer and the dielectric layer in sequence and forms an ohmic contact with the epitaxial layer.
[0007] The penetration barrier layer is used to prevent the constituent components of the ohmic metal layer from penetrating into the dielectric layer.
[0008] Optionally, the penetration barrier layer is used to prevent the constituent components from penetrating into the dielectric layer when the ohmic metal layer is undergoing an annealing process;
[0009] The melting point of the penetration barrier layer is greater than the annealing temperature of the annealing process; and / or, when the ohmic metal layer is in the annealing process, the penetration barrier layer does not react with the dielectric layer.
[0010] Optionally, the ohmic metal layer includes an ohmic contact electrode, the ohmic contact electrode including a first portion extending on the penetration barrier layer, and a second portion that sequentially passes through the penetration barrier layer and the dielectric layer to form an ohmic contact with the epitaxial layer;
[0011] The different types of ohmic contact electrodes are disconnected from the penetration barrier layer through which they pass.
[0012] Optionally, the ohmic metal layer further includes an ohmic metal field plate;
[0013] The penetration barrier layer beneath the ohmic metal field plate is disconnected from the penetration barrier layer through which the ohmic contact electrode passes.
[0014] Optionally, the material forming the penetration barrier layer is a conductive compound with metallic properties.
[0015] Optionally, the semiconductor device further includes a capping dielectric layer covering the penetration barrier layer.
[0016] According to a second aspect of the embodiments of this application, a method for fabricating a semiconductor device is provided, comprising:
[0017] A dielectric layer is formed on the epitaxial layer;
[0018] A penetration barrier layer is formed on the ohmic contact area of the dielectric layer, the penetration barrier layer being used to prevent the constituent components of the ohmic metal layer from penetrating into the dielectric layer;
[0019] An ohmic metal layer is formed on the penetration barrier layer, passing sequentially through the penetration barrier layer and the dielectric layer and contacting the epitaxial layer.
[0020] Optionally, forming a penetration barrier layer on the ohmic contact region of the dielectric layer includes:
[0021] A penetration barrier material is deposited on the surface of the second dielectric layer to form a penetration barrier layer;
[0022] Based on photolithography, the ohmic contact region and non-ohmic contact region of the dielectric layer are defined.
[0023] The penetration barrier layer is etched to remove the penetration barrier layer located on the non-ohmic contact area.
[0024] Optionally, before defining the ohmic contact region and non-ohmic contact region of the dielectric layer based on the photolithography process, the method further includes:
[0025] A capping medium material is deposited on the penetration barrier layer to form a capping medium layer;
[0026] Optionally, forming an ohmic metal layer on the penetration barrier layer that sequentially passes through the penetration barrier layer and the dielectric layer and contacts the epitaxial layer includes:
[0027] The capping layer, the penetration barrier layer, and the dielectric layer are etched sequentially to form an ohmic contact trench that penetrates the capping dielectric layer, the penetration barrier layer, and the dielectric layer and extends to the surface of the epitaxial layer or the epitaxial layer.
[0028] An ohmic metal material is deposited on the cap medium layer and in the ohmic contact trench to form an ohmic metal film.
[0029] Optionally, etching the penetration barrier layer to remove the penetration barrier layer located on the non-ohmic contact region includes:
[0030] The ohmic metal film, the capping dielectric layer, and the penetration barrier layer in the non-ohmic contact area are etched away in sequence to form an ohmic metal layer in which a first portion extends on the surface of the capping dielectric layer and a second portion is located in the ohmic contact trench and forms an ohmic contact with the epitaxial layer.
[0031] As can be seen from the above, the semiconductor device provided in this application introduces a penetration barrier layer below the ohmic metal layer to prevent the constituent components of the ohmic metal layer from penetrating into the dielectric layer. This prevents the constituent components of the ohmic metal layer from penetrating into the dielectric layer during the high-temperature annealing process, thus preventing the formation of a low-resistivity region in the epitaxial layer below the dielectric layer. Consequently, the actual gate-source distance and gate-drain distance formed in the semiconductor device do not decrease compared to the corresponding preset values, or the decrease is significantly reduced. Therefore, the semiconductor device provided in this application has high ohmic contact stability and excellent withstand voltage and reliability. The fabrication method provided in this application can achieve the same technical effects as the semiconductor device provided in this application, and will not be repeated here. Attached Figure Description
[0032] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:
[0033] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided according to some embodiments of this application;
[0034] Figure 2 This is a schematic flowchart of the preparation method provided according to some embodiments of this application;
[0035] Figures 3a to 3f This is a schematic cross-sectional view of the semiconductor structure formed in each method step according to the preparation method provided in the embodiments of this application;
[0036] Figure 4 This is a schematic diagram of the process for forming a dielectric layer on an epitaxial layer. Detailed Implementation
[0037] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.
[0038] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. The term "located on" should be understood to mean that, when describing the structure of a device, referring to a layer or region as being "above" or "over" another layer or region can mean being directly above another layer or region, or including other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.
[0039] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.
[0040] In this application, the semiconductor device may be, but is not limited to, a high electron mobility transistor, such as an AlGaN / GaN high electron mobility transistor (GaN HEMT). In a high electron mobility transistor, the source and drain electrodes are interconnected with a 2-DEG (Two-dimensional electron gas) to form a non-rectified contact, i.e., an ohmic contact. Annealing the various stacked metal layers in contact with the epitaxial layer at a suitable temperature to form an ohmic contact with low contact resistance, high adhesion, and resistance to degradation is key to improving device performance. Currently, the widely used ohmic contact technology utilizes a Ti (titanium) / Al (aluminum) stacked metal layer to prepare ohmic contacts through a high-temperature rapid annealing process. In this process, the Ti metal in the stacked metal layer can react with the N element in the AlGaN layer of the epitaxial layer at high temperatures to generate low-resistance TiN.
[0041] However, the inventors of this application have discovered that during the high-temperature annealing of Ti / Al multilayer metal layers to form low ohmic contact resistance, a large number of donor defects such as N vacancies and lattice cracks appear in the AlGaN layer. This allows the molten Al or TiAl alloy at high temperatures to penetrate into the underlying dielectric layer, thereby expanding the ohmic contact area. Specifically, for cases where Ti, Al, Au, and / or Ni layers are used as the ohmic metal layer, the high-temperature annealing temperature is generally between 800-950°C. At this temperature, at least some of the constituent components of the ohmic metal layer (such as Al and / or TiAl alloy) not only penetrate downwards into the AlGaN layer to increase the contact with the 2-DEG, but also penetrate into the underlying dielectric layer and further into the epitaxial layer below the underlying dielectric layer, causing the low-resistance region to expand outwards from the predetermined ohmic contact region. This expansion of the low-resistance region not only shortens the gate-source distance (Lgs) and gate-drain distance (Lgd) of gallium nitride (GaN) HEMTs, but also causes changes in the position of the drain-source field plates, leading to a deterioration in the breakdown voltage and dynamic characteristics of GaN HEMTs. Especially for small-size GaN HEMTs used in low-voltage applications, the shortened gate-source distance easily causes TDDB (Time Dependent Dielectric Breakdown) type gate-source short circuits, resulting in device failure.
[0042] Based on the problems discovered by the inventors during the research process, this application provides a semiconductor device and its fabrication method to solve the problems of poor ohmic contact stability and deterioration of device withstand voltage and stability reliability caused by the diffusion of the constituent components of the ohmic metal layer into the underlying dielectric layer during the high-temperature annealing process.
[0043] Please see Figure 1 The diagram shown is a schematic representation of a semiconductor device provided according to some embodiments of this application. In some embodiments, the semiconductor device provided in this application includes an epitaxial layer 10, a dielectric layer 20, a penetration barrier layer 30, and an ohmic metal layer 40. The epitaxial layer 10 and the dielectric layer 20 are stacked together. The penetration barrier layer 30 is disposed on the ohmic contact region of the dielectric layer 20. The ohmic metal layer 40 passes through the penetration barrier layer 30 and the dielectric layer 20 in sequence, and forms an ohmic contact with the epitaxial layer 10. The penetration barrier layer 30 is used to prevent the constituent components of the ohmic metal layer 40 from penetrating into the dielectric layer 20.
[0044] An ohmic contact refers to a situation where an ohmic metal layer 40 is in contact with an epitaxial layer 10, and a very small contact barrier is formed at the contact interface, or no contact barrier is formed at the contact interface. In other words, an ohmic contact has a low contact resistivity. Ohmic contacts can also be called non-rectifying contacts.
[0045] The dielectric layer 20 can be divided into ohmic contact regions and non-ohmic contact regions. Specifically, if an ohmic metal layer and an epitaxial layer form an ohmic contact at a first location, the ohmic contact region of the dielectric layer 20 refers to the portion of the dielectric layer 20 located above the first location, while the non-ohmic contact region of the dielectric layer 20 refers to the regions other than its ohmic contact region.
[0046] In some embodiments, "the penetration barrier layer 30 is disposed on the ohmic contact area of the dielectric layer 20" means that the penetration barrier layer 30 is only disposed on the ohmic contact area of the dielectric layer 20, while no penetration barrier layer 30 is disposed on the non-ohmic contact area of the dielectric layer 20. In other embodiments, "the penetration barrier layer 30 is disposed on the ohmic contact area of the dielectric layer 20" means that the penetration barrier layer 30 is disposed on the ohmic contact area of the dielectric layer 20, while the non-ohmic contact area of the dielectric layer 20 may or may not have a penetration barrier layer 30.
[0047] The dielectric layer 20 is disposed above the epitaxial layer 10 to expose the ohmic contact formation area of the epitaxial layer 10, i.e., the area where the first position is located, and to cover other areas of the epitaxial layer 10 except for the first position, thereby protecting the other areas of the epitaxial layer 10. The ohmic metal layer 40 is disposed above the penetration barrier layer 30, i.e., the penetration barrier layer 30 is disposed between the ohmic metal layer 40 and the dielectric layer 20. By selecting a suitable material, the penetration barrier layer 30 can prevent the constituent components of the ohmic metal layer 40 from penetrating into the dielectric layer 20 below the barrier layer 30 during the high-temperature annealing process of the ohmic metal layer 40.
[0048] The semiconductor device provided according to embodiments of this application further includes an ohmic contact trench (also called an ohmic contact channel) that sequentially penetrates the penetration barrier layer 30 and the dielectric layer 20 and extends to the surface of the epitaxial layer 10 or within the epitaxial layer 10. The ohmic contact trench is used to expose the region in the epitaxial layer where the first location for forming an ohmic contact is to be formed. A first portion of the ohmic metal layer 40 extends above the penetration barrier layer 30, and a second portion fills the ohmic contact trench to form an ohmic contact with the epitaxial layer 10 at the bottom of the ohmic contact trench.
[0049] Based on the semiconductor device provided in this application embodiment, the constituent components of its ohmic metal layer 40 do not penetrate into the dielectric layer 20, thereby preventing the formation of a low-resistivity region in the epitaxial layer 10 below the dielectric layer 20. Instead, a low-resistivity region is formed only at a first position in the epitaxial layer 10, i.e., an ohmic contact is formed only at the preset first position, and ohmic contacts are not formed on either side of the first position. This ensures that the actual gate-source distance and gate-drain distance formed in the semiconductor device do not decrease compared to the corresponding preset values, or the decrease is significantly reduced. Therefore, the semiconductor device provided in this application embodiment has high ohmic contact stability and excellent withstand voltage and reliability.
[0050] In some embodiments, the ohmic metal layer 40 can be a single metal layer or a multi-metal stacked structure composed of multiple metal layers. The forming material of the ohmic metal layer 40 has good fluidity at high temperatures (the annealing temperature corresponding to the above-described annealing process), i.e., good downward miscibility. For example, at least one of titanium, aluminum, gold, and nickel can be selected to form the ohmic metal layer 40. In some embodiments, the ohmic metal layer 40 can be a multi-metal stacked structure composed of titanium (Ti), aluminum (Al), titanium (Ti), and gold (Au) in sequence. In some embodiments, the ohmic metal layer 40 can also be a multi-metal stacked structure composed of titanium (Ti), aluminum (Al), titanium (Ti), and titanium nitride (TiN) in sequence, or a multi-metal stacked structure composed of titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au) in sequence.
[0051] In some embodiments, the penetration barrier layer 30 is formed of a material that can prevent the constituent components of the ohmic metal layer 40 from penetrating into the dielectric layer 20 during the annealing process of the ohmic metal layer 40. Specifically, the penetration barrier layer 30 can be formed of a material with a melting point higher than the annealing temperature of the ohmic metal layer 40 during the annealing process, which is typically set to 800-950°C. The annealing temperature of the ohmic metal layer 40 can be specifically determined based on the constituent components of the ohmic metal layer 40. The annealing process refers to a high-temperature treatment of the ohmic metal layer, which causes the constituent components of the ohmic metal layer 40 to penetrate downwards into the epitaxial layer 10 at a first location (the location where an ohmic contact needs to be formed, which is not covered by the dielectric layer 20 and the penetration barrier layer 30) to form an ohmic contact. In the semiconductor device provided in this application embodiment, the melting point of the penetration barrier layer 30 is higher than the annealing temperature of the ohmic metal layer 40. Therefore, when the ohmic metal layer 40 is undergoing the annealing process, the penetration barrier layer 30 will not melt, thus preventing the constituent components in the ohmic metal layer 40 from penetrating downwards into the dielectric layer 20. This prevents the constituent components of the ohmic metal layer 40 from penetrating downwards into the epitaxial layers on both sides of the first position via the dielectric layer 20. Therefore, the actual ohmic contact of the semiconductor device provided according to this application embodiment is closer to the desired ohmic contact, and the ohmic contact performance is stable.
[0052] In some embodiments, the material forming the penetration barrier layer 30 does not react with the dielectric layer 20 during the annealing process described above. Reactions here include chemical and / or physical reactions, where physical reactions primarily refer to miscibility reactions. Because the penetration barrier layer 30 does not react with the dielectric layer 20 during the annealing process, it effectively prevents the components constituting the ohmic metal layer 40 from penetrating into the dielectric layer 20.
[0053] In some embodiments, the ohmic metal layer 40 is formed by a conductive compound with metallic properties, such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), etc.
[0054] As can be seen from the above, based on the semiconductor devices provided in some embodiments of this application, a penetration barrier layer 30, formed of a conductive compound with metallic properties, is introduced below the ohmic metal layer 40. The penetration barrier layer 30 remains stable during the high-temperature annealing process of the ohmic metal layer 40 and does not react with the dielectric layer 20, thereby preventing the constituent components of the ohmic metal layer 40 from penetrating into the dielectric layer 20. Therefore, the semiconductor devices provided in some embodiments of this application can ensure the stability of dimensions such as the gate-source distance Lgs, the gate-drain distance Lgd, and the leads Loc on the chip, improving the device's withstand voltage rating and long-term application stability.
[0055] Specifically, such as Figure 1 As shown, for GaN HEMT devices with an ohmic metal field plate 42 (such as a source field plate) structure, the presence of the penetration barrier layer 30 defines the distance from the lowest edge of the ohmic metal field plate 42 to the 2-DEG and the distance from the ohmic metal field plate 42 to the drain electrode 412, which is beneficial to increase the mass production of semiconductor devices and improve the process stability of semiconductor devices.
[0056] Please continue reading. Figure 1 As shown, in some embodiments, the ohmic metal layer 40 includes ohmic metal electrodes. The ohmic metal electrodes include a first portion extending over the penetration barrier layer 30, and a second portion forming an ohmic contact with the epitaxial layer 10, sequentially passing through the penetration barrier layer 30 and the dielectric layer 20. Different types of ohmic contact electrodes are disconnected between the penetration barrier layers 30 they pass through; that is, the non-ohmic contact areas of the dielectric layer 20 are not provided with the penetration barrier layer 30, or the penetration barrier layer 30 on the non-ohmic contact areas of the dielectric layer 20 is removed. The types of ohmic contact electrodes include source electrodes and drain electrodes. Specifically, the ohmic metal layer 40 may include a source electrode 411 and a drain electrode 412. Figure 1 In the example, the first portion 4111 of the source electrode 411 and the second portion 4112 of the source electrode 411 are marked.
[0057] Continue reading Figure 1 As shown, in some embodiments, the ohmic metal layer 40 further includes an ohmic metal field plate 42, and the penetration barrier layer 30 below the ohmic metal field plate 42 is disconnected from the penetration barrier layer 30 through which the ohmic contact electrodes (such as the source electrode 411 and / or the drain electrode 412) pass. That is, the penetration barrier layer 30 is not provided on the dielectric layer 20 between the ohmic metal field plate 42 and the ohmic contact electrodes, or the penetration barrier layer 30 on the dielectric layer 20 between the ohmic metal field plate 42 and the ohmic contact electrodes is removed. Therefore, the semiconductor device structure provided based on the embodiments of this application is less prone to source-drain short circuit problems, and the device performance is good.
[0058] The semiconductor device provided in this application embodiment is a transistor, specifically a field-effect transistor, a high electron mobility transistor (HEMT), a heterojunction field-effect transistor (HFET), or a modulation-doped field-effect transistor (MODFET). Of course, the semiconductor device provided in this application embodiment can also be other types of transistors, and this application embodiment is not limited thereto.
[0059] Please continue reading. Figure 1 As shown, in some embodiments, the semiconductor device provided in this application is a high electron mobility transistor (HEMT). In this embodiment, the ohmic contact electrode includes a source electrode 411 and a drain electrode 412. Further, the semiconductor device also includes a gate electrode 50. The dielectric layer 20 includes a first dielectric layer 21 covering the epitaxial layer 10, and a second dielectric layer 22 covering the first dielectric layer 21 and the gate electrode 50. The gate electrode 50 passes through the first dielectric layer 21 to form a Schottky contact with the epitaxial layer 10. The semiconductor device provided according to the embodiments of this application also includes a gate contact trench (also called a gate contact channel) disposed in the first dielectric layer 21. The gate contact trench penetrates the first dielectric layer 21 to expose the region in the epitaxial layer 10 where the second location of the Schottky contact needs to be formed. A first portion of the gate electrode 50 extends on the surface of the first dielectric layer 21, and a second portion fills the gate contact trench to form a Schottky contact with the region in the epitaxial layer 10 where the second location is located. A Schottky contact refers to the contact between the gate electrode 50 and the region containing the second position of the epitaxial layer 10, where the energy band bends at the contact interface, forming a contact barrier (Schottky barrier). A Schottky contact can also be called a rectifying contact.
[0060] The materials of the first dielectric layer 21 and the second dielectric layer 22 can be selected from SiO2, SiN, and Al2O3, respectively. The materials of the first dielectric layer 21 and the second dielectric layer 22 can be the same or different. Specifically, increasing the relative permittivity of the first dielectric layer 21 and / or the second dielectric layer 22 can improve the insulation of the dielectric layer 20, thereby reducing the static current of the semiconductor device and lowering its static power consumption. Of course, the materials of the first dielectric layer 21 and the second dielectric layer 22 can also be other materials, and this application embodiment does not limit this.
[0061] The gate electrode 50 can be made of any one or more materials such as titanium (Ti), gold (Au), and nickel (Ni). That is, the gate electrode 50 can be made of titanium (Ti), gold (Au), or nickel (Ni), or an alloy of at least two of these metals. Of course, the gate electrode 50 can also be made of other materials, and this embodiment does not limit its application.
[0062] Please continue reading. Figure 1 As shown, in some embodiments, the HEMT provided in this application further includes a substrate layer 01. Further, the epitaxial layer 10 includes a buffer layer 11, a channel layer 12, a barrier layer 13, and a cap layer 14 sequentially stacked on the substrate layer 01. The material of the substrate layer 01 can be any one or more of silicon (Si, which can be either doped or undoped), silicon carbide (SiC), sapphire, etc. Of course, the material of the substrate layer 01 can also be other materials, and this application does not limit the specific materials used in the embodiments.
[0063] The unintentionally doped (UID) semi-insulating buffer layer 11 has high resistivity and is typically on the micrometer scale. It is used to form a 2DEG and reduce the background carrier concentration to reduce drain current collapse caused by the buffer layer trap effect, which is beneficial to improving the reliability of semiconductor devices. It should be noted that in some embodiments, the channel layer 12 can also be formed directly on the substrate layer 01, that is, the epitaxial layer 10 does not include the buffer layer 11.
[0064] The channel layer 12 and barrier layer 13 can directly generate a two-dimensional electron gas, where barrier layer 13 can cover part or all of the channel layer 12. The material forming the ohmic metal layer 40 is matched with the work function of the channel layer 12 to obtain a lower ohmic contact resistance. It should be noted that a system in which the movement of electron groups in one direction is confined to a very small range using physical methods such as quantum confinement, while they can move freely in the other two directions, is called a two-dimensional electron system. Therefore, the lower electron density in a two-dimensional electron system can be called a two-dimensional electron gas. The channel layer 12 can increase the concentration of the two-dimensional electron gas, increase the current density of the semiconductor device, and thus increase the output current of the semiconductor device.
[0065] The channel layer 12 and the barrier layer 13 are made of different materials, forming a heterojunction. For example, in some embodiments, the HEMT provided in this application is a gallium nitride HEMT. Specifically, the barrier layer 13 can be made of aluminum gallium nitride (AlGaN), and the buffer layer 11 and the channel layer 12 can both be made of gallium nitride (GaN). Thus, a heterojunction can be formed between the barrier layer 13 and the channel layer 12. A two-dimensional electron gas can be obtained at the interface of the heterojunction.
[0066] In other embodiments, the material of the barrier layer 13 may also be any one of indium aluminum nitride (InAlN), indium gallium nitride (InGaN), and aluminum indium aluminum nitride (AlInGaN), or any combination of the aforementioned materials (including aluminum gallium nitride (AlGaN)). The barrier layer 13 and the channel layer 12 can also form a heterojunction. Furthermore, the material of the barrier layer 13 may also be other materials; this application does not limit the specific materials used in the embodiments.
[0067] The cap layer 14 in the epitaxial layer 10 can be made of GaN. The cap layer 14 is used to prevent the barrier layer 13 from oxidizing, thereby protecting the interface of the barrier layer 13. Of course, the material of the cap layer 14 can also be other materials, and this embodiment does not limit it. In this embodiment, the region where the second position is located is located in the cap layer 14, and the gate electrode 50 forms a Schottky contact with the cap layer 14. It should be noted that in other embodiments, the cap layer 14 may not be provided on the barrier layer 13, in which case the gate electrode 50 can directly form a Schottky contact with the barrier layer 13.
[0068] To further reduce the ohmic contact resistance, a doped region is formed at the location corresponding to the ohmic contact region between the barrier layer 13 or the channel layer 12 and the dielectric layer 20. Figure 1 (Unmarked in the text), the ohmic metal layer 40 forms an ohmic contact with the doped region. Specifically, the doped region is located at the bottom of the ohmic contact trench, i.e., the region at the first location, and the doping type of this doped region is opposite to that of the cap layer 14. For example, the doped region is an N-type doped GaN layer, specifically a heavily N-type doped GaN layer, and the cap layer 14 is a P-type doped GaN layer. Of course, in other embodiments, the material of the doped layer can also be any one or more of Si, silicon oxide SiO2, silicon nitride SiN, and silicon oxynitride SiON. The material of the doped layer can also be other materials, which are not limited in this embodiment. Furthermore, the cap layer 14 is not limited to a material layer with the opposite doping type to the doped region; it can also be an intrinsic layer or other types of materials.
[0069] Please continue reading. Figure 1As shown, in some embodiments, the semiconductor device further includes a third dielectric layer 60 covering the penetration barrier layer 30, also known as a capping dielectric layer. The aforementioned ohmic contact trench passes through the sandwich structure protective layer composed of the second dielectric layer 22, the penetration barrier layer 30, and the third dielectric layer 60, and further extends through the first dielectric layer 21 to the surface or within the epitaxial layer 10. Specifically, the ohmic contact trench can extend into the barrier layer 13; that is, when etching to form the ohmic contact trench, a portion of the barrier layer 13 at the first location needs to be etched away, so that the barrier layer 13 is partially recessed at the first location. The ohmic contact trench can also extend into the surface or within the channel layer 12; in this case, when etching to form the ohmic contact trench, the entire barrier layer 13 at the first location needs to be etched away, so that the barrier layer 13 is completely recessed at the first location, and a portion of the channel layer 12 can be further etched away, so that the channel layer 12 is partially recessed at the first location.
[0070] The third dielectric layer 60 covers the penetration barrier layer 30, preventing the penetration barrier layer 30, which is formed of a conductive compound with metallic properties, from being directly exposed on the device surface during high-temperature semiconductor device fabrication processes (such as the regeneration process or ion implantation process for forming the doped region in the ohmic contact trench). This avoids problems such as chamber contamination and device surface roughness caused by cation overflow or precipitation. Therefore, the semiconductor devices provided in some embodiments of this application, by adding a third dielectric layer 60 as a cap over the penetration barrier layer 30 to cover it, can effectively reduce the exposure of the penetration barrier layer 30 in subsequent high-temperature processes, increasing the stability and versatility of the fabrication process.
[0071] To further reduce the mutual solubility between the ohmic metal layer 40 and the dielectric layer 20, thereby improving the withstand voltage rating of the dielectric layer 20, a high-k dielectric material can be selected to form the third dielectric layer 60. Specifically, the material forming the third dielectric layer 60 can be, but is not limited to, alumina (Al2O3), aluminum nitride (AlN), or hafnium oxide (HfO2). It should be noted that any two or three of the materials forming the first dielectric layer 21, the second dielectric layer 22, and the third dielectric layer 60 may be the same or different.
[0072] Please see Figure 2 The diagram shows a schematic flow chart of a semiconductor device fabrication method according to some embodiments of this application. Specifically, in some embodiments, the semiconductor device fabrication method provided by this application can fabricate the semiconductor device according to the embodiments of this application, which includes steps S02, S04, and S06, and the specific description of each step is as follows.
[0073] S02: A dielectric layer is formed on the epitaxial layer.
[0074] A dielectric material can be deposited on the epitaxial layer 10 using a deposition process to form a dielectric film, and then etched using an etching process to pattern the dielectric film, thereby forming a dielectric layer 20 through which the ohmic metal layer 40 can pass. Optionally, the deposition process can include any one of atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, low-pressure chemical vapor deposition, electron beam evaporation, and sputtering deposition.
[0075] S04: A penetration barrier layer is formed on the ohmic contact area of the dielectric layer. The penetration barrier layer is used to prevent the constituent components of the ohmic metal layer from penetrating into the dielectric layer.
[0076] In some embodiments, a penetration barrier layer 30 may be deposited in the ohmic contact region and non-ohmic contact region on the side surface of the dielectric layer 20 away from the epitaxial layer 10, and then the portion of the penetration barrier layer 30 located in the non-ohmic contact region may be etched away using a photolithography process, leaving only the penetration barrier layer 30 located in the ohmic contact region.
[0077] In other embodiments, the ohmic contact region of the dielectric layer 20 can be exposed directly on the side of the dielectric layer 20 away from the epitaxial layer 10 based on the mask layer, while the non-ohmic contact region of the dielectric layer 20 is covered. Then, a penetration barrier layer 30 is deposited on the mask layer, and the mask layer thickness is removed to form a patterned penetration barrier layer 30 located in the ohmic contact region.
[0078] S06: An ohmic metal layer is formed on the penetration barrier layer, passing sequentially through the penetration barrier layer and the dielectric layer and contacting the epitaxial layer.
[0079] As an optional implementation, forming the ohmic metal layer 40 specifically includes: depositing a single or multiple metal film layers on the penetration barrier layer 30 and the dielectric layer 20, and patterning the metal film layers based on an etching process to form the ohmic metal layer 40. As another optional implementation, the patterned ohmic metal layer 40 can also be directly formed on the penetration barrier layer 30 based on a patterned mask.
[0080] Based on the semiconductor device fabrication method provided in this application, before forming the ohmic metal layer 40, a penetration barrier layer 30 is first formed on the dielectric layer 20 to prevent the constituent components of the ohmic metal layer 40 from penetrating into the dielectric layer 20. This effectively solves the problem of mutual solubility between the ohmic metal layer 40 and the dielectric layer 20 that occurs in traditional high-temperature ohmic processes (annealing processes), ensuring the source / drain metal dimensions and field plate positions of the semiconductor device, thereby improving process stability. Especially for small-sized semiconductor devices in low-voltage applications, the fabrication method provided in this application can provide a larger design window for semiconductor device design, assisting in the design of smaller gate-source distance Lgs, gate-drain distance Lgd, and chip lead Loc, improving the reliability and process temperature performance of small-sized semiconductor devices.
[0081] Figures 3a to 3f This is a cross-sectional schematic diagram of the semiconductor structure formed in each method step according to the preparation method provided in the embodiments of this application. The following will be combined with... Figures 3a to 3f The preparation methods provided in some embodiments of this application will be further described in detail.
[0082] In some embodiments, the fabrication method provided in this application further includes forming an epitaxial layer 10 on the substrate layer 01. Specifically, as shown... Figure 3a As shown, the epitaxial layer 10 includes a buffer layer 11, a channel layer 12, a barrier layer 13, and a cap layer 14 sequentially deposited on a substrate layer 01. The cap layer 14 is located above the region where the second position of the barrier layer 13 is located. Specifically, the region where the second position is located can be exposed by covering the other regions of the barrier layer 13 except for the region where the second position is located with a mask, and then depositing the cap layer material on the mask to form the cap layer 14.
[0083] Please see Figure 4 ,in, Figure 4 This is a schematic diagram of the process flow for forming a dielectric layer 10 on the epitaxial layer 10. In some embodiments, the dielectric layer 20 includes a first dielectric layer 21 and a second dielectric layer 22. In this case, S02 specifically includes S021, S022, S023, S024 and S025, and the specific description of each step is as follows.
[0084] S021: Deposit the first dielectric layer on the surface of the epitaxial layer.
[0085] A first dielectric material is deposited on the surface of the epitaxial layer 10 away from the substrate layer 01 using any of the above-described deposition processes to form a first dielectric layer 21. The first dielectric layer 21 is a passivation layer required for forming the gate electrode 50, and it can be a silicon dioxide dielectric layer.
[0086] S022: Etch the Schottky contact region of the first dielectric layer to form a gate contact trench exposing the epitaxial layer.
[0087] Photolithography is performed on the first dielectric layer 21 to form a shape such as... Figure 3b The gate contact trench 50' is shown. The bottom of the gate contact trench 50' extends to the surface or interior of the cap layer 14 to expose the cap layer 14 in the epitaxial layer 10.
[0088] S023: Deposit gate electrode material on the first dielectric layer and in the gate contact trench to form a gate electrode film.
[0089] Gate electrode material is deposited on the surface of the first dielectric layer 21 away from the barrier layer 13 and in the gate contact trench 50' to form a gate electrode film.
[0090] S024: Etch the gate electrode film to form a gate electrode that is at least partially located in the gate contact trench and forms a Schottky contact with the epitaxial layer.
[0091] like Figure 3c As shown, the area where the gate electrode 50 is located is defined based on the photolithography process, so as to etch away the part of the gate electrode film layer other than the gate electrode 50, thereby forming a gate electrode 50 that partially fills the gate contact trench 50' and partially extends a certain distance on the surface of the first dielectric layer 21. The gate electrode 50 passes through the gate contact trench 50' and forms a Schottky contact with the cap layer 14 through the first dielectric layer 21.
[0092] S025: Deposit a second dielectric layer on the surface of the first dielectric layer and the gate electrode.
[0093] A second dielectric material is deposited on a dielectric layer 21 and a gate electrode 50 to form a second dielectric layer 22.
[0094] Furthermore, following S025, a penetration barrier layer 30 and a third dielectric layer 60 are sequentially deposited on the second dielectric layer 22. Wherein, as... Figure 3d As shown, the second dielectric layer 22, the penetration barrier layer 30, and the third dielectric layer 60 form a sandwich structure protective layer on the first dielectric layer 21 and the gate electrode 50.
[0095] It should be noted that when the dielectric layer 20 includes a first dielectric layer 21 and a second dielectric layer 22, the ohmic contact region of the dielectric layer 20 refers to the ohmic contact region of the first dielectric layer 20. Therefore, after forming the protective layer with the aforementioned sandwich structure, the location where the ohmic contact trench needs to be formed is defined based on the photolithography process. Then, the third dielectric layer 60, the penetration barrier layer 30, the second dielectric layer 22, and the first dielectric layer 21 at that location are etched away sequentially, with the etching stopping at the barrier layer 13 or the channel layer 12, thereby forming the ohmic contact trench, as shown below. Figure 3eThe source ohmic contact trench 411' and drain ohmic contact trench 412' are shown in the figure. Specifically, the ohmic contact trenches can be formed by etching using inductively coupled plasma technology.
[0096] In some embodiments, forming a penetration barrier layer 30 only on the ohmic contact region of the dielectric layer 20 includes: depositing a penetration barrier material on the surface of the second dielectric layer 22 to form a penetration barrier layer 30, and then forming a third dielectric layer 60 on the penetration barrier layer 30 to protect the penetration barrier material from contamination of the device by the high-temperature process; then defining the location of the ohmic contact trench based on the photolithography process; and then sequentially etching the third dielectric layer 60, the penetration barrier layer 30, the second dielectric layer 22, and the first dielectric layer 21 at the location of the ohmic contact trench, with the etching stopping at the barrier layer 13 or the channel layer 12 to form the ohmic contact trench.
[0097] In some embodiments, the specific steps of forming the penetration barrier layer 30 located only in the ohmic contact region and forming the ohmic metal layer include: after forming the ohmic contact trench, depositing an ohmic metal material on the third dielectric layer 60 and in the ohmic contact trench to form an ohmic metal film covering the third dielectric layer 60 and filling the ohmic metal trench; then defining the ohmic contact region and non-ohmic contact region of the second dielectric layer 22 based on a photolithography process; and sequentially etching away the ohmic metal film in the non-ohmic contact region, the third dielectric layer 60, and the penetration barrier layer 30 to form an ohmic metal layer 40 with a first portion extending on the surface of the penetration barrier layer 30 and a second portion located in the ohmic contact trench and forming an ohmic contact with the epitaxial layer, and retaining the penetration barrier layer 30 in the ohmic contact region. Specifically, the ohmic metal film is prepared by methods such as physical vapor deposition, magnetron sputtering, or electron beam evaporation, and its formation method is not specifically limited in this application.
[0098] Additionally, in some embodiments, such as Figure 1 The ohmic metal layer 40 retained in the ohmic contact area includes not only ohmic metal electrodes but also an ohmic metal field plate 42, such as a source field plate or a gate field plate. After the ohmic metal layer 40 is formed, it is annealed at a preset annealing temperature. This not only achieves ohmic contact between the ohmic metal layer 40 and the epitaxial layer 10, but also, during the annealing process, the penetration barrier layer 30 prevents the constituent components of the ohmic metal layer 40 from penetrating into the second dielectric layer 22, effectively preventing the lateral expansion of the ohmic contact area. This ensures the stability of dimensions such as the gate-source distance Lgs, the gate-drain distance Lgd, and the leads Loc on the chip, improving the device's withstand voltage rating and long-term stability.
[0099] Furthermore, in some embodiments, to reduce the ohmic contact resistance, the fabrication method provided in this application further includes forming a doped region in the epitaxial layer at the bottom of the ohmic contact trench before forming the ohmic metal 40. This doped region can be an N+ type gallium nitride doped region. The specific formation process of the doped region is not specifically limited in this application; it can be an in-situ growth process or a plasma implantation process.
[0100] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, It includes an epitaxial layer, a dielectric layer, a penetration barrier layer, and an ohmic metal layer; The epitaxial layer and the dielectric layer are stacked together. The penetration barrier layer is disposed on the ohmic contact region of the dielectric layer. The ohmic metal layer passes through the penetration barrier layer and the dielectric layer in sequence and forms an ohmic contact with the epitaxial layer. The penetration barrier layer is used to prevent the constituent components of the ohmic metal layer from penetrating into the dielectric layer.
2. The semiconductor device according to claim 1, characterized in that, The penetration barrier layer is used to prevent the constituent components from penetrating into the dielectric layer when the ohmic metal layer is undergoing an annealing process. The melting point of the penetration barrier layer is greater than the annealing temperature of the annealing process; And / or, when the ohmic metal layer is undergoing an annealing process, the penetration barrier layer does not react with the dielectric layer.
3. The semiconductor device according to claim 2, characterized in that, The ohmic metal layer includes an ohmic contact electrode, which includes a first portion extending over the penetration barrier layer and a second portion that sequentially passes through the penetration barrier layer and the dielectric layer to form an ohmic contact with the epitaxial layer. The different types of ohmic contact electrodes are disconnected from the penetration barrier layer through which they pass.
4. The semiconductor device according to claim 3, characterized in that, The ohmic metal layer also includes an ohmic metal field plate; The penetration barrier layer beneath the ohmic metal field plate is disconnected from the penetration barrier layer through which the ohmic contact electrode passes.
5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The material forming the penetration barrier layer is a conductive compound with metallic properties.
6. The semiconductor device according to any one of claims 1 to 4, characterized in that, It also includes a capping medium layer covering the penetration barrier layer.
7. A method for fabricating a semiconductor device, characterized in that, include: A dielectric layer is formed on the epitaxial layer; A penetration barrier layer is formed on the ohmic contact area of the dielectric layer, the penetration barrier layer being used to prevent the constituent components of the ohmic metal layer from penetrating into the dielectric layer; An ohmic metal layer is formed on the penetration barrier layer, passing sequentially through the penetration barrier layer and the dielectric layer and contacting the epitaxial layer.
8. The preparation method according to claim 7, characterized in that, The formation of a penetration barrier layer on the ohmic contact region of the dielectric layer includes: A penetration barrier material is deposited on the surface of the dielectric layer to form a penetration barrier layer; Based on photolithography, the ohmic contact region and non-ohmic contact region of the dielectric layer are defined. The penetration barrier layer is etched to remove the penetration barrier layer located on the non-ohmic contact area.
9. The preparation method according to claim 8, characterized in that, Before defining the ohmic contact region and non-ohmic contact region of the dielectric layer based on photolithography, the method further includes: A capping medium material is deposited on the penetration barrier layer to form a capping medium layer.
10. The preparation method according to claim 9, characterized in that, The formation of an ohmic metal layer on the penetration barrier layer, which sequentially passes through the penetration barrier layer and the dielectric layer and contacts the epitaxial layer, includes: The capping dielectric layer, the penetration barrier layer, and the dielectric layer are etched sequentially to form an ohmic contact trench that penetrates the capping dielectric layer, the penetration barrier layer, and the dielectric layer and extends to the surface of the epitaxial layer or the epitaxial layer. An ohmic metal material is deposited on the cap medium layer and in the ohmic contact trench to form an ohmic metal film.
11. The preparation method according to claim 10, characterized in that, The etching of the penetration barrier layer to remove the penetration barrier layer located on the non-ohmic contact region includes: The ohmic metal film, the capping dielectric layer, and the penetration barrier layer in the non-ohmic contact area are etched away in sequence to form an ohmic metal layer in which a first portion extends on the surface of the capping dielectric layer and a second portion is located in the ohmic contact trench and forms an ohmic contact with the epitaxial layer.