Optical interconnection processor and memory module

Abstract

Optical interconnect modules may include logic and / or memory blocks and optical transceiver subsystems. The optical transceiver subsystem may include an array of micro LEDs and an array of photodetectors. The optical transceiver subsystem of each module may be optically coupled to optical transceiver subsystems of other modules. Each module may include a processor and / or memory chip and an optical transceiver subsystem chip mounted on a common substrate, and the processor and / or memory chip and the optical transceiver chip may be coupled through a die-to-die interface.

Description

Optical interconnect processor and memory module Background Technology

[0001] Processors, memory, and other integrated circuits (ICs) used in applications such as high-performance computing (HPC) and artificial intelligence / machine learning (AI / ML) have input / output (I / O) bandwidth requirements of several megabits per second (Tbps). The performance of systems using these ICs is currently bottlenecked by I / O bandwidth limitations. Notably, processor-to-memory and processor-to-processor bandwidth constraints are limiting the performance of AI / ML and HPC systems in critical data center applications.

[0002] Various types of high-performance memory (HPM) with high I / O bandwidth have been developed. Currently, the memory with the highest I / O bandwidth is high-bandwidth memory (HBM). HBM uses vertically stacked memory dies with through-silicon vias (TSVs) to maximize memory capacity within extremely limited interconnect distances. HBMs are connected to the processor via wide (e.g., 1024 channels) HBM buses, which are typically implemented as die-to-die (D2D) interconnects on a silicon interposer. The length of the HBM bus is typically limited to a maximum length of only a few millimeters due to signal integrity constraints. This means that the maximum HBM memory capacity accessible to the processor can be limited by the processor's "shoreline" length. Due to the need for higher refresh rates, this often requires the HBM to be very close to the hot processor, which degrades the performance of HBM DRAM. The I / O bandwidth of HBM3 variants is exceeding 5 Tbps and can be substantially increased in future HHBM versions. Summary of the Invention

[0003] According to various embodiments of the present invention, a module for optical interconnection is provided, comprising: a logic and / or memory integrated circuit chip; a plurality of optical transceiver subsystems, each including an integrated circuit chip, a micro-LED array mounted to a surface of the integrated circuit chip, a photodetector array mounted to the surface of the integrated circuit chip, a transmitter circuit system integrated in the integrated circuit chip, and a receiver circuit system integrated in the integrated circuit chip; an interposer layer to which the logic or memory block and the plurality of optical transceiver subsystems are mounted; a die-to-die interface coupling the logic or memory block to each of the optical transceiver systems via the interposer layer; a plurality of fiber arrays, each in the form of a fiber bundle, each of the optical transceiver subsystems corresponding to a fiber bundle; and a plurality of optical coupling assemblies for coupling light between the optical transceiver subsystems and their corresponding fiber bundles. In some embodiments, the interposer layer is a passive interposer layer. In some embodiments, the surface of the integrated circuit chip of each of the optical transceiver subsystems having the micro-LED array and the photodetector array faces away from the passive interposer layer. In some embodiments, the integrated circuit chip of each of the optical transceiver subsystems includes a through-surface via (TSV) extending from a surface of the integrated circuit chip opposite to the surface having the microLED array and the photodetector array toward the surface having the microLED array and the photodetector array. In some embodiments, the surface of the integrated circuit chip of each of the optical transceiver subsystems having the microLED array and the photodetector array faces the passive interposer layer. In some embodiments, the passive interposer layer includes apertures located around the positions of the microLED array and the photodetector array of the optical transceiver subsystem. In some embodiments, the optical coupling assembly is located in the apertures of the passive interposer layer.

[0004] According to various embodiments of the present invention, an optical interconnect module is provided, comprising: a first module having a first logic and / or memory integrated block and a first plurality of optical transceiver subsystems, each of the first plurality of optical transceiver subsystems including an integrated circuit chip, a micro-LED array mounted on the surface of the integrated circuit chip, a photodetector array mounted on the surface of the integrated circuit chip, a transmitter circuit system integrated in the integrated circuit chip, and a receiver circuit system integrated in the integrated circuit chip, the first logic and / or memory block being coupled to the first plurality of optical transceiver subsystems via a die-to-die interface; and a second module having a second logic and / or memory block and a second plurality of optical transceiver subsystems, each of the second plurality of optical transceiver subsystems including an integrated circuit chip, a micro-LED array mounted on the surface of the integrated circuit chip, a photodetector array mounted on the surface of the integrated circuit chip, a transmitter circuit system integrated in the integrated circuit chip, and... A receiver circuit system integrated in the integrated circuit chip, wherein the second logic and / or memory block is coupled to the second plurality of optical transceiver subsystems via a die-to-die interface; a third module having a third logic and / or memory block and a third plurality of optical transceiver subsystems, each of the third plurality of optical transceiver subsystems including an integrated circuit chip, a micro-LED array mounted on the surface of the integrated circuit chip, a photodetector array mounted on the surface of the integrated circuit chip, a transmitter circuit system integrated in the integrated circuit chip, and a receiver circuit system integrated in the integrated circuit chip, wherein the third logic and / or memory block is coupled to the third plurality of optical transceiver subsystems via a die-to-die interface; and a plurality of fiber bundles coupling the first plurality of optical transceiver subsystems to the second plurality of optical transceiver subsystems, the first plurality of optical transceiver subsystems to the third plurality of optical transceiver subsystems, and the second plurality of optical transceiver subsystems to the third plurality of optical transceiver subsystems. In some embodiments, at least one of the first, second, and third logical and / or memory blocks includes high-performance memory, and at least another of the first, second, and third logical and / or memory blocks includes a processor.

[0005] These and other aspects of the invention will become more fully understood immediately upon review of this disclosure. Attached Figure Description

[0006] Figure 1 is a block diagram of an optical interconnect module system according to various aspects of the present invention.

[0007] Figure 2A is a block diagram illustrating a module comprising two processors according to various aspects of the present invention.

[0008] Figure 2B is a block diagram illustrating a module having multiple high-performance memory (HPM) blocks according to various aspects of the present invention.

[0009] Figure 2C is a block diagram of a module including multiple memory subsystems connected to a switch IC according to various aspects of the present invention.

[0010] Figure 3A is a simplified cross-sectional view of an example OTRS according to various aspects of the present invention.

[0011] Figure 3B illustrates an example optical coupling assembly according to various aspects of the present invention.

[0012] Figures 4A to 4D illustrate various embodiments of optical interconnect modules according to various aspects of the present invention, wherein the optical interface is "facing upward" away from the fan-out package substrate.

[0013] Figures 5A to 5D illustrate various embodiments of optical interconnect modules according to various aspects of the present invention, wherein the optical interface passes through a fan-out package substrate and faces "down". Detailed Implementation

[0014] It may be necessary to be able to interconnect processors to each other and to the HPM at data rates > 10 Tbps, while allowing interconnect ICs to be separated by tens or hundreds of centimeters. Preferably, this will be achieved with extremely low power per bit, low latency, and low cost. The ability to implement much longer interconnects to the HPM will provide several benefits, such as: (1) enabling processors to access much more HPM capacity; (2) physically separating the HPM from the hot processors potentially allowing the HPM to operate at lower temperatures, thereby improving its performance; and (3) with appropriate architecture, a given HPM die or stack can be accessed by multiple processors in a so-called “de-aggregated memory” architecture.

[0015] Optical interconnects offer density and power dissipation benefits and are far less dependent on distance than electrical interconnects. The disclosures herein relate to the use of optical interconnects to connect high-performance processors to each other and to high-performance memory.

[0016] In some embodiments of the optical interconnect module, the first module includes one or more logic and / or memory ICs and one or more optical transceiver subsystems (OTRS). The first module is connected to one or more other modules via the OTRS through an optical transmission medium. The other modules (in some embodiments, each of the other modules) also include one or more logic and / or memory ICs and one or more OTRS, wherein the OTRS of the other modules is used for connection to the optical transmission medium.

[0017] Figure 1 is a block diagram of a system of optical interconnect modules. The system is shown to include three modules 111a to 111c. Each of the modules is optically connected to the other modules via an optical transmission medium; wherein the first module 111a and the second module 111b are optically connected via a first optical transmission medium 117b, the first module is optically connected to the third module via a second optical transmission medium 117a, and the second module and the third module are optically connected via a third optical transmission medium 117c. In various embodiments, there may be more or fewer optical interconnect modules, and in some embodiments, not all modules may be optically connected to all other modules.

[0018] The module is shown in Figure 1 as comprising logic and memory blocks 113a to 113c. In some embodiments, some modules of the module may alternatively comprise logic blocks, and in some embodiments, some modules of the module may alternatively comprise memory blocks. The module also includes an optical transceiver subsystem (OTRS). The OTRS has an electrical interface connected to the logic and memory blocks of its module and an optical interface connected to an optical transmission medium connected to its module.

[0019] In the embodiment of FIG1, an OTRS is present at each end of the optical transmission medium. A first module includes an OTRS 115a2 optically coupled to one end of the optical transmission medium 117b, and a second module includes an OTRS 115b1 optically coupled to the other end of the optical transmission medium 117b. Similarly, the first module includes an OTRS 115a1 optically coupled to one end of the optical transmission medium 117a, and a third module includes an OTRS 115c1 optically coupled to the other end of the optical transmission medium 117a. Also similarly, the second module includes an OTRS 115b2 optically coupled to one end of the optical transmission medium 117c, and the third module includes an OTRS 115c2 optically coupled to the other end of the optical transmission medium 117c.

[0020] In some embodiments of the optical connectivity module, the module includes one or more processor ICs connected to one or more OTRSs. Examples of processor ICs are central processing units (CPUs), graphics processing units (GPUs), data processing units (DPUs), tensor processing units (TPUs), and various specialized processing "accelerators." Figure 2A is a block diagram showing a module 211 comprising two processors 213. The module may be one of the modules in the system of Figure 1. Each processor is coupled to two OTRSs 115. Each OTRS is connected to an optical transmission medium 117 via an optical connector 215. In some cases, the optical connector is an optical coupling assembly, and in some cases, the optical connector is an in-line optical connector with the optical transmission medium.

[0021] In some embodiments of the optical interconnect module, the module includes one or more memory subsystems connected to one or more OTRSs. Examples of memory subsystems are high-bandwidth memory (HBM), synchronous dynamic random access memory (SDRAM), and static random access memory (SRAM). Figure 2B is a block diagram illustrating a module with multiple high-performance memory (HPM) blocks, where four HPM blocks 223 are shown in the embodiment of Figure 2B. In the case of HBM, the memory subsystem includes stacked DRAM dies and may also include a substrate die containing nano-buffer circuitry and / or memory controller circuitry. Each HPM block is connected to a corresponding OTRS 115. Each OTRS is connected to an optical transmission medium 117 via an optical connector 215. In some embodiments, the optical connector may be an optical connector serially coupled to the optical transmission medium.

[0022] In some embodiments of the optical connectivity module, the module includes one or more logic ICs and one or more memory subsystems connected to one or more OTRSs. As an example, Figure 2C is a block diagram of a module including multiple memory subsystems 233 connected to a switch IC 235. The switch IC is in turn connected to one or more OTRSs 234. For example, the switch IC may be a packet switch or a circuit switch. As those skilled in the art will understand, the switch IC enables any of the memory subsystems to connect to any of the OTRSs. Each OTRS is connected to the optical transmission medium 117 via an optical connector 215, which in some cases may be an optical connector serially coupled to the optical transmission medium.

[0023] An OTRS includes one or more optical transmitters (Tx) and / or one or more optical receivers (Rx). Figure 3A is a simplified cross-sectional view of an example OTRS. In some embodiments, the Tx portion includes a two-dimensional (2D) array of microLEDs 311 (in some cases, GaN microLEDs 313) mounted to the surface of IC 315. In some embodiments, the microLED array may be electrically connected to a transmitter circuitry 317 integrated into the IC substrate to which the microLED array is mounted. In some embodiments, each microLED may be surrounded and encapsulated by a microlens to refract the generated light in a desired direction. In some embodiments, the Rx portion includes a 2D array of photodetectors (PDs) 317 (in some cases, Si PD 319) integrated into or mounted to the surface of IC. In some embodiments, the photodetector array may be electrically connected to a receiver circuitry 321 integrated into or mounted to the IC substrate to which the photodetector array is mounted. In some embodiments, the transmitter array and PD array are located on a regular grid. In some embodiments, the transmitter and PD grids are hexagonal close-packed (HCP), square, or rectangular grids. In some embodiments, the center-to-center spacing of the grid elements is in the range of 10 μm to 100 μm. In some embodiments, the IC substrate on which the transmitter and receiver circuitry, as well as the micro-LED array and photodetector array are mounted or embedded, may also have circuitry 323 for other logic functions.

[0024] In some embodiments, the optical transmitter and receiver are optically coupled to the transmission medium via an optical coupling assembly. The optical coupling assembly may include one or more refractive elements (e.g., lenses) and one or more reflective elements (e.g., mirrors). In some embodiments, the reflective element is a 45-degree deflecting mirror that changes the direction of emitted and received light between a vertical and a horizontal direction. In some embodiments, one or more refractive elements may focus light onto the transmission medium (e.g., the fiber optic core of the transmission medium). In some embodiments, the optical transmitter and receiver are directly mated to the transmission medium without the need for an intermediate optical coupling assembly.

[0025] Figure 3B illustrates an example optical coupling assembly. The optical coupling assembly of Figure 3B is shown positioned and configured to couple light from a microLED 357 to an optical fiber 365. In various embodiments, the optical coupling assembly may alternatively or additionally couple light from the optical fiber to a photodetector (not shown in Figure 3B). In Figure 3B, the microLED is shown mounted on a semiconductor substrate 361, with a transmitter circuitry 363 for driving the microLED located within the substrate and below the microLED. An optional encapsulant 359 is also shown located on the substrate, substantially encapsulating the microLED. Light from the microLED is reflected at a 45-degree angle by a mirror 351 within the optical coupling assembly to guide the light from a vertical to a horizontal direction. The light then passes through a pair of lenses 353a, b, and exits the optical coupling assembly into the fiber core.

[0026] In some embodiments, the transmission medium comprises an array of optical fibers or an array of optical waveguides in the form of an optical fiber bundle. The optical fiber bundle includes multiple optical fiber elements (FEs). Each FE includes a core surrounded by a concentric cladding layer with a lower refractive index than the core, thereby enabling light to be guided within the core. In some embodiments, all FEs have the same nominal size and properties. In some embodiments of OTRS using microLED arrays and PD arrays, each microLED is optically coupled to one FE in the optical fiber bundle, and each PD is optically coupled to one FE in the optical fiber bundle. In some embodiments, one or more refractive elements of the optical coupling assembly may form this one-to-one relationship between the microLED and the optical fiber element, and between the photodetector and the optical fiber element.

[0027] In some embodiments, the optical transmission medium includes a planar waveguide array. In some embodiments, the optical transmission medium includes a series of free-space optical elements, such as lenses and mirrors, for relaying light from one or more transmitters to a set of corresponding one or more receivers.

[0028] Figures 4A to 4D illustrate various embodiments of the optical interconnect module, where the optical interface faces upwards away from the fan-out package substrate. In some embodiments of the optical interconnect module, one or more logic and / or memory ICs are connected to one or more OTRS ICs via a passive interposer. Various ICs are bonded to the passive interposer using flip-chip IC bonding techniques, such as C4 bumps, copper pillar bumps, or direct bonding interconnects (DBI). Figure 4A illustrates an embodiment of the optical interconnect module where one logic and / or memory IC 425 is connected to two OTRS ICs 411 via a die-to-die interface 429 through a passive interposer 421. Both the logic and / or memory IC and the OTRS IC are mounted on the passive interposer. The logic and / or memory IC and the OTRS IC can be bonded to the passive interposer, for example, using flip-chip IC bonding techniques, such as C4 bumps, copper pillar bumps, or direct bonding interconnects (DBI). Examples of logic ICs that can be used in the module are processor ICs, such as CPUs, GPUs, DPUs, and TPUs. Examples of memory include HBM, SDRAM, and SRAM. In some embodiments, the electrical interface between the various ICs may be a die-to-die interface, such as UCIe, Open HBI, or Wire Harness (BoW). In some embodiments, each of the OTRS ICs is electrically connected to one or more logic and / or memory ICs via a passive interposer using a die-to-die interface. In the case of connection to HBM, an HBM interface may be used. The optical interface on each OTRS IC (e.g., a micro-LED and photodetector array) faces upward and may be connected to the optical transmission medium 413 via an optical coupling assembly 415 or may be directly coupled to the optical transmission medium. The optical coupling assembly may deflect light at a 90° angle relative to the IC surface or may project light in a straight direction. Each OTRS IC may have a through-silicon via (TSV) 427 to allow power, ground, and signals to pass through the die. In some embodiments, the passive interposer may be bonded to the fan-out substrate 423, for example, via C4 solder bumps or copper pillar bumps. In some embodiments, the fan-out substrate may be an organic packaging substrate, a printed circuit board (PCB), or a redistribution layer (RDL) on a molded wafer. A heat sink (not shown in Figure 4A) may be attached to the top of the IC.

[0029] Figure 4B illustrates an embodiment of an optical interconnect module, similar to the embodiment of Figure 4A, except that only one or more passive bridging interposers 430, rather than a full interposer, are used to interconnect the ICs. In some embodiments, each bridging interposer is embedded in a cavity in a fan-out substrate 423 and is typically much smaller than the ICs (e.g., logic, memory, and / or OTRS ICs) for which it is used for interconnection.

[0030] Figure 4C illustrates an embodiment of an optical interconnect module in which one or more OTRSs are integrated into a substrate IC 443. One or more logic and / or memory ICs 425 are bonded to the top of the substrate IC, for example using conventional flip-chip IC bonding techniques (e.g., copper pillar bumps or direct bonding interconnects (DBI)). Examples of logic ICs that can be used in the module are processor ICs, such as CPUs, GPUs, and DPUs. Examples of memory are HBMs, SDRAMs, and SRAMs. An optical interface (e.g., a micro-LED and photodetector array) on each OTRS 411 is upward-facing and can be connected to a transmission medium via an optical coupling assembly 415 or directly coupled to an optical transmission medium 413. The optical coupling assembly can deflect light at 90° relative to the IC surface or can project light in a straight direction. The substrate IC may have through-silicon vias (TSVs) 427 to allow power, ground, and signals to pass through the die. In some embodiments, the logic and / or memory ICs may be electrically connected to the TSVs of the substrate IC. In some embodiments, the integrated OTRSs may be electrically connected to the TSVs of the substrate IC. In some embodiments, the substrate IC may be bonded to the fan-out substrate 423, for example, via solder bumps or copper pillar bumps. In some embodiments, logic and / or memory ICs may be electrically connected to the fan-out substrate via TSVs. In some embodiments, an integrated OTRS may be electrically connected to the fan-out substrate via TSVs. In some embodiments, the fan-out substrate may be an organic package substrate, a PCB, or a redistribution layer (RDL) on a molded wafer. In some embodiments, a heat sink may be bonded to the top of the IC (e.g., logic, memory, and / or substrate IC).

[0031] Figure 4D illustrates an embodiment of the optical interconnect module, similar to the embodiment of Figure 4C, except that multiple substrate ICs 443, each having at least one OTRS 411, are embedded in cavities of a fan-out substrate (or package substrate) 431, rather than a single substrate IC being mounted on top of the fan-out substrate. In some embodiments, logic and / or memory ICs may be directly but partially mounted to the fan-out substrate, while also being electrically connected to the substrate ICs embedded in the fan-out substrate using TSVs.

[0032] Figures 5A through 5D illustrate various embodiments of the optical interconnect module, where the optical interface passes through a fan-out package substrate and faces "down". Figure 5A illustrates an embodiment of the optical interconnect module in which one or more logic and / or memory ICs 425 are connected to one or more OTRS ICs 511 via a passive interposer 521. The various ICs are bonded to the passive interposer using, for example, conventional flip-chip IC bonding techniques (e.g., copper pillar bumps or direct bonding interconnect (DBI)). Examples of logic ICs that can be used in the module are processor ICs, such as CPUs, GPUs, and DPUs. Examples of memory are HBMs, SDRAMs, and SRAMs. In some embodiments, the interface between the various ICs may be a die-to-die interface 429, such as UCIe, open HBI, or wire harness (BoW). In some embodiments, each of the OTRS ICs may be connected to one or more logic and / or memory ICs via a die-to-die interface through a passive interposer. An HBM interface may be used to connect to an HBM. The optical interface (e.g., a micro-LED and photodetector array) on each OTRS IC faces downward and can be connected to the optical transmission medium 413 via an optical coupling assembly 513 or directly coupled to the optical transmission medium. The optical coupling assembly can deflect light at a 90° angle relative to the IC surface or project light in a straight direction. In some embodiments, a passive interposer can be bonded to a fan-out substrate 523, for example, via C4 solder bumps or copper pillar bumps. In some embodiments, the fan-out substrate can be an organic package substrate, a PCB, or a redistribution layer (RDL) on a molded wafer. A heat sink can be bonded to the top of the IC. The passive interposer and the fan-out substrate have apertures located under each OTRS, which allow the optical coupling assembly and transmission medium to be attached to the optical interface on the bottom of each OTRS IC.

[0033] Figure 5B illustrates an embodiment of the optical interconnect module, similar to the embodiment of Figure 5A, except that one or more passive bridging interposers 533, rather than a full interposer, are used to interconnect the ICs. Each bridging interposer is embedded in a cavity in a fan-out substrate and is typically much smaller than the IC it is used to interconnect (e.g., logic, memory, and / or OTRS ICs). The fan-out substrate has an aperture located under each OTRS, which allows the optical coupling assembly and transmission medium to be attached to an optical interface on the bottom of each OTRS IC, while one or more embedded passive bridging interposers may not have such an aperture because they are located on the side of the aperture in the fan-out substrate.

[0034] Figure 5C illustrates an embodiment of an optical interconnect module in which one or more OTRS 511 are integrated into a substrate IC 543. The optical interface faces downwards through a fan-out substrate 523. In some embodiments, the OTRS may be located at the bottom of the substrate IC and contact and directly mounted to the fan-out substrate. One or more logic and / or memory ICs are bonded to the top of the substrate IC, for example using conventional flip-chip IC bonding techniques (e.g., copper pillar bumps or direct bonding interconnects (DBI)). Examples of logic ICs that can be used in the module are processor ICs, such as CPUs, GPUs, and DPUs. Examples of memory are HBMs, SDRAMs, and SRAMs. The optical interface (e.g., a micro-LED and photodetector array) on each integrated OTRS faces downwards and may be connected to a transmission medium via an optical coupling assembly or may be directly coupled to an optical transmission medium. The optical coupling assembly may deflect light at 90° relative to the IC surface or may project light in a straight direction. The substrate IC may have through-silicon vias (TSVs) 511 to allow power, ground, and signals to pass through the die. In some embodiments, the logic and / or memory IC may be electrically connected to the TSV of the substrate IC. In some embodiments, the substrate IC may be bonded to the fan-out substrate, for example, via solder bumps or copper pillar bumps. In some embodiments, the logic and / or memory IC may be electrically connected to the fan-out substrate via TSV. In some embodiments, the fan-out substrate may be an organic package substrate, a PCB, or a redistribution layer (RDL) on a molded wafer. The substrate IC and the fan-out substrate have apertures located under each OTRS, which allow optical coupling assemblies and transmission media to be attached to an optical interface on the bottom of each OTRS IC. A heat sink may be attached to the top of the IC.

[0035] Figure 5D illustrates an embodiment of the optical interconnect module, similar to the embodiment of Figure 5C, except that multiple substrate ICs 543, each having at least one OTRS, are embedded in cavities within a fan-out substrate 523 instead of a single substrate IC being mounted on top of the fan-out substrate. In some embodiments, logic and / or memory ICs may be directly, but partially, mounted to the fan-out substrate, while also being electrically connected to the substrate ICs embedded in the fan-out substrate using TSVs. The fan-out substrate has an aperture located beneath each OTRS, which allows optical coupling assemblies and transmission media to be attached to an optical interface on the bottom of each OTRS IC.

[0036] Modules incorporating memory have many important applications. In the embodiments of Figures 4C, 4D, 5C, and 5D, the memory controller can be integrated into the base IC. In the embodiments of Figures 4A, 4B, 5A, and 5B, the memory controller can be integrated into the OTRS IC.

[0037] Although the invention has been discussed with respect to various embodiments, it should be understood that the invention includes novel and non-obvious claims supported by this disclosure.

Claims

1. A module for optical interconnection, comprising: Logic and / or memory integrated circuit chips; Multiple optical transceiver subsystems, each including an integrated circuit chip, a micro-LED array mounted on the surface of the integrated circuit chip, a photodetector array mounted on the surface of the integrated circuit chip, a transmitter circuit system integrated in the integrated circuit chip, and a receiver circuit system integrated in the integrated circuit chip; an interposer layer, a logic or memory block, and the multiple optical transceiver subsystems are mounted on the interposer layer; A die-to-die interface that couples the logic or memory block to each of the optical transceiver systems via the interposer layer; a plurality of fiber arrays, each in the form of a fiber bundle, with each of the optical transceiver subsystems corresponding to a fiber bundle; and a plurality of optical coupling assemblies for coupling light between the optical transceiver subsystems and their corresponding fiber bundles.

2. The module according to claim 1, wherein the intermediary layer is a passive intermediary layer.

3. The module of claim 1, wherein the surface of the integrated circuit chip of each of the optical transceiver subsystems having the micro-LED array and the photodetector array faces away from the passive interposer layer.

4. The module of claim 3, wherein the integrated circuit chip of each of the optical transceiver subsystems includes a through-surface via (TSV) extending from a surface of the integrated circuit chip opposite to the surface having the microLED array and the photodetector array toward the surface having the microLED array and the photodetector array.

5. The module of claim 1, wherein the surface of the integrated circuit chip of each of the optical transceiver subsystems having the micro-LED array and the photodetector array faces the passive interposer layer.

6. The module of claim 5, wherein the passive interposer layer comprises apertures located around the positions of the micro-LED array and the photodetector array of the optical transceiver subsystem.

7. The module of claim 6, wherein the optical coupling assembly is located in the aperture of the passive interposer layer.

8. An optical interconnect module, comprising: The first module has a first logic and / or memory integrated block and a first plurality of optical transceiver subsystems. Each of the first plurality of optical transceiver subsystems includes an integrated circuit chip, a micro LED array mounted on the surface of the integrated circuit chip, a photodetector array mounted on the surface of the integrated circuit chip, a transmitter circuit system integrated in the integrated circuit chip, and a receiver circuit system integrated in the integrated circuit chip. The first logic and / or memory block is coupled to the first plurality of optical transceiver subsystems through a die-to-die interface. The second module has a second logic and / or memory block and a second plurality of optical transceiver subsystems. Each of the second plurality of optical transceiver subsystems includes an integrated circuit chip, a micro LED array mounted on the surface of the integrated circuit chip, a photodetector array mounted on the surface of the integrated circuit chip, a transmitter circuit system integrated in the integrated circuit chip, and a receiver circuit system integrated in the integrated circuit chip. The second logic and / or memory block is coupled to the second plurality of optical transceiver subsystems through a die-to-die interface. The third module has a third logic and / or memory block and a third plurality of optical transceiver subsystems, each of the third plurality of optical transceiver subsystems including an integrated circuit chip, a micro LED array mounted on the surface of the integrated circuit chip, a photodetector array mounted on the surface of the integrated circuit chip, a transmitter circuit system integrated in the integrated circuit chip, and a receiver circuit system integrated in the integrated circuit chip. The third logic and / or memory block is coupled to the third plurality of optical transceiver subsystems through a die-to-die interface. And multiple fiber bundles, which couple the first multiple optical transceiver subsystems to the second multiple optical transceiver subsystems, the first multiple optical transceiver subsystems to the third multiple optical transceiver subsystems, and the second multiple optical transceiver subsystems to the third multiple optical transceiver subsystems.

9. The optical interconnect module of claim 8, wherein at least one of the first, second, and third logical and / or memory blocks comprises a high-performance memory, and at least another of the first, second, and third logical and / or memory blocks comprises a processor.

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