Semiconductor device

Abstract

The invention provides a semiconductor device capable of realizing miniaturization or high integration, a semiconductor device with high reliability, a semiconductor device with low power consumption, or a semiconductor device with fast operation speed. The semiconductor device includes: a first transistor including first to third conductive layers, a first oxide semiconductor layer, and a charge storage layer; a second transistor including a fourth conductive layer, a fifth conductive layer, and a second oxide semiconductor layer; and a first insulating layer. The first insulating layer is on the first conductive layer and the fourth conductive layer and includes a first opening portion overlapping the first conductive layer and a second opening portion overlapping the fourth conductive layer. The second conductive layer and the fifth conductive layer are located on the first insulating layer. The first oxide semiconductor layer is located in the first opening portion. The charge storage layer is located between the first oxide semiconductor layer and the third conductive layer within the first opening portion. The second oxide semiconductor layer is located in the second opening portion.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device and a memory device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include display devices, light-emitting devices, energy storage devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and methods for driving or manufacturing the aforementioned devices.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that house chips in packages. Additionally, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes all include semiconductor devices. Background Technology

[0004] In recent years, semiconductor devices have been developed, with LSIs, CPUs, and memory being the main components. A CPU is an assembly of semiconductor integrated circuits (including at least transistors and memory) that are fabricated from semiconductor wafers into chips and have electrodes formed as connection terminals. Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0005] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted considerable attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as suitable for use in transistors, while oxide semiconductors are also gaining attention as another type of material.

[0006] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely small in the off state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Additionally, for example, Patent Document 2 discloses a storage device that utilizes the characteristic of low leakage current of transistors using oxide semiconductors to achieve long-term retention of stored content.

[0007] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which multiple memory cells are stacked in an overlapping manner by layering a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of integrated circuits. Additionally, Patent Document 4 discloses a technique for achieving high-density integrated circuits by arranging the channels of transistors using oxide semiconductor films longitudinally.

[0008] Furthermore, Non-Patent Document 2 discloses CAAC-IGZO as a crystalline oxide semiconductor. Non-Patent Document 2 also discloses the growth mechanism of CAAC-IGZO, etc.

[0009] Furthermore, Patent Document 5 discloses a non-volatile memory including an oxide semiconductor layer. Additionally, as shown in Patent Document 6, in a non-volatile semiconductor memory device, storage transistors can be arranged in a three-dimensional manner.

[0010] [Preliminary Technology Documents]

[0011] [Patent Literature]

[0012] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0013] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0014] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0015] [Patent Document 4] Japanese Patent Application Publication No. 2013-211537

[0016] [Patent Document 5] Japanese Patent Application Publication No. 2011-124563

[0017] [Patent Document 6] Japanese Patent Application Publication No. 2007-266143

[0018] [Non-patent literature]

[0019] [Non-patent literature 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53

[0020] [Non-Patent Literature 2] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO: FUNDAMENTALS”, Wiley-SID Series in Display Technology, 2017, pp. 50-150. Summary of the Invention

[0021] The technical problem that the invention aims to solve

[0022] One objective of this invention is to provide a transistor, semiconductor device, or memory device capable of miniaturization or high integration. Another objective is to provide a transistor, semiconductor device, or memory device with high reliability. Another objective is to provide a transistor, semiconductor device, or memory device with low power consumption. Another objective is to provide a transistor, semiconductor device, or memory device with high operating speed. Another objective is to provide a novel transistor, semiconductor device, or memory device. Finally, one objective is to provide a method for manufacturing the aforementioned transistor, semiconductor device, or memory device.

[0023] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims.

[0024] means of solving technical problems

[0025] One aspect of the present invention is a semiconductor device comprising a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first oxide semiconductor layer, a second insulating layer, a third insulating layer, and a charge storage layer. The second transistor includes a fourth conductive layer, a fifth conductive layer, and a second oxide semiconductor layer. The first insulating layer is located on the first and fourth conductive layers and includes a first opening overlapping the first conductive layer and a second opening overlapping the fourth conductive layer. The second conductive layer is located on the first insulating layer, and the fifth conductive layer is located on the first insulating layer. The first oxide semiconductor layer... The body layer has a region along the side of the first insulating layer within the first opening and a region along the top surface of the first conductive layer at the bottom of the first opening. The third conductive layer has a region within the first opening. The second insulating layer, the third insulating layer, and the charge storage layer are located between the first oxide semiconductor layer and the third conductive layer within the first opening. The second insulating layer has a region sandwiched between the first oxide semiconductor layer and the charge storage layer. The third insulating layer has a region sandwiched between the charge storage layer and the third conductive layer. The second oxide semiconductor layer has a region along the side of the first insulating layer within the second opening and a region along the top surface of the fourth conductive layer at the bottom of the second opening.

[0026] In addition, in the above-described manner, the second insulating layer preferably comprises one or more selected from silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, and aluminum oxide.

[0027] In addition, in the above-described manner, the third insulating layer preferably comprises one or more selected from silicon oxide, silicon oxynitride, aluminum oxide, and hafnium oxide.

[0028] In addition, in the above-described manner, it is preferred that the second transistor includes a gate insulating layer on a second oxide semiconductor layer, the second insulating layer comprising, as a first material, one selected from silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, and aluminum oxide, and the gate insulating layer comprising the first material.

[0029] In addition, in the above-described manner, it is preferred that the second transistor includes a gate insulating layer on a second oxide semiconductor layer, and the third insulating layer, as a second material, comprises one selected from silicon oxide, silicon oxynitride, aluminum oxide, and hafnium oxide, and the gate insulating layer comprises the second material.

[0030] In addition, in the above-described manner, it is preferable that the second conductive layer includes a third opening that overlaps with the first opening, and the first oxide semiconductor layer has a region within the third opening along the sidewall of the second conductive layer.

[0031] In addition, in the above-described manner, it is preferable that the fifth conductive layer includes a fourth opening that overlaps with the second opening, and the second oxide semiconductor layer has a region within the fourth opening along the sidewall of the fifth conductive layer.

[0032] Another aspect of the present invention is a semiconductor device comprising a first memory cell array, a second memory cell array, and a first insulating layer. The first memory cell array includes a plurality of first transistors, and the second memory cell array includes a plurality of memory cells. Each memory cell includes a second transistor and a capacitor. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first oxide semiconductor layer, a second insulating layer, a third insulating layer, and a charge storage layer. The first conductive layer is used as one of the source and drain electrodes of the first transistor, the second conductive layer is used as the other of the source and drain electrodes of the first transistor, and the third conductive layer is used as the control gate electrode of the first transistor. The second transistor includes a fourth conductive layer, a fifth conductive layer, and a second oxide semiconductor layer. The capacitor includes a fourth conductive layer, a seventh conductive layer, and a fourth insulating layer between the fourth and seventh conductive layers. The fourth conductive layer is used as one of the source and drain electrodes of the first transistor and also serves as the capacitor. One electrode, the fifth conductive layer is used as the other of the source and drain electrodes of the first transistor, the fourth insulating layer is used as the dielectric of the capacitor, the first insulating layer is located on the first conductive layer and the fourth conductive layer, the first insulating layer includes a first opening overlapping the first conductive layer and a second opening overlapping the fourth conductive layer, the first oxide semiconductor layer has a region along the side of the first insulating layer in the first opening and a region along the top surface of the first conductive layer at the bottom of the first opening, the third conductive layer has a region in the first opening, the second insulating layer, the third insulating layer and the charge storage layer are located between the first oxide semiconductor layer and the third conductive layer in the first opening, the second insulating layer has a region sandwiched between the first oxide semiconductor layer and the charge storage layer, the third insulating layer has a region sandwiched between the charge storage layer and the third conductive layer, the second oxide semiconductor layer has a region along the side of the first insulating layer in the second opening and a region along the top surface of the fourth conductive layer at the bottom of the second opening.

[0033] In addition, in the above-described manner, it is preferable that the second conductive layer includes a third opening that overlaps with the first opening, and the first oxide semiconductor layer has a region within the third opening along the sidewall of the second conductive layer.

[0034] In addition, in the above-described manner, it is preferable that the fifth conductive layer includes a fourth opening that overlaps with the second opening, and the second oxide semiconductor layer has a region within the fourth opening along the sidewall of the fifth conductive layer.

[0035] In addition, in the above-described manner, the charge storage layer preferably comprises one or more metallic elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys with these metallic elements as components, or alloys combining these metallic elements.

[0036] In addition, in the above-described manner, the charge storage layer preferably comprises a metal nitride or a metal oxide.

[0037] In addition, in the above-described manner, the charge storage layer preferably comprises one or more selected from silicon and germanium.

[0038] In addition, in the above-described manner, the charge storage layer preferably comprises one or more selected from silicon nitride and silicon oxynitride.

[0039] Invention Effects

[0040] According to one aspect of the present invention, a transistor, semiconductor device, or memory device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a transistor, semiconductor device, or memory device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a transistor, semiconductor device, or memory device with low power consumption can be provided. Furthermore, according to one aspect of the present invention, a transistor, semiconductor device, or memory device with high operating speed can be provided. Furthermore, according to one aspect of the present invention, a novel transistor, semiconductor device, or memory device can be provided. Furthermore, according to one aspect of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, or memory device can be provided.

[0041] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims. Attached Figure Description

[0042] Figure 1A This is a plan view showing an example of a semiconductor device. Figure 1B and Figure 1C This is a cross-sectional view showing an example of a semiconductor device. Figure 1D This is a plan view showing an example of a semiconductor device.

[0043] Figure 2A and Figure 2B This is a cross-sectional view showing an example of a semiconductor device.

[0044] Figure 3A and Figure 3B This is a cross-sectional view showing an example of a semiconductor device.

[0045] Figure 4A This is a plan view showing an example of a semiconductor device. Figure 4B This is a cross-sectional view showing an example of a semiconductor device.

[0046] Figure 5A and Figure 5B This is a circuit diagram illustrating an example of a semiconductor device.

[0047] Figure 6 This is a circuit diagram illustrating an example of a semiconductor device.

[0048] Figure 7A This is a plan view showing an example of a semiconductor device. Figure 7B This is a cross-sectional view showing an example of a semiconductor device.

[0049] Figure 8A This is a cross-sectional view showing an example of a semiconductor device. Figure 8B and Figure 8C This is a circuit diagram illustrating an example of a semiconductor device.

[0050] Figures 9A to 9C This is a cross-sectional view showing an example of a semiconductor device.

[0051] Figure 10 This is a cross-sectional view showing an example of a semiconductor device.

[0052] Figure 11A and Figure 11B This is a cross-sectional view showing an example of a semiconductor device.

[0053] Figure 12A and Figure 12B This is a cross-sectional view showing an example of a semiconductor device.

[0054] Figures 13A to 13D This is a cross-sectional view illustrating an example of a method for manufacturing an oxide semiconductor.

[0055] Figures 14A to 14D This is a cross-sectional view showing an example of an oxide semiconductor.

[0056] Figure 15A and Figure 15B This is a cross-sectional view showing an example of a semiconductor device.

[0057] Figure 16A and Figure 16B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0058] Figure 17A and Figure 17B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0059] Figure 18A This is a cross-sectional view showing an example of a semiconductor device. Figure 18B This is a circuit diagram illustrating an example of a semiconductor device.

[0060] Figure 19 This is a cross-sectional view showing an example of a semiconductor device.

[0061] Figure 20A and Figure 20B This is a plan view showing an example of a semiconductor device.

[0062] Figure 21 This is a cross-sectional view showing an example of a semiconductor device.

[0063] Figure 22A This is a plan view showing an example of a semiconductor device. Figure 22B This is a cross-sectional view showing an example of a semiconductor device.

[0064] Figure 23A and Figure 23B This is a plan view showing an example of a semiconductor device.

[0065] Figure 24 This is a cross-sectional view showing an example of a semiconductor device.

[0066] Figure 25 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0067] Figure 26 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0068] Figures 27A to 27H This is a diagram illustrating an example of the circuit structure of a memory cell.

[0069] Figure 28A and Figure 28B This is a three-dimensional diagram illustrating an example of the structure of a semiconductor device.

[0070] Figure 29 This is a block diagram illustrating the CPU.

[0071] Figure 30A and Figure 30B It is a 3D diagram of a semiconductor device.

[0072] Figure 31A and Figure 31B It is a 3D diagram of a semiconductor device.

[0073] Figure 32A and Figure 32B It is a diagram showing the hierarchy of various storage devices.

[0074] Figure 33It is a 3D diagram of a semiconductor device.

[0075] Figure 34A and Figure 34B This is a diagram showing an example of an electronic component.

[0076] Figures 35A to 35C This is a diagram illustrating an example of a large computer. Figure 35D This is a diagram illustrating an example of a space device. Figure 35E This is a diagram illustrating an example of a storage system that can be used in a data center.

[0077] Figure 36 This is a circuit diagram illustrating an example of a semiconductor device. Detailed Implementation

[0078] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0079] Note that in the invention structure described below, the same symbols are used in different figures to represent the same parts or parts with the same function, and repeated descriptions are omitted. Additionally, when representing parts with the same function, the same shading lines are sometimes used without special additional symbols.

[0080] Furthermore, for ease of understanding, the positions, sizes, and extents of the constituent elements shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0081] Note that, for convenience, ordinal numbers such as "first" and "second" are used in this specification, etc., but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, the ordinal numbers used for constituent elements in one part of this specification may sometimes differ from those used for the same constituent element in other parts of this specification or in the claims.

[0082] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning on or off), etc. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0083] In this specification and other materials, transistors that use oxide semiconductors or metal oxides as semiconductor layers and transistors that include oxide semiconductors or metal oxides in the channel formation region are sometimes referred to as OS transistors. Additionally, transistors that include silicon in the channel formation region are sometimes referred to as Si transistors.

[0084] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (also called a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) that forms a channel, and current can flow between the source and drain through the channel-forming region. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0085] Furthermore, in cases where transistors of different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0086] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration below 0.1 atomic% can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity in the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1, Group 2, Group 13, Group 14, and Group 15 elements, as well as transition metals other than the main components of the oxide semiconductor. Specifically, examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water sometimes also acts as an impurity. Furthermore, the incorporation of impurities can sometimes lead to oxygen vacancies (also referred to as V vacancies) in the oxide semiconductor. O The formation of ).

[0087] Note that in this specification, oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content.

[0088] For example, the content of elements such as hydrogen, oxygen, carbon, and nitrogen in the membrane can be analyzed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less or 1 atomic% or less). When comparing elemental contents, it is more preferable to use a combined analysis of SIMS and XPS.

[0089] Furthermore, depending on the circumstances, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be replaced with a "conductive film." Similarly, an "insulating film" can be replaced with an "insulating layer."

[0090] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10 degrees and less than 10 degrees. Therefore, it also includes states where the angle is greater than or equal to -5 degrees and less than 5 degrees. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -20 degrees and less than 20 degrees. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 80 degrees and less than 100 degrees. Therefore, it also includes states where the angle is greater than or equal to 85 degrees and less than 95 degrees. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 70 degrees and less than 110 degrees.

[0091] In this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, and other elements with various functions.

[0092] In this specification, unless otherwise specified, off-state current refers to the leakage current between the source and drain of a transistor when it is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and source. gs Below the threshold voltage V th (V in p-channel transistor) gs Higher than V th ) state.

[0093] In this specification, normally-on characteristic refers to the state where a channel exists and current flows through the transistor even when no voltage is applied to the gate. Normally-off characteristic refers to the state where no current flows through the transistor when no potential is applied to the gate or when the gate is supplied with a ground potential.

[0094] In this specification and the like, the top surface shape of a constituent element refers to the edge shape of the constituent element when viewed from above. Furthermore, "viewing from above" refers to the view taken from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0095] In this specification, "generally consistent top surface shape" means that at least a portion of the edges of each layer in a stack overlaps. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, in practice, there are cases where the edges do not overlap; sometimes the upper layer is inside or outside the lower layer. In such cases, it can also be said that the "top surface shape is generally consistent." When the top surface shape is consistent or generally consistent, it can also be said that the ends are aligned or substantially aligned, or that the side ends are consistent or generally consistent.

[0096] In this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region where the angle (also referred to as the cone angle) formed by the inclined side surface of the constituent element and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Here, the side surface of the constituent element, the substrate surface, and the surface to be formed do not necessarily have to be completely flat; they may be approximately planar with slight curvature or approximately planar with slight irregularities.

[0097] In this specification and the like, when it is stated that "A is in contact with B", at least a portion of A is in contact with B. Therefore, for example, it can be referred to as A having a region in contact with B.

[0098] In this specification, etc., when it is stated that "A is located on B", at least a portion of A is located on B. Therefore, for example, it can be said that A has a region located on B.

[0099] In this specification, etc., when there is a description of A covering B, at least a portion of A covers B. Therefore, for example, it can be referred to as A having a region that covers B.

[0100] In this specification and the like, when it is stated that "A overlaps with B", at least a portion of A overlaps with B. Therefore, for example, it can be said that A has a region that overlaps with B.

[0101] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is disconnected due to the shape of the surface on which it is formed (e.g., a step).

[0102] Note that arrows indicating the X, Y, and Z directions are sometimes included in the accompanying drawings and other materials of this specification. Note that in this specification, "X direction" refers to the direction along the X-axis, and unless explicitly stated otherwise, its direction (clockwise or counterclockwise) is not always distinguished. The same applies to "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are intersecting directions. For example, the X, Y, and Z directions are orthogonal to each other.

[0103] (Implementation Method 1)

[0104] In this embodiment, a semiconductor device according to one aspect of the present invention will be described.

[0105] One aspect of the semiconductor device of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a first insulating layer, and a second insulating layer.

[0106] A first insulating layer is located on a first conductive layer, and a second conductive layer is located on the first insulating layer. The first insulating layer and the second conductive layer include an opening extending into the first conductive layer. An oxide semiconductor layer is in contact with at least the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer within the opening. The second insulating layer is located on the oxide semiconductor layer within the opening. A third conductive layer overlaps with the oxide semiconductor layer within the opening, separated by the second insulating layer. Note that the opening is also referred to as an aperture.

[0107] The first conductive layer is used as one of the source and drain electrodes of the transistor. The second conductive layer is used as the other of the source and drain electrodes of the transistor. The third conductive layer is used as the gate electrode of the transistor, and the second insulating layer is used as the gate insulating layer.

[0108] In this specification, etc., it is simply referred to as "when viewed in section," but more specifically, it can sometimes be changed to "when viewed in section along the same direction." For example, when explaining the relationship between multiple constituent elements, the relationship when viewed in section along the same direction is explained. In this case, the relationship between the multiple constituent elements can be explained with reference to a cross-sectional view.

[0109] In one embodiment of the present invention, the source and drain electrodes of the transistor are located at different heights (e.g., at a height perpendicular to the substrate surface or insulating plane on which the transistor is disposed), so the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction has a height (vertical) component, therefore the transistor of one embodiment of the present invention can also be referred to as a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc.

[0110] Because the source electrode, semiconductor layer, and drain electrode can be stacked, the area occupied by a transistor of one aspect of the present invention can be much smaller than that of a so-called planar transistor in which the semiconductor layer is configured as a planar shape.

[0111] Note that in this specification, etc., "end-aligned" means that at least a portion of the edges of each layer in a stack overlaps when viewed from above. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, strictly speaking, sometimes the edges do not overlap and the edge of the upper layer is inside the edge of the lower layer or the edge of the upper layer is outside the edge of the lower layer; these cases can also be described as "end-aligned".

[0112] Note that, generally speaking, it is sometimes difficult to clearly distinguish between "completely identical" and "substantially identical". Therefore, in this specification and other materials, "identical" sometimes includes both cases of complete identicalness and cases of substantial identicalness.

[0113] <Example 1 of semiconductor device structure>

[0114] Reference Figures 1A to 1D The structure of a semiconductor device according to one aspect of the present invention is described. Figure 1A It is a plan view of a semiconductor device including transistor 500. Figure 1B It corresponds to Figure 1A The cross-sectional view of the dotted line A1-A2 shown. Figure 1C It corresponds to Figure 1A The cross-sectional view shown is the dotted-dash line A3-A4. Figure 1D This is a cross-sectional view of the XY plane including the insulating layer 280. Note that in Figure 1A In the plan view, some constituent elements are omitted for clarity. Sometimes, some constituent elements are also omitted in the plan view shown below.

[0115] Transistor 500 is used as a storage element. In particular, transistor 500 can be used as a non-volatile storage element. By arranging the storage cells including transistor 500 in a matrix, a storage device capable of storing large amounts of data can be constructed. Storage cells including transistor 500 can, for example, be used as NOR storage cells, NAND storage cells, etc. Referring later to Figure 5... Figure 6 and Figure 36 This diagram illustrates a memory cell array using NOR and NAND memory cells. Note that transistor 500 is sometimes referred to as a storage transistor. Additionally, transistor 500 can be represented as non-volatile memory. Furthermore, semiconductor devices including transistor 500 are sometimes referred to as non-volatile semiconductor devices or non-volatile memory devices, etc.

[0116] Figures 1A to 1DThe semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 500 on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 283 on the transistor 500, and an insulating layer 285. The insulating layers 210, 280, 283, and 285 are used as interlayer films.

[0117] Transistor 500 includes a conductive layer 520, a conductive layer 540 on an insulating layer 280, an oxide semiconductor layer 530, an insulating layer 551 on the oxide semiconductor layer 530, a charge storage layer 552 on the insulating layer 551, an insulating layer 553 on the charge storage layer 552, and a conductive layer 560 on the insulating layer 553. The conductive layers 520 and 540 are located at different heights.

[0118] In transistor 500, oxide semiconductor layer 530 is used as semiconductor layer, conductive layer 560 is used as gate electrode, conductive layer 520 is used as one of source electrode and drain electrode, and conductive layer 540 is used as the other of source electrode and drain electrode.

[0119] In one aspect of the semiconductor device of the present invention, a metal oxide (also known as an oxide semiconductor) used as a semiconductor can be used as the oxide semiconductor layer 530.

[0120] The region of the oxide semiconductor layer 530 that contacts the conductive layers 520 and 540 is preferably used as a low-resistance region.

[0121] An oxide semiconductor layer 530 is disposed inside the opening in the insulating layer 280. Furthermore, in the transistor 500, one of the source and drain electrodes (here, conductive layer 520) is located below and the other of the source and drain electrodes (here, conductive layer 540) is located above, thus current flows longitudinally. That is, a channel is formed along the sidewall of the opening in the insulating layer 280.

[0122] An insulating layer 551, a charge storage layer 552, and an insulating layer 553 are stacked between an oxide semiconductor layer 530 and a conductive layer 560. The insulating layer 551 has a region sandwiched between the oxide semiconductor layer 530 and the charge storage layer 552. The insulating layer 553 has a region sandwiched between the charge storage layer 552 and the conductive layer 560. Information is written to the transistor 500 by changing the amount of charge stored in the charge storage layer. Furthermore, charge carriers such as electrons and holes can be stored in the charge storage layer. For example, a conductor can be used as the charge storage layer. When a conductor is used as the charge storage layer, it is preferable to surround the conductor with an insulator. Alternatively, an insulator with the function of trapping charge carriers can be used as the charge storage layer. For example, by applying a positive high potential to the gate with the source or drain as a reference, electrons are injected from the oxide semiconductor layer 530 through the insulating layer 551 and stored in the charge storage layer. Alternatively, for example, by applying a negative high potential to the gate with the source or drain as a reference, electrons are released from the charge storage layer to the oxide semiconductor layer 530 through the insulating layer 551. Furthermore, the charge storage layer can retain the stored charge.

[0123] In the memory cell array, multiple transistors 500 can be arranged in a row.

[0124] Figure 2A An example structure is shown when two transistors 500 are arranged in the Y direction. Figure 2A An example is shown in which adjacent transistors 500 share conductive layers 540 and 520.

[0125] in addition, Figure 2B An example of a structure with multiple transistors connected in series is shown. Figure 2B Four transistors 500 (hereinafter referred to as transistor 500_1, transistor 500_2, transistor 500_3, and transistor 500_4, respectively, arranged in the Y direction) are shown. Transistor 500 (e.g., transistor 500_2) shares conductive layer 520 with the adjacent transistor 500 (e.g., transistor 500_1), and shares conductive layer 540 with the transistor 500 on the opposite side of the adjacent transistor 500 (e.g., transistor 500_3).

[0126] When the conductivity of the charge storage layer 552 is high, such as Figure 2A and Figure 2B As shown, each of the plurality of adjacently arranged transistors 500 preferably has a charge storage layer 552 disposed separately.

[0127] In addition, adjacent transistors 500 can also share the insulating layer 553. Figure 3A yes Figure 2AIn a modified example, each transistor has an insulating layer 553 as a common insulating layer, which is mainly similar to... Figure 2A Different. Figure 3A In the structure shown, since the ends of the charge storage layer 552 are covered by the insulating layer 553, the leakage current between the charge storage layer 552 and the conductive layer 560 can sometimes be reduced when the conductivity of the charge storage layer 552 is high. Additionally, the leakage current between the charge storage layers 552 included in adjacent transistors 500 can sometimes be reduced.

[0128] In addition, when the charge storage layer 552 has high insulation, multiple adjacent transistors 500 may also be configured with a common charge storage layer 552. Figure 3B An example is shown where two adjacent transistors 500 share a common charge storage layer 552, an insulating layer 551, and an insulating layer 553.

[0129] The conductive layer 560 is sometimes referred to as the control gate or control gate electrode. Additionally, when the conductivity of the charge storage layer 552 is high, it is referred to as the floating gate or floating gate electrode.

[0130] Information can be written to transistor 500 by injecting or releasing charge carriers into or from charge storage layer 552. The threshold voltage of transistor 500 can be altered by injecting or releasing charge carriers into or from charge storage layer 552, thereby changing the current flowing between the source and drain during readout. Carrier injection or release can be performed using tunneling current flowing through insulating layer 551 between oxide semiconductor layer 530 and charge storage layer 552. Therefore, insulating layer 551 is sometimes referred to as a tunneling insulating layer.

[0131] exist Figures 1A to 1C In the semiconductor device shown, Figure 1C In the cross-section shown, the end of the charge storage layer 552 is located outside the end of the conductive layer 560. That is, in the direction along the Y-axis, the end of the charge storage layer 552 is positioned outside the end of the conductive layer 560, and the top surface of the charge storage layer 552 has a region not covered by the conductive layer 560. By employing... Figure 1C In the structure shown, insulating layer 551, charge storage layer 552 and insulating layer 553 are sandwiched between conductive layer 560 and conductive layer 540, so leakage current between conductive layer 560 and conductive layer 540 can be suppressed.

[0132] On the other hand, Figure 1B In the cross-section shown, the end of the charge storage layer 552 is located outside the end of the conductive layer 560. This is because the conductive layer 560 extends along the X-axis.

[0133] In addition, such as Figure 4A and Figure 4B As shown, along the Y-axis, the end of the charge storage layer 552 can also be located inside the end of the conductive layer 560. Here, Figure 4B It corresponds to Figure 4A The diagram shown is an example of the dotted lines A3-A4. (This is achieved by using...) Figure 4B The structure shown increases the overlapping area of ​​the charge storage layer 552 and the conductive layer 560. Therefore, the capacitance between the charge storage layer 552 and the conductive layer 560 can be increased. By increasing this capacitance, the write efficiency of the storage element can sometimes be improved.

[0134] In addition, corresponding to Figure 4A The attached diagram showing the dotted lines A1-A2 is similar to... Figure 1B Similarly, the explanation is omitted here.

[0135] like Figure 1B and Figure 1C As shown, the insulating layer 280 and the conductive layer 540 have openings 590 that extend to the conductive layer 520. Additionally, the conductive layer 520 has a recess that overlaps with the opening 590. The opening 590 and the recess in the conductive layer 520 form a continuous opening. The bottom of this continuous opening is used as the top surface of the conductive layer 520.

[0136] The sidewalls of the opening 590 are the sidewalls of the insulating layer 280 and the conductive layer 540. The opening 590 includes openings in the insulating layer 280 and openings in the conductive layer 540. In other words, the opening in the region of the insulating layer 280 overlapping with the conductive layer 520 is part of the opening 590, and the opening in the region of the conductive layer 540 overlapping with the conductive layer 520 is another part of the opening 590. The opening 590 provided in the insulating layer 280 is designated as opening 590a, and the opening 590 provided in the conductive layer 540 is designated as opening 590b.

[0137] At least a portion of the constituent elements of transistor 500 are disposed inside opening 590. Specifically, oxide semiconductor layer 530, insulating layer 551, charge storage layer 552, insulating layer 553, and conductive layer 260 are all disposed such that at least a portion of each is located inside opening 590. Oxide semiconductor layer 530 contacts the top surface of conductive layer 520, the side surface of insulating layer 280, and the side surface of conductive layer 540 in opening 590. The angle formed by the top surface of conductive layer 520 (or the top surface of the insulating layer on which conductive layer 520 is disposed, or the top surface of the substrate) and the sidewall of insulating layer 280 of opening 590 is set as angle θ280m. θ280m is preferably an angle of 90 degrees or close to 90 degrees. For example, θ280m is preferably 75 degrees or more and 90 degrees or less.

[0138] The area occupied by transistor 500, specifically, for example, the area of ​​the transistor when viewed from above, is approximately determined by the width of the opening 590. In transistor 500, the channel forming region, source region, and drain region can be arranged at different heights, thereby reducing its area compared to transistors where the semiconductor layer is arranged on a plane and the channel forming region, source region, and drain region are also arranged on a plane. This allows for high integration of the semiconductor device. Furthermore, by using the semiconductor device according to one aspect of the present invention in a memory device, the storage capacity per unit area can be increased.

[0139] Furthermore, in transistor 500, conductive layer 520, which serves as one of the source and drain electrodes, and conductive layer 540, which serves as the other of the source and drain electrodes, are configured at different heights. Additionally, conductive layer 520 can be shared by multiple transistors 500, and similarly, conductive layer 540 can be shared by multiple transistors 500. The conductive layer shared by multiple transistors can also be extended and used for wiring.

[0140] In a semiconductor device according to one aspect of the present invention, since the conductive layers 520 and 540 are disposed at different heights, when the conductive layers 520 and 540 are extended and used as wiring, the wiring using the conductive layer 520 and the wiring using the conductive layer 540 can be configured to cross each other without short-circuiting them. Therefore, the area of ​​the memory cell can be reduced.

[0141] like Figure 1D As shown, the insulating layer 280 is in complete contact with the outer periphery of the oxide semiconductor layer 530. Therefore, the channel formation region of the transistor 500 may be formed entirely around the outer periphery of the oxide semiconductor layer 530 within the opening 590 (the entire area in contact with the insulating layer 280). Furthermore, Figure 1D It can also be described as a cross-sectional view of the XY plane including the channel formation region of the oxide semiconductor layer 530.

[0142] The channel length Lm of transistor 500 is the distance between the source and drain regions. In other words, the channel length Lm of transistor 500 can be determined based on the thickness of the insulating layer 280 on the conductive layer 520. Figure 1C In the diagram, the channel length Lm of transistor 500 is indicated by a dashed double arrow. The channel length Lm is equivalent to the distance between the end of the region where the oxide semiconductor layer 530 contacts the conductive layer 520 and the end of the region where the oxide semiconductor layer 530 contacts the conductive layer 540 in cross-section. In other words, the channel length Lm is equivalent to the length of the side surface of the opening 590 of the insulating layer 280 in cross-section.

[0143] In planar transistors, the minimum channel length is limited by the exposure precision of photolithography, making further miniaturization difficult. However, in the transistor included in a semiconductor device according to one aspect of the present invention, since the channel length corresponds to the thickness of the insulating layer 280, the channel length can be smaller than the minimum value limited by the exposure precision of photolithography (e.g., 60nm or less, 50nm or less, 40nm or less, 30nm or less, 20nm or less, or 10nm or less and 0.1nm or more, 1nm or more, or 5nm or more). As a result, the on-state current of the transistor 500 increases, thereby improving the response speed of the memory element.

[0144] Furthermore, since the channel length of the transistor included in one aspect of the semiconductor device of the present invention depends on the thickness of the insulating layer 280 on the conductive layer 520, for example, even when using a large channel length of 60 nm or more, the occupied area of ​​the transistor, specifically, the area of ​​the transistor when viewed from above, is roughly determined by the width of the opening 590. As described later, the width Dm of the opening 590 is preferably, for example, 5 nm or more, 10 nm or more, or 20 nm or more and 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. For example, when the channel length is 150 nm, the width of the opening 590 can be less than 150 nm. That is, a transistor with an opening width smaller than the channel length can be formed, the occupied area of ​​the transistor can be reduced, and high integration of the semiconductor device can be achieved. By increasing the channel length, the withstand voltage between the source and drain when writing to the memory element can be improved, thereby increasing reliability.

[0145] Furthermore, by setting the channel length of the transistor to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the insulating layer 280 and the formation of the opening 590 in the insulating layer 280.

[0146] Therefore, the channel length of the transistor included in the semiconductor device of one aspect of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more and 1 μm or less, 500 nm or less, or 300 nm or less.

[0147] Furthermore, during data writing and deletion, a high voltage is sometimes applied between the drain and source of transistor 500. Therefore, the channel length Lm of transistor 500 is preferably long enough to withstand the high voltage between the drain and source. Thus, the channel length Lm of transistor 500 can be, for example, 10 nm or more, 20 nm or more, or 30 nm or more. As described above, the occupied area of ​​transistor 500 is approximately determined by the width of the opening 590, and even with a large channel length, the occupied area of ​​the transistor is hardly affected. Therefore, transistor 500 can achieve high voltage withstand capability and integration.

[0148] Furthermore, in transistor 500, the charge storage layer 552 covers both the side and top surfaces of the conductive layer 540, which increases the area of ​​the charge storage layer 552 covering the conductive layer 540 compared to covering only one of the side and top surfaces. When data is written to transistor 500, the electric field between the gate and drain causes carrier injection from the oxide semiconductor layer 530 into the charge storage layer 552, and increasing the area of ​​the charge storage layer 552 covering the conductive layer 540 improves the write efficiency. The transistor of one embodiment of the present invention improves write efficiency compared to a planar transistor.

[0149] Note that the above describes an example of using conductive layer 540 as the drain. The same applies when conductive layer 520 is used as the drain. Figure 1B In the structure shown, an oxide semiconductor layer 530 is formed by embedding a recess in the conductive layer 520. Therefore, an electric field can be applied to the drain from both the bottom and side directions. This improves write efficiency.

[0150] Furthermore, in planar transistors where the semiconductor layer is formed as an island, the island-shaped semiconductor layer has an end at the boundary between the channel formation region and the drain formation region. When heat is generated due to the current flowing through the transistor, the end of the island-shaped semiconductor layer in the channel width direction may be significantly affected by the heat. This heat generation may lead to a decrease in breakdown voltage, and since transistors with large channel widths have large current flows, the effect is sometimes more pronounced. On the other hand, in transistor 500, since the semiconductor layer can be disposed along the sidewall of the opening of the insulating layer, the semiconductor layer may not have an end at the boundary between the channel formation region and the drain formation region. Therefore, the source and drain withstand voltages of the transistor can be improved. Furthermore, the breakdown voltage between the gate and drain or between the gate and source can also be improved. Therefore, when a high electric field is applied between the drain and source, between the gate and source, or between the gate and drain during writing and erasure, transistor degradation can be suppressed and the reliability of the memory element can be improved.

[0151] In addition, such as Figure 1D As shown, the oxide semiconductor layer 530 and the conductive layer 260 are arranged in a concentric circle. Therefore, the side of the conductive layer 260 located at the center faces the side of the oxide semiconductor layer 230. In other words, when viewed from above, the entire outer periphery of the oxide semiconductor layer 530 forms the channel formation region. At this time, for example, the channel width of the transistor 500 is determined based on the length of the outer periphery of the oxide semiconductor layer 530. That is, it can be said that the channel width of the transistor 500 can be determined based on the size of the width of the opening 590 (which is the diameter when the opening 590 is circular when viewed from above). Figure 1C and Figure 1D In the diagram, a double-headed arrow with a double-dotted line indicates the width Dm of the opening 590. Figure 1D In the diagram, the double-headed dotted arrow represents the channel width Wm of transistor 500. By increasing the width Dm of the opening 590, the channel width per unit area can be increased, thereby increasing the on-state current.

[0152] When forming the opening 590 using photolithography, the minimum value of the opening 590's width Dm depends on the exposure precision of the photolithography. The width D of the opening 590 is preferably, for example, 5 nm or more, 10 nm or more, or 20 nm or more but less than 100 nm, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 590 is circular in top view, the width Dm of the opening 590 is equivalent to the diameter of the opening 590, and the channel width Wm can be calculated as "D×π".

[0153] Furthermore, by making the channel length Lm of transistor 500 smaller than the channel width Wm of transistor 500, the current drive capability of the transistor can be improved. Therefore, for example, the write speed of the memory element can be increased.

[0154] Furthermore, by making the channel length Lm of transistor 500 greater than the channel width Wm of transistor 500, the breakdown voltage between the source and drain of the transistor can be improved. Therefore, for example, the rewrite resistance of the memory element can be improved.

[0155] Furthermore, by forming the opening 590 in a circular manner when viewed from above, the oxide semiconductor layer 530 and the conductive layer 560 are arranged in a concentric circle. This allows a gate electric field to be applied to the oxide semiconductor layer 530 in a substantially uniform manner.

[0156] Note that in this embodiment, an example is shown where the opening 590 is circular when viewed from above, but the present invention is not limited thereto. For example, the opening 590 may also be in a generally circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a shape in which the corners of the quadrilateral or other polygons are rounded when viewed from above.

[0157] like Figure 1B and Figure 1C As shown, a recess overlapping the opening 590 is formed in the conductive layer 520, and at least a portion of the oxide semiconductor layer 530, insulating layer 551, charge storage layer 552, insulating layer 553, and conductive layer 560 are formed in such a way that they are embedded in the recess. By adopting this structure, the gate electric field of the conductive layer 560 can be easily applied to the oxide semiconductor layer 530 near the conductive layer 520.

[0158] Note that sometimes the conductive layer 520 does not have recesses.

[0159] Furthermore, by having regions where conductive layers 520 and 560 overlap, for example, a gate electric field can be easily applied to the channel formation region of the oxide semiconductor layer 530, which can sometimes reduce the write voltage of the memory element. This can, in turn, reduce the power consumption of the semiconductor device.

[0160] Refer to Figure 5 to illustrate an application example of a memory cell including transistor 500.

[0161] Figure 5A An example circuit diagram of a memory cell array 601 including multiple NOR memory cells 602 is shown. Each memory cell 602 includes a transistor M1. The transistor M1 may be the transistor 500 described above.

[0162] In memory cell 602, one of the source and drain terminals of transistor M1 is connected to wiring BL, and the other is connected to wiring SL. Additionally, the control gate of transistor M1 is connected to wiring WL. Wiring WL is used as a word line, and wiring BL is used as a bit line.

[0163] The memory cell array 601 includes multiple wirings BL, multiple wirings SL, and multiple wirings WL. A wiring BL is connected to each transistor M1 included in multiple memory cells 602 arranged in the same column. A wiring SL is connected to each transistor M1 included in multiple memory cells 602 arranged in the same column. A wiring WL is connected to each transistor M1 included in multiple memory cells 602 arranged in the same row.

[0164] in addition, Figure 5B The shown memory cell array 601b includes multiple NOR memory cells 602, and the wiring SL and the connection between the memory cells 602 are similar to those of the NOR memory cells 602. Figure 5A Different. Figure 5B In memory cell 602, one of the source and drain terminals of transistor M1 is connected to wiring BL, and the other is connected to wiring SL. Additionally, the control gate of transistor M1 is connected to wiring WL. Figure 5B In this configuration, a wiring SL is connected to each transistor M1 included in a plurality of memory cells 602 arranged on the same row.

[0165] In the memory cell array 601b, the same signal can be simultaneously supplied to the control gate and one of the source and drain in the transistors M1 included in the plurality of memory cells 602 arranged in the same row. When the transistor M1 is an n-channel transistor, for example, by supplying a negative potential to one of the source and drain relative to the control gate, data deletion can be performed simultaneously in the plurality of memory cells 602 arranged in the same row.

[0166] Figure 6 An example circuit diagram of a memory cell array 611 including multiple NAND memory cells 612 is shown. Each memory cell 612 includes transistors M[0] to M

[31] , transistor S1, and transistor S2 connected in series. Transistors M[0] to M

[31] may use the aforementioned transistor 500.

[0167] In each of transistors M[0] to M

[31] , transistor S1, and transistor S2, one of the source and drain will be referred to as the first terminal, and the other of the source and drain will be referred to as the second terminal. The first terminal of transistor M[k] is connected to the second terminal of transistor M[k-1], and the second terminal of transistor M[k] is connected to the first terminal of transistor M[k+1]. Here, k is an integer greater than 2 and less than 30.

[0168] The first terminal of transistor S1 is connected to wiring SL, and the second terminal is connected to the first terminal of transistor M[0]. The first terminal of transistor S2 is connected to the second terminal of transistor M

[31] , and the second terminal is connected to wiring BL.

[0169] The memory cell array 611 includes multiple wirings BL. One wiring BL is connected to one memory cell 612. In addition, the memory cell array 611 includes wirings SG1, SG2, WL[0] to WL

[31] .

[0170] Wiring SG1 is connected to the gate of each transistor S1 in the plurality of memory cells 612. Wiring SG2 is connected to the gate of each transistor S2 in the plurality of memory cells 612. Wiring WL[0] to wiring WL

[31] are connected to each transistor M[0] to transistor M

[31] in the plurality of memory cells 612.

[0171] Wiring SG1 and wiring SG2 are used to select the memory cell 612 when performing write, read, delete and other operations.

[0172] Figure 6 An example of a wiring connection with a storage unit 612 is shown, but one aspect of the invention is not limited thereto.

[0173] <Structure Example of a Semiconductor Device 2>

[0174] Reference Figure 7A , Figure 7B and Figure 8A An example of the structure of a semiconductor device according to one aspect of the present invention is provided. Figure 7A It is a plan view of a semiconductor device including transistor 500, transistor 200 and capacitor 100. Figure 7B It corresponds to Figure 7A The cross-sectional view shown is the dotted-dash line A7-A8. Figure 8A It corresponds to Figure 7A The cross-sectional view shown is for the dashed-dot lines A5-A6. Additionally, corresponding to... Figure 7A The cross-sectional view of the dotted-dash line A1-A2 shown can be referred to Figure 1B Note that in Figure 7A In the plan view, some constituent elements are omitted for clarity. Sometimes, some constituent elements are also omitted in the plan view shown below.

[0175] Figure 7A , Figure 7B and Figure 8A The semiconductor device shown includes a transistor 500 and a memory cell 150. As described above, the transistor 500 can be used for... Figure 5A and Figure 5B The storage unit 602 shown or Figure 6 The storage unit 612 shown is an example.

[0176] like Figure 8BAs shown, a memory cell array 621 can be constructed by arranging multiple memory cells 150 in a matrix. Here, transistor 200 can be used as the transistor M1 included in the memory cell 150, and capacitor 100 can be used as the capacitor CA. One of the source and drain terminals of transistor M1 is connected to one of the pair of electrodes of capacitor CA. The other of the source and drain terminals of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The other of the pair of electrodes of capacitor CA is connected to wiring CAL.

[0177] Here, wiring BIL corresponds to conductive layer 240, wiring WOL corresponds to conductive layer 260, and wiring CAL corresponds to conductive layer 110.

[0178] in addition, Figure 8C A modified example of the memory cell array 621 is shown, in which two adjacent memory cells 150 in the X direction share a wiring BIL. Additionally, a wiring BIL is connected to a plurality of memory cells 150 arranged in the Z direction. Figure 8C In the memory cell array shown, different wiring WOLs are connected to each of two adjacent memory cells 150 in the X direction. Figure 8C The storage cell array shown can be used, for example, for storage cell arrays with a three-dimensional structure. Figure 8C Each of the wiring loops shown can, for example, be connected to a storage cell 150 arranged in the Y direction (depth direction).

[0179] One aspect of the semiconductor device of the present invention may include a memory cell array (e.g., memory cell array 601, memory cell array 601b, or memory cell array 611) having a plurality of memory cells using transistors 500 (e.g., memory cells 602 or 612) and a memory cell array (e.g., memory cell array 621) having a plurality of memory cells using transistors 200 (e.g., memory cells 150). Additionally, as... Figure 7A , Figure 7B and Figure 8A As shown, transistor 500 and a portion of transistor 200 are disposed on the same insulating layer ( Figure 7B and Figure 8A The opening of the insulating layer 280 can be manufactured through a common process.

[0180] Regarding the transistor 500, please refer to... Figures 1A to 1D The transistor 500 is shown.

[0181] Transistor 200 includes a conductive layer 120, a conductive layer 540 on an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 551 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 551. The conductive layers 120 and 240 are located at different heights.

[0182] In transistor 200, oxide semiconductor layer 230 is used as semiconductor layer, conductive layer 260 is used as gate electrode, insulating layer 551 is used as gate insulating layer, conductive layer 120 is used as one of source electrode and drain electrode, and conductive layer 240 is used as the other of source electrode and drain electrode.

[0183] In one aspect of the semiconductor device of the present invention, a metal oxide (also known as an oxide semiconductor) used as a semiconductor can be used as the oxide semiconductor layer 230.

[0184] The region of oxide semiconductor layer 230 that contacts conductive layer 120 and conductive layer 240 is preferably used as a low resistance region.

[0185] The oxide semiconductor layer 230 is disposed inside the opening 290 included in the insulating layer 280. Furthermore, in the transistor 200, one of the source and drain electrodes (here, the conductive layer 120) is located below, and the other of the source and drain electrodes (here, the conductive layer 240) is located above, so current flows longitudinally. That is, a channel is formed along the sidewall of the opening 290a. The channel length L of the transistor 200 is the distance between the end of the region where the oxide semiconductor layer 230 contacts the conductive layer 120 and the end of the region where the oxide semiconductor layer 230 contacts the conductive layer 240 in cross-section. In other words, the channel length L is equivalent to the length of the side surface of the insulating layer 280 on the side of the opening 290a in cross-section.

[0186] The insulating layer 551 is shared by transistors 500 and 200. This simplifies the manufacturing process of the semiconductor device. The insulating layer 551 has a region sandwiched between the oxide semiconductor layer 530 and the charge storage layer 552 of transistor 500, and a region sandwiched between the oxide semiconductor layer 230 and the conductive layer 260 of transistor 200.

[0187] An opening 590 is provided in the insulating layer 280 and the conductive layer 540 to reach the conductive layer 520, and an opening 290 is provided in the insulating layer 280 and the conductive layer 240 to reach the conductive layer 120.

[0188] In the opening 290, the opening 290 provided in the insulating layer 280 is referred to as opening 290a, and the opening 290 provided in the conductive layer 240 is referred to as opening 290b.

[0189] At least a portion of the components of transistor 200 are disposed inside opening 290. Specifically, each of oxide semiconductor layer 230, insulating layer 551, and conductive layer 260 is disposed such that at least a portion of each is located inside opening 290. Oxide semiconductor layer 230 contacts the top surface of conductive layer 120, the side surface of insulating layer 280, and the side surface of conductive layer 240 in opening 290.

[0190] Capacitor 100 includes a conductive layer 115 on conductive layer 110, an insulating layer 130 on conductive layer 115, and a conductive layer 120 on insulating layer 130. Conductive layer 120 is used as one of a pair of electrodes (sometimes referred to as the upper electrode), conductive layer 115 is used as the other of a pair of electrodes (sometimes referred to as the lower electrode), and insulating layer 130 is used as a dielectric. That is, capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0191] The insulating layer 180 has an opening 190 leading to the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in the opening 190 that contacts the top surface of the conductive layer 110, a region in the opening 190 that contacts the side surface of the insulating layer 180, and a region that contacts at least a portion of the top surface of the insulating layer 180. The insulating layer 130 is disposed with at least a portion located in the opening 190. The conductive layer 120 is disposed with at least a portion located in the opening 190. The conductive layer 120 is preferably disposed in a manner that embeds it into the opening 190.

[0192] The capacitor 100 has a structure in which the upper and lower electrodes are opposed to each other not only on the bottom surface but also on the side surface within the opening 190, separated by a dielectric material. Therefore, the electrostatic capacitance per unit area can be increased. Consequently, the deeper the opening 190, the larger the electrostatic capacitance of the capacitor 100 can be. Thus, by increasing the electrostatic capacitance per unit area of ​​the capacitor 100, the read operation of the storage device can be stabilized. Furthermore, it can promote the miniaturization or high integration of storage devices.

[0193] Figure 7A , Figure 7B and Figure 8A An example is shown where the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. By adopting this structure, miniaturization or high integration of the storage device can be achieved.

[0194] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. Additionally, a conductive layer 120 is provided on the insulating layer 130 in a manner that embeds into the opening 190. A capacitor 100 having this structure can be referred to as a trench capacitor or trench capacitor.

[0195] An insulating layer 280 is disposed on the capacitor 100. That is, the insulating layer 280 is disposed on the conductive layer 115, the insulating layer 130, and the conductive layer 120. In other words, the conductive layer 120 is disposed beneath the insulating layer 280.

[0196] The transistor 200 is arranged to overlap with the capacitor 100. Furthermore, the opening 290 of the structure where the transistor 200 is disposed has a region that overlaps with the opening 190 of the structure where the capacitor 100 is disposed. Additionally, the conductive layer 120 serves as one of the source and drain electrodes of the transistor 200 and as the upper electrode of the capacitor 100. By employing this structure, the transistor 200 and capacitor 100 can be disposed in a top view without significantly increasing the occupied area.

[0197] By placing transistors 500 and 200 above capacitor 100, transistors 500 and 200 are not affected by the heat treatment during the manufacture of capacitor 100. Therefore, in transistors 500 and 200, the degradation of electrical characteristics, such as fluctuations in threshold voltage and increases in parasitic resistance, as well as the increase in non-uniformity of electrical characteristics accompanying the degradation of electrical characteristics, can be suppressed.

[0198] In one aspect of the semiconductor device of the present invention, the memory cell using transistor 500 and the memory cell 150 can be formed on the same substrate. Alternatively, the memory cell using transistor 500 and the memory cell 150 can share a common component. This improves the integration density of the semiconductor device.

[0199] Both transistor 500 and memory cell 150 can be used as storage elements. Furthermore, both transistor 500 and memory cell 150 are non-volatile. That is, data can be retained even after power is cut off. Compared to memory cell 150, transistor 500 is preferably used for applications requiring longer data retention times. For example, transistor 500 can be used as storage. Conversely, compared to transistor 500, memory cell 150 is preferably used for applications requiring faster operating speeds. For example, memory cell 150 can be used in caches, main memory, etc. Additionally, the communication time and power consumption required for communication between the circuitry including the memory cell using transistor 500 and the circuitry including the memory cell 150 can be reduced. Therefore, for example, the communication time and power consumption required when reading data stored in memory to caches, main memory, etc., can be reduced.

[0200] Furthermore, in one embodiment of the semiconductor device of the present invention, transistors 500 and 200 can be formed in the same layer. Additionally, a portion of the constituent elements included in each of transistors 500 and 200 can be formed by processing the same film. In other words, the same manufacturing process can be used. This simplifies the manufacturing process of the semiconductor device and reduces the manufacturing cost.

[0201] Although Figure 7A , Figure 7B and Figure 8A The illustration shows an example where insulating layer 551 is used as the gate insulating layer of transistor 200, but the gate insulating layer of transistor 200 can also be formed as a layer different from insulating layer 551. For example, as Figure 9A As shown, in transistor 200, insulating layer 553 can be used as gate insulating layer. Insulating layer 553 has a region sandwiched between charge storage layer 552 and conductive layer 560 of transistor 500 and a region sandwiched between oxide semiconductor layer 230 and conductive layer 260 of transistor 200.

[0202] In addition, such as Figure 9B As shown, the stack of insulating layer 551 and insulating layer 553 can also be used as the gate insulating layer of transistor 200.

[0203] For example, such as Figure 9C As shown, transistor 200 may also include insulating layer 250. Insulating layer 250 is manufactured through a different process than insulating layers 551 and 553. Alternatively, a portion of insulating layer 250 may be manufactured through a common process with insulating layer 551 or insulating layer 553. For example, when insulating layer 551 or insulating layer 553 has a stacked structure, a portion of the stacked layer may be shared with insulating layer 250.

[0204] The insulating layer 551 preferably provides high coverage of the sidewalls of the opening 590. Furthermore, by reducing the thickness of the insulating layer 551, the voltage between the control gate and source during writing to the transistor 500 can be reduced. Therefore, the power consumption of the memory device can be reduced. By reducing the voltage, the writing time can be reduced. This, in turn, improves the operating speed of the memory device.

[0205] On the other hand, if the thickness of the insulating layer 551 is too small, there is a concern that the number of charge carriers stored in the charge storage layer 552 may decrease due to leakage current. In other words, the retention characteristics of the storage device will deteriorate.

[0206] Therefore, the thickness of the insulating layer 551 can be, for example, 1 nm or more and 20 nm or less. Furthermore, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, etc., are preferably used as the insulating layer 551.

[0207] For example, the thickness of the insulating layer 553 is preferably greater than that of the insulating layer 551. This reduces the tunneling current flowing through the insulating layer 553 and suppresses charge transfer from the charge storage layer 552 to the control gate side. The thickness of the insulating layer 553 can be, for example, 8 nm or more and 30 nm or less. Silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, etc., are preferably used as the insulating layer 553.

[0208] Materials that can be used in charge storage layer 552 will be described later.

[0209] The layer used as the gate insulating layer of transistor 200 preferably has a structure that provides high coverage of the sidewalls of opening 290 and can suppress short circuits between conductive layer 240 and conductive layer 260.

[0210] The layer used as the gate insulating layer of transistor 200 is used as the gate insulating layer of transistor 200. By thinning the gate insulating layer, the gate potential applied when transistor 200 is operating can be reduced. In addition, transistor 200 can be operated at high speed.

[0211] Openings 590 and 290 can be formed, for example, using the same manufacturing process. A conductive film, which will become a conductive layer such as conductive layer 540 or conductive layer 240, is formed on the insulating layer 280, and openings are formed simultaneously in the conductive film and the insulating layer 280, thereby forming openings 590 and 290.

[0212] By simultaneously forming openings, the conductive layer 540 may, for example, include an opening 590b in the region overlapping with the conductive layer 520 without being disposed inside the opening 590a included in the insulating layer 280. That is, the conductive layer 540 may not have a region that contacts the side of the insulating layer 280 in the opening 590a. Similarly, the conductive layer 240 may, for example, include an opening 290b in the region overlapping with the conductive layer 120 without being disposed inside the opening 290a included in the insulating layer 280. That is, the conductive layer 240 may not have a region that contacts the side of the insulating layer 280 in the opening 290a.

[0213] Furthermore, by making the side surface of the conductive layer 540 in the opening 590b consistent with or substantially consistent with the side surface of the insulating layer 280 in the opening 590a, the thickness distribution of the oxide semiconductor layer 530 disposed inside the opening 590 can be made uniform. Additionally, separation of the oxide semiconductor layer 530 due to the step between the conductive layer 540 and the insulating layer 280 can be suppressed. Similarly, by making the side surface of the conductive layer 240 in the opening 290b consistent with or substantially consistent with the side surface of the insulating layer 280 in the opening 290a, the thickness distribution of the oxide semiconductor layer 230 disposed inside the opening 290 can be made uniform. Additionally, separation of the oxide semiconductor layer 230 due to the step between the conductive layer 240 and the insulating layer 280 can be suppressed.

[0214] When the oxide semiconductor layer 530 contacts not only the side surface of the conductive layer 540 but also its top surface, for example, compared to the case where the oxide semiconductor layer 530 contacts only the side surface of the conductive layer 540 but not its top surface, the contact area between the oxide semiconductor layer 530 and the conductive layer 540 can be increased. Therefore, the contact resistance between the oxide semiconductor layer 530 and the conductive layer 540 can be reduced. Similarly, when the oxide semiconductor layer 230 contacts not only the side surface of the conductive layer 240 but also its top surface, for example, compared to the case where the oxide semiconductor layer 230 contacts only the side surface of the conductive layer 240 but not its top surface, the contact area between the oxide semiconductor layer 230 and the conductive layer 240 can be increased. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0215] The width of opening 590 is Dm. Additionally, the width of opening 290 is D. Widths Dm and D sometimes vary in the depth direction. For example, it can be the width of the upper end of the opening in insulating layer 280. Alternatively, it can be the width of the lower end. Or, it can be half the depth of the opening in insulating layer 280. Alternatively, it can be the width of the opening in conductive layer 540 and the width of the opening in conductive layer 240.

[0216] The sidewalls of opening 590 and opening 290 are preferably perpendicular or approximately perpendicular to the top surface of the surface on which the insulating layer 280 is formed. By giving openings 590 and 290 the above-described shapes, the occupied area of ​​transistors 500 and 200 can be reduced. Therefore, miniaturization of semiconductor devices can be achieved.

[0217] The angle formed by the top surface of the conductive layer 520 (or the top surface of the insulating layer on which the conductive layer 520 is disposed, or the top surface of the substrate) and the sidewall of the insulating layer 280 of the opening 590 is set as angle θ280m. Furthermore, the angle formed by the top surface of the conductive layer 120 (or the top surface of the insulating layer on which the conductive layer 120 is disposed, or the top surface of the substrate) and the sidewall of the insulating layer 280 of the opening 290 is set as angle θ280. θ280m and θ280 are preferably angles of 90 degrees or close to 90 degrees. For example, θ280m and θ280 are preferably 75 degrees or more and 90 degrees or less.

[0218] In addition, θ280m and θ280 are sometimes less than 75 degrees, less than 70 degrees, less than 65 degrees, or less than 60 degrees, respectively. By forming the sidewalls of the opening into a conical shape, the coverage of the membrane formed on the sidewalls of the opening can be improved.

[0219] The sidewall of the opening 190 is preferably perpendicular or approximately perpendicular to the top surface of the surface on which the insulating layer 180 is formed. By giving the opening 190 the above shape, the occupied area of ​​the capacitor 100 can be reduced. Therefore, miniaturization of the semiconductor device can be achieved.

[0220] Figure 10 The structure shown is Figure 7B The main difference in the structure shown is that the sidewalls of opening 590, opening 290 and opening 190 are all tapered.

[0221] The films disposed inside the openings 590, 290, and 190 can be formed using methods such as atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), vacuum evaporation, and pulsed laser deposition (PLD). In particular, methods with high coverage, such as ALD, are preferred.

[0222] Alternatively, insulating layer 280, conductive layer 560, conductive layer 540, conductive layer 260, and conductive layer 240 may all have a stacked structure. Figure 11A and Figure 11B Shown in Figure 1B and Figure 1CThe illustrated structure includes an example where insulating layer 280, conductive layer 560, and conductive layer 540 all have a stacked structure. Alternatively, one or two of insulating layer 280, conductive layer 560, and conductive layer 540 may have a stacked structure, while the others may not. Furthermore, the stacked structure of conductive layer 260 can refer to the materials and structure of the stacked structure of conductive layer 560, and the stacked structure of conductive layer 240 can refer to the materials and structure of the stacked structure of conductive layer 540.

[0223] exist Figure 11A and Figure 11B In the structural example shown, insulating layer 280 includes insulating layer 280a, insulating layer 280b on insulating layer 280a, and insulating layer 280c on insulating layer 280b. Insulating layer 280 can be a single layer, two layers, or a stacked structure with four or more layers. Insulating layer 280a has a region contacting the top surface of insulating layer 210, a region contacting the side surface of conductive layer 520, and a region contacting the top surface of conductive layer 520. Insulating layer 280c has a region contacting the bottom surface of conductive layer 540. Details of insulating layers 280a, 280b, and 280c will be described later.

[0224] exist Figure 11A and Figure 11B In the structural example shown, the conductive layer 540 has a stacked structure of conductive layer 540a and conductive layer 540b on conductive layer 540a. The conductive layer 540 can be a single layer or a stacked structure of three or more layers. The details of conductive layer 540a and conductive layer 540b will be described later.

[0225] exist Figure 11A and Figure 11B In the structural example shown, the conductive layer 560 has a stacked structure of conductive layer 560a and conductive layer 560b on conductive layer 560a. The conductive layer 560 can be a single layer or a stacked structure of three or more layers. The conductive layer 560a is preferably formed using a deposition method with high coverage. Furthermore, by reducing the thickness of the conductive layer 560a, the coverage of the sidewalls of the opening 590 can be further improved. The thickness of the conductive layer 560b can be greater than that of the conductive layer 560a. By increasing the thickness of the conductive layer, the resistance of the conductive layer can be reduced. Details of the conductive layers 560a and 560b will be described later.

[0226] <Examples of variations of semiconductor devices>

[0227] Figure 12A Show Figure 7B The example shown is a modified version of the semiconductor device. Figure 12A The semiconductor device shown is Figure 7BThe main difference in the semiconductor device shown is that it includes insulating layer 535 and insulating layer 235.

[0228] exist Figure 12A In this structure, insulating layer 535 is disposed along at least a portion of the sidewall of opening 590 and has a region located between oxide semiconductor layer 530 and insulating layer 280. Additionally, insulating layer 235 is disposed along at least a portion of the sidewall of opening 590 and has a region located between oxide semiconductor layer 230 and insulating layer 280. Materials used for insulating layer 283, etc., can be used as insulating layers 535 and 235. Insulating layers 535 and 235, for example, have the function of trapping or fixing impurities in the oxide semiconductor layer. Additionally, for example, they are used as impurity blocking layers. Additionally, for example, they have the function of supplying oxygen to the oxide semiconductor layer.

[0229] exist Figure 12B In the semiconductor device shown, a portion of the conductive layer 560 is disposed in the opening 570 of the insulating layer 285, a portion of the conductive layer 260 is disposed in the opening 270 of the insulating layer 285, and the insulating layer 283 has a region sandwiched between the sidewall of the opening 570 and the conductive layer 560, and a region sandwiched between the sidewall of the opening 270 and the conductive layer 260, etc., mainly in this respect... Figure 12A The structures shown are different.

[0230] exist Figure 12B In the semiconductor device shown, opening 570 overlaps with opening 590, and opening 270 overlaps with opening 290.

[0231] exist Figure 12B In the semiconductor device shown, the overlapping area of ​​conductive layer 260 and conductive layer 240 is small, so the parasitic capacitance between conductive layer 260 and conductive layer 240 can be reduced.

[0232] Materials Constituting Semiconductor Devices

[0233] The following describes the materials that can be used in the semiconductor device of this embodiment. Note that the layers constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked structure.

[0234] [Conductive layer]

[0235] The conductive layers (conductive layer 115, conductive layer 120, conductive layer 240, conductive layer 260, conductive layer 520, conductive layer 540, and conductive layer 560, etc.) in the semiconductor device preferably use one or more metallic elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing the above-mentioned metallic elements, or alloys combining the above-mentioned metallic elements. Alternatively, nitrides or oxides of the above-mentioned metallic elements may also be used. Furthermore, as alloys containing the above-mentioned metallic elements, nitrides or oxides of the alloy may also be used. For example, tantalum nitride, titanium nitride, ruthenium nitride, nitrides containing molybdenum, nitrides containing tungsten, titanium, and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferably used. Alternatively, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used.

[0236] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, as well as conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metallic elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also known as ITSO), indium zinc oxide (also known as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification, conductive films deposited using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0237] Conductive materials with tungsten, copper, or aluminum as the main components have high conductivity and are therefore preferred.

[0238] Alternatively, multiple conductive layers formed from the above-described materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0239] Furthermore, when using metal oxides in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material is preferably used as the conductive layer serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0240] Furthermore, when a two-layer structure of conductive layer 560a and conductive layer 560b is used as conductive layer 560, by using a conductive material with the function of suppressing oxygen diffusion as conductive layer 560a, for example, the release of oxygen from the oxide semiconductor layer can be suppressed, thereby suppressing the formation of oxygen vacancies in the oxide semiconductor layer. In addition, by using a conductive material that is not easily oxidized as conductive layer 560a, for example, the oxidation of conductive layer 560a due to the release of oxygen from the oxide semiconductor layer or from insulating layers 551, 553, 250, etc., can be suppressed, thus preventing a decrease in conductivity.

[0241] The material used for conductive layer 560b preferably has higher conductivity than the material used for conductive layer 560a. Furthermore, by increasing the thickness of conductive layer 560b, the current flowing through conductive layer 560b can be further increased.

[0242] As the conductive layer 560a, for example, a conductive material containing nitrogen or a conductive material containing oxygen can be used. Alternatively, as the conductive layer 560a, for example, a conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed can be used.

[0243] Examples of conductive materials containing metallic elements and nitrogen include tantalum nitride, titanium nitride, ruthenium nitride, molybdenum-containing nitrides, tungsten, titanium, and aluminum nitrides, and tantalum and aluminum nitrides. Additionally, examples of conductive materials containing metallic elements and oxygen include ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel.

[0244] Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used.

[0245] Furthermore, as the conductive layer 560a, the material comprising one or more of titanium, tantalum, ruthenium and these metallic elements is preferably a conductive material that is not easily oxidized, a conductive material that has the function of inhibiting oxygen diffusion, or a material that absorbs oxygen while maintaining conductivity.

[0246] As the conductive layer 560b, for example, the aforementioned metal element, an alloy containing the aforementioned metal element, or an alloy combining the aforementioned metal elements can be used. For example, tungsten can be used.

[0247] Since conductive layers 120, 240, 520, and 540 are all conductive layers in contact with the oxide semiconductor layer, it is preferable to use conductive materials that are not easily oxidized, conductive materials that maintain low resistance even if oxidized, oxide conductive materials, or conductive materials that have the function of suppressing oxygen diffusion. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. This helps to suppress the decrease in conductivity of the conductive layers.

[0248] As oxygen-containing conductive materials, ITO, ITSO, IZO (registered trademark) and the like are preferred.

[0249] In addition, when both conductive layer 120 and conductive layer 520 have a stacked structure, a conductive material containing nitrogen and a conductive material containing oxygen can be used as the upper conductive layer in contact with the oxide semiconductor layer.

[0250] In addition, when both conductive layer 240 and conductive layer 540 have a stacked structure, for example, a material with higher conductivity than the upper layer can be used as the lower layer, and a conductive material containing nitrogen, a conductive material containing oxygen, a conductive material that is not easily oxidized, a conductive material that has the function of inhibiting oxygen diffusion, or a material that absorbs oxygen and maintains conductivity can be used as the upper layer.

[0251] In each of conductive layers 240 and 540, specifically, for example, it is preferable to use ruthenium, tungsten, titanium nitride, or tantalum nitride as the lower layer and ITO or ITSO as the upper layer. In this case, ITO or ITSO is in contact with the oxide semiconductor layer. By adopting this structure, conductivity can be maintained even when the conductive layer is in contact with the oxide semiconductor layer. In addition, by using a material with higher conductivity than the upper layer as the lower layer, the conductivity of the conductive layer can be improved.

[0252] Note that when the conductive layer has a two-layer stacked structure, the upper layer can be made of a material with high conductivity, while the lower layer can be made of a conductive material containing nitrogen, a conductive material containing oxygen, a conductive material that is not easily oxidized, a conductive material that inhibits oxygen diffusion, or a material that maintains conductivity even when absorbing oxygen. In this case, for example, by making the oxide semiconductor layer contact the top surface of the conductive layer, the contact resistance between the conductive layer and the oxide semiconductor layer can be reduced.

[0253] As the conductive layer 115, it is preferable to use a conductive material that is not easily oxidized, either as a single layer or in a stack, or a conductive material that has the function of suppressing oxygen diffusion. For example, titanium nitride or indium tin oxide with added silicon may also be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may also be used. Alternatively, for example, a structure in which first titanium nitride, tungsten, and second titanium nitride are stacked sequentially may also be used. By adopting this structure, oxidation of the conductive layer 110 due to the insulating layer 130 can be suppressed when an oxide is used in the insulating layer 130. In addition, oxidation of the conductive layer 110 due to the insulating layer 180 can be suppressed when an oxide is used in the insulating layer 180.

[0254] [Insulating layer]

[0255] The insulating layers (insulating layers 130, 140, 180, 210, 250, 280, 283, 285, 551, 553, etc.) included in the semiconductor device are preferably inorganic insulating films. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Furthermore, organic insulating films can also be used as insulating layers included in semiconductor devices.

[0256] Furthermore, by surrounding a transistor using metal oxides with an insulating layer that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. For example, the insulating layer that suppresses the permeation of impurities and oxygen can be a single layer or a stack of insulating layers selected from one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the material used for the insulating layer that suppresses the permeation of impurities and oxygen can be metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0257] Specifically, it is preferable to use an insulating layer that blocks impurities such as water, hydrogen, and oxygen.

[0258] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, barrier properties refer to properties that make it difficult for the corresponding substance to diffuse, properties that make it difficult for the corresponding substance to pass through, properties that result in low permeability of the corresponding substance, functions that inhibit the diffusion of the corresponding substance, or functions that inhibit the permeation of the corresponding substance. Additionally, hydrogen, referred to as the corresponding substance, includes, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Additionally, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel formation region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Furthermore, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc.

[0259] Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. For example, oxides containing aluminum and hafnium (hafnium aluminate) can be included. Additionally, nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be included.

[0260] Furthermore, insulating layers that are in contact with or near the oxide semiconductor layer, such as gate insulating layers, preferably have regions containing oxygen that has been removed by heating (hereinafter sometimes referred to as excess oxygen). For example, by contacting or placing an insulating layer with regions containing excess oxygen in contact with or near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or porous silicon oxide.

[0261] For example, with the advancements in transistor miniaturization and high integration, problems such as leakage current sometimes arise due to the thinning of the gate insulating layer. By using a material with a high relative permittivity (high-k) in the gate insulating layer, it is possible to achieve lower voltage during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. Additionally, by using a material with a high relative permittivity in the dielectric layer of a capacitor, devices with larger capacitance values ​​can be realized. On the other hand, by using a material with a low relative permittivity in the insulating layer used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, materials can be selected based on the function of the insulating layer. Furthermore, materials with a low relative permittivity are also materials with high dielectric strength.

[0262] Materials with relatively high permittivity include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0263] Examples of materials with low relative permittivity include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. Other examples of inorganic insulating materials with low relative permittivity besides those mentioned above include fluorinated silica, carbon-containing silica, and silica containing both carbon and nitrogen. Porous silica is also an example. Furthermore, these silicas may contain nitrogen.

[0264] For example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride can be used on both sides of layers such as gate insulating layers where materials with high relative permittivity are used, and layers such as interlayer films where materials with low relative permittivity are used. These materials have relatively low relative permittivity compared to, for example, high-k materials such as hafnium oxide, and are therefore sometimes referred to as materials with low relative permittivity in this specification, etc.

[0265] Furthermore, ferroelectric materials can be used as the insulating layer included in semiconductor devices. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO. X Metal oxides such as (X is a real number greater than 0). Additionally, materials that can exhibit ferroelectric properties include hafnium oxide with the addition of element J1 (here, element J1 is selected from one or more of zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of hafnium atoms to element J1 atoms can be set to 1:1 or close to that. Furthermore, materials that can exhibit ferroelectric properties include zirconium oxide with the addition of element J2 (here, element J2 is selected from one or more of hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Furthermore, the ratio of the number of zirconium atoms to the number of element J2 atoms can be appropriately set; for example, the ratio of zirconium atoms to element J2 atoms can be set to 1:1 or close to that. Additionally, lead titanate (PbTiO2) can also be used as a material that can exhibit ferroelectric properties. X Piezoelectric ceramics with perovskite structure include barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate.

[0266] Furthermore, metal nitrides containing elements Me1, Me2, and nitrogen can be cited as materials that can exhibit ferroelectric properties. Here, element Me1 is selected from one or more of aluminum, gallium, indium, etc. Element Me2 is selected from one or more of boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium, etc. Note that the ratio of the number of atoms of element Me1 to the number of atoms of element Me2 can be appropriately set. Additionally, metal oxides containing elements Me1 and nitrogen sometimes exhibit ferroelectric properties even without the presence of element Me2. Furthermore, materials that can exhibit ferroelectric properties include those to which element Me3 is added. Note that element Me3 is selected from one or more of magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element Me1, the number of atoms of element Me2, and the number of atoms of element Me3 can be appropriately set.

[0267] In addition, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-Al2O3 structure can be cited as materials that can have ferroelectric properties.

[0268] Note that while metal oxides and metal nitrides are shown among the ferroelectric materials described above, the list is not limited to these. For example, metal oxynitrides (containing nitrogen in the metal oxides) or metal oxynitrides (containing oxygen in the metal nitrides) may also be used.

[0269] Furthermore, as a material that can exhibit ferroelectricity, for example, a mixture or compound composed of multiple materials selected from the above-mentioned materials can be used. Alternatively, the insulating layer 130 can have a stacked structure formed of multiple materials selected from the above-mentioned materials. In addition, the crystal structure (properties) of the above-mentioned materials may vary not only depending on the deposition conditions but also depending on various processes, so in this specification, materials exhibiting ferroelectricity are referred not only to ferroelectric materials but also to materials that can exhibit ferroelectricity.

[0270] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when processed into thin films of a few nanometers. Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when their area is extremely small. Therefore, by using metal oxides containing one or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0271] In this specification and the like, a material that can be formed in a layered manner and possess ferroelectric properties is sometimes referred to as a ferroelectric layer. Furthermore, in this specification and the like, a device comprising such a ferroelectric layer, metal oxide film, or metal nitride film is sometimes referred to as a ferroelectric device.

[0272] Furthermore, ferroelectricity is believed to arise from the displacement of oxygen or nitrogen in the crystal contained within the ferroelectric layer under the influence of an applied electric field. Additionally, the presence of ferroelectricity is presumed to depend on the crystal structure of the crystal contained within the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 needs to contain a crystal. In particular, the insulating layer preferably has a crystal with an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure of the crystal contained in the insulating layer can be any one or more selected from isometric, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. Alternatively, the insulating layer may also have an amorphous structure. In this case, the insulating layer may also have a composite structure of amorphous and crystalline structures.

[0273] Hydrogen-barrier insulating layers are preferably used as one or more of insulating layers 140, 180, and 130. Additionally, hydrogen-barrier insulating layers are preferably used as one or more of insulating layers 283 and 285. This suppresses hydrogen diffusion into the oxide semiconductor layer.

[0274] Furthermore, materials with low relative permittivity can be used, for example, as insulating layers 140, 180, and 285. By using materials with low relative permittivity in the interlayer films, the parasitic capacitance generated between the wirings can be reduced.

[0275] In one embodiment of the present invention, the concentration of impurities such as water and hydrogen is preferably reduced in the insulating layer. This suppresses the incorporation of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer.

[0276] The insulating layer 280 preferably comprises a hydrogen-barrier insulating layer. The insulating layer 280 is disposed around the oxide semiconductor layer. By providing hydrogen barrier properties to the insulating layer 280 disposed on the outside of the oxide semiconductor layer, hydrogen diffusion into the oxide semiconductor layer can be suppressed. For example, the insulating layer 280 preferably comprises a silicon nitride film.

[0277] In addition, silicon nitride also has oxygen-barrier properties. Therefore, by using silicon nitride in the insulating layer 280, it is possible to suppress the extraction of oxygen from the oxide semiconductor layer and the formation of excessive oxygen vacancies in the oxide semiconductor layer.

[0278] Furthermore, by using silicon nitride as the insulating layer 280, excess oxygen supply to the oxide semiconductor layer can be prevented. Therefore, oxygen excess in the channel formation region of the oxide semiconductor layer can be prevented, thus improving transistor reliability.

[0279] In addition, the insulating layer 280 preferably includes the above-mentioned oxide insulating film, oxynitride insulating film or insulating layer having a region containing excess oxygen.

[0280] For example, an insulating layer having regions containing excess oxygen can be deposited by sputtering in an oxygen-containing atmosphere. By using a sputtering method that does not require the use of hydrogen-containing molecules as a deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. Thus, by depositing at least a portion of the layer constituting the insulating layer 280, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer, thereby reducing oxygen vacancies and VoH.

[0281] Furthermore, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulating layer 280. This can suppress the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer.

[0282] The insulating layer 280 preferably has a stacked structure having an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b.

[0283] The insulating layer 280b is a layer that contacts the channel formation region of the oxide semiconductor layer. By using an oxygen-containing insulating layer as the insulating layer 280b, oxygen can be supplied to the oxide semiconductor layer.

[0284] The insulating layer 280b preferably has a region with a higher oxygen content compared to at least one of the insulating layers 280a and 280c. In particular, the insulating layer 280b preferably has a region with a higher oxygen content compared to each of the insulating layers 280a and 280c. By increasing the oxygen content of the insulating layer 280b, an i-type region is easily formed in the oxide semiconductor layer near the insulating layer 280b.

[0285] As the insulating layer 280b, a film that releases oxygen upon heating is more preferably used. By applying heat during the transistor manufacturing process, the insulating layer 280b releases oxygen, thereby supplying oxygen to the oxide semiconductor layer. By supplying oxygen from the insulating layer 280b to the oxide semiconductor layer, particularly to the channel formation region of the oxide semiconductor layer, oxygen vacancies and Vo in the oxide semiconductor layer can be reduced. O H, thus enabling the realization of transistors that exhibit good electrical characteristics and high reliability.

[0286] In addition, in order to improve the electrical characteristics and reliability of OS transistors, it is important to optimize the amount of oxygen supplied to the oxide semiconductor while sufficiently reducing the hydrogen concentration in the oxide semiconductor.

[0287] As an example, the amount of oxygen molecules released from the insulating layer 280b is preferably 1.0 × 10⁻⁶. 14 molecules / cm 2 Above and less than 1.0 × 10 15 molecules / cm 2Note that the amount of oxygen molecules released can also be measured using thermal desorption spectroscopy.

[0288] In particular, when the channel length of the transistor is small, the oxygen vacancies and V in the channel formation region... O Hydrogen (H) has a particularly significant impact on electrical characteristics and reliability. Therefore, by sufficiently reducing the hydrogen concentration in the oxide semiconductor layer while optimizing the oxygen supply to the oxide semiconductor layer, transistors with good electrical characteristics, high reliability, and short channel lengths can be achieved.

[0289] The insulating layer 280b is preferably formed using a deposition method such as sputtering or PECVD. In particular, when using sputtering, hydrogen gas is not required as the deposition gas, thereby achieving a film with extremely low hydrogen content. Therefore, the supply of hydrogen to the oxide semiconductor layer can be suppressed, thus stabilizing the electrical characteristics of the transistor.

[0290] To increase the amount of oxygen supplied to the oxide semiconductor layer, it is preferable to perform heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere after forming the insulating layer 280b. Alternatively, an oxide film can be deposited on the top surface of the insulating layer 280b using a sputtering method in an oxygen atmosphere to supply oxygen. This oxide film can then be removed. By performing this process, oxygen can be supplied to the insulating layer 280b, thereby increasing the amount of oxygen supplied to the oxide semiconductor layer.

[0291] Furthermore, in the oxide semiconductor layer, the oxygen supply to the regions contacting the insulating layer 280a and 280c is less than that to the region contacting the insulating layer 280b. Therefore, the regions of the oxide semiconductor layer contacting the insulating layer 280a and 280c are sometimes made to have low resistance. In other words, by adjusting the thickness of the insulating layer 280a, the range of the region used as one of the source and drain regions can be controlled. Similarly, by adjusting the thickness of the insulating layer 280c, the range of the other region used as the source and drain region can be controlled. Thus, the thicknesses of the insulating layers 280a and 280c can be appropriately set according to the required characteristics of the transistor.

[0292] Furthermore, a material with a low relative permittivity is preferably used as the insulating layer 280b. This reduces parasitic capacitance generated between wirings. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280b.

[0293] Oxygen-barrier insulating layers are preferably used as insulating layers 280a and 280c. By providing insulating layer 280a between insulating layer 280b and conductive layer 520 (or conductive layer 120), oxidation of the conductive layer and its increased resistance can be suppressed. Furthermore, by providing insulating layer 280c between insulating layer 280b and conductive layer 540 (or conductive layer 240), oxidation of the conductive layer and its increased resistance can be suppressed.

[0294] Alternatively, an insulating layer with hydrogen trapping or fixing function can be used as insulating layer 280a. By employing this structure, hydrogen diffusion from below insulating layer 280a to the oxide semiconductor layer can be suppressed, and hydrogen contained in the oxide semiconductor layer can be trapped or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer can be reduced. Magnesium oxide, aluminum oxide, hafnium oxide, or oxides containing hafnium and silicon can be used as insulating layer 280a. Alternatively, for example, a laminate of aluminum oxide and silicon nitride on the aluminum oxide can be used as insulating layer 280a. Similarly, an insulating layer with hydrogen trapping or fixing function can be used as insulating layer 280c.

[0295] For example, silicon nitride can be used for insulating layers 280a and 280c, and silicon oxide can be used for insulating layer 280b.

[0296] A material with a high relative permittivity (high-k) is preferably used as the insulating layer 130. By using a high-k material for the insulating layer 130, the thickness of the insulating layer 130 can be increased to a level that can suppress leakage current and sufficiently ensure the electrostatic capacitance of the capacitor 100.

[0297] Furthermore, as the insulating layer 130, it is preferable to use an insulating layer made of a high-k material, and more preferably, a laminated structure of a high-k material with a high relative permittivity and a material with a dielectric strength greater than that high-k material can be used. For example, as the insulating layer 130, an insulating film in which zirconium oxide, alumina, and zirconium oxide are stacked sequentially can be used. Alternatively, for example, an insulating film in which zirconium oxide, alumina, zirconium oxide, and alumina are stacked sequentially can be used. Alternatively, for example, an insulating film in which hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina are stacked sequentially can be used. By using an insulating layer with a high dielectric strength, such as alumina, the dielectric strength can be increased and electrostatic breakdown of the capacitor 100 can be suppressed.

[0298] Alternatively, a material that is ferroelectric can be used as the insulating layer 130.

[0299] [Insulating layer 551, insulating layer 553, charge trapping layer 552, insulating layer 250]

[0300] The aforementioned materials may be appropriately used as insulating layers 551, 553, and 250.

[0301] Information can be written to transistor 500 using the tunneling current flowing through insulating layer 551. Therefore, insulating layer 551 is preferably an insulating layer through which tunneling current can easily flow. In addition, by reducing the thickness of insulating layer 551, tunneling current can flow more easily, thereby reducing the power consumption required for the operation of the memory element.

[0302] However, when the leakage current of insulating layer 551 or insulating layer 553 is large, the written information cannot be retained.

[0303] Furthermore, when writing to transistor 500, charge trapping in areas outside charge storage layer 552, specifically, in the films of insulating layers 551 and 553, or at the interface between insulating layer 551 and the semiconductor layer, is undesirable. This is because charge trapping in such areas presents the following concerns: the trapped charge cannot be released at the desired voltage, leading to increased power consumption required for the storage element to operate; the trapped charge is easily released due to leakage current, making it difficult to retain information; or charge trapping leads to a decrease in the reliability of transistor 500, etc.

[0304] From the above perspective, insulating layers 551 and 553 are preferably films with fewer defects, such as leakage current or defects that cause charge trapping. Particularly preferred is insulating layer 551, which has a smaller thickness and therefore fewer defects.

[0305] As the insulating layer 551, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, etc. are preferably used.

[0306] The thickness of the insulating layer 551 can be, for example, 1 nm or more and 20 nm or less. When a highly conductive material is used as the charge storage layer 552, the thickness of the insulating layer 551 can be, for example, 5 nm or more and 20 nm or less, more preferably 6 nm or more and 15 nm or less. Furthermore, when a highly insulating material is used as the charge storage layer 552, the thickness of the insulating layer 551 can be, for example, 1 nm or more and 6 nm or less, more preferably 1.5 nm or more and 4.5 nm or less.

[0307] For example, the thickness of insulating layer 553 is preferably greater than that of insulating layer 551. This reduces the tunneling current flowing through insulating layer 553 and suppresses the transfer of charge from charge storage layer 552 to the control gate side.

[0308] The thickness of the insulating layer 553 can be, for example, greater than 8 nm and less than 30 nm.

[0309] As the insulating layer 553, the material shown above as the insulating layer can be used. Alternatively, a stack of multiple materials can be used. For example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, etc. are preferably used as the insulating layer 553.

[0310] As the charge storage layer 552, a material with high conductivity can be used. For example, the material shown above as the conductive layer can be used appropriately. Specifically, for example, one or more metallic elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or alloys containing these metallic elements, or alloys combining these metallic elements, can be used. Additionally, nitrides or oxides of the aforementioned metallic elements can be used. Furthermore, as alloys containing the aforementioned metallic elements, nitrides or oxides of the alloy can also be used.

[0311] Alternatively, semiconductor materials such as silicon and germanium can be used as the charge storage layer 552. Furthermore, when using semiconductor materials, for example, a layer whose resistance has been reduced due to impurity implantation can be used.

[0312] Furthermore, a material with high insulating properties can be used as the charge storage layer 552. For example, among the materials shown above as the insulating layer, an insulating layer with charge trapping properties can be used. Specifically, for example, silicon nitride, silicon oxynitride, etc., can be used. Alternatively, a layer in which conductive nanodots are dispersed in the insulating layer can also be used.

[0313] By having an amorphous structure, the formation of grain boundaries in the insulating layer can be suppressed. Suppressing grain boundary formation improves the flatness of the insulating layer. This results in a more uniform thickness distribution of the insulating layer, reducing extremely thin portions and thus improving its withstand voltage. Furthermore, it allows for a more uniform thickness distribution of the film disposed on the insulating layer. Additionally, suppressing grain boundary formation reduces leakage current caused by defect states at grain boundaries. This allows the insulating layer to be used as an insulating film with low leakage current. Therefore, insulating layers such as insulating layers 551, 553, and 250 preferably have an amorphous structure.

[0314] By utilizing the gate insulating layer of the transistor, which has the function of trapping and fixing hydrogen, the Vt in the channel formation region can be reduced. O H, and can make the channel forming region type i or substantially type i.

[0315] In addition, by including a hydrogen barrier insulating layer in the gate insulating layer of the transistor, hydrogen diffusion into the oxide semiconductor layer can be suppressed.

[0316] In addition, the characteristics of a transistor can be stabilized by using a thermally stable insulating layer, such as silicon oxide or silicon oxynitride, as the gate insulating layer.

[0317] In addition, by using an oxygen barrier insulating layer as the gate insulating layer of a transistor, oxygen diffusion from the oxide semiconductor layer into the surrounding layers can be suppressed, thus preventing the formation of oxygen vacancies in the oxide semiconductor layer.

[0318] As the gate insulating layer of transistor 200, it can be used in combination with two or more of the following: a layer that has the function of trapping and fixing hydrogen, an insulating layer that has hydrogen barrier properties, an insulating layer that has a thermally stable structure, and an insulating layer that has oxygen barrier properties.

[0319] Here, as an example, starting from the layer closest to the oxide semiconductor layer, an aluminum oxide layer, a silicon oxide layer (or a silicon oxynitride layer), an oxide layer containing one or both of aluminum and hafnium, and a silicon nitride layer can be used sequentially. The aluminum oxide layer has oxygen barrier properties. Additionally, the silicon oxide layer has a thermally stable structure. Furthermore, the oxide layer containing one or both of aluminum and hafnium has a high relative permittivity, enabling it to trap and fix hydrogen. Additionally, the silicon nitride layer provides barrier properties against both hydrogen and oxygen. Alternatively, this stacked structure may not include any of the aforementioned layers. Furthermore, the stacking order of some layers may sometimes be interchanged.

[0320] exist Figure 7B In the example shown, insulating layer 551 is used as the gate insulating layer of transistor 200. In this case, for example, a silicon oxide layer or a silicon oxynitride layer can be used as the gate insulating layer of transistor 200 by using a silicon oxide layer or a silicon oxynitride layer as the insulating layer 551.

[0321] In addition, Figure 9A In the example shown, insulating layer 553 is used as the gate insulating layer of transistor 200. In this case, insulating layer 553 can be, for example, an aluminum oxide layer, a silicon oxide layer (or a silicon oxynitride layer), an oxide layer containing one or both of aluminum and hafnium, or a silicon nitride layer stacked structure. Alternatively, the stacked structure may not include any of the above-mentioned layers.

[0322] In addition, Figure 9BIn the example shown, a stacked structure of insulating layers 551 and 553 is used as the gate insulating layer of transistor 200. In this case, for example, silicon oxide or silicon oxynitride can be used as insulating layer 551, and a stacked structure of oxide and silicon nitride containing one or both of aluminum and hafnium can be used as insulating layer 553. Alternatively, a stacked structure of silicon oxide or silicon oxynitride, oxide and silicon nitride containing one or both of aluminum and hafnium can be used as insulating layer 553. Furthermore, insulating layer 553 may also include an aluminum oxide layer in addition to the layers described above.

[0323] In addition, Figure 9C In the example shown, insulating layer 250 is used as the gate insulating layer of transistor 200. For details regarding insulating layer 250, please refer to the description above of it as the gate insulating layer of a transistor.

[0324] The thickness of the gate insulating layer of transistor 200 is preferably 0.1 nm or more and 30 nm or less, preferably 0.1 nm or more and 20 nm or less, preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 8.0 nm or less, and even more preferably 0.5 nm or more and 7.0 nm or less.

[0325] [Substrate]

[0326] Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Additionally, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0327] <Oxide Semiconductor Layer>

[0328] Transistor 200 preferably contains a metal oxide (also called an oxide semiconductor) serving as a semiconductor in the oxide semiconductor layer 230 including the channel formation region. Similarly, transistor 500 preferably contains a metal oxide serving as a semiconductor in the oxide semiconductor layer 530 having the channel formation region. In other words, transistors 200 and 500 are preferably OS transistors.

[0329] Alternatively, transistors using other semiconductor materials in the channel formation region can be used in the semiconductor device of this embodiment. Examples of such other semiconductor materials include semiconductors or compound semiconductors composed of a single element. Examples of semiconductors composed of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. Additionally, examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may also contain impurities as dopants.

[0330] Silicon, as a semiconductor material that can be used as a transistor, can be categorized into monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. For example, low-temperature polycrystalline silicon (LTPS) can be cited as a polycrystalline silicon.

[0331] Furthermore, the semiconductor layer of a transistor can also contain layered materials used as semiconductors. Layered materials are a general term for a group of materials with layered crystal structures. A layered crystal structure is a structure formed by layers of covalent or ionic bonds stacked together by bonds weaker than covalent and ionic bonds, such as van der Waals bonds. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material with high two-dimensional conductivity as a semiconductor in the channel formation region, transistors with large on-state currents can be provided.

[0332] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (elements belonging to Group 16). Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0333] The oxide semiconductor layer that can be used as oxide semiconductor layer 230 and oxide semiconductor layer 530 will be described below.

[0334] The oxide semiconductor layer 30 shown below can be used as the oxide semiconductor layer 230 and oxide semiconductor layer 530.

[0335] In one aspect of the present invention, the oxide semiconductor layer preferably comprises a crystalline metal oxide. Examples of structures with crystalline metal oxides include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nanocrystalline structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. Therefore, the reliability of transistors using the oxide semiconductor layer of one aspect of the present invention can be improved, and the reliability of semiconductor devices in which transistors are mounted can be improved.

[0336] In one aspect of the present invention, the oxide semiconductor layer particularly preferably comprises a metal oxide having a CAAC structure. A CAAC structure is a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) have a c-axis orientation and are connected without orientation on the ab plane. When a cross-section of an oxide semiconductor layer with a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that the metal atoms are arranged in layers within the crystalline region. Therefore, it can also be said that the oxide semiconductor layer with a CAAC structure has layered crystalline regions. In the cross-section of the oxide semiconductor layer observed using TEM images, the layered metal atoms can be observed as bright spots.

[0337] The CAAC structure is formed, for example, with the c-axis perpendicular or substantially perpendicular to the surface being formed. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface being formed. In the region having the CAAC structure, the angle of the c-axis relative to the surface being formed is preferably within 90° ± 20° (70° or more and 110° or less), more preferably within 90° ± 15° (75° or more and 105° or less), even more preferably within 90° ± 10° (80° or more and 100° or less), and even more preferably within 90° ± 5° (85° or more and 95° or less).

[0338] Polycrystalline structures possess grain boundaries. Furthermore, when heat treatment is performed after forming a polycrystalline oxide semiconductor layer, tiny gaps (also called nanocracks or microcracks) or tiny spaces (also called nanospaces or microspaces) may form between the crystalline regions. If tiny gaps or tiny spaces form within the oxide semiconductor layer, the resistance of the oxide semiconductor layer increases. This is because the resistance of tiny gaps or tiny spaces is extremely high, for example, infinite. When an oxide semiconductor layer with tiny gaps or tiny spaces is used in the channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of the source and drain electrodes increases. Therefore, this negatively impacts the initial characteristics or reliability of the transistor. The CAAC structure does not exhibit well-defined grain boundaries on the ab plane, thus enabling highly reliable semiconductor devices. Additionally, due to fewer grain boundaries, the barrier for carrier conduction in the transistor channel is smaller, and an increase in on-state current can be expected.

[0339] The crystallinity of oxide semiconductor layers can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, multiple methods can be combined for analysis.

[0340] When an oxide semiconductor layer with a CAAC structure is subjected to electron diffraction, spots (bright spots) representing the c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to the normal vector of the formed surface of the oxide semiconductor layer or the normal vector of the surface of the oxide semiconductor layer.

[0341] In addition, the FFT pattern obtained by processing the TEM image with Fast Fourier Transform (FFT) reflects the same reciprocal space information as the electron diffraction pattern.

[0342] By obtaining a cross-sectional TEM image of an oxide semiconductor layer with a CAAC structure and performing FFT processing on each region in the cross-sectional TEM image to generate an FFT image, the crystal axis orientation of each region can be calculated based on the generated FFT image. Specifically, the direction of the line segment connecting two spots with high brightness and approximately equal distance from the center observed in the generated FFT image can be taken as the crystal axis orientation. Regions where the angle of the crystal axis orientation calculated from the FFT image relative to the formed surface is preferably 70° or more and 110° or less (within 90° ± 20°), more preferably 75° or more and 105° or less (within 90° ± 15°), more preferably 80° or more and 100° or less (within 90° ± 10°), and even more preferably 85° or more and 95° or less (within 90° ± 5°) can be considered as CAAC structures.

[0343] When an oxide semiconductor layer with a CAAC structure is observed using TEM images from a direction perpendicular to the formed surface, triangular or hexagonal atomic arrangements with crystallinity are observed on the ab surface. Furthermore, in Voronoi diagrams created by image analysis of TEM images of the oxide semiconductor layer with a CAAC structure observed from a direction perpendicular to the formed surface, pentagonal, hexagonal, and heptagonal Voronoi regions are primarily observed, with hexagonal Voronoi regions being particularly prevalent. For example, in the Voronoi regions observed in Voronoi diagrams, hexagonal Voronoi regions account for more than 30% but less than 100%.

[0344] The following explains how to create a Voronoi diagram. First, when performing image analysis on a TEM image, after FFT processing, filtering is applied to retain only a certain range of information, followed by an inverse Fast Fourier Transform (IFFT) to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image to construct the perpendicular bisectors of line segments connecting nearby lattice points. The point where the three perpendicular bisectors intersect is the Voronoi point, and the polygonal region enclosed by the line segments connecting the Voronoi points is the Voronoi region. This allows the creation of the Voronoi diagram.

[0345] Additionally, as an example of the observation range of a TEM when creating a Voronoi diagram, a rectangular region measuring 50 nm vertically and 50 nm horizontally can be observed. Note that the observation range is not limited to this.

[0346] Furthermore, when analyzing the distribution of hexagonal lattice orientations using lattice points extracted through image analysis of planar TEM images, the differences in hexagonal lattice orientations were observed to be small at the boundaries of two structures with different orientations, resulting in blurred boundaries and the two structures being connected in an intertwined manner. In other words, no clear boundary was observed in the CAAC structure.

[0347] Note that the orientation of a hexagonal lattice can be calculated from the orientation of the hexagon formed by the six lattice points closest to each lattice point.

[0348] There are no particular restrictions on the crystallinity of the semiconductor material contained in the oxide semiconductor layer. For example, the oxide semiconductor layer may sometimes contain one or more of the following: amorphous semiconductor (semiconductor with an amorphous structure), single-crystal semiconductor (semiconductor with a single-crystal structure), and semiconductor with crystallinity other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor with partially crystalline regions). When the oxide semiconductor layer is crystallinous, it can sometimes suppress the degradation of transistor characteristics.

[0349] According to one aspect of the invention, the metal oxide preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide may contain indium as a main component and also contain element Me. The metal oxide preferably contains two or three selected from indium, element Me, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide may contain indium and zinc as main components and also contain element Me. Note that element Me is a metallic or half-metallic element with a high bond energy with oxygen, for example, a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specifically, examples of element Me include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element Me contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element Me contained in the metal oxide is gallium, the metal oxide according to one embodiment of the invention preferably contains one or more elements selected from indium, gallium, and zinc. In this specification and the like, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the term "metallic element" as used in this specification and the like sometimes includes half-metallic elements.

[0350] In cross-sections of oxide semiconductor layers observed using TEM images, metal atoms were confirmed to be arranged in layers parallel to or substantially parallel to the formed surface. The metal atoms were observed as bright spots in the TEM image. For example, in metal oxides containing indium, indium was confirmed to be arranged in layers. Furthermore, for example, in metal oxides containing indium and zinc, indium and zinc were confirmed to be arranged in layers.

[0351] As one embodiment of the metal oxide according to the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also denoted as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. Alternatively, examples include indium tin oxide (also denoted as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide), which contain silicon. Furthermore, as a metal oxide according to one aspect of the present invention, indium oxide, gallium oxide, zinc oxide, etc., can be used.

[0352] When the proportion of indium atoms relative to the total number of atoms of all metal elements in a metal oxide is increased, transistors can achieve large on-state current and high frequency characteristics.

[0353] Note that metal oxides can also contain one or more metals with high period numbers in the periodic table to replace indium. Alternatively, metal oxides can also contain one or more metals with high period numbers in the periodic table in addition to indium. The greater the overlap of the orbitals of a metal element, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers in the periodic table, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers in the periodic table include metals belonging to period 5 and period 6. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0354] In addition, metal oxides may also contain one or more non-metallic elements. The inclusion of non-metallic elements in metal oxides can sometimes improve the field-effect mobility of transistors. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0355] Furthermore, by increasing the proportion of zinc atoms relative to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystallizable, thereby suppressing the diffusion of impurities in the metal oxide. This, in turn, suppresses variations in the electrical characteristics of the transistor and improves reliability.

[0356] Furthermore, by increasing the proportion of element Me atoms relative to the total number of atoms of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, thereby enabling transistors with low off-state currents. Additionally, variations in the transistor's electrical characteristics are suppressed, thus improving reliability.

[0357] In this embodiment, In-Ga-Zn oxide is sometimes used as an example of a metal oxide.

[0358] One embodiment of the present invention provides an oxide semiconductor layer that can be fabricated by forming a metal oxide using two deposition methods. For example, one embodiment of the present invention provides an oxide semiconductor layer that can be fabricated by forming a metal oxide using a first deposition method and a second deposition method. An oxide semiconductor layer formed using two deposition methods can also be referred to as a Hybrid OS.

[0359] In one embodiment of the present invention, the oxide semiconductor layer is crystalline. Furthermore, in another embodiment of the present invention, the oxide semiconductor layer preferably has a CAAC structure.

[0360] In the fabrication of an oxide semiconductor layer according to one aspect of the present invention, a crystalline metal oxide is deposited using a first deposition method. The deposited metal oxide preferably has a CAAC structure. For example, metal oxides deposited using sputtering methods tend to be crystalline.

[0361] When forming a metal oxide using a first deposition method, a mixed layer sometimes forms at the interface between the metal oxide and the layer that is being formed. For example, when sputtering is used as the first deposition method, this mixed layer sometimes forms due to particles released from a target or the like (also called sputtered particles) or energy supplied to the substrate side by the sputtered particles. This mixed layer may hinder the crystallization of the metal oxide.

[0362] For example, when an insulating layer containing silicon, such as silicon oxide, is used as the surface to be formed, silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide using a first deposition method. The inclusion of impurities such as silicon in the metal oxide may hinder the crystallization of the metal oxide.

[0363] Therefore, in one aspect of the present invention, a second deposition method is used to form a metal oxide before forming it using a first deposition method. That is, after forming a metal oxide as a first layer using the second deposition method, a second metal oxide layer is formed using the first deposition method on the first layer. In this case, it is preferable to use a deposition method that causes less damage to the surface being formed compared to the first deposition method as the second deposition method. By using a deposition method that causes less damage to the surface being formed as the second deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer that forms the surface of the oxide semiconductor layer can be suppressed. Furthermore, the incorporation of impurities such as silicon can be suppressed in the second layer, thus potentially improving crystallinity. For example, atomic layer deposition (ALD) and chemical vapor deposition (CVD) methods can suppress damage to the surface being formed compared to sputtering methods, making them suitable as the second deposition method.

[0364] Furthermore, as the first layer, a metal oxide with a microcrystalline or amorphous structure having a lower crystallinity than the CAAC structure is sometimes formed. By forming a highly crystalline second layer on the first layer with low crystallinity, or by forming the second layer and heat-treating it, the crystallinity of the first layer is sometimes improved with the second layer as the nucleus. Thus, the crystallinity of the entire oxide semiconductor layer, including the area near the interface with the formed surface, can sometimes be improved.

[0365] In one aspect of the oxide semiconductor layer of the present invention, it is preferred that a metal oxide is first formed on the surface to be formed using a second deposition method, and then a metal oxide is formed on top of it using a first deposition method.

[0366] Examples of primary deposition methods include sputtering and pulsed laser deposition (PLD).

[0367] Examples of secondary deposition methods include ALD (Alternating Layer Deposition), Plasma Enhanced CVD (PECVD), Thermal CVD, PhotoCVD, Metal-Organic CVD (MOCVD), and Molecular Beam Epitaxy (MBE). MBE is a deposition method that grows thin films with a crystal structure reflecting the crystal system of the substrate, and it is considered one of the deposition methods that causes minimal damage to the surface being formed. Additionally, wet deposition methods can be used as a secondary deposition method. Wet deposition methods are among the deposition methods that cause minimal damage to the surface being formed. Examples of wet deposition methods include spray coating.

[0368] As an example, the oxide semiconductor layer of one aspect of the present invention can be manufactured by forming a metal oxide as a first layer using a second deposition method, followed by forming a metal oxide as a second layer using a first deposition method. Specifically, the second deposition method can be the ALD method, and the first deposition method can be sputtering. Furthermore, the metal oxide formed using the first deposition method preferably has a CAAC structure.

[0369] Furthermore, a third layer can also be formed on the second layer. Since the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even without using a deposition method that readily produces crystals as the deposition method for the third layer, the third layer can be crystallized. For example, by using a deposition method with higher coverage than the second layer as the deposition method for the third layer, the entire oxide semiconductor layer can possess both high crystallinity and high coverage. Additionally, for example, by using a deposition method that causes less damage than the second layer as the deposition method for the third layer, damage to the second layer can be reduced, thereby enabling the entire oxide semiconductor layer to have high crystallinity.

[0370] Furthermore, by setting a first layer to reduce the influence of the formed surface, the crystallinity of the second layer is improved, resulting in extremely excellent crystallinity. Therefore, it is expected that an extremely crystallinity layer will also be formed in the third layer, which crystallizes with the second layer as the nucleus or seed.

[0371] Furthermore, the third layer is the topmost layer of the oxide semiconductor layer. When the oxide semiconductor layer is used as the semiconductor layer of the transistor described later, the third layer is, for example, the layer that contacts the gate insulating layer. By increasing the crystallinity of the layer that contacts the gate insulating layer, the carrier mobility of the transistor in the on state can be improved.

[0372] As an example, an oxide semiconductor layer according to one aspect of the present invention can be manufactured by the following steps: after forming a metal oxide as a first layer using a second deposition method, forming a metal oxide as a second layer using a first deposition method, and forming a metal oxide as a third layer using a second deposition method. Specifically, the ALD method can be used as the second deposition method, and sputtering can be used as the first deposition method. Furthermore, the metal oxide formed using the first deposition method preferably has a CAAC structure. The ALD method is a deposition method with higher coverage than sputtering; by using the ALD method as the deposition method for the first and third layers, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can effectively cover steps and openings with high aspect ratios.

[0373] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing conductive metal films. Additionally, pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0374] Examples of ALD methods include thermal ALD (thermal ALD) which uses only thermal energy to react precursors and reactants, and plasma ALD (PEALD) which uses reactants excited by plasma.

[0375] The ALD method allows for atomic deposition layer by layer, resulting in the following advantages: it enables the deposition of very thin films; it allows deposition on structures with high aspect ratios or surfaces with large steps; it allows deposition with fewer defects such as pinholes; it allows for high coverage deposition; and it allows deposition at low temperatures. Furthermore, in the PEALD method, deposition can be performed at even lower temperatures by utilizing plasma, which is sometimes preferred. Additionally, the precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, films deposited using the ALD method sometimes contain more carbon or chlorine than films deposited using other deposition methods. Furthermore, the quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Note that while the metal oxide deposition method used in this invention employs the ALD method, due to the use of high substrate temperatures during deposition and one or both of the impurity removal treatment, the amount of carbon and chlorine contained in the film is sometimes less than when using the ALD method without these conditions.

[0376] Unlike deposition methods that use particles released from a target, ALD (Alternating Discharge) deposition is a deposition method where a film is formed due to a reaction on the surface of the workpiece. Therefore, ALD is a deposition method that is less affected by the shape of the workpiece and exhibits good step coverage. In particular, ALD has excellent step coverage and thickness uniformity, making it suitable for forming films covering surfaces with high aspect ratio openings.

[0377] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because plasma is not used in thermal CVD, plasma damage to the workpiece is reduced. Additionally, since no plasma damage occurs during deposition in thermal CVD, films with fewer defects can be obtained.

[0378] Furthermore, when using CVD, films of arbitrary composition can be deposited by adjusting the source gas flow rate ratio. For example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. When deposition is performed while changing the source gas flow rate ratio, the deposition time can be shortened compared to deposition using multiple deposition chambers because the time required for transfer or pressure adjustment is eliminated. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0379] [Manufacturing method of oxide semiconductor layer]

[0380] The oxide semiconductor layer 30 can be manufactured, for example, by forming oxide semiconductor layer 30a on layer 229, which is the surface to be formed, using an ALD method; forming oxide semiconductor layer 30b on oxide semiconductor layer 30a using a sputtering method; and forming oxide semiconductor layer 30c on oxide semiconductor layer 30b using an ALD method. Furthermore, after forming the oxide semiconductor layer 30, heat treatment is preferably performed. Heat treatment can improve the crystallinity of the oxide semiconductor layer 30. Here, heat treatment is not limited to heating. For example, heat applied during the manufacturing process can also be used. Layer 229 is an insulating film, such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc. Alternatively, as layer 229, a film that serves as an insulator in a semiconductor device, as described later, can be used.

[0381] Alternatively, layer 229 may sometimes be a conductive film. For example, an oxide semiconductor layer 30 may also be formed on a conductive film used as an electrode in a semiconductor device.

[0382] Layer 229 may also be non-crystalline. In other words, layer 229 may also have an amorphous structure. Alternatively, if layer 229 is crystalline, it may have a crystal structure with low lattice matching with the metal oxide contained in the oxide semiconductor layer 30.

[0383] Reference Figures 13A to 14D An example illustrating a method for manufacturing the oxide semiconductor layer 30.

[0384] First, an oxide semiconductor layer 30a is formed on layer 229. Figure 13A Next, an oxide semiconductor layer 30b is formed on the oxide semiconductor layer 30a. Figure 13B ).

[0385] The oxide semiconductor layer 30b is preferably formed using a sputtering method. Furthermore, the oxide semiconductor layer 30b preferably has a composition suitable for forming a CAAC structure.

[0386] Compared to the deposition method of the oxide semiconductor layer 30b, it is preferable to use a deposition method that causes less damage to the surface to be formed to form the oxide semiconductor layer 30a. Here, the ALD method is used to form the oxide semiconductor layer 30a.

[0387] When depositing metal oxide films using sputtering, alloying sometimes occurs between the components contained in the metal oxide film and the components contained in the layer on the surface being formed, due to damage to the surface being formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even during the heat treatment described later. Furthermore, there is a concern that using an oxide semiconductor layer with alloyed regions in a transistor could negatively impact the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying between the components contained in the metal oxide film and the components contained in the layer on the surface being formed.

[0388] In one embodiment of the present invention, an oxide semiconductor layer 30a is formed on layer 229, and then an oxide semiconductor layer 30b is formed by sputtering. Preferably, the oxide semiconductor layer 30a is formed using a deposition method that minimizes damage to the surface to which it is formed. By forming the oxide semiconductor layer 30a between the oxide semiconductor layer 30b and layer 229 using a deposition method that minimizes damage to the surface to which it is formed, alloying of the components contained in the oxide semiconductor layer 30 with those contained in layer 229 can be suppressed, thereby further improving the crystallinity of the oxide semiconductor layer 30.

[0389] By employing the above structure, the thickness of the alloyed region can be reduced or reduced to a level that is difficult to observe. For example, the thickness of the alloyed region can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Furthermore, Figure 13A and Figure 13B An example is shown where no alloying region is formed between layer 229 and oxide semiconductor layer 30a.

[0390] In addition, the thickness of the alloyed region can sometimes be calculated by performing a linear analysis of the composition of the region and its surroundings using SIMS or Energy Dispersive X-ray Spectroscopy (EDX).

[0391] For example, using the direction perpendicular to the surface where the oxide semiconductor layer 30a is formed as the depth direction, EDX line analysis is performed on the aforementioned region and its surrounding area. Next, in the distribution of quantitative values ​​of each element relative to the depth direction obtained through this analysis, the depth (position) of the interface between the aforementioned region and the oxide semiconductor layer 30a is defined as the depth where the quantitative value of a metal that is a major component of the oxide semiconductor layer 30a but not a major component of the layer forming the surface (here, layer 229) reaches half its value. Additionally, the depth (position) of the interface between the aforementioned region and the layer forming the surface is defined as the depth where the quantitative value of an element that is a major component of the layer forming the surface but not a major component of the oxide semiconductor layer 30a (e.g., Si) reaches half its value. Through these steps, the thickness of the alloyed region can be calculated.

[0392] In one aspect of the oxide semiconductor layer of the present invention, when the thickness of the alloyed region is observed by EDX analysis, for example, its thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0393] Additionally, for example, when using a silicon oxide layer as layer 229 and performing SIMS analysis on the oxide semiconductor layer 30 formed on layer 229, the interface is defined as the depth at which the silicon concentration reaches 50% of the maximum concentration value in layer 229, and the silicon concentration is reduced to 1.0 × 10⁻⁶. 21 atoms / cm 3 The preferred size is 5.0×10. 20 atoms / cm 3 More preferably 1.0×10 20 atoms / cm 3 The distance between the depth and the interface is the thickness t_s2. The thickness t_s2 is preferably less than 3 nm, and more preferably less than 2 nm.

[0394] By setting the thickness t_s2 to a value within the above range, the thickness of the alloyed region can be reduced, thereby allowing the thickness t_s2 to be set to a value within the above range.

[0395] Furthermore, by reducing the alloying region, a CAAC structure can be formed near the surface to be formed. Here, "near the surface to be formed" refers, for example, to a region in the substantially vertical direction of the surface to be formed of the oxide semiconductor layer 30 that is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably more than 1 nm and less than 2 nm.

[0396] Note that CAAC structures near the formed surface can sometimes be identified during TEM observation. For example, when a cross-sectional view of the oxide semiconductor layer 30 is performed using a high-resolution TEM, layered bright spots arranged in a direction parallel to the formed surface are identified near the formed surface.

[0397] Alternatively, a diagram showing crystal orientation can sometimes be used to evaluate the CAAC structure near the formed surface. For example, by obtaining a cross-sectional TEM image, performing a Fast Fourier Transform (FFT) on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the crystal axis orientation of each region, a diagram showing crystal orientation can be obtained. The FFT pattern reflects the same reciprocal space information as the electron diffraction pattern. For example, regions where the calculated crystal axis orientation relative to the formed surface is preferably 70° or more and 100° or less (within 90° ± 20°), more preferably 75° or more and 105° or less (within 90° ± 15°), more preferably 80° or more and 100° or less (within 90° ± 10°), and even more preferably 85° or more and 95° or less (within 90° ± 5°) can be considered as CAAC structures.

[0398] Furthermore, when forming the oxide semiconductor layer 30a using the ALD method, sometimes an oxide semiconductor layer with a microcrystalline or amorphous structure having lower crystallinity than the CAAC structure is formed. That is, in Figure 13A In the manufacturing stages shown, the oxide semiconductor layer 30a sometimes includes regions whose crystallinity is lower than that of the oxide semiconductor layer 30b.

[0399] Here, we will describe the method for forming In-Me-Zn oxide as the oxide semiconductor layer 30a using the ALD method. Further details on the formation of metal oxides using the ALD method will be described later.

[0400] First, a source gas containing an indium-containing precursor is introduced into the chamber and adsorbed onto the surface of layer 229. Here, the substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor.

[0401] Next, the introduction of the source gas is stopped, and the chamber is purged to remove the remaining precursors and reaction products. Then, an oxidant is introduced into the chamber as a reactant, causing it to react with the adsorbed precursors. While indium is adsorbed onto the substrate, components other than indium are desorbed, thereby forming a layer bonded to indium and oxygen. Ozone, oxygen, water, etc., can be used as the oxidant. Next, the introduction of the oxidant is stopped, and the chamber is purged to remove the remaining reactants and reaction products.

[0402] Next, a source gas containing a precursor of element Me is introduced into the chamber and adsorbed onto the indium-oxygen bonded layer. Here, the substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor.

[0403] Next, the introduction of the source gas is stopped, and the chamber is purged to remove the remaining precursors and reaction products. Then, an oxidant is introduced into the chamber as a reactant, causing it to react with the adsorbed precursors. While element Me is adsorbed onto the substrate, components other than element Me are desorbed, thereby forming a layer of element Me bonded to oxygen. Next, the introduction of the oxidant is stopped, and the chamber is purged to remove the remaining reactants and reaction products.

[0404] Next, a source gas containing a zinc precursor is introduced into the processing chamber and adsorbed onto the layer where element Me is bonded to oxygen. Here, the substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor.

[0405] In the thermal ALD process where triethylin is used as a precursor containing indium, triethylgallium is used as a precursor containing gallium, and diethylzinc is used as a precursor containing zinc, for example, the substrate heating temperature is 100°C or higher and 350°C or lower, preferably 150°C or higher and 300°C or lower.

[0406] Next, the introduction of the source gas is stopped, and the chamber is purged to remove the remaining precursors and reaction products. Then, an oxidant is introduced into the chamber as a reactant, causing it to react with the adsorbed precursors. While zinc is adsorbed onto the substrate, components other than zinc are desorbed, thereby forming a zinc-oxygen bonded layer. Next, the introduction of the oxidant is stopped, and the chamber is purged to remove the remaining reactants and reaction products.

[0407] Next, an indium-oxygen bonded layer is formed again on the zinc-oxygen bonded layer using the method described above. By repeating the above method, an In-Me-Zn oxide can be formed on layer 229 as an oxide semiconductor layer 30a using the ALD method.

[0408] The ALD (Alternating Discharge) method allows control over the composition of the resulting film based on the amount of source gas introduced. For example, when using the ALD method, films of arbitrary composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also known as the number of pulses), and the time required for one pulse (also known as the pulse duration). Furthermore, for example, when using the ALD method, films with continuously varying compositions can be deposited by changing the source gas simultaneously with deposition. When deposition is performed while changing the source gas, the deposition time can be shortened compared to deposition using multiple deposition chambers because the time required for transmission or pressure adjustment is eliminated. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0409] After forming an oxide semiconductor layer 30a using the ALD method, an In-Me-Zn oxide is formed on the oxide semiconductor layer 30a as an oxide semiconductor layer 30b using a sputtering method.

[0410] Here, when the oxide semiconductor layer 30b is formed using sputtering, a mixed layer 231 is formed on or near the surface of the oxide semiconductor layer 30a. Furthermore, due to sputtering particles during the formation of the oxide semiconductor layer 30b, or energy supplied to the substrate side by sputtering particles, small crystalline regions may sometimes form in the mixed layer 231. In subsequent heat treatment processes, at least a portion of the oxide semiconductor layer 30a may crystallize using the mixed layer 231 or the small crystalline regions formed in the mixed layer 231 as nuclei.

[0411] In-Me-Zn oxides can be used as the target material for sputtering. When forming metal oxides using sputtering, oxygen or a mixture of oxygen and rare gases can be used as the sputtering gas. Furthermore, by increasing the proportion of oxygen in the sputtering gas, excess oxygen in the deposited oxide film can be increased.

[0412] In addition, sometimes the higher the oxygen flow rate ratio relative to the overall deposit gas used during formation (hereinafter also referred to as the oxygen flow ratio), the more crystalline metal oxides can be formed.

[0413] When forming metal oxides using sputtering, oxygen-excess metal oxides can sometimes be formed by deposition under conditions where the oxygen content in the sputtering gas is higher than 30% and lower than 100%, preferably higher than 70% and lower than 100%. Transistors using oxygen-excess oxide semiconductor layers in the channel formation region can achieve higher reliability. Note that one aspect of the invention is not limited to this. Oxygen-deficient metal oxides can be formed by deposition under conditions where the oxygen content in the sputtering gas is higher than 1% and lower than 30%, preferably higher than 5% and lower than 20%. Transistors using oxygen-deficient metal oxides in the channel formation region can have higher field-effect mobility.

[0414] When metal oxides are formed using sputtering, the composition of the metal oxide after formation sometimes differs from that of the sputtering target. In particular, the zinc content of the metal oxide after formation sometimes decreases to about 50% of the zinc content in the sputtering target.

[0415] When depositing the oxide semiconductor layer 30b using sputtering, it is preferable to heat the substrate. When forming a metal oxide, by increasing the substrate temperature (stage temperature) during metal oxide formation, it is sometimes possible to form a highly crystalline metal oxide. When depositing the oxide semiconductor layer 30b using sputtering, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, more preferably 200°C or higher and 300°C or lower.

[0416] Through the above processes, such as Figure 13B As shown, an oxide semiconductor layer 30a and an oxide semiconductor layer 30b on the oxide semiconductor layer 30a can be formed on layer 229.

[0417] Next, an oxide semiconductor layer 30c is formed on the oxide semiconductor layer 30b. Figure 13C Here, the oxide semiconductor layer 30c is formed using the ALD method. For the formation of the oxide semiconductor layer 30c using the ALD method, please refer to the method for forming the oxide semiconductor layer 30a.

[0418] When an oxide semiconductor layer 30c with lower crystallinity than the CAAC structure is formed on an oxide semiconductor layer 30b using the ALD method, the oxide semiconductor layer 30c is sometimes epitaxially grown with the oxide semiconductor layer 30b as the core. Therefore, when the oxide semiconductor layer 30c is formed, it sometimes includes the region with the CAAC structure. Furthermore, this region with the CAAC structure is preferably formed throughout the entire oxide semiconductor layer 30c.

[0419] Next, a heat treatment process can be carried out.

[0420] The heat treatment temperature can be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, more preferably 350°C or higher and 550°C or lower. Typically, it can be 400°C ± 25°C (375°C or higher and 425°C or lower). Furthermore, the processing time can be 10 hours or less, 1 minute or more and 5 hours or less, or 1 minute or more and 2 hours or less. Additionally, when using an RTA apparatus, the processing time is preferably, for example, 1 second or more and 5 minutes or less. Through this heat treatment, it is expected that the atomic-level crystalline voids in the CAAC structure of the oxide semiconductor layer 30b will be repaired by the oxide semiconductor layer 30c (in other words, the individual crystalline molecules formed using the ALD method).

[0421] There are no particular limitations on the heating apparatus used for heat treatment; it can also include devices that heat the workpiece using heat conduction or thermal radiation from a heating element such as a resistance heating element. For example, electric furnaces or RTA (Rapid Thermal Anneal) devices such as LRTA (Lamp Rapid Thermal Anneal) and GRTA (Gas Rapid Thermal Anneal) devices can be used. An LRTA device heats the workpiece using radiation (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps. A GRTA device uses high-temperature gas for heat treatment.

[0422] Through this heat treatment process, the crystallinity of the region with the CAAC structure in the oxide semiconductor layer 30c is sometimes improved. Furthermore, when this region is only formed below the oxide semiconductor layer 30c after deposition using the ALD method, sometimes the heat treatment process causes the region to extend upwards. Figure 13D In other words, by performing this heat treatment, regions with CAAC structures are sometimes formed throughout the entire oxide semiconductor layer 30c.

[0423] In addition, through this heat treatment process, the oxide semiconductor layer 30b is sometimes further repaired by the oxide semiconductor layer 30c (in other words, each crystal molecule formed using the ALD method) that fills the gaps between the atomic-level crystal portions of the CAAC structure of the oxide semiconductor layer 30b.

[0424] Furthermore, it is preferable to use this heat treatment process to CAAC at least a portion of the oxide semiconductor layer 30a. Figure 13D It is expected that CAAC formation can easily occur using the mixed layer 231 formed in the oxide semiconductor layer 30a during the deposition of the oxide semiconductor layer 30b as a core or seed. The CAAC formation region in the oxide semiconductor layer 30a is preferably large, and preferably extends to the vicinity of layer 229.

[0425] Furthermore, since CAAC formation occurs from the top to the bottom of the oxide semiconductor layer 30a, it is not limited by the material or crystallinity of layer 229 and can reach the vicinity of layer 229. For example, even if layer 229 has an amorphous structure, a highly crystalline oxide semiconductor layer 30a can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one aspect of the present invention is particularly suitable for cases where the layer to be formed has an amorphous structure.

[0426] Notice, Figures 13A to 13D This is a cross-sectional view illustrating a method for depositing metal oxides according to one aspect of the present invention. Additionally, Figures 13A to 13DThis can also be viewed as a schematic diagram illustrating a metal oxide deposition model of one aspect of the present invention. For example... Figures 13A to 13D As shown, oxide semiconductor layers 30a and 30c exhibit high crystallinity by using highly crystallinity oxide semiconductor layer 30b as a nucleus or seed. Specifically, the crystallinity of oxide semiconductor layer 30a is sometimes improved by heat treatment during or after deposition of oxide semiconductor layer 30b. Similarly, the crystallinity of oxide semiconductor layer 30c is sometimes improved by heat treatment during or after deposition of oxide semiconductor layer 30c. Furthermore, the aforementioned heat treatment plays an auxiliary role in improving crystallinity.

[0427] Thus, in one aspect of the metal oxide deposition method of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, oxide semiconductor layers 30a and 30c) can be improved by using a highly crystalline oxide semiconductor layer 30b (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor. In other words, by using oxide semiconductor layer 30b as a nucleus or seed to grow the upper and lower oxide semiconductors in a solid phase, a highly crystalline oxide semiconductor can be formed. The oxide semiconductor formed using the above deposition method, in this case, the CAAC film, can be referred to as axially grown CAAC (AG CAAC).

[0428] In the entire oxide semiconductor layer 30, including oxide semiconductor layer 30a and oxide semiconductor layer 30c, regions having CAAC structures are preferably widely present throughout the entire layer. Figure 14A The diagram shows the crystallized state of oxide semiconductor layers 30a, 30b, and 30c. The crystals in the CAAC-structured regions of oxide semiconductor layer 30a are connected to the crystals in the CAAC-structured regions of oxide semiconductor layer 30b. Similarly, the crystals in the CAAC-structured regions of oxide semiconductor layer 30c are connected to the crystals in the CAAC-structured regions of oxide semiconductor layer 30b. Therefore, sometimes the boundary between oxide semiconductor layers 30a and 30b is not observed. Additionally, sometimes the boundary between oxide semiconductor layers 30b and 30c is not observed. Sometimes oxide semiconductor layer 30 can be described as a single layer without a clearly observed interface. Sometimes oxide semiconductor layer 30 can be described as a monolayer.

[0429] In the regions with CAAC structures in each of the oxide semiconductor layers 30a, 30b, and 30c, bright spots arranged parallel or substantially parallel to the formed surface were identified, for example, during cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the oxide semiconductor layers 30a, 30b, and 30c is preferably substantially parallel to the normal direction of the formed surface of the oxide semiconductor layer.

[0430] In addition, sometimes a portion of the oxide semiconductor layer 30a or oxide semiconductor layer 30c is not crystallized. Figure 14B The example shown illustrates the case where the oxide semiconductor layer 30a is not crystallized near the interface with layer 229. Figure 14C This illustrates the case where the surface of the oxide semiconductor layer 30c is not crystallized. Figure 14D This illustrates a situation where neither the area near the interface between oxide semiconductor layer 30a and layer 229 nor the area near the surface of oxide semiconductor layer 30c is crystallized.

[0431] By improving the crystallinity of the oxide semiconductor layer, the increase in semiconductor layer resistance in transistors using oxide semiconductor layers is suppressed, or the initial characteristics of the transistor (especially the on-state current) are improved, thereby making it possible to realize transistors suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0432] The method for manufacturing an oxide semiconductor layer according to one aspect of the present invention can improve the crystallinity of the metal oxides above and below a metal oxide having a CAAC structure, thereby making the oxide semiconductor layer as a whole a highly crystalline layer.

[0433] In one embodiment of the present invention, the oxide semiconductor layer has high overall crystallinity. Therefore, in the oxide semiconductor layer 30, the boundaries between the stacked films in oxide semiconductor layers 30a, 30b, and 30c are sometimes not identified. In particular, after heat treatment, it is sometimes difficult to identify the boundaries between the stacked films. For example, cross-sectional TEM, cross-sectional STEM, etc., can be used to confirm the presence or absence of boundaries between the stacked films.

[0434] As described above, using metal oxides with a high In content ratio in transistors can improve the transistor's field-effect mobility. On the other hand, oxide semiconductors with a high In content ratio tend to polycrystalline. When using metal oxides with polycrystalline structures in transistors, it negatively impacts the transistor's initial characteristics or reliability. Therefore, by using oxide semiconductors with a high In content ratio in one or both of oxide semiconductor layers 30a and 30c, forming a crystal that reflects the orientation of the crystals contained in oxide semiconductor layer 30b, polycrystalline formation can be suppressed.

[0435] Furthermore, the lattice mismatch between the crystals contained in the oxide semiconductor layer 30b and the crystals contained in the oxide semiconductor layer 30a or 30c is preferably small. Therefore, the oxide semiconductor layer 30a or 30c can form crystals that reflect the orientation of the crystals contained in the oxide semiconductor layer 30b. In this case, for example, when observing a cross-section of the oxide semiconductor layer 30 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the surface to which they are formed can be identified in the oxide semiconductor layer 30a or 30c.

[0436] As long as the lattice mismatch between the crystal contained in the oxide semiconductor layer 30b and the crystal contained in the oxide semiconductor layer 30a or oxide semiconductor layer 30c is small, there are no particular restrictions on the crystal structure of the oxide semiconductor layer 30a or oxide semiconductor layer 30c. The crystal structure of the oxide semiconductor layer 30a or oxide semiconductor layer 30c can be any of the following: cubic, tetragonal, orthorhombic, hexagonal, monoclinic, or trigonal.

[0437] [Composition of the oxide semiconductor layer]

[0438] The composition of oxide semiconductor layer 30a is preferably different from that of oxide semiconductor layer 30b. Similarly, the composition of oxide semiconductor layer 30c is preferably different from that of oxide semiconductor layer 30b. Alternatively, oxide semiconductor layer 30a may use the same composition as oxide semiconductor layer 30c. Or, the composition of oxide semiconductor layer 30a may differ from that of oxide semiconductor layer 30c.

[0439] As described above, the composition of the oxide semiconductor layer 30b is preferably suitable for forming a CAAC structure. The oxide semiconductor layer 30b can be formed, for example, using a sputtering method. The oxide semiconductor layer 30b preferably contains zinc, for example. By including zinc, a highly crystalline metal oxide can be obtained. Furthermore, the oxide semiconductor layer 30b preferably contains the element Me in addition to zinc. By including the element Me in the oxide semiconductor layer 30b, the formation of oxygen vacancies in the metal oxide can be suppressed, for example. Therefore, the reliability of transistors using the oxide semiconductor layer can be improved. Specifically, as the oxide semiconductor layer 30b, a metal oxide with the following composition can be used: In:Me:Zn = 1:1:1 [atomic ratio] or a near-atomic ratio; In:Me:Zn = 1:1:1.2 [atomic ratio] or a near-atomic ratio; In:Me:Zn = 1:1:0.5 [atomic ratio] or a near-atomic ratio; In:Me:Zn = 1:1:2 [atomic ratio] or a near-atomic ratio; In:Me:Zn = 4:2:3 [atomic ratio] or a near-atomic ratio; In:Me:Zn = 1:3:2 [atomic ratio] or a near-atomic ratio; or In:Me:Zn = 1:3:4 [atomic ratio] or a near-atomic ratio. Furthermore, the near-atomic composition includes a range of ±30% of the desired atomic ratio. Additionally, one or more of gallium, aluminum, and tin are preferably used as the element Me.

[0440] The oxide semiconductor layer 30b may also not contain element Me. For example, In-Zn oxide can be used. Specifically, it can have an In:Zn ratio of 1:1 or similar, an In:Zn ratio of 2:1 or similar, or an In:Zn ratio of 4:1 or similar. Alternatively, indium oxide can be used. Additionally, it may contain trace amounts of element Me. For example, it can have an In:Ga:Zn ratio of 4:0.1:1 or similar, or an In:Ga:Zn ratio of 2:0.1:1 or similar. Alternatively, it can have an In:Sn:Zn ratio of 4:0.1:1 or similar, or an In:Sn:Zn ratio of 2:0.1:1 or similar.

[0441] The oxide semiconductor layers 30a and 30c can be metal oxides with a high In content. The oxide semiconductor layers 30a and 30c can be formed, for example, using the ALD method. Furthermore, metal oxides with a higher In content than elemental Me are particularly preferred. By using metal oxides with a high In content, the on-state current can be increased and the frequency characteristics improved when the oxide semiconductor layer is used in a transistor.

[0442] Alternatively, oxide semiconductor layers 30a and 30c may not contain element Me. For example, In-Zn oxide may be used. Specifically, compositions with an In:Zn ratio of 1:1 or similar, an In:Zn ratio of 2:1 or similar, or an In:Zn ratio of 4:1 or similar may be used. Alternatively, indium oxide may be used. Furthermore, oxide semiconductor layers 30a and 30c may also contain trace amounts of element Me. Specifically, compositions with an In:Ga:Zn ratio of 4:0.1:1 or similar, an In:Ga:Zn ratio of 2:0.1:1 or similar, an In:Sn:Zn ratio of 4:0.1:1 or similar, or an In:Sn:Zn ratio of 2:0.1:1 or similar may be used.

[0443] In addition, oxide semiconductor layers 30a and 30c can use metal oxides with a higher In content than oxide semiconductor layer 30b.

[0444] For example, metal oxides with a higher Ga content than oxide semiconductor layer 30b can be used as oxide semiconductor layers 30a and 30c. For instance, oxide semiconductor layers 30a and 30c preferably use metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar. By increasing the Ga content, the band gaps of oxide semiconductor layers 30a and 30c can sometimes be made larger than those of oxide semiconductor layer 30b. Thus, oxide semiconductor layer 30b is sandwiched between oxide semiconductor layers 30a and 30c with larger band gaps, and oxide semiconductor layer 30b is primarily used as a current path (channel). By sandwiching oxide semiconductor layer 30b between oxide semiconductor layers 30a and 30c, trapped states at and near the interface of oxide semiconductor layer 30b can be reduced. This enables buried-channel transistors with the channel located far from the insulating layer interface, thereby improving field-effect mobility. Furthermore, the influence of interface states that can form on the back channel side is reduced, suppressing transistor optical degradation (e.g., optical negative bias degradation), thus improving transistor reliability.

[0445] Alternatively, one of the oxide semiconductor layers 30a and 30c may use a metal oxide with a higher proportion of In than the oxide semiconductor layer 30b, and the other may use a metal oxide with a higher proportion of Ga than the oxide semiconductor layer 30b.

[0446] Alternatively, multiple layers having the above-described composition may be stacked in oxide semiconductor layers 30a, 30b, and 30c. For example, oxide semiconductor layer 30c may also have a structure in which a metal oxide with a high proportion of In is stacked on top of a metal oxide with a high proportion of Ga.

[0447] Furthermore, in one embodiment of the oxide semiconductor layer of the present invention, even if the oxide semiconductor layers 30a and 30c are composed of a structure that is not easily formed when forming a single layer, the entire oxide semiconductor layer including the oxide semiconductor layers 30a and 30c can have a CAAC structure by crystal growth with the oxide semiconductor layer 30b as the nucleus. Alternatively, a region including at least a portion of each of the oxide semiconductor layers 30a and 30c extending to the region of the oxide semiconductor layer 30b can have a CAAC structure.

[0448] In particular, when the oxide semiconductor layers 30a and 30c have a high In ratio, a crystallinity suitable for transistors can be obtained. In one embodiment of the oxide semiconductor layer of the present invention, the following effects can be simultaneously achieved: improving the on-state characteristics of the transistor by increasing the In ratio; and improving reliability by employing a highly crystallinity CAAC structure.

[0449] Alternatively, oxide semiconductor layers 30a and 30c can also use metal oxides with the same composition as oxide semiconductor layer 30b. By using the same composition, it is sometimes easy to achieve CAAC after heat treatment.

[0450] Furthermore, compared to oxide semiconductor layers with CAAC structures formed using one deposition method, oxide semiconductor layers with CAAC structures formed using the two deposition methods described above sometimes have higher relative permittivity, film density, and film hardness, among one or more of these.

[0451] By using the oxide semiconductor layer with CAAC structure formed by the above two deposition methods to form the channel region of the transistor, transistors with excellent characteristics can be realized (e.g., transistors with large on-state current, transistors with high field-effect mobility, transistors with small S-value, transistors with high frequency characteristics (also known as f-characteristics), transistors with high reliability, etc.).

[0452] Analysis of the composition of the metal oxide in the oxide semiconductor layer 30 can be performed using methods such as EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, multiple methods can be combined. Note that the actual content ratio of elements with low abundance may differ from the analytically obtained ratio due to the limitations of analytical precision. For example, when the content of element Me is low, the analytically obtained content ratio of element Me may sometimes be lower than the actual content ratio.

[0453] In one embodiment of the present invention, the oxide semiconductor layer comprises a metal oxide.

[0454] Metal oxides sometimes exhibit lattice defects. Lattice defects refer to point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. In addition, the main causes of lattice defects include differences in the proportion of atoms of the constituent elements (too many or too few constituent atoms) and impurities.

[0455] When metal oxides are used as the semiconductor layer of a transistor, lattice defects in the metal oxide can lead to carrier generation or trapping. Therefore, when a metal oxide with many lattice defects is used as the semiconductor layer of a transistor, the transistor's electrical characteristics may become unstable. Thus, it is preferable to use metal oxides with fewer lattice defects in the semiconductor layer of a transistor.

[0456] The types and quantities of lattice defects that are likely to exist in metal oxides vary depending on the structure of the metal oxide or the deposition method of the metal oxide.

[0457] Therefore, it is preferable to use highly crystalline metal oxides for the semiconductor layer of transistors. For example, metal oxides with a CAAC structure or single-crystal structures are preferred. By using this metal oxide in the transistor, a transistor with good electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0458] Furthermore, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. To increase the on-state current of the transistor, it is preferable to improve the mobility of the metal oxide used in the transistor. To improve the mobility of the metal oxide, it is necessary to improve the transport of charge carriers (electrons in an n-channel transistor) or reduce scattering factors that affect the transport of charge carriers. Additionally, charge carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region where charge carriers can easily flow along the length of the channel, the on-state current of the transistor can be increased.

[0459] Impurities in oxide semiconductors

[0460] Here, we will explain the effects of various impurities in oxide semiconductors.

[0461] In the channel formation region of a transistor using oxide semiconductors as the semiconductor layer, it is preferable to have fewer oxygen vacancies or lower concentrations of impurities such as hydrogen, nitrogen, and metal elements compared to the source and drain regions. When oxygen vacancies (V0) are present in the channel formation region of the oxide semiconductor... O When oxygen vacancies are present and impurities are present, the electrical properties are easily altered, which may reduce reliability. Additionally, hydrogen near oxygen vacancies forms V0. O H may generate electrons that become charge carriers. Therefore, when oxygen vacancies are included in the channel formation region of an oxide semiconductor, the transistor tends to have always-on characteristics. Thus, in the channel formation region, V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high-resistivity region with low carrier concentration. Therefore, the channel formation region of the transistor can be described as i-type (intrinsic) or substantially i-type.

[0462] Therefore, reducing the impurity concentration in oxide semiconductors is effective in stabilizing the electrical characteristics of transistors. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in oxide semiconductors refer to elements other than the main components constituting the oxide semiconductor. For example, elements with a concentration below 0.1 atomic% can be considered impurities.

[0463] When an oxide semiconductor contains silicon or carbon, one of Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 Below. Additionally, the silicon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 the following.

[0464] Furthermore, when nitrogen is included in an oxide semiconductor, electrons are generated as charge carriers, increasing the charge carrier concentration and making it easier to n-type. As a result, transistors using nitrogen-containing oxide semiconductors tend to have always-on characteristics. Alternatively, when nitrogen is included in an oxide semiconductor, trapped states sometimes form. Consequently, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0465] Furthermore, hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using hydrogen-containing oxide semiconductors tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably below 5×10 19 atoms / cm 3 More preferably, less than 1×10 19 atoms / cm 3 Further optimization of less than 5×10 18 atoms / cm 3 Further optimization is to select those with a value lower than 1×10 18 atoms / cm 3 Furthermore, it is preferred to have a value lower than 1×10 17 atoms / cm 3 .

[0466] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect states can sometimes form, generating charge carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0467] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0468] The carrier concentration of the oxide semiconductor used as the channel formation region is preferably 1 × 10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 Further optimization of less than 1×10 16 cm -3 Further optimization of less than 1×10 13 cm -3 Further optimization of less than 1×10 12 cm -3Note that there is no specific limit to the lower limit of the carrier concentration of the oxide semiconductor in the region used as the channel formation region; for example, it can be set to 1 × 10⁻⁶. -9 cm -3 .

[0469] [c-axis orientation]

[0470] One embodiment of the present invention has an oxide semiconductor layer with a CAAC structure. For example, crystal orientation can be used to evaluate the crystallinity of the oxide semiconductor layer of one embodiment of the present invention.

[0471] Crystal orientation can be obtained from TEM images by performing a Fast Fourier Transform (FFT). Specifically, the crystal axis orientation can be obtained from the FFT pattern. The FFT pattern obtained through FFT processing reflects the same reciprocal lattice space information as the electron diffraction pattern.

[0472] By performing FFT processing on each region within a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region within a certain area, a map showing the crystal orientation can be created. Specifically, two high-intensity spots are observed in the FFT pattern of a region with layered crystals. The crystal axis orientation of this region can be obtained from the angle of the line segment connecting these two spots.

[0473] The degree of c-axis orientation can be calculated by determining the proportion of the c-axis orientation region in a diagram showing crystal orientation. Here, the c-axis orientation region refers to a region whose orientation aligns with the c-axis, and the difference between its orientation and the c-axis is preferably within 20°, more preferably within 15°, even more preferably within 10°, and still more preferably within 5°. Here, the angle of the c-axis is relative to the surface being formed.

[0474] In one embodiment of the oxide semiconductor layer of the present invention, cross-sectional or planar TEM observation of the oxide semiconductor layer can be performed, and the c-axis orientation can be calculated using the above-described diagram showing crystal orientation. Furthermore, the region for performing the FFT (also called the FFT window) can, for example, be a circle with a diameter of 1.0 nm. Note that the region for performing the FFT is not limited to a circle.

[0475] Alternatively, when using cross-sectional TEM images for analysis, the observation area of ​​the cross-sectional TEM image can be set to a region with a longitudinal direction perpendicular to the formed surface and a transverse width of 100 nm. Note that the observation area is not limited to this.

[0476] In one embodiment of the oxide semiconductor layer of the present invention, the c-axis orientation degree is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, even more preferably 80% or more, still more preferably 90% or more, and still more preferably 95% or more. Here, it is preferable to calculate the c-axis orientation degree, for example, as the proportion of the region whose difference from the c-axis is within 20°.

[0477] Furthermore, the c-axis orientation degrees of the regions where the oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c are deposited are Rc1, Rc2, and Rc3, respectively. Rc2 is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, even more preferably 80% or more, still more preferably 90% or more, and still more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, even more preferably 80% or more, still more preferably 90% or more, and still more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1. Here, it is preferable to calculate the c-axis orientation degree, for example, as the proportion of regions whose difference from the c-axis is within 20°.

[0478] Sometimes the boundaries of oxide semiconductor layers 30a, 30b and 30c are not observed after the oxide semiconductor layer 30 is fabricated.

[0479] In one embodiment of the present invention, the oxide semiconductor layer 30 can be sequentially divided into three regions—a first region, a second region, and a third region—from one side of layer 229. Each region is a layered region.

[0480] The first, second, and third regions all have a CAAC structure. Furthermore, the c-axis orientation degree of the third region is preferably higher than that of the first region. Similarly, the c-axis orientation degree of the second region is preferably higher than that of the first region. The c-axis orientation degree of the third region is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, even more preferably 80% or more, still more preferably 90% or more, and even more preferably 95% or more. The c-axis orientation degree of the second region is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, even more preferably 80% or more, still more preferably 90% or more, and even more preferably 95% or more. Here, it is preferable to calculate the c-axis orientation degree, for example, as the proportion of regions whose difference from the c-axis is within 20°.

[0481] The first region is located on the top surface of the delamination layer 229 at a distance of 0 nm to 3 nm, and the third region is located on the top surface of the delamination oxide semiconductor layer 30 at a distance of 0 nm to 3 nm.

[0482] Alternatively, the thickness of the layers in each region may be approximately equal.

[0483] [Oxide semiconductor layer of a transistor]

[0484] The oxide semiconductor layer of one aspect of the present invention can be used as the semiconductor layer of a transistor.

[0485] Figure 15A yes Figure 2B The enlarged view of the area including transistor 500 in the cross-sectional view shown. Figure 15B yes Figure 2B An enlarged view of the area including transistor 200 in the cross-sectional view shown.

[0486] The oxide semiconductor layer 530 includes oxide semiconductor layer 530a, oxide semiconductor layer 530b, and oxide semiconductor layer 530c. As oxide semiconductor layer 530a, oxide semiconductor layer 530b, and oxide semiconductor layer 530c, the aforementioned oxide semiconductor layer 30a, oxide semiconductor layer 30b, and oxide semiconductor layer 30c can be used.

[0487] The oxide semiconductor layer 230 includes oxide semiconductor layer 230a, oxide semiconductor layer 230b, and oxide semiconductor layer 230c. As oxide semiconductor layer 230a, oxide semiconductor layer 230b, and oxide semiconductor layer 230c, the aforementioned oxide semiconductor layer 30a, oxide semiconductor layer 30b, and oxide semiconductor layer 30c can be used.

[0488] Note that in other figures, oxide semiconductor layers 530a, 530b, 530c, 230a, 230b, and 230c are sometimes omitted for clarity.

[0489] The oxide semiconductor layer 530a contacts the top surface of the recess in the conductive layer 520, the side surface of the recess in the conductive layer 520, the side surface of the opening 590a in the insulating layer 280, the side surface of the opening 590b in the conductive layer 540, and the top surface of the conductive layer 540. Additionally, the oxide semiconductor layer 230a contacts the top surface of the conductive layer 120, the side surface of the recess in the conductive layer 120, the side surface of the opening 290a in the insulating layer 280, the side surface of the opening 290b in the conductive layer 240, and the top surface of the conductive layer 240.

[0490] The insulating layer 551 is disposed in contact with the oxide semiconductor layer 530c and the oxide semiconductor layer 230c.

[0491] The oxide semiconductor layer 530 is disposed along the side of the opening 590a of the insulating layer 280. Therefore, the c-axis direction of the CAAC structure of the oxide semiconductor layer 530 is, for example, a direction approximately perpendicular to the side of the opening 590a at an angle θ280m. Furthermore, the oxide semiconductor layer 230 is disposed along the side of the opening 290a of the insulating layer 280. Therefore, the c-axis direction of the CAAC structure of the oxide semiconductor layer 230 is, for example, a direction approximately perpendicular to the side of the opening 290a at an angle θ280.

[0492] In an OS transistor, when oxygen vacancies (V0) exist in the channel formation region of the oxide semiconductor... O When impurities are present, the electrical properties are prone to change, which may reduce reliability. Additionally, hydrogen near oxygen vacancies forms defects where hydrogen enters the oxygen vacancy (sometimes referred to below as V). O H) may generate electrons that become charge carriers. Therefore, when the channel formation region in an oxide semiconductor contains oxygen vacancies, the OS transistor tends to have always-on characteristics. Thus, it is preferable to minimize oxygen vacancies and impurities in the channel formation region of an oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region of the oxide semiconductor is reduced and is i-typed (intrinsicized) or substantially i-typed.

[0493] On the other hand, the source and drain regions of the OS transistor are preferably the following regions: due to the greater number of oxygen vacancies compared to the channel formation region, V O The higher concentration of impurities such as hydrogen, nitrogen, and metal elements leads to an increased carrier concentration and thus lower resistance. In other words, compared to the channel formation region, the source and drain regions of an OS transistor are preferably n-type regions with higher carrier concentration and lower resistance.

[0494] In transistor 500, the region of oxide semiconductor layer 530 in contact with insulating layer 280 and its vicinity are used as the channel formation region of transistor 500. Similarly, the region of oxide semiconductor layer 230 in contact with insulating layer 280 and its vicinity are used as the channel formation region of transistor 200.

[0495] One of the regions of oxide semiconductor layer 530 that contact conductive layer 520 and that contact conductive layer 540 is used as a source region, and the other is used as a drain region. Similarly, one of the regions of oxide semiconductor layer 230 that contact conductive layer 120 and that contact conductive layer 240 is used as a source region, and the other is used as a drain region. In other words, in transistors 500 and 200, the channel formation region is sandwiched between the source and drain regions.

[0496] When the oxide semiconductor layer comes into contact with the source and drain electrodes, metal compounds or oxygen vacancies are formed, reducing the resistance of the region of the oxide semiconductor layer in contact with the source and drain electrodes. This reduces the contact resistance between the oxide semiconductor layer and the source and drain electrodes.

[0497] One embodiment of the present invention provides an oxide semiconductor layer having a CAAC structure. In the oxide semiconductor layer having a CAAC structure, metal atoms in the crystalline portion are arranged in layers in a direction parallel to or substantially parallel to the surface to be formed.

[0498] In oxide semiconductor layers 530 and 230, metal atoms are arranged in layers in a direction parallel or substantially parallel to the sidewalls of openings 590 and 290, which serve as the formed surfaces. Alternatively, the ab plane of the CAAC structure can be provided in a direction parallel or substantially parallel to the formed surfaces. By employing this structure, the ab plane of the CAAC structure can be provided in the channel of the transistor 200 along the direction of current flow. This increases the on-state current of the transistor.

[0499] For example, the thickness of the oxide semiconductor layer 530 or the oxide semiconductor layer 230 is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less.

[0500] <Examples of Semiconductor Device Manufacturing Methods>

[0501] Reference Figures 16A to 17B This describes a method for manufacturing semiconductor devices. Here, we illustrate it as an example. Figure 7B The manufacturing method of the structure shown. Note that, regarding the materials and forming methods of each component, the same parts as those already described are sometimes omitted.

[0502] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, CVD, vacuum evaporation, PLD, ALD, and other methods.

[0503] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. Additionally, there is RF-DC sputtering, which combines RF and DC sputtering. RF sputtering is preferred for deposition using insulating targets. DC sputtering is primarily used when depositing conductive targets. Furthermore, in DC sputtering, in addition to forming conductive films, insulating films can also be formed through reactive sputtering. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-DC sputtering allows for control of ion energy during deposition and the potential on the target side. Therefore, compared to RF sputtering, deposition-related damage can be reduced. Furthermore, films of high quality can be obtained.

[0504] As sputtering methods, ionization sputtering and long-range ballistic sputtering can be used, for example. Ionization sputtering involves ionizing sputtered particles generated from a target using RF or similar methods, and then depositing them anisotropically using a self-bias voltage or similar method. Furthermore, in long-range ballistic sputtering, anisotropic deposition can be achieved by increasing the distance between the sputtering target and the substrate.

[0505] Note that CVD methods can be categorized into PECVD, thermal CVD (TCVD), and photoCVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0506] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because plasma is not used in thermal CVD, plasma damage to the workpiece is reduced. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes accumulate charge due to receiving charge from plasma. This accumulated charge can sometimes damage these components. On the other hand, because such plasma damage does not occur in thermal CVD, the yield of semiconductor devices can be improved. Additionally, since plasma damage during deposition is absent in thermal CVD, films with fewer defects can be obtained.

[0507] As ALD methods, there are thermal ALD (thermal ALD) methods that use only thermal energy to cause the precursors and reactants to react, and PEALD (Plasma Enhanced ALD) methods that use reactants excited by plasma.

[0508] Alternating current deposition (ALD) can deposit atoms in each layer, thus achieving advantages such as the ability to deposit very thin films, deposit structures with high aspect ratios, deposit with fewer defects such as pinholes, achieve excellent coverage, and deposit at low temperatures. In the PEALD (Plasma Enhanced Alternating Current) method, deposition can be performed at even lower temperatures by utilizing plasma, making it sometimes preferred. The precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method sometimes contain more impurities such as carbon compared to films formed using other deposition methods. Furthermore, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Note that while the metal oxide deposition method of this invention uses the ALD method, due to the use of high substrate temperatures during deposition and one or both of the impurity removal process, the amount of carbon and chlorine contained in the film is sometimes less compared to cases where the ALD method is used without these conditions.

[0509] Unlike deposition methods that use particles released from a target, CVD and ALD methods are deposition methods that form films due to reactions on the surface of the workpiece. Therefore, ALD is a deposition method with good step coverage, less affected by the shape of the workpiece. In particular, ALD has good step coverage and thickness uniformity, making it suitable for forming films covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to use it in combination with other deposition methods such as sputtering or CVD, which have faster deposition rates. For example, when creating a stacked structure of a first metal oxide and a second metal oxide, a method can be used to deposit the first metal oxide using sputtering and then deposit the second metal oxide using ALD on the first metal oxide. For example, if the first metal oxide has crystalline portions, the second metal oxide may sometimes grow crystals using these crystalline portions as nuclei.

[0510] CVD or ALD methods allow control of the film composition by adjusting the source gas flow rate ratio. For example, when using CVD and ALD, films with arbitrary compositions can be deposited based on the source gas flow rate ratio. Furthermore, for example, when using CVD or ALD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. When deposition is performed while changing the source gas flow rate ratio, the time required for transmission and pressure adjustment is eliminated, thus reducing deposition time compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0511] Furthermore, when using the ALD method, membranes of arbitrary composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also known as the number of pulses), and the time required for one pulse (also known as the pulse time). When using the ALD method, membranes of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, when introducing multiple different precursors, membranes of arbitrary composition can be deposited by controlling the number of cycles for each precursor.

[0512] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0513] In addition, when processing thin films constituting semiconductor devices, photolithography or similar methods can be used. Alternatively, nanoimprint lithography, sandblasting, or lift-off methods can be used to process the thin films. Furthermore, island-shaped thin films can also be directly formed using deposition methods that utilize metal masks or similar masking techniques.

[0514] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, then processing the film through etching or similar means, and finally removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to shape the film into the desired form.

[0515] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these rays. Alternatively, ultraviolet light, KrF lasers, or ArF lasers can also be used. Immersion exposure can also be employed. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams allow for extremely fine processing and are therefore preferred. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0516] As a method for etching thin films, dry etching, wet etching, and sandblasting can be used.

[0517] First, a conductive layer 110 is formed on the insulating layer 140, and an insulating layer 180 is formed on the insulating layer 140 and the conductive layer 110.

[0518] Next, an opening 190 is provided in the insulating layer 180 to reach the conductive layer 110.

[0519] Then, a conductive layer 115 is formed inside the opening 190 of the insulating layer 180 and on the insulating layer 180. The conductive layer 115 is preferably provided in such a way that it contacts the top surface of the conductive layer 110 inside the opening 190.

[0520] Next, an insulating layer 130 is formed on the insulating layer 180 and the conductive layer 115. The insulating layer 130 is disposed within the opening 190 such that it covers the sidewall of the opening 190 through the conductive layer 115. In addition, the uniformity of the thickness of the region of the insulating layer 130 covering the conductive layer 115 is preferably high.

[0521] Next, a conductive film that will become conductive layer 120 and conductive layer 520 is formed on the insulating layer 130, and the conductive film is processed to form conductive layer 120 and conductive layer 520. Figure 16A The conductive film is preferably arranged to fill the opening 190. Alternatively, a planarization process (also known as CMP treatment) can be performed after the conductive film is formed using chemical mechanical polishing (CMP).

[0522] Subsequently, an insulating layer 280 is formed on the insulating layer 130, the conductive layer 120 and the conductive layer 520, and a conductive film that will become the conductive layer 240 and the conductive layer 540 is formed on the insulating layer 280.

[0523] Furthermore, it is preferable to perform a planarization process using CMP (Continuous Motion Processing) after depositing the insulating layer 280 to planarize the top surface of the insulating layer 280. By performing the planarization process on the insulating layer 280, the surfaces on which the conductive layers 240 and 540 for wiring are formed can be flattened, thereby suppressing the disconnection of the conductive layers 240 and 540. Alternatively, the planarization process can be omitted, which can reduce manufacturing costs.

[0524] Next, an opening 290 is provided at a position overlapping with the conductive layer 120, which will become the conductive layer 240 and the insulating layer 280. Figure 16B An opening 590 is provided at a position overlapping with the conductive layer 520, which will become the conductive layer 540 and the insulating layer 280. At this time, a recess is formed at a position where the conductive layer 120 overlaps with the opening 290, and a recess is formed at a position where the conductive layer 520 overlaps with the opening 590.

[0525] Next, heat treatment may be performed. The heat treatment may be performed at a temperature of 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. For example, it is preferable to perform the treatment at a temperature of 350°C or higher and 550°C or lower for 1 minute or more and 1 hour or more and 10 minutes or more and 30 minutes or lower.

[0526] The heating treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heating treatment is performed in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio is preferably set to about 20%. The heating treatment can also be performed under reduced pressure. Alternatively, the heating treatment can be performed in a nitrogen or inert gas atmosphere, and then, in order to replenish the detached oxygen, the heating treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above-described heating treatment, impurities such as water contained in the insulating layer 280 and the like can be reduced before depositing the oxide semiconductor layer 230 and the oxide semiconductor layer 530.

[0527] The gas used in the heat treatment is preferably of high purity. For example, the water content in the gas used in the above-mentioned heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulating layer 280 can be prevented as much as possible.

[0528] Next, a film that will become an oxide semiconductor layer 230 is formed in a manner that covers the opening 290, and a film that will become an oxide semiconductor layer 530 is formed in a manner that covers the opening 590.

[0529] Then, the films that will become conductive layer 240, oxide semiconductor layer 230, conductive layer 540, and oxide semiconductor layer 530 are processed into islands to form conductive layer 240, oxide semiconductor layer 230, conductive layer 540, and oxide semiconductor layer 530. In this process, by using the same mask as the mask for processing conductive layer 240 and conductive layer 540 and the mask for processing oxide semiconductor layer 230 and oxide semiconductor layer 530, the conductive layer and the oxide semiconductor layer can be processed simultaneously.

[0530] Next, an insulating layer 551 is formed on the oxide semiconductor layer 230, the oxide semiconductor layer 530 and the insulating layer 280.

[0531] Heat treatment can be performed after the insulating layer 551 is formed. By performing heat treatment, for example, the crystallinity of the oxide semiconductor layer 230 and the oxide semiconductor layer 530 can be improved.

[0532] Next, a film that will become the charge storage layer 552 is formed on the insulating layer 551. Then, an insulating film that will become the insulating layer 553 is formed on this film. Next, the insulating layer 553 is formed by processing the insulating film. During this processing, the region of the insulating film that overlaps with the oxide semiconductor layer 230 is removed.

[0533] Subsequently, the film that will become the charge storage layer 552 is processed to form the charge storage layer 552. Figure 17A During this process, the region of the film overlapping with the oxide semiconductor layer 230 is removed. Here, the same mask can be used to process both the film that will become the charge storage layer 552 and the film that will become the insulating layer 551.

[0534] Furthermore, by not performing the processing of the film that will become the insulating layer 553 or by not removing the region of the insulating layer 553 that overlaps with the oxide semiconductor layer 230, it is possible to manufacture... Figure 9A The structure shown.

[0535] Then, a conductive film is formed to become conductive layer 260 and conductive layer 560, and the conductive film is processed to form conductive layer 260 and conductive layer 560. Figure 17B ).

[0536] Next, an insulating layer 283 is formed on conductive layer 260 and conductive layer 560. Then, an insulating layer 285 is formed on insulating layer 283. Through the above steps, a semiconductor device according to one aspect of the present invention can be manufactured.

[0537] <Structure Example of a Semiconductor Device 3>

[0538] Figure 18AThe semiconductor device shown includes a memory cell 151 instead of a memory cell 150, mainly in this respect... Figure 7B The semiconductor devices shown are different.

[0539] The storage cell 151 includes a transistor 200_2 on the insulating layer 140 and a transistor 200 on the transistor 200_2.

[0540] A transistor 200_2 and an insulating layer 280_2 are disposed on the insulating layer 140.

[0541] Transistor 200_2 includes conductive layer 120_2, conductive layer 240_2 on insulating layer 280_2, oxide semiconductor layer 230_2, insulating layer 551_2 on oxide semiconductor layer 230_2, and conductive layer 120 on insulating layer 551_2.

[0542] The oxide semiconductor layer 230_2 is disposed inside the opening 290_2 included in the insulating layer 280_2 and the conductive layer 240_2.

[0543] Regarding the structure of transistor 200_2, the structure of transistor 200 can be referred to. Furthermore, regarding insulating layer 280_2, conductive layer 240_2, oxide semiconductor layer 230_2, insulating layer 551_2, and conductive layer 120, references can be made to the materials and structures applicable to insulating layer 280, conductive layer 120, conductive layer 240, oxide semiconductor layer 230, insulating layer 551, and conductive layer 260, respectively.

[0544] Furthermore, the shape of conductive layer 120_2 differs from that of conductive layer 120 of transistor 200. Conductive layer 120_2 is formed in an island shape on insulating layer 140. Conductive layer 120_2 can use materials that are also suitable for conductive layer 120.

[0545] exist Figure 18A In the conductive layer 120_2, a recess is provided that overlaps with the opening 290_2.

[0546] Note that the conductive layer 120 of transistor 200_2 can be used as the conductive layer 120 of transistor 200. An insulating layer 280 is provided on the conductive layer 120. A recess is provided in the conductive layer 120 that overlaps with the opening 290 of the insulating layer 280 and the conductive layer 240.

[0547] exist Figure 18A In the storage cell 151 shown, a capacitor generated between the conductive layer 240_2 and the conductive layer 120 can be used, thereby allowing data to be stored without forming a separate capacitor.

[0548] Transistor 200 is arranged to overlap with transistor 200_2. Opening 290 has an area that overlaps with opening 290_2.

[0549] like Figure 18B As shown, a memory cell array 631 can be constructed by arranging multiple memory cells 151 in a matrix. Here, transistor 200 can be used as transistor M2 included in memory cell 151, and transistor 200_2 can be used as transistor M3.

[0550] One of the source and drain of transistor M2 is connected to the gate of transistor M3. The other of the source and drain of transistor M1 is connected to wiring WBL. The gate of transistor M2 is connected to wiring WOL. One of the source and drain of transistor M3 is connected to wiring RBL. The other of the source and drain of transistor M3 is connected to wiring SL.

[0551] Wiring WBL corresponds to conductive layer 240, and wiring WOL corresponds to conductive layer 260.

[0552] <Example 4 of semiconductor device structure>

[0553] like Figure 19 As shown, in the semiconductor device of the present invention, memory cells can be stacked on the layer of the circuit in which the driving memory cells are disposed.

[0554] exist Figure 19 In the middle, transistor 500 and memory cell 150 (transistor 200 and capacitor 100) are arranged above transistor 300.

[0555] Transistor 300 can, for example, be used as a transistor included in the sense amplifier described later.

[0556] about Figure 19 The transistor 500 and memory cell 150 shown can be referred to Figure 7B Records such as those of [etc.]

[0557] Transistor 300 is disposed on substrate 311 and includes a conductive layer 316 serving as a gate, an insulating layer 315 serving as a gate insulator, a semiconductor region 313 formed by a portion of substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. Transistor 300 can be a p-channel transistor or an n-channel transistor. Transistor 300 is electrically separated from other transistors by a device separation region 321. The device separation region can be formed using methods such as LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation).

[0558] Here, in Figure 19 In the transistor 300 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductive layer 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulating layer 315 in between. Alternatively, the conductive layer 316 can be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 300 is also referred to as a FIN-type transistor. Alternatively, an insulating layer used to form a mask for the convex portion can be included in contact with the upper surface of the convex portion. Although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with a convex shape can also be formed by processing an SOI substrate.

[0559] Notice, Figure 19 The transistor 300 shown is just an example and is not limited to this structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0560] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be configured according to the design. Here, in conductive layers that function as plugs or wiring, the same symbol is sometimes used to represent multiple structures. Additionally, in this specification, wiring and plugs electrically connected to wiring can also be considered as a single component. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a plug.

[0561] For example, on transistor 300, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductive layers 328 are embedded in insulating layers 320 and 322, and conductive layers 330 are embedded in insulating layers 324 and 326. Additionally, conductive layers 328 and 330 are used as connectors or wiring.

[0562] In addition, the insulating layer used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulating layer 322, its top surface can also be planarized by using a planarization process such as CMP.

[0563] Wiring layers can also be formed on the insulating layer 326 and the conductive layer 330. Figure 19 In the structural example shown, insulating layers 350, 352, and 354 are stacked sequentially. Furthermore, a conductive layer 356 is formed within insulating layers 350, 352, and 354. The conductive layer 356 is used as a plug or wiring.

[0564] The insulating layer 352 and insulating layer 354 used as interlayer films can be referred to the description of insulating layers that can be used in the above-mentioned semiconductor devices.

[0565] As conductive layers used as plugs or wiring, such as conductive layer 328, conductive layer 330, and conductive layer 356, refer to the description of conductive layers that can be used in the above-mentioned semiconductor devices.

[0566] The conductive layer 240 included in transistor 200 is electrically connected to the low-resistance region 314b, which serves as the source or drain region of transistor 300, through conductive layers 357, 356, 330, and 328 embedded in insulating layers 280, 130, 180, and 140.

[0567] <Example 5 of semiconductor device structure>

[0568] In a memory cell array, the transistors and other components of the memory cells can also be configured in a three-dimensional matrix.

[0569] Figure 20A and Figure 20B These are plan views of the storage cell array. Figure 20A In the shown memory cell array 901, 2×2 transistors 500 are arranged in the X and Y directions. Additionally, in Figure 20B In the storage cell array 902 shown, there are 2×2 storage cells 150 arranged in the X and Y directions.

[0570] Figure 21 It is along Figure 20A The dotted lines between B1 and B2 shown are Figure 20B The cross-sectional view between the dotted lines B5 and B6 is shown.

[0571] exist Figure 21 In the middle, multiple layers 60 are stacked. Figure 21 Layers 60_1 and 60_2 are shown. Layer 60_1 contains memory cell array 901 and memory cell array 902. Layer 60_2 contains memory cell array 901 and memory cell array 902. That is to say, Figure 20A and Figure 20B This is a plan view when layer 60_2 is stacked on top of layer 60_1.

[0572] In the memory cell array 901 of layer 60, multiple transistors 500 share conductive layers 520 and 540. The conductive layers 520 of the multiple transistors 500 are interconnected. In addition, the conductive layers 540 are interconnected.

[0573] Figure 20A and Figure 21 The storage cell array 901 shown can, for example, be used Figure 5A The circuit of the memory cell array 601 shown.

[0574] exist Figure 21 In layer 60_1, the conductive layer 540 of the memory cell array 901 is connected to the upper conductive layer via conductive layer 244b. Additionally, the conductive layer 540 of the memory cell array 901 in layer 60_2 is connected to the upper conductive layer via conductive layer 244a.

[0575] Furthermore, in the memory cell array 902 of layer 60, adjacent memory cells 150 share a conductive layer 240. The conductive layer 240 can be connected to the conductive layers 240 included in the stacked layer 60. Figure 21 An example is shown where the conductive layer 240 included in layer 60_1 is connected to the conductive layer 240 included in layer 60_2 via conductive layer 246a.

[0576] Figure 20B and Figure 21 The storage cell array 902 shown can, for example, be used Figure 8C The circuit of the memory cell array 621 shown.

[0577] Note that although not illustrated, in Figure 21 In addition, the memory cell array included in layer 60 can also be used. Figure 2B The structure shown replaces the storage cell array 901.

[0578] Figure 22A and Figure 22B Show Figure 20A and Figure 21 A modified example of the storage cell array 901 shown.

[0579] Figure 22A This is a plan view of the 901b memory cell array. Figure 22B It is along Figure 22A The cross-sectional view shown is the dotted-dash line B3-B4.

[0580] Figure 22A and Figure 22B The memory cell array 901b shown is Figure 20A and Figure 21 The main difference in the memory cell array 901 shown is that the transistors 500 arranged in the Y direction share conductive layers 560 and 520 but do not share conductive layer 540.

[0581] Figure 22A and Figure 22B The storage cell array 901b shown can, for example, use Figure 5B The circuit of the memory cell array 601b shown.

[0582] in addition, Figure 23A Show Figure 22A The diagram shown is a variation of the plan view. Figure 23A In the memory cell array 901c shown, the conductive layer 520 extends between two columns of transistors 500 arranged in the Y direction, and the conductive layer 520 is shared by both columns. To facilitate viewing of the conductive layers 520 and 540, in... Figure 23B omitted in Figure 23A Some of the constituent elements. For example, the storage cell array 901c can use... Figure 36 The circuit of the memory cell array 601c shown.

[0583] in addition, Figure 24 An example is shown of transistors 500 arranged in a three-dimensional direction to form a memory cell array.

[0584] exist Figure 24 In this stacked layer 60, the conductive layers 540 of the transistors 500 included in each layer are connected via connectors or the like connecting the upper and lower layers. Additionally, the conductive layers 520 of the transistors 500 included in each stacked layer 60 are connected via connectors or the like connecting the upper and lower layers. Figure 24 In layer 60_1, the conductive layer 540 of the transistor 500 is connected to the conductive layer 540 of the transistor 500 in layer 60_2 via conductive layer 245a. Additionally, the conductive layer 520 of the transistor 500 in layer 60_1 is connected to the conductive layer 520 of the transistor 500 in layer 60_2 via conductive layer 245b.

[0585] Figure 24 The storage cell array shown can, for example, use Figure 5A The circuit of the memory cell array 601 shown.

[0586] This implementation method can be appropriately combined with other implementation methods.

[0587] (Implementation Method 2)

[0588] This embodiment describes a semiconductor device according to one aspect of the present invention. The semiconductor device according to one aspect of the present invention can be used as a storage device.

[0589] Figure 25 This is a block diagram illustrating a structural example of a semiconductor device 900. Figure 25 The semiconductor device 900 shown includes a driving circuit 910 and a memory cell array 920.

[0590] As the storage cell array 920, the storage cell arrays 601, 601b, 601c, 611, and 621 shown in the above embodiments can be used.

[0591] The storage cell array 920 includes one or more storage cells 950. Storage cells 950 can be the storage cells 602, 612, 150, etc., as described in the above embodiments.

[0592] In addition, one aspect of the semiconductor device of the present invention may include multiple memory cell arrays of different types. Figure 26 An example of the structure of a semiconductor device 900 is shown. Figure 26 In the diagram, two different types of memory cell arrays 920 are shown: memory cell array 920a and memory cell array 920b. As an example, one of memory cell arrays 920a and 920b may use a memory cell array including transistors 500, while the other may use a memory cell array including memory cells 150 or as described later. Figures 27B to 27H The diagram shows an array of storage cells for OS memories such as DOSRAM, NOSRAM, and OS-SRAM.

[0593] The semiconductor device 900 includes a driving circuit 910 connected to a memory cell array 920a and a driving circuit 910 connected to a memory cell array 920b. Here, the driving circuit 910 connected to the memory cell array 920a is referred to as driving circuit 910a, and the driving circuit 910 connected to the memory cell array 920b is referred to as driving circuit 910b.

[0594] Note that sometimes the components can be shared by both drive circuit 910a and drive circuit 910b.

[0595] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and peripheral circuit 915. The peripheral circuit 915 includes peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0596] In the semiconductor device 900, circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0597] Additionally, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Alternatively, signals PON1 and PON2 can also be generated in the control circuit 912.

[0598] The control circuit 912 is a logic circuit that controls the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 to execute the aforementioned operating mode. The control circuit 912 may also have the function of error detection and correction (also known as ECC: Error Check and Correct) when reading data from the memory cell array 920.

[0599] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 928. For example, when a signal of level H is applied as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0600] The peripheral circuit 911 is used to write and read data from the storage unit 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0601] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row specified by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0602] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data Din written to memory cell 950. The data Dout read from memory cell 950 by column driver 924 is output to output circuit 926. Output circuit 926 has the function of holding data Dout. In addition, output circuit 926 has the function of outputting data Dout to the outside of semiconductor device 900. The data output from output circuit 926 is signal RDA.

[0603] PSW931 controls the supply of V to the external circuit 915. DD The PSW932 has the function of controlling the supply of V to the line driver 923. HM The function of the semiconductor device 900. Here, the high supply voltage of the semiconductor device 900 is V. DD The low power supply voltage is ground potential GND. Additionally, V HM It is more than V DD A high voltage is used as the potential applied during writing and deleting. Signal PON1 controls the on / off state of PSW931, and signal PON2 controls the on / off state of PSW932. Figure 25 In the middle, the peripheral circuit 915 is supplied with V DD The number of power domains can be 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0604] Reference Figures 27A to 27H This section describes an example of the structure of a storage cell that can be used in storage cell 950.

[0605] The following discussion of connecting two components includes cases where they are electrically connected via circuit elements (transistors, switches, diodes, resistors, etc.). An electrical connection refers to a state where current can flow between two components. Additionally, when two components are connected via a switch or transistor, current can flow even when the switch or transistor is in the ON state; therefore, this is also included within the scope of an electrical connection.

[0606] [DOSRAM]

[0607] Figure 27A The storage unit shown is equivalent to Figure 8B The storage cell 150 shown is an example of the circuit structure of a DRAM storage cell. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Storage cell 150 includes transistor M1 and capacitor CA.

[0608] Transistor M1 may also include a front gate (sometimes simply referred to as the gate) and a back gate. In this case, the back gate may also be connected to a wiring supplied with a constant potential or signal, and the front gate and the back gate may also be connected.

[0609] The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitor CA is connected to wiring CAL.

[0610] The BIL (Bite Line) is used as the bit line, and the WOL (Word Line) is used as the word line. The CAL (Chip Line) is used to apply a predetermined potential to the second terminal of the capacitor CA. During data writing and reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to the CAL.

[0611] Data writing and reading are performed by applying a high-level potential to the wiring WOL to turn on the transistor M1, thereby making the wiring BIL and the first terminal of the capacitor CA in a conductive state (a state that allows current to flow).

[0612] Furthermore, the memory cell that can be used in memory cell 950 is not limited to memory cell 150, and its circuit structure can be changed. For example, it can also be... Figure 27B The storage cell 952 is shown. Storage cell 952 is an example excluding capacitor CA and wiring CAL. The first terminal of transistor M1 is in a floating state.

[0613] In memory cell 952, the potential written by transistor M1 is maintained in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0614] An OS transistor is preferably used as transistor M1. OS transistors have the characteristic of extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. That is, transistor M1 can hold written data for a longer period, thereby reducing the refresh frequency of the memory cell. Alternatively, the refresh operation of the memory cell can be omitted. Furthermore, due to the extremely low leakage current, multi-valued data or analog data can be stored in memory cells 150 and 952.

[0615] [NOSRAM]

[0616] Figure 27CAn example circuit structure of a gain-cell type memory cell including two transistors and a capacitor is shown. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and the like, memory devices that include a gain-cell type memory cell using transistor OS as transistor M2 are sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0617] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; and transistor M2's gate is connected to wiring WOL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0618] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a predetermined potential to the second terminal of capacitor CB. During data writing, data holding, and data reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0619] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M2 and thus connects wiring WBL to the first terminal of capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL to write that potential to the first terminal of capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL, which turns off transistor M2, thereby maintaining the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3.

[0620] Data is read out by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate and the second terminal of transistor M3, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0621] For example, a structure that combines the wiring WBL and wiring RBL into a single wiring BIL can also be adopted. Figure 27DAn example of the circuit structure of the memory cell in this case is shown. In memory cell 954, the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. That is, memory cell 954 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0622] Figure 27E The storage cell 151 shown is an example where the capacitor CB and wiring CAL in storage cell 953 are omitted, which is equivalent to Figure 18B The storage unit 151 is shown. Additionally... Figure 27F The memory cell 956 shown is an example of omitting the capacitor CB and wiring CAL found in memory cell 954. This structure improves the integration density of the memory cells.

[0623] Note that it is preferable to use the OS transistor as at least as transistor M2. In particular, it is preferable to use the OS transistor as both transistor M2 and transistor M3.

[0624] Because the OS transistor has extremely low off-state current, transistor M2 can be used to hold written data for a long time, thereby reducing the refresh frequency of the memory cell. Alternatively, the refresh operation of the memory cell can be omitted. In addition, due to the extremely low leakage current, multi-valued data or analog data can be stored in memory cells 953, 954, 151, and 956.

[0625] The memory cells 953, 954, 151, and 956, which use OS transistors as transistor M2, are a type of NOSRAM.

[0626] Si transistors can also be used as transistor M3. Si transistors can improve field-effect mobility and can be p-channel transistors, thus increasing the freedom of circuit design.

[0627] In addition, when the OS transistor is used as transistor M3, the memory cell can be constructed from a unipolar circuit.

[0628] in addition, Figure 27G A gain-cell type memory cell 957 is shown, comprising three transistors and a capacitor. Memory cell 957 includes transistors M4 to M6 and capacitor CC.

[0629] Transistor M4's first terminal is connected to capacitor CC's first terminal; transistor M4's second terminal is connected to wiring BIL; and transistor M4's gate is connected to wiring WOL. Capacitor CC's second terminal is connected to transistor M5's first terminal and wiring GNDL. Transistor M5's second terminal is connected to transistor M6's first terminal; transistor M5's gate is connected to capacitor CC's first terminal. Transistor M6's second terminal is connected to wiring BIL; and transistor M6's gate is connected to wiring RWL.

[0630] The BIL (Bite Line) is used as the bit line, the WOL (Write Word Line) is used as the write word line, and the RWL (Read Word Line) is used as the read word line. The GNDL (Ground Node Line) is used to supply a low-level potential.

[0631] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M4 and connects wiring BIL to the first terminal of capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to wiring BIL to write that potential to the first terminal of capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to wiring WOL, which turns off transistor M4, thereby maintaining the potential of the first terminal of capacitor CC and the potential of the gate of transistor M5.

[0632] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high-level potential to the wiring RWL. Since the wiring RWL has a high-level potential, transistor M6 is in the on state, and the wiring BIL and the second terminal of transistor M5 are in a conducting state. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL will change correspondingly to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. That is, the information written in the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0633] Note that it is preferable to use the OS transistor as at least transistor M4.

[0634] Si transistors can also be used as transistors M5 and M6. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystallization state of the silicon used in the semiconductor layer.

[0635] In addition, when OS transistors are used as transistors M5 and M6, the memory cell can be constructed from unipolar circuits.

[0636] [OS-SRAM]

[0637] Figure 27H An example of SRAM (Static Random Access Memory) using OS transistors is shown. In this specification, SRAM using OS transistors will be referred to as OS-SRAM (Oxide Semiconductor-SRAM). Furthermore, Figure 27H The storage unit 958 shown is an SRAM storage unit capable of being backed up.

[0638] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, capacitor CD1, and capacitor CD2. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0639] Transistor M7's first terminal is connected to wiring BIL. Transistor M7's second terminal is connected to the first terminal of transistors MS1 and MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. Transistor M7's gate is connected to wiring WOL. Transistor M8's first terminal is connected to wiring BILB. Transistor M8's second terminal is connected to the first terminal of transistors MS2 and MS4, the gate of transistor MS1 and MS3, and the first terminal of transistor M9. Transistor M8's gate is connected to wiring WOL.

[0640] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0641] The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, and the gate of transistor M9 is connected to the wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, and the gate of transistor M10 is connected to the wiring BRL.

[0642] The second terminal of capacitor CD1 is connected to wiring GNDL, and the second terminal of capacitor CD2 is also connected to wiring GNDL.

[0643] The BIL and BILB wirings are used as bit lines, the WOL wiring is used as word lines, and the BRL wiring is used to control the on and off states of transistors M9 and M10.

[0644] Wiring VDL is a wiring that supplies a high-level potential, and wiring GNDL is a wiring that supplies a low-level potential.

[0645] Data is written by applying a high-level potential to the wiring WOL and the wiring BRL. Specifically, when transistor M10 is in the ON state, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the second terminal side of transistor M10.

[0646] Storage cell 958 uses transistors MS1 to MS2 to form an inverter loop, so the inverted signal of the data signal corresponding to this potential is input to the second terminal of transistor M8. Since transistor M8 is in the on state, the inverted signal of the signal input to wiring BIL, which is the potential applied to wiring BIL, is output to wiring BIL. Furthermore, since transistors M9 and M10 are in the on state, the potentials of the second terminals of transistors M7 and M8 are maintained by the first terminals of capacitors CD2 and CD1, respectively. Then, by applying a low-level potential to wiring WOL and a low-level potential to wiring BRL, transistors M7 to M10 are turned off, thereby maintaining the potentials of the first terminals of capacitors CD1 and CD2.

[0647] Data reading is performed as follows: First, the wiring BIL and wiring BILB are pre-charged to a predetermined potential. Then, a high-level potential is applied to wiring WOL and wiring BRL. This causes the potential of the first terminal of capacitor CD1 to be refreshed by the inverter loop of storage cell 958 and output to wiring BILB. Similarly, the potential of the first terminal of capacitor CD2 is refreshed by the inverter loop of storage cell 958 and output to wiring BIL. Since wiring BIL and wiring BILB change from their pre-charged potentials to the potentials of the first terminals of capacitor CD2 and capacitor CD1, respectively, the potential held by the storage cell can be read from the potentials of wiring BIL or wiring BILB.

[0648] Transistors M7 to M10 are preferably OS transistors. This allows transistors M7 to M10 to hold written data for an extended period, thus reducing the refresh frequency of the memory cell. Alternatively, the refresh operation of the memory cell can be omitted.

[0649] Alternatively, Si transistors can be used as transistors MS1 to MS4.

[0650] The driving circuitry and memory cell array 920 included in the semiconductor device 900 can also be disposed on the same plane. Additionally, as... Figure 28AAs shown, the drive circuit and the memory cell array 920 can also be stacked. Figure 28A An example is shown where the drive circuit 910a and the memory cell array 920a are arranged in an overlapping manner, and the drive circuit 910b and the memory cell array 920b are also arranged in an overlapping manner. By overlapping the drive circuits and the memory cell array 920, the signal transmission distance can be shortened.

[0651] The memory cell array 920a and memory cell array 920b can be disposed in the same layer. Specifically, the semiconductor elements such as transistors, capacitors, and diodes included in memory cell array 920a and memory cell array 920b can share some of their constituent elements. In addition, some of the constituent elements included in each can be formed by processing the same film.

[0652] Furthermore, drive circuit 910a and drive circuit 910b can be disposed in the same layer. For example, they can be disposed in a layer where... Figure 19 The transistor 300 shown is provided with driving circuit 910a and driving circuit 910 in the layer.

[0653] To facilitate understanding of the structure of semiconductor device 900, in Figure 28A The layer containing drive circuits 910a and 910b and the layer containing memory cell arrays 920a and 920b are shown separately.

[0654] In addition, such as Figure 28B As shown, multiple memory cell arrays 920 can also be stacked on the driving circuit.

[0655] [Arithmetic processing unit]

[0656] The description may include an example of a computing device that is a semiconductor device such as a storage device.

[0657] Figure 29 This is a block diagram of the arithmetic unit 960. Figure 29 The computing device 960 shown can be used, for example, as a CPU (Central Processing Unit). Alternatively, the computing device 960 can also be used with processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units), which have multiple (tens to hundreds) processor cores capable of parallel processing compared to a CPU.

[0658] Figure 29The illustrated arithmetic unit 960, on a substrate 990, includes: an ALU 991 (ALU: Arithmetic Logic Unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also include a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be located on different chips.

[0659] Cache 999 is connected to the main memory located on different chips via cache interface 989. Cache interface 989 has the function of supplying a portion of the data stored in the main memory to cache 999. In addition, cache interface 989 has the function of outputting a portion of the data held in cache 999 to ALU 991 or register 996, etc., via bus interface 998.

[0660] As described later, the memory cell array 920 can be arranged in a manner that stacks on the computing device 960. The memory cell array 920 can be used as a cache. In this case, the cache interface 989 can have the function of supplying data held in the memory cell array 920 to the cache 999. In addition, in this case, it is preferable that a portion of the cache interface 989 includes a driver circuit 910.

[0661] Note that you can also use only the storage cell array 920 as a cache instead of setting cache 999.

[0662] Figure 29 The arithmetic device 960 shown is merely an example with a simplified structure; therefore, the actual arithmetic device 960 has a wide variety of structures depending on its application. For example, it is preferable to include... Figure 29 The computing device 960 shown has a multi-core structure, which consists of a single core and multiple cores that operate simultaneously. The more cores, the better the computing performance. More cores are preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, and sixteen cores or more are even more preferred. Furthermore, when used in servers or other applications requiring very high computing performance, a multi-core structure with 16 or more cores is preferred, more preferably 32 or more cores, and more preferably 64 or more cores. Additionally, the number of bits that can be processed in the internal computing circuitry, data bus, etc., of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0663] Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993 and, after being decoded, are input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0664] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing the program of the arithmetic unit 960, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask state. The register controller 997 generates the address of register 996 and reads and writes register 996 according to the state of the arithmetic unit 960.

[0665] In addition, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0666] exist Figure 29 In the illustrated arithmetic unit 960, the register controller 997 selects the holding operation of register 996 based on instructions from ALU 991. In other words, the register controller 997 selects whether data is held in the memory cells of register 996 by flip-flops or by capacitors. When data is held by flip-flops, a power supply voltage is supplied to the memory cells of register 996. When data is held by capacitors, the data is overwritten to the capacitors, and the power supply voltage to the memory cells of register 996 can be stopped.

[0667] The storage cell array 920 and the computing device 960 can be arranged overlappingly. Figure 30A and Figure 30B This is a perspective view of semiconductor device 970A. Semiconductor device 970A includes a layer 930 on a computing device 960, on which memory cell arrays are disposed. Layer 930 is provided with memory cell arrays 920L1, 920L2, and 920L3. The computing device 960 and each memory cell array have overlapping areas. To facilitate understanding of the structure of semiconductor device 970A, in... Figure 30B The computing device 960 and the layer 930 are shown separately in the middle.

[0668] By overlapping the layer 930, which includes the memory cell array, and the computing device 960, the connection distance between them can be shortened. This improves the communication speed between them. Furthermore, the shorter connection distance reduces power consumption.

[0669] As a stacking method for the layer 930 including the memory cell array and the arithmetic device 960, the following methods can be used: directly stacking the layer 930 including the memory cell array on the arithmetic device 960 (also known as monolithic stacking); or forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates together, and electrically connecting them using through-hole or conductive film bonding techniques (such as Cu-Cu bonding). The former method does not require consideration of misalignment during bonding, thus reducing both chip size and manufacturing costs.

[0670] Here, the computing device 960 does not include cache 999, and the memory cell arrays 920L1, 920L2, and 920L3 disposed in layer 930 can all be used as caches. For example, memory cell arrays 920L1, 920L2, and 920L3 can be used as L1 cache (also called level 1 cache), L2 cache (also called level 2 cache), and L3 cache (also called level 3 cache), respectively. Among the three memory cell arrays, memory cell array 920L3 has the largest capacity and the lowest access frequency. Conversely, memory cell array 920L1 has the smallest capacity and the highest access frequency.

[0671] Note that when the cache 999 in the arithmetic unit 960 is used as an L1 cache, the memory cell arrays in layer 930 can be used as lower-level caches or main memory. Main memory is memory with a larger capacity and lower access frequency than cache.

[0672] In addition, such as Figure 30B As shown, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory cell array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory cell array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory cell array 920L3 via connection electrode 940L3.

[0673] Note that although the case shown here is a three-cell storage array used as a cache, it can also be one, two, or more than four.

[0674] When the memory cell array 920L1 is used as a cache, the drive circuit 910L1 can also be used as part of the cache interface 989, and the drive circuit 910L1 can also be connected to the cache interface 989. Similarly, the drive circuits 910L2 and 910L3 can also be used as part of the cache interface 989 or connected to a part of the cache interface 989.

[0675] Whether the memory cell array 920 is used as a cache or as main memory depends on the control circuit 912 included in each drive circuit 910. The control circuit 912 can use a portion of the multiple memory cells 950 contained in the semiconductor device 900 as RAM based on signals supplied from the arithmetic device 960.

[0676] In the semiconductor device 900, a portion of the multiple storage cells 950 can be used as a cache and the remainder as main memory. That is, the semiconductor device 900 can function as both a cache and main memory. The semiconductor device 900 according to one embodiment of the invention can, for example, be used as a general-purpose memory.

[0677] Alternatively, a layer 930 including a memory cell array 920 may be provided in a manner that overlaps with the computing device 960. Figure 31A This is a 3D view of the semiconductor device 970B.

[0678] In the semiconductor device 970B, a memory cell array 920 can be divided into multiple regions and assigned different functions for use. Figure 31A This shows an example of using region L1, region L2, and region L3 as L1 cache, L2 cache, and L3 cache, respectively.

[0679] Furthermore, in the semiconductor device 970B, the capacity of each of regions L1 to L3 can be changed according to the situation. For example, the capacity of the L1 cache can be increased by increasing the area of ​​region L1. By adopting this structure, efficient computational processing can be achieved, thereby increasing processing speed.

[0680] Alternatively, multiple storage cell arrays can be stacked. Figure 31B This is a 3D view of the semiconductor device 970C.

[0681] Semiconductor device 970C includes a layer 930L1 comprising a memory cell array 920L1, a layer 930L2 comprising a memory cell array 920L2, and a layer 930L3 comprising a memory cell array 920L3. The memory cell array 920L1, physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory cell array 920L3, furthest from the arithmetic unit 960, can be used as a lower-level cache or main memory. By employing this structure, the capacity of each memory cell array can be increased, thus further improving processing power.

[0682] This implementation method can be appropriately combined with other implementation methods.

[0683] (Implementation Method 3)

[0684] This embodiment illustrates an example of the application of a storage device according to one aspect of the present invention.

[0685] Generally speaking, various storage devices are used in semiconductor devices such as computers, depending on their purpose. Figure 32A The various memory devices used in semiconductor devices are shown in a hierarchical manner. Higher-level memory devices are required to operate at faster speeds, while lower-level memory devices are required to have larger storage capacities and higher recording densities. Figure 32A In this hierarchy, from the topmost level, the cache includes memory installed as registers in the CPU and other processing devices, L1 cache, L2 cache, L3 cache, main memory, and storage. Note that although an example including up to L3 cache is shown here, it may also include caches at lower levels.

[0686] Because the memory installed along with registers in arithmetic processing devices such as CPUs is used for temporary storage of calculation results, it is accessed frequently by the processing device. Therefore, a faster operating speed is required compared to storage capacity. Furthermore, registers also have the function of holding settings information of the processing device.

[0687] A cache is a system that copies and maintains a portion of the information held in main memory. By copying frequently used data into the cache, the speed of data access can be improved. A cache requires less storage capacity than main memory, but its operating speed is higher. Additionally, data that is overwritten in the cache is copied and fed back to main memory.

[0688] Main memory has the function of storing programs, data, etc. read from storage.

[0689] Storage serves to hold data that needs to be preserved long-term and various programs used by computing devices. Therefore, compared to faster operating speeds, storage requires larger storage capacities and higher recording densities. For example, high-capacity non-volatile storage devices such as 3D NAND can be used.

[0690] According to one aspect of the present invention, a storage device (OS memory) using oxide semiconductors offers high operating speed and long-term data retention. Specifically, as the OS memory, for example, DOSRAM, NOSRAM, OS-SRAM, etc., as described in the above embodiments can be used. Figure 32A As shown, a storage device according to one aspect of the present invention can be applied to both a cache-based hierarchy and a main memory-based hierarchy. Additionally, a storage device according to one aspect of the present invention can also be used in a storage-based hierarchy. For example, a storage device using the transistor 500 shown in the above embodiment can be used in a storage-based hierarchy.

[0691] in addition, Figure 32B Examples are shown of cases where SRAM is used for one part of the cache and OS memory of one aspect of the present invention is used for another part.

[0692] The lowest level cache can be referred to as an LLC (Last Level Cache). LLCs do not require faster operating speeds than their parent caches, but are required to have larger storage capacity. One embodiment of the OS memory of this invention has a fast operating speed and can retain data for long periods, making it suitable for use with LLCs. Note that one embodiment of the OS memory of this invention can also be used with FLCs (Final Level Cache).

[0693] For example, such as Figure 32B As shown, SRAM can be used for higher-level caches (L1 cache, L2 cache, etc.), and the OS memory of one embodiment of the present invention can be used for LLC. Additionally, as... Figure 32B As shown, DRAM can also be used in main memory in addition to OS memory.

[0694] Figure 33 The above embodiments are shown. Figure 30A and Figure 30B The illustrated semiconductor device 970A is an example of an additional memory device located at the memory level. Figure 33In the semiconductor device 970A shown, a memory cell array 920S is provided in layer 930, and a drive circuit 910S is provided in the arithmetic unit 960. The drive circuit 910S is connected to the memory cell array 920S via a connection electrode. The memory cell array 920S can be used for storage. As the memory cell array 920S, a memory cell array including transistor 500 shown in the above embodiment can be used; specifically, memory cell array 601, memory cell array 601b, memory cell array 611, etc., can be used.

[0695] This implementation method can be appropriately combined with other implementation methods.

[0696] (Implementation Method 4)

[0697] In this embodiment, an application example of a semiconductor device according to one aspect of the present invention is described.

[0698] For example, the semiconductor device of one aspect of the present invention can be used in electronic components, mainframe computers, space equipment, data centers (also known as DCs), and various electronic devices. By using the semiconductor device of one aspect of the present invention, low power consumption and high performance can be achieved in electronic components, mainframe computers, space equipment, data centers, and various electronic devices.

[0699] Furthermore, the display device incorporating the semiconductor device according to one aspect of the present invention can be used in the display section of various electronic devices. The display device incorporating the semiconductor device according to one aspect of the present invention can easily achieve high definition and high resolution.

[0700] As electronic devices, in addition to large-screen electronic devices such as television sets, desktop or laptop personal computers, monitors for computers, digital signage, and large game machines such as pinball machines, other examples include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0701] The electronic device in this embodiment may also include a sensor (which has the function of sensing, detecting, and measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0702] The electronic device of this embodiment can have various functions. For example, it can have the following functions: displaying various information (static images, dynamic images, text images, etc.) on the display unit; touch panel function; displaying calendar, date, or time, etc.; executing various software (programs); wireless communication function; reading programs or data stored in the storage medium; etc.

[0703] [Electronic Components]

[0704] Figure 34A A perspective view of a substrate (circuit board 704) on which electronic components 700 are mounted is shown. Figure 34A The electronic component 700 shown includes a semiconductor device 710 within the mold 711. Figure 34A In this description, a portion of the electronic component 700 is omitted to indicate its internal structure. The electronic component 700 includes a connecting pad 712 on the outside of the mold 711. The connecting pad 712 is electrically connected to an electrode pad 713, which is electrically connected to a semiconductor device 710 via a lead 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. By combining multiple such electronic components and electrically connecting them individually on the printed circuit board 702, a circuit board 704 is completed.

[0705] Furthermore, the semiconductor device 710 includes a driver circuit layer 715 and a memory layer 716. The memory layer 716 has a structure in which multiple memory cell arrays are stacked. The structure with the driver circuit layer 715 and the memory layer 716 stacked can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without through-hole electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When a monolithic stacked structure with a driver circuit layer 715 and a memory layer 716 is used, for example, a so-called on-chip memory structure in which memory is directly formed on the processor can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0706] Furthermore, by employing an on-chip memory structure, the size of interconnect wiring can be reduced compared to through-electrode techniques such as TSVs, thus allowing for an increase in the number of pins. Increasing the number of pins enables parallel operation, thereby improving the memory's bandwidth.

[0707] Furthermore, it is preferable to use OS transistors to form multiple memory cell arrays in memory layer 716, stacking these multiple memory cell arrays monolithically. When multiple memory cell arrays have a monolithic stacked structure, one or both of the memory bandwidth and memory access latency can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between accessing and starting data exchange. When using Si transistors in memory layer 716, it is more difficult to adopt a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0708] Alternatively, the semiconductor device 710 may be referred to as a bare die. In this specification, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into rectangular pieces during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0709] then, Figure 34B A perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is disposed on a package substrate 732 (printed circuit board), and semiconductor devices 735 and multiple semiconductor devices 710 are disposed on the interposer 731.

[0710] Electronic component 730 illustrates an example of using semiconductor device 710 as high-bandwidth memory (HBM). Additionally, semiconductor device 735 can be used in integrated circuits such as CPUs, GPUs, or FPGAs (Field Programmable Gate Arrays).

[0711] The packaging substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The through-hole plate 731 can be, for example, a silicon through-hole plate or a resin through-hole plate.

[0712] The through-hole board 731 has multiple wirings and multiple integrated circuits with different spacing between their electrical connection terminals. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 has the function of electrically connecting the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 732. Therefore, the through-hole board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". Additionally, sometimes a through electrode is provided in the through-hole board 731, through which the integrated circuit is electrically connected to the package substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0713] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0714] Furthermore, in SiP and MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally on the interposer.

[0715] On the other hand, when multiple integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSVs, space is required for the width of these terminal pitches. Therefore, when the size of the electronic component 730 is to be reduced, the width of the aforementioned terminal pitch becomes a problem, and it is sometimes difficult to set to achieve the required amount of wiring to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a memory cell array stacked monolithically can also be used.

[0716] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the integrated circuits provided on the insert 731 have the same height. For example, in the electronic component 730 shown in this embodiment, it is preferable that the semiconductor device 710 and the semiconductor device 735 have the same height.

[0717] In order to mount the electronic component 730 on other substrates, an electrode 733 may also be provided on the bottom of the package substrate 732. Figure 34BAn example of forming electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0718] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0719] [Mainframe Computer]

[0720] then, Figure 35A A 3D view of the 5600 mainframe computer is shown. Figure 35A In the mainframe computer 5600 shown, multiple rack-mounted computers 5620 are housed in rack 5610. Alternatively, the mainframe computer 5600 can also be referred to as a supercomputer.

[0721] Computer 5620, for example, can have Figure 35B The structure shown in the 3D diagram. In Figure 35B In the computer 5620, a motherboard 5630 is included, which includes multiple slots 5631 and multiple connection terminals. A personal computer card 5621 is inserted into the slots 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, whi...

Claims

1. A semiconductor device, comprising: First transistor; Second transistor; as well as First insulating layer, The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first oxide semiconductor layer, a second insulating layer, a third insulating layer, and a charge storage layer. The second transistor includes a fourth conductive layer, a fifth conductive layer, and a second oxide semiconductor layer. The first insulating layer is located on the first conductive layer and the fourth conductive layer. The first insulating layer includes a first opening overlapping the first conductive layer and a second opening overlapping the fourth conductive layer, wherein the second conductive layer and the fifth conductive layer are located on the first insulating layer. The first oxide semiconductor layer has a region within the first opening along the side surface of the first insulating layer and a region at the bottom of the first opening along the top surface of the first conductive layer. The third conductive layer has a region within the first opening. The second insulating layer, the third insulating layer, and the charge storage layer are located within the first opening, between the first oxide semiconductor layer and the third conductive layer. The second insulating layer has a region sandwiched between the first oxide semiconductor layer and the charge storage layer. The third insulating layer has a region sandwiched between the charge storage layer and the third conductive layer. Furthermore, the second oxide semiconductor layer has a region inside the second opening along the side of the first insulating layer and a region at the bottom of the second opening along the top surface of the fourth conductive layer.

2. The semiconductor device according to claim 1, The second insulating layer comprises one or more selected from silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, and aluminum oxide.

3. The semiconductor device according to claim 1 or 2, The third insulating layer comprises one or more selected from silicon oxide, silicon oxynitride, aluminum oxide, and hafnium oxide.

4. The semiconductor device according to claim 1, The second transistor includes a gate insulating layer on the second oxide semiconductor layer. The second insulating layer, as the first material, comprises one selected from silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, and aluminum oxide. And the gate insulating layer contains the first material.

5. The semiconductor device according to claim 1, The second transistor includes a gate insulating layer on the second oxide semiconductor layer. The third insulating layer, as a second material, comprises one selected from silicon oxide, silicon oxynitride, aluminum oxide, and hafnium oxide. Furthermore, the gate insulating layer comprises the second material.

6. The semiconductor device according to claim 1, The second conductive layer includes a third opening that overlaps with the first opening. Furthermore, the first oxide semiconductor layer has a region within the third opening along the sidewall of the second conductive layer.

7. The semiconductor device according to claim 1 or 6, The fifth conductive layer includes a fourth opening that overlaps with the second opening. Furthermore, the second oxide semiconductor layer has a region within the fourth opening along the sidewall of the fifth conductive layer.

8. A semiconductor device, comprising: First storage cell array; Second storage cell array; as well as First insulating layer, The first memory cell array includes a plurality of first transistors. The second storage cell array includes multiple storage cells. Each of the plurality of memory cells includes a second transistor and a capacitor. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first oxide semiconductor layer, a second insulating layer, a third insulating layer, and a charge storage layer. The first conductive layer is used as one of the source and drain electrodes of the first transistor. The second conductive layer is used as the other of the source and drain electrodes of the first transistor. The third conductive layer is used as the control gate electrode of the first transistor. The second transistor includes a fourth conductive layer, a fifth conductive layer, and a second oxide semiconductor layer. The capacitor includes the fourth conductive layer, the seventh conductive layer, and a fourth insulating layer between the fourth conductive layer and the seventh conductive layer. The fourth conductive layer is used as one of the source and drain electrodes of the first transistor and as one electrode of the capacitor. The fifth conductive layer is used as another of the source and drain electrodes of the first transistor. The fourth insulating layer is used as the dielectric of the capacitor. The first insulating layer is located on the first conductive layer and the fourth conductive layer. The first insulating layer includes a first opening that overlaps with the first conductive layer and a second opening that overlaps with the fourth conductive layer. The first oxide semiconductor layer has a region within the first opening along the side surface of the first insulating layer and a region at the bottom of the first opening along the top surface of the first conductive layer. The third conductive layer has a region within the first opening. The second insulating layer, the third insulating layer, and the charge storage layer are located within the first opening, between the first oxide semiconductor layer and the third conductive layer. The second insulating layer has a region sandwiched between the first oxide semiconductor layer and the charge storage layer. The third insulating layer has a region sandwiched between the charge storage layer and the third conductive layer. Furthermore, the second oxide semiconductor layer has a region along the side of the first insulating layer within the second opening and a region along the top surface of the fourth conductive layer at the bottom of the second opening.

9. The semiconductor device according to claim 8, The second conductive layer includes a third opening that overlaps with the first opening. Furthermore, the first oxide semiconductor layer has a region within the third opening along the sidewall of the second conductive layer.

10. The semiconductor device according to claim 1 or 9, The fifth conductive layer includes a fourth opening that overlaps with the second opening. Furthermore, the second oxide semiconductor layer has a region within the fourth opening along the sidewall of the fifth conductive layer.

11. The semiconductor device according to claim 1 or 8, The charge storage layer comprises one or more metallic elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing these metallic elements, or alloys combining these metallic elements.

12. The semiconductor device according to claim 1 or 8, The charge storage layer therein comprises a metal nitride or a metal oxide.

13. The semiconductor device according to claim 1 or 8, The charge storage layer comprises one or more selected from silicon and germanium.

14. The semiconductor device according to claim 1 or 8, The charge storage layer comprises one or more selected from silicon nitride and silicon oxynitride.

Images