Semiconductor device and electronic apparatus

Abstract

[Problem] To achieve miniaturization and pressure resistance. [Solution] This semiconductor device is provided with: a semiconductor substrate having a first diffusion region; a first transistor having a first gate disposed over the semiconductor substrate; a second transistor having a second gate disposed over the semiconductor substrate, and sharing a first diffusion region with the first transistor; and a silicide barrier film disposed over the semiconductor substrate. When viewed from a direction substantially perpendicular to the semiconductor substrate, one silicide barrier film is provided so as to overlap both at least a portion of the first gate and at least a portion of the second gate, and when viewed from the direction substantially perpendicular to the semiconductor substrate, an outer periphery of the silicide barrier film and an outer periphery of the first diffusion region are in contact with each other.

Description

Semiconductor devices and electronic equipment Technical Field

[0001] Embodiments of this disclosure relate to semiconductor devices and electronic devices. Background Technology

[0002] In semiconductor devices, there is a desire to miniaturize the circuitry.

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application No. 2011-258966 Summary of the Invention

[0006] The problem to be solved by the present invention

[0007] However, miniaturization of circuits can be difficult, for example, due to the voltage tolerance requirements of transistors.

[0008] Therefore, this disclosure provides a semiconductor device and electronic device that can achieve miniaturization and high voltage resistance.

[0009] Solution to the problem

[0010] To address the aforementioned problems, according to this disclosure, a semiconductor device is provided, comprising: a semiconductor substrate having a first diffusion region; a first transistor having a first gate disposed above the semiconductor substrate; a second transistor having a second gate disposed above the semiconductor substrate, and the second transistor sharing the first diffusion region with the first transistor; and a silicide barrier film disposed above the semiconductor substrate; wherein, when viewed from a direction substantially perpendicular to the semiconductor substrate, a silicide barrier film is configured to overlap at least a portion of the first gate and at least a portion of the second gate, and when viewed from a direction substantially perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region is in contact with the outer periphery of the silicide barrier film.

[0011] The semiconductor substrate may further include a second diffusion region containing impurities at a concentration lower than that of the first diffusion region. The lower end of the second diffusion region may be disposed below the lower end of the first diffusion region. When viewed from a direction substantially perpendicular to the semiconductor substrate, the second diffusion region may include the first diffusion region, and the second diffusion region is configured to extend to the first gate and the second gate.

[0012] At least one of the following can have one or more corners: the shortest path between the first transistor and the first diffusion region on the second diffusion region; and the shortest path between the second transistor and the first diffusion region on the second diffusion region.

[0013] At least one of the shortest path between the first transistor and the first diffusion region on the second diffusion region; and the shortest path between the second transistor and the first diffusion region on the second diffusion region may have a curved portion.

[0014] When viewed from a direction approximately perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region and the outer periphery of the silicide barrier film are in contact with each other on one side.

[0015] When viewed from a direction approximately perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region is in contact with the outer periphery of the silicide barrier film on two or more sides.

[0016] The first transistor and the second transistor can be metal-oxide-semiconductor field-effect transistors (MOSFETs) with the same polarity.

[0017] The first transistor and the second transistor can be arranged side by side along a first direction that is generally parallel to the semiconductor substrate. The width of the first transistor along a second direction that is generally parallel to the semiconductor substrate and generally perpendicular to the first direction can be greater than the width of the second transistor along the second direction. The second transistor and the first diffusion region can be arranged at different positions along the second direction.

[0018] It may also include a contact portion that is electrically connected to the first diffusion region.

[0019] According to this disclosure, an electronic device is provided, comprising: a semiconductor substrate having a first diffusion region; a first transistor having a first gate disposed above the semiconductor substrate; a second transistor having a second gate disposed above the semiconductor substrate, and the second transistor sharing the first diffusion region with the first transistor; and a silicide barrier film disposed above the semiconductor substrate; wherein, when viewed from a direction substantially perpendicular to the semiconductor substrate, a silicide barrier film is configured to overlap at least a portion of the first gate and at least a portion of the second gate, and when viewed from a direction substantially perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region is in contact with the outer periphery of the silicide barrier film. Attached Figure Description

[0020] [Figure 1] is a block diagram showing a schematic structure of the display device according to Embodiment 1.

[0021] [Figure 2] is a circuit diagram showing a construction example of a semiconductor device according to Embodiment 1.

[0022] [Figure 3] is a top view showing a construction example of a semiconductor device according to Embodiment 1.

[0023] [Figure 4] is a cross-sectional view showing a construction example of a semiconductor device according to Embodiment 1.

[0024] [Figure 5] is a top view showing a construction example of a semiconductor device according to a comparative example.

[0025] [Figure 6] is a cross-sectional view showing a construction example of a semiconductor device according to a comparative example.

[0026] [Figure 7] is a top view showing a construction example of a semiconductor device according to Embodiment 2.

[0027] [Figure 8] is a top view showing a construction example of a semiconductor device according to Embodiment 3.

[0028] [Figure 9] is a top view showing a construction example of a semiconductor device according to a variation of Example 1 of Embodiment 3.

[0029] [Figure 10] is a top view showing a construction example of a semiconductor device according to a variation 2 of Embodiment 3.

[0030] [Figure 11] is a top view showing a structural example of a semiconductor device according to Embodiment 4.

[0031] [Figure 12] is a top view showing a construction example of a semiconductor device according to Embodiment 5.

[0032] [Figure 13] is a top view showing a construction example of a semiconductor device according to Embodiment 6.

[0033] [Figure 14] is a top view showing a construction example of a semiconductor device according to Embodiment 7.

[0034] [Figure 15] is a circuit diagram showing a construction example of a semiconductor device according to Embodiment 8.

[0035] [Figure 16] is a top view showing a construction example of a semiconductor device according to Embodiment 8.

[0036] [Figure 17] is a top view showing a construction example of a semiconductor device according to Embodiment 9.

[0037] [Figure 18] is a top view showing a construction example of a semiconductor device according to Embodiment 10.

[0038] [Figure 19] is a top view showing a construction example of a semiconductor device according to Embodiment 11.

[0039] [Figure 20] is a top view showing a construction example of a semiconductor device according to Embodiment 12.

[0040] [Figure 21] is a top view showing a construction example of a semiconductor device according to Embodiment 13.

[0041] [Figure 22 is a top view showing a construction example of a semiconductor device according to Embodiment 14.]

[0042] [Figure 23] is a top view showing a construction example of a semiconductor device according to Embodiment 15.

[0043] [Figure 24] is a top view showing a construction example of a semiconductor device according to Embodiment 16.

[0044] [Figure 25] is a circuit diagram showing an example of the circuit construction of a pixel (pixel circuit) according to Circuit Example 1.

[0045] [Figure 26] is a circuit diagram showing an example of the circuit construction of a pixel (pixel circuit) according to circuit example 2.

[0046] [Figure 27] is a top view showing a construction example of a semiconductor device according to circuit example 2.

[0047] [Figure 28] is a cross-sectional view showing a construction example of the semiconductor device according to circuit example 2.

[0048] [Figure 29] is a top view showing a construction example of a semiconductor device according to circuit example 2.

[0049] [Figure 30] is a circuit diagram showing an example of the circuit construction of a pixel (pixel circuit) according to circuit example 3.

[0050] [Figure 31] is a circuit diagram showing an example of the circuit construction of a pixel (pixel circuit) according to circuit example 4.

[0051] [Figure 32] is a circuit diagram showing an example of the circuit construction of a pixel (pixel circuit) according to circuit example 5.

[0052] [Figure 33] is a circuit diagram showing an example of the circuit construction of a pixel (pixel circuit) according to circuit example 6.

[0053] [Figure 34] is a circuit diagram showing an example of the circuit construction of a pixel (pixel circuit) according to circuit example 7.

[0054] [Figure 35] is a circuit diagram showing an example of the circuit construction of a pixel (pixel circuit) according to circuit example 8.

[0055] [Figure 36] is an external view of a head-mounted display as an application example 1 of a display system (electronic device).

[0056] [Figure 37] is an external view of a head-mounted display as an application example 2 of a display system (electronic device).

[0057] [Figure 38A] is a front view of a digital camera used as an application example 3 of a display system (electronic device).

[0058] [Figure 38B] is a rear view of a digital camera.

[0059] [Figure 39] is an external view of a television device as an application example 4 of a display system (electronic device).

[0060] [Figure 40] is an appearance diagram of a smartphone as an application example 5 of a display system (electronic device).

[0061] [Figure 41A] is a view of the interior of the vehicle from the rear.

[0062] [Figure 41B] is a view of the interior of the vehicle from the left rear. Detailed Implementation

[0063] In the following description, embodiments of semiconductor devices and electronic devices will be described with reference to the accompanying drawings. Although the main components of semiconductor devices and electronic devices will be described primarily below, semiconductor devices and electronic devices may have components and functions not shown or described. The following description is not intended to exclude components and functions not shown or described.

[0064] <1. Example>

[0065] (Example 1)

[0066] Figure 1 is a block diagram illustrating a schematic structure of a display device 1 according to Embodiment 1 of the present disclosure. The display device 1 in Figure 1 can exemplify organic EL display devices, liquid crystal display devices, plasma display devices, etc. In these display devices, the organic EL display device uses organic EL elements (hereinafter, organic light-emitting devices (OLEDs)) as the light-emitting elements (electro-optical elements) of the pixels. These organic EL elements utilize the electroluminescent properties of organic materials and the phenomenon of light emission when an electric field is applied to an organic thin film. Furthermore, the display device 1 can use micro-OLEDs (M-OLEDs) as the light-emitting elements of the pixels.

[0067] The display device 1 in Figure 1 includes a pixel array unit 2, a scan line driving unit 3, a signal line driving unit 4, a video signal processing unit 5, and a timing generation unit 6.

[0068] The pixel array 2 includes pixels 8 arranged in a matrix having multiple rows and multiple columns. Each pixel 8 has multiple sub-pixels 8a. The multiple sub-pixels 8a may include, for example, three sub-pixels 8a of red, blue, and green. The multiple sub-pixels 8a may also include sub-pixels 8a of colors other than red, blue, and green (e.g., white). In this specification, sub-pixels 8a may be collectively referred to as pixels 8.

[0069] Each sub-pixel 8a in pixel 8, as described below, includes a display element and pixel circuitry. The display element is, for example, an OLED. Note that the display element can be a liquid crystal element or a self-emissive element other than an OLED.

[0070] The pixel array section 2 includes multiple scan lines WSL arranged along the row direction for each pixel group and multiple signal lines SIG arranged along the column direction for each pixel group. Pixels 8 are disposed near each intersection of the scan lines WSL and signal lines SIG. In this specification, the row direction may be referred to as the horizontal line direction, and the column direction may be referred to as the vertical line direction.

[0071] Scan line driving unit 3 sequentially drives multiple scan lines WSL. Signal line driving unit 4 synchronizes the timing of each horizontal line driven by the scan lines WSL, and simultaneously drives multiple signal lines SIG in the horizontal direction. Driving signal lines SIG means providing a grayscale signal corresponding to each signal line SIG.

[0072] The video signal processing unit 5 performs predetermined signal processing on the video signal provided from an external source (e.g., a processor) to generate a grayscale signal. The predetermined signal processing is, for example, processing such as gamma correction and overdrive correction.

[0073] The timing generation unit 6 provides timing control signals to the scan line drive unit 3 and the signal line drive unit 4 based on the synchronization signal provided from the outside, and operates the scan line drive unit 3 and the signal line drive unit 4 synchronously.

[0074] The number of pixels in the pixel array section 2 in Figure 1 is not particularly limited. In the high-definition display device 1 with a large number of pixels, the scan line driving unit 3 can be provided on both ends in the horizontal line direction. In addition, in order to drive multiple signal lines SIG in the horizontal line direction respectively, multiple signal line driving units 4 can be provided.

[0075] Next, the semiconductor device 100 included in the pixel circuit of sub-pixel 8a will be described. Note that a circuit example of the pixel circuit will be described later. Furthermore, the semiconductor device 100 is not limited to the display device 1, and can be used in other devices.

[0076] Figure 2 is a circuit diagram showing a construction example of the semiconductor device 100 according to Embodiment 1.

[0077] Semiconductor device 100 includes transistor T1 and transistor T2.

[0078] Transistor T1 and transistor T2 are connected in series. Transistor T1 and transistor T2 are MOSFETs with the same polarity.

[0079] Transistor T1 is connected between nodes N1 and N3. The gate of transistor T1 is connected to node N2.

[0080] Transistor T2 is connected between nodes N3 and N5. The gate of transistor T2 is connected to node N4.

[0081] Node N3 is located between transistors T1 and T2. At node N3, the source and drain of transistors T1 and T2 are short-circuited. Node N3 is located in a common source / drain region shared by the source and drain diffusion layers.

[0082] Figure 3 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 1. Note that Figure 3 shows a portion of the active region. Furthermore, in Figure 3, conductive layers 22, 32, 42, and 52, which will be described later with reference to Figure 4, are omitted.

[0083] Node N3 is located in the impurity diffusion region 51, which serves as a common source / drain region. The impurity diffusion region 51 is shared by transistors T1 and T2.

[0084] In the example shown in Figure 3, the impurity diffusion region 51 is configured to be offset toward the transistor T2 side. Transistors T1 and T2 are arranged side-by-side along a first direction substantially parallel to the semiconductor substrate 10 (shown as the vertical direction of the page in Figure 3). The length of transistor T1 along the first direction is greater than the length of transistor T2 along the first direction. The width of transistor T1 along a second direction (shown as the left-right direction of the page in Figure 3) is greater than the width of transistor T2 along the second direction. Transistor T2 and the impurity diffusion region 51 are located at different positions relative to each other along the second direction (shown as the left-right direction of the page in Figure 3).

[0085] Note that the details of setting up the impurity diffusion region 51 will be explained later.

[0086] Figure 4 is a cross-sectional view showing a construction example of the semiconductor device 100 according to Embodiment 1. The upper part of Figure 4 is a cross-sectional view corresponding to the section taken along line AA in Figure 3. The lower part of Figure 4 is a cross-sectional view corresponding to the section taken along line BB in Figure 3.

[0087] The semiconductor device 100 also includes a semiconductor substrate 10. The semiconductor substrate 10 is, for example, a silicon (Si) substrate. Transistors T1 and T2 are disposed on the semiconductor substrate 10.

[0088] A well region 11 is provided in the semiconductor substrate 10. The well region 11 is a region containing N-type or P-type impurities.

[0089] Electrode 20 and electrode 30 are installed above well area 11.

[0090] Electrode 20 serves as the gate of transistor T1. Electrode 20 has a conductive layer 21 and a conductive layer 22. Conductive layer 21 is the gate electrode and is disposed on the gate insulating film 61. Conductive layer 21 comprises, for example, polysilicon. Conductive layer 22 is disposed in a region of conductive layer 21 where no silicide barrier film SLB is disposed. Conductive layer 22 comprises, for example, a silicide. The silicide is, for example, a metal silicide.

[0091] Electrode 30 functions as the gate of transistor T2. Electrode 30 has a conductive layer 31 and a conductive layer 32. Conductive layer 31 is the gate electrode and is disposed on the gate insulating film 61. Conductive layer 31 contains, for example, polysilicon. Conductive layer 32 is disposed in the region of conductive layer 31 where no silicide barrier film SLB is disposed. Conductive layer 32 contains, for example, a silicide. The silicide is, for example, a metal silicide.

[0092] Additionally, electrode 30 is connected to contact portion (via) C1. Contact portion C1 is electrically connected to conductive layer 31.

[0093] Impurity diffusion regions 12 and 13 are provided in the well region 11. Impurity diffusion regions 12 and 13 are, for example, lightly doped drain (LDD) regions. Impurity diffusion regions 12 and 13 are shallow implantation regions (low-concentration ion implantation regions) used to mitigate the electric field. Impurity diffusion regions 12 and 13 contain impurity concentrations lower than those in impurity diffusion regions 41 and 51.

[0094] The lower ends of impurity diffusion regions 12 and 13 are respectively disposed below the lower ends of impurity diffusion regions 51 and 41. Impurity diffusion regions 12 and 13 include impurity diffusion regions 51 and 41 respectively, and are configured to extend to conductor layers 21 and 31 when viewed from a direction substantially perpendicular to the semiconductor substrate 10.

[0095] No electrode is provided along section A in impurity diffusion region 12. Electrode 50 is provided along section B in impurity diffusion region 12. Electrode 40 is provided in impurity diffusion region 13.

[0096] Electrode 40 includes an impurity diffusion region 41 and a conductive layer 42. The impurity diffusion region 41 is a region used as a source or drain electrode. The impurity diffusion region 41 contains an impurity concentration higher than that of the impurity diffusion region 13. That is, the impurity diffusion region 41 is a high-concentration ion implantation region. The conductive layer 42 is disposed on the impurity diffusion region 41. The conductive layer 22 contains, for example, a silicide. The silicide is, for example, a metal silicide.

[0097] In addition, electrode 40 is connected to contact portion (via) C2. Contact portion C2 is electrically connected to impurity diffusion region 41.

[0098] Electrode 50 includes an impurity diffusion region 51 and a conductive layer 52. The impurity diffusion region 51 is a region used as a source or drain electrode. The impurity diffusion region 51 contains an impurity concentration higher than that of the impurity diffusion region 12. That is, the impurity diffusion region 51 is a high-concentration ion implantation region. The conductive layer 52 is disposed on the impurity diffusion region 51. The conductive layer 22 contains, for example, a silicide. The silicide is, for example, a metal silicide.

[0099] In addition, electrode 50 is connected to contact portion (via) C3. Contact portion C3 is electrically connected to impurity diffusion region 51.

[0100] The semiconductor substrate 10 is also provided with an insulating layer 60. The insulating layer 60 serves as, for example, a component isolation region.

[0101] On the semiconductor substrate 10, a silicide barrier film SLB is disposed in the region other than the region where conductive layers 22, 32, 42 and 52 and insulating layer 60 are disposed.

[0102] The silicide barrier film SLB is an insulating film that prevents silicon from silicided in areas exposed on the well region 11 or conductor layers 21 and 31. A silicided process is performed to form conductor layers 22, 32, 42, and 52. The silicide barrier film SLB contains, for example, SiO, but is not limited to, it.

[0103] Furthermore, in the example shown in Figure 3, a (monolithic) silicide barrier film SLB is configured to overlap at least a portion of the conductor layer 21 and at least a portion of the conductor layer 31 when viewed from a direction substantially perpendicular to the semiconductor substrate 10.

[0104] The configuration of the impurity diffusion region 51 will be described in detail with reference to Figure 3.

[0105] In the example shown in Figure 3, the impurity diffusion region 51, which serves as the common source / drain region, is not located in the impurity diffusion region 12 between transistors T1 and T2. The impurity diffusion region 51 is arranged side-by-side with transistor T2, which has a width smaller than that of transistor T1. Thus, as shown in Figure 3, the semiconductor device 100 can be miniaturized in the vertical direction of the figure.

[0106] Furthermore, in the example shown in FIG3, the impurity diffusion region 12 has a protruding shape when viewed from a direction substantially perpendicular to the semiconductor substrate 10. When viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 51 is disposed within the protruding portion of the impurity diffusion region 12. This is because, as shown in FIG4, the impurity diffusion region 12 is disposed below the impurity diffusion region 51.

[0107] Furthermore, the end positions of the impurity diffusion regions 41 and 51 are approximately aligned with the end positions of the silicide barrier film SLB. This is because the impurity diffusion regions 41 and 51 are formed by ion implantation of high-concentration impurities using the silicide barrier film SLB as a mask. Therefore, in the example shown in FIG3, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the outer periphery of the impurity diffusion region 51 and the outer periphery of the silicide barrier film SLB are in contact with each other. More specifically, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the outer periphery of the impurity diffusion region 51 and the outer periphery of the silicide barrier film SLB are in contact with each other on one side.

[0108] Figure 5 is a top view showing a construction example of the semiconductor device 100a according to the comparative example. The left half of Figure 5 shows the comparative example. The right half of Figure 5 shows Embodiment 1 and corresponds to Figure 3.

[0109] In the comparative example, an impurity diffusion region 51, serving as a common source / drain region, is provided on the impurity diffusion region 12 between transistor T1 and transistor T2. That is, transistor T1, impurity diffusion region 51, and transistor T2 are arranged in this order in one direction.

[0110] Furthermore, to ensure the transistor's withstand voltage and suppress junction leakage, the shortest path P1 between transistor T1 and impurity diffusion region 51 on impurity diffusion region 12, and the shortest path P2 between impurity diffusion region 12 and transistor T2 on impurity diffusion region 12, need to have predetermined dimensions. However, in the comparative example, it becomes difficult to reduce the size of the semiconductor device 100a in the vertical direction shown in FIG5. That is, there is a trade-off between miniaturization and withstand voltage (the distance between paths P1 and P2).

[0111] On the other hand, in Embodiment 1, the impurity diffusion region 51 and the transistor T2 are disposed at different positions along the left-right direction of the paper shown in FIG. 5. The path P2 extends in the left-right direction of the paper shown in FIG. 5. As a result, the semiconductor device 100 can be reduced in the vertical direction of the paper shown in FIG. 5. Therefore, the semiconductor device 100 can be reduced in the vertical direction of the paper shown in FIG. 5 while maintaining the withstand voltage (suppressing the decrease in withstand voltage). That is, miniaturization and withstand voltage can be balanced.

[0112] Figure 6 is a cross-sectional view showing a construction example of the semiconductor device 100a according to the comparative example. The upper part of Figure 6 shows the comparative example. The upper part of Figure 6 is a cross-sectional view corresponding to the section taken along line CC in Figure 5. The lower part of Figure 6 shows Embodiment 1 and corresponds to the upper part of Figure 4. The lower part of Figure 6 is a cross-sectional view corresponding to the section taken along line AA in Figure 5.

[0113] In the comparative example, similar to FIG. 5, the impurity diffusion region 51, serving as a common source / drain region, is provided on the impurity diffusion region 12 between transistors T1 and T2. Therefore, it becomes difficult to reduce the size of the semiconductor device 100a in the left-right direction of the paper shown in FIG. 6.

[0114] On the other hand, in Embodiment 1, the impurity diffusion region 51 is not provided in the impurity diffusion region 12 between transistor T1 and transistor T2. As a result, the semiconductor device 100 can be reduced in size in the left-right direction of the paper shown in FIG6.

[0115] As described above, according to Example 1, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, a silicide barrier film SLB is configured to overlap at least a portion of the conductive layer 21 and at least a portion of the conductive layer 31. Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the outer periphery of the impurity diffusion region 51 and the outer periphery of the silicide barrier film SLB are in contact with each other. Thus, the semiconductor device 100 can be reduced in size in the vertical direction shown in FIG. 5 while maintaining voltage withstand capability (suppressing a decrease in voltage withstand capability). That is, miniaturization and voltage withstand capability can be balanced.

[0116] Furthermore, in Embodiment 1, miniaturization can be achieved while meeting the characteristics required for pixels without large-scale development (such as process development). Note that the semiconductor device 100 is not limited to the display device 1 and can be used in other devices.

[0117] Alternatively, a self-aligned polycrystalline silicide barrier film or sidewall can be provided instead of a silicide barrier film SLB.

[0118] (Example 2)

[0119] Figure 7 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 2. The difference between Embodiment 2 and Embodiment 1 lies in the shape of the impurity diffusion region 12.

[0120] In the example shown in Figure 7, the impurity diffusion region 12 and the silicide barrier film SLB on the impurity diffusion region 12 are L-shaped.

[0121] At least one of paths P1 and P2 has a polyline portion. At least one of paths P1 and P2 has one or more corners.

[0122] In the example shown in Figure 7, path P2 has a broken line portion and a corner. Path P2 has an L-shape. This allows path P2 to be longer. Consequently, the breakdown voltage of transistor T2 can be easily ensured.

[0123] As in Example 2, the shape of the impurity diffusion region 12 can also be varied. Similarly, in this case, the same effect as in Example 1 can be obtained.

[0124] (Example 3)

[0125] Figure 8 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 3. Embodiment 3 differs from Embodiment 2 in the shape of the impurity diffusion region 12.

[0126] In the impurity diffusion region 12 shown in Figure 8, a portion of the L-shape of the impurity diffusion region 12 shown in Figure 7 is etched. The impurity diffusion region 12 has a J-shape.

[0127] In the example shown in Figure 8, path P2 has a broken section and two corners. Path P2 has a J-shape. This allows path P2 to be longer. Therefore, the breakdown voltage of transistor T2 can be easily ensured.

[0128] Similar to Example 3, the shape of the impurity diffusion region 12 can also be changed. In this case, the same effect as in Example 2 can be obtained.

[0129] (Modification 1 of Example 3)

[0130] Figure 9 is a top view showing a construction example of a semiconductor device 100 according to a variation of Example 1 of Embodiment 3. The variation of Example 1 of Embodiment 3 differs from Embodiment 3 in the shape of the impurity diffusion region 12.

[0131] In the example shown in Figure 9, the shape of the removed portion of the impurity diffusion region 12 is concave-convex.

[0132] Path P2 has a broken section and six corners. A portion of path P2 has a convex-concave shape.

[0133] The shape of the impurity diffusion region 12 can also be changed in the same way as in Modified Example 1 of Example 3. Similarly, in this case, the same effect as in Example 3 can be obtained.

[0134] (Modification 2 of Example 3)

[0135] Figure 10 is a top view showing a construction example of a semiconductor device 100 according to a modified example 2 of Embodiment 3. The shape of the impurity diffusion region 12 differs from that of Embodiment 3 in Modified Example 2 of Embodiment 3.

[0136] In the example shown in Figure 10, the shape of the removed portion of the impurity diffusion region 12 is arc-shaped.

[0137] Path P2 has a polyline portion and two corners. A portion of path P2 has a curved section.

[0138] As in Modification 2 of Example 3, the shape of the impurity diffusion region 12 can also be changed. Similarly, in this case, the same effect as in Example 3 can be obtained.

[0139] (Example 4)

[0140] Figure 11 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 4. The shape of the impurity diffusion region 12 differs from that of Embodiment 1 in Embodiment 4.

[0141] In the example shown in Figure 11, the impurity diffusion region 12 does not have a protruding shape when viewed from a direction substantially perpendicular to the semiconductor substrate 10. When viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 51 is located at the corner of the impurity diffusion region 12.

[0142] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the outer periphery of the impurity diffusion region 51 and the outer periphery of the silicide barrier film SLB are in contact with each other on two or more sides. In the example shown in FIG11, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the outer periphery of the impurity diffusion region 51 and the outer periphery of the silicide barrier film SLB are in contact with each other on two sides.

[0143] Similar to Example 4, the shape of the impurity diffusion region 12 can also be varied. In this case, the same effect as in Example 1 can be obtained.

[0144] (Example 5)

[0145] Figure 12 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 5. The shape of the impurity diffusion region 12 differs from that of Embodiment 1 in Embodiment 5.

[0146] In the example shown in Figure 12, the impurity diffusion region 12 has a path with a 90° rotation shape between transistor T1 and transistor T2.

[0147] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 12 has a protruding shape. When viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 51 is disposed in the protruding portion of the impurity diffusion region 12.

[0148] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the outer periphery of the impurity diffusion region 51 and the outer periphery of the silicide barrier film SLB are in contact with each other on one side.

[0149] As in Example 5, the shape of the impurity diffusion region 12 can also be changed. Similarly, in this case, the same effect as in Example 1 can be obtained.

[0150] (Example 6)

[0151] Figure 13 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 6. The shape of the impurity diffusion region 12 differs from that of Embodiment 1 in Embodiment 6.

[0152] In the example shown in Figure 13, the impurity diffusion region 12 has a path with a 90° rotation shape between transistor T1 and transistor T2.

[0153] Furthermore, when viewed from a direction substantially orthogonal to the semiconductor substrate 10, the impurity diffusion region 12 does not have a protruding shape. When viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 51 is located at the corner of the impurity diffusion region 12.

[0154] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the outer periphery of the impurity diffusion region 51 and the outer periphery of the silicide barrier film SLB are in contact with each other on both sides.

[0155] As in Example 6, the shape of the impurity diffusion region 12 can also be changed. Similarly, in this case, the same effect as in Example 1 can be obtained.

[0156] (Example 7)

[0157] Figure 14 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 7. The shape of the impurity diffusion region 12 differs from that of Embodiment 1 in Embodiment 7.

[0158] In the example shown in Figure 14, transistors T1 and T2 are approximately the same size. Transistors T1 and T2 are arranged opposite each other. Note that transistors T1 and T2 are not necessarily the same size.

[0159] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 12 has a protruding shape. When viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 51 is disposed in the protruding portion of the impurity diffusion region 12.

[0160] When viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 51 is connected after being rotated 90° from the respective directions of transistors T1 and T2.

[0161] As in Example 7, the shape of the impurity diffusion region 12 can also be changed. Similarly, in this case, the same effect as in Example 1 can be obtained.

[0162] (Example 8)

[0163] Figure 15 is a circuit diagram showing a construction example of the semiconductor device 100 according to Embodiment 8. The shape of the impurity diffusion region 12 and the number of transistors differ in Embodiment 8 compared to Embodiment 7.

[0164] The semiconductor device 100 also includes a transistor Tr3. Transistors T1, T2, and T3 each have the same polarity.

[0165] Transistor T3 is connected between nodes N3 and N7. The gate of transistor T3 is connected to node N6.

[0166] Node N3 is shared by transistors T1, T2, and T3. Note that the number of transistors is not limited to three; it can also be four or more.

[0167] Figure 16 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 8.

[0168] In the example shown in Figure 16, transistors T1, T2, and T3 are approximately the same size.

[0169] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 12 has a protruding shape. When viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 51 is disposed in the protruding portion of the impurity diffusion region 12.

[0170] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the outer periphery of the impurity diffusion region 51 and the outer periphery of the silicide barrier film SLB are in contact with each other on one side.

[0171] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 51 is connected to transistors T1 and T3 from a direction rotated 90° relative to transistor T2.

[0172] As in Example 8, the shape of the impurity diffusion region 12 and the number of transistors can be changed. Similarly, in this case, the same effect as in Example 7 can be obtained.

[0173] (Example 9)

[0174] Figure 17 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 9. The shape of the impurity diffusion region 12 differs from that of Embodiment 8 in Embodiment 9.

[0175] In the example shown in FIG17, when viewed from a direction approximately perpendicular to the semiconductor substrate 10, the impurity diffusion region 51 is connected to transistors T1 and T3 from a direction rotated 45° relative to the plane of the paper shown in FIG17.

[0176] As in Example 9, the shape of the impurity diffusion region 12 can also be changed. Similarly, in this case, the same effect as in Example 8 can be obtained.

[0177] (Example 10)

[0178] Figure 18 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 10. Embodiment 10 differs from Embodiment 9 in the shape of the impurity diffusion region 12 and the number of transistors.

[0179] In the example shown in Figure 18, transistor T3 is not provided, and transistor T2 is provided at the location of transistor T3 in Figure 17.

[0180] Furthermore, in the example shown in Figure 18, paths P1 and P2 have polyline portions.

[0181] As in Example 10, the shape of the impurity diffusion region 12 and the number of transistors can also be changed. Similarly, in this case, the same effect as in Example 9 can be obtained.

[0182] (Example 11)

[0183] Figure 19 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 11. The shape of the impurity diffusion region 12 differs from that of Embodiment 10 in Embodiment 11.

[0184] In the example shown in Figure 19, paths P1 and P2 do not include the polyline portion.

[0185] As in Example 11, the shape of the impurity diffusion region 12 can also be changed. Similarly, in this case, the same effect as in Example 10 can be obtained.

[0186] (Example 12)

[0187] Figure 20 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 12. The shape of the impurity diffusion region 12 differs from that of Embodiment 10 in Embodiment 12.

[0188] The impurity diffusion region 12 shown in Figure 20 is narrower than that shown in Figure 18. This allows for longer paths P1 and P2, improving pressure resistance. Furthermore, to achieve the same pressure resistance as in Figure 18 with the impurity diffusion region 12 removed, the layout can be further reduced in size.

[0189] As in Example 12, the shape of the impurity diffusion region 12 can also be changed. Similarly, in this case, the same effect as in Example 10 can be obtained.

[0190] (Example 13)

[0191] Figure 21 is a top view showing a construction example of a semiconductor device 100 according to Embodiment 13. The shape of the impurity diffusion region 12 differs from that of Embodiment 13.

[0192] In the example shown in Figure 21, transistors T1 and T2 are arranged to face the same direction (the up-down direction on the paper shown in Figure 21).

[0193] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 12 has a protruding shape. When viewed from a direction substantially perpendicular to the semiconductor substrate 10, the electrode 50 (impurity diffusion region 51 and conductive layer 52) is disposed at the protruding portion of the impurity diffusion region 12.

[0194] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the outer periphery of the impurity diffusion region 51 and the outer periphery of the silicide barrier film SLB are in contact with each other on one side.

[0195] As in Example 13, the shape of the impurity diffusion region 12 can also be changed. Similarly, in this case, the same effect as in Example 1 can be obtained.

[0196] (Example 14)

[0197] Figure 22 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 14. The shape of the impurity diffusion region 12 differs from that of Embodiment 13 in Embodiment 14.

[0198] In the example shown in Figure 22, the impurity diffusion region 12 does not have a protruding shape when viewed from a direction substantially perpendicular to the semiconductor substrate 10. When viewed from a direction substantially perpendicular to the semiconductor substrate 10, the impurity diffusion region 51 is located at the corner of the impurity diffusion region 12.

[0199] Furthermore, when viewed from a direction substantially perpendicular to the semiconductor substrate 10, the outer periphery of the impurity diffusion region 51 and the outer periphery of the silicide barrier film SLB are in contact with each other on both sides.

[0200] As in Example 14, the shape of the impurity diffusion region 12 can also be changed. Similarly, in this case, the same effect as in Example 13 can be obtained.

[0201] (Example 15)

[0202] Figure 23 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 15. The difference between Embodiment 15 and Embodiment 2 (Figure 7) is that the silicide barrier film SLB is not provided on the impurity diffusion region 12.

[0203] By using a silicide barrier film SLB, breakdown voltage can be ensured by taking regions where low-resistance silicides do not form. However, if such high breakdown voltage is not required, the silicide barrier film SLB on the impurity diffusion region 12 can be omitted, thereby widening the regions of the conductor layers 21 and 31.

[0204] As in Example 15, the silicide barrier film SLB on the impurity diffusion region 12 may not be provided. Similarly, in this case, the same effect as in Example 2 can be obtained. Note that the present invention is not limited to Example 2, and the silicide barrier film SLB may not be provided in other examples.

[0205] (Example 16)

[0206] Figure 24 is a top view showing a construction example of the semiconductor device 100 according to Embodiment 16. The difference between Embodiment 15 and Embodiment 4 (Figure 11) is that the silicide barrier film SLB is not provided on the impurity diffusion region 12.

[0207] As in Example 16, the silicide barrier film SLB on the impurity diffusion region 12 may not be provided. In this case, the same effect as in Example 4 can be obtained.

[0208] <2. Circuit Example>

[0209] Next, a circuit example applied to the pixel circuit of the semiconductor device 100 described in the above embodiments and variations will be described.

[0210] (Circuit Example 1)

[0211] Figure 25 illustrates a construction example of a pixel PIX. The pixel PIX includes a capacitor C01, transistors MN02 to MN03, and a light-emitting element EL. Transistors MN02 to MN03 are N-type metal-oxide-semiconductor field-effect transistors (MOSFETs). Transistor MN02 has a gate connected to the control line WSL, a drain connected to the signal line SGL, and a source connected to the gate of transistor MN03 and the capacitor C01. One end of capacitor C01 is connected to the source of transistor MN02 and the gate of transistor MN03, and the other end is connected to the source of transistor MN03 and the anode of the light-emitting element EL. Transistor MN03 has a gate connected to the source of transistor MN02 and one end of capacitor C01, a drain connected to the power line VCCP, and a source connected to the other end of capacitor C01 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the source of transistor MN03 and the other end of capacitor C01, and the cathode is connected to the power line Vcath. The voltage of the power line VCCP is appropriately switched to a first voltage and a second voltage lower than the first voltage.

[0212] Using this configuration, in the pixel PIX, since transistor MN02 is set to the on state, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During the period when the voltage on power line VCCP is the first voltage, transistor MN03 causes current to flow to the light-emitting element EL according to the voltage across capacitor C01. The light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, the pixel PIX emits light with a brightness according to the pixel signal. Note that during the period when the voltage on power line VCCP is the second voltage, the light-emitting element EL is off.

[0213] (Circuit Example 2)

[0214] Figure 26 is a diagram showing another construction example of a pixel PIX. The pixel PIX includes capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to the control line WSL, the source is connected to the signal line SGL, and the drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to the power supply line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, the source is connected to the power supply line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12. Its source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12. The drain of MP14 is connected to the anode of the light-emitting element EL and the source of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, its source is connected to the drain of transistor MP14 and the anode of the light-emitting element EL, and its drain is connected to the power line VSS.

[0215] Using this configuration, in the pixel PIX, since transistor MP12 is set to the on state, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal from control line DSL. During the on state of transistor MP13, transistor MP14 causes a current corresponding to the voltage across capacitor C12 to flow through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, the pixel PIX emits light with a brightness according to the pixel signal. Transistor MP15 is turned on and off based on the signal from control line AZSL. During the on state of transistor MP15, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0216] Note that transistors MP12 to MP15 may be transistors using low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP12 and MP15 may be a transistor using oxide semiconductor.

[0217] In circuit example 2, for example, the semiconductor device 100 is applied to a node where a relatively high voltage is applied. The two MOSFET elements of the semiconductor device 100 are, for example, a pair of transistors MP14 and MP15. Alternatively, the semiconductor device 100 can also be applied without the silicide barrier film SLB described in Examples 15 and 16. In this case, the pair of two MOSFET elements of the semiconductor device 100 are, for example, a pair of transistors MP13 and MP14.

[0218] Figure 27 is a top view showing a construction example of the semiconductor device 100 according to circuit example 2. Figure 27 is a diagram showing the semiconductor device 100 when embodiment 1 shown in Figure 3 is applied to circuit example 2. Figure 28 is a cross-sectional view showing a construction example of the semiconductor device 100 according to circuit example 2. Figure 28 is a cross-sectional view corresponding to the section taken along line DD in Figure 27.

[0219] Transistor MP14 corresponds to transistor T1, and transistor MP15 corresponds to transistor T2. Transistor MP12 is arranged in the same layer as transistors MP14 and MP15.

[0220] The semiconductor device 100 also includes wirings L1 and L2. As shown in FIG28, wirings L1 and L2 are disposed in a layer above transistor MP14. As shown in FIG27, wiring L1 electrically connects the gate of transistor MP14 and the drain of transistor MP12. Two wirings L2 are arranged to sandwich wiring L1 and are electrically connected to the source of transistor MP14. An insulating film is disposed between wirings L1 and L2, and a metal-oxide-semiconductor (MOM) element, serving as capacitor C12, is formed between wirings L1 and L2. Note that capacitor C12 is not limited to MOM and can be an element such as metal-insulator-metal (MIM) or metal-oxide-semiconductor (MOS).

[0221] Furthermore, as shown in the circuit diagram, the holding capacitor is connected to the gate of the driving transistor that drives the light-emitting element EL based on the signal voltage held in the holding capacitor, and the write transistor for performing writing to the holding capacitor is connected to the holding capacitor. In circuit example 2, a pair of transistors T1 and T2 correspond to a pair of transistors MP14 and MP15, the write transistor corresponds to transistor MP12, the holding capacitor corresponds to capacitor C12, and the transistor connected to the holding capacitor and the write transistor corresponds to transistor MP14.

[0222] Figure 29 is a top view showing a construction example of the semiconductor device 100 according to circuit example 2. Figure 29 is a diagram showing the semiconductor device 100 when embodiment 4 shown in Figure 11 is applied to circuit example 2.

[0223] (Circuit Example 3)

[0224] Figure 30 is a diagram showing another construction example of a pixel PIX. The pixel PIX includes a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to the control line WSL, its drain is connected to the signal line SGL, and its source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN23 is connected to the control line DSL, its drain is connected to the power line VCCP, and its source is connected to the drain of transistor MN24. The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, its drain is connected to the source of transistor MN23, and its source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN25 is connected to the control line AZSL, the drain is connected to the source of transistor MN24, the other end of capacitor C21 and the anode of light-emitting element EL, and the source is connected to the power line VSS.

[0225] Using this configuration, in the pixel PIX, since transistor MN22 is set to the on state, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal from control line DSL. During the on state of transistor MN23, transistor MN24 causes a current corresponding to the voltage across capacitor C21 to flow through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, the pixel PIX emits light with a brightness according to the pixel signal. Transistor MN25 is turned on and off based on the signal from control line AZSL. During the on state of transistor MN25, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0226] Note that transistors MN22 to MN25 may be transistors using low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MN22 and MN25 may be a transistor using oxide semiconductor.

[0227] In circuit example 3, for example, the semiconductor device 100 is applied to a node where a relatively high voltage is applied. The two MOSFET element pairs of the semiconductor device 100 are, for example, a pair of transistors MN24 and MN25. Alternatively, the semiconductor device 100 can also be applied without the silicide barrier film SLB described in Examples 15 and 16. In this case, the two MOSFET element pairs of the semiconductor device 100 are, for example, a pair of transistors MN23 and MN24.

[0228] Furthermore, as shown in the circuit diagram, a configuration in which a holding capacitor is connected to the gate of a driving transistor can also be applied to circuit example 3. This driving transistor drives the light-emitting element EL based on the signal voltage held in the holding capacitor, and a write transistor for performing writing to the holding capacitor is connected to the holding capacitor. In circuit example 3, a pair of transistors T1 and T2 correspond to a pair of transistors MN24 and MN25, and the transistor connected to the holding capacitor and the write transistor corresponds to transistor MN24.

[0229] (Circuit Example 4)

[0230] Figure 31 is a diagram showing another construction example of a pixel PIX. The pixel PIX includes a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to the control line WSL, the source is connected to the signal line SGL, and the drain is connected to the gate of transistor MP33, the drain of transistor MP34, and the capacitor C31. One end of capacitor C31 is connected to the power supply line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the drain of transistor MP34. The gate of transistor MP34 is connected to the control line AZSL1, the source is connected to the drain of transistor MP33 and the source of transistor MP35, and the drain is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to the control line DSL, the source is connected to the drain of transistor MP33 and the source of transistor MP34, and the drain is connected to the source of transistor MP36 and the anode of the light-emitting element EL. The gate of transistor MP36 is connected to control line AZSL2, the source is connected to the drain of transistor MP35 and the anode of light-emitting element EL, and the drain is connected to power line VSS.

[0231] Using this configuration, in the pixel PIX, since transistor MP32 is set to the on state, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off according to the signal of control line DSL. During the period when transistor MP35 is on, transistor MP33 causes a current corresponding to the voltage across capacitor C31 to flow to the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, the pixel PIX emits light with a brightness according to the pixel signal. Transistor MP34 is turned on and off according to the signal of control line AZSL1. During the period when transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off according to the signal of control line AZSL2. During the period when transistor MP36 is on, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0232] Note that transistors MP32 through MP36 may be transistors using low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP32, MP34, and MP36 may be a transistor using oxide semiconductor.

[0233] In circuit example 4, for example, semiconductor device 100 is applied to a node where a relatively high voltage is applied. Examples of two MOSFET element pairs using semiconductor device 100 include: a pair of transistors MP33 and MP34, a pair of transistors MP33 and MP35, a pair of transistors MP34 and MP35, and a pair of transistors MP35 and MP36. Alternatively, semiconductor device 100 can also be applied in cases where the silicide barrier film SLB shown in embodiments 15 and 16 is not provided. In this case, the two MOSFET element pairs using semiconductor device 100 are, for example, a pair of transistors MP32 and MP34.

[0234] Furthermore, as shown in the circuit diagram, a configuration in circuit example 4 can also be applied where the holding capacitor is connected to the gate of the driving transistor. This driving transistor drives the light-emitting element EL based on the signal voltage held in the holding capacitor, and a write transistor for performing the writing operation is connected to the holding capacitor. In circuit example 4, a pair of transistors T1 and T2 correspond to a pair of transistors MP33 and MP35 or a pair of transistors MP33 and MP34, and the transistor connected to the holding capacitor and the write transistor corresponds to transistor MP33.

[0235] (Circuit Example 5)

[0236] Figure 32 is a diagram showing another construction example of a pixel PIX. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power line VSS. Capacitor C49 has one end connected to signal line SGL1 and the other end connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, and its gate is connected to control line WSL2, its source is connected to signal line SGL1, and its drain is connected to signal line SGL2.

[0237] The pixel PIX includes capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to control line WSL1, the source is connected to signal line SGL2, and the drain is connected to the gate of transistor MP43 and capacitor C41. One end of capacitor C41 is connected to power line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the drain of transistor MP42 and the other end of capacitor C41, the source is connected to power line VCCP, and the drain is connected to the sources of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, the source is connected to the drain of transistor MP43 and the source of transistor MP45, and the drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, the source is connected to the drain of transistor MP43 and the source of transistor MP44, and the drain is connected to the source of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, the source is connected to the drain of transistor MP45 and the anode of light-emitting element EL, and the drain is connected to power line VSS.

[0238] Using this configuration, in the pixel PIX, since transistor MP42 is set to the ON state, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 is switched on and off based on the signal from control line DSL. During the ON state of transistor MP45, transistor MP43 causes a current corresponding to the voltage across capacitor C41 to flow through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, the pixel PIX emits light with brightness according to the pixel signal. Transistor MP44 is switched on and off based on the signal from control line AZSL1. During the ON state of transistor MP44, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is switched on and off based on the signal from control line AZSL2. During the ON state of transistor MP46, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0239] Note that transistors MP42 through MP46 and MP49 may be transistors made of low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP42, MP46, and MP49 may be a transistor made of oxide semiconductor.

[0240] In circuit example 5, for example, semiconductor device 100 is applied to a node where a relatively high voltage is applied. Examples of two MOSFET element pairs using semiconductor device 100 include: a pair of transistors MP43 and MP44, a pair of transistors MP43 and MP45, a pair of transistors MP44 and MP45, and a pair of transistors MP45 and MP46. Alternatively, semiconductor device 100 can also be applied in cases where the silicide barrier film SLB shown in embodiments 15 and 16 is not provided. In this case, the two MOSFET element pairs using semiconductor device 100 are, for example, a pair of transistors MP42 and MP49.

[0241] Furthermore, as shown in the circuit diagram, a configuration in circuit example 5 can also be applied whereby a holding capacitor is connected to the gate of a driving transistor. This driving transistor drives the light-emitting element EL based on the signal voltage held in the holding capacitor, and a write transistor for performing writing to the holding capacitor is connected to the holding capacitor. In circuit example 5, a pair of transistors T1 and T2 correspond to a pair of transistors MP43 and MP45 or a pair of transistors MP43 and MP44, and the transistor connected to the holding capacitor and the write transistor corresponds to transistor MP43.

[0242] (Circuit Example 6)

[0243] Figure 33 is a diagram showing another example of the construction of a pixel PIX. Multiple pixel PIXs are arranged in a matrix in a display area 100, and the display area 100 is located between the first control unit 40 and the second control unit 70.

[0244] The first control unit 40 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and capacitor C61. Transistors MP56 and MP57 are P-type MOSFETs. Pixel signals are provided to the input of transmission gate TG45, and the output of transmission gate TG45 is connected to one end of signal line 14a. The input of transmission gate TG46 is connected to signal line 14b, and the output of transmission gate TG46 is connected to power line Vorst. One end of capacitor C61 is connected to signal line 14a, and the other end is connected to power line VSS1. The gate of transistor MP56 is connected to control line INIL, the source is connected to power line Vini, and the drain is connected to signal line 14b. The gate of transistor MP57 is connected to control line ELL, the source is connected to power line Vel, and the drain is connected to signal line 14b.

[0245] The second control unit 70 includes a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input terminal of the transmission gate TG72 is connected to the other end of signal line 14a, and its output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, its source is connected to the power supply line Vref, and its drain is connected to the output terminal of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of signal line 14b.

[0246] The pixel PIX includes capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to control line WSL, its source is connected to signal line 14b, and its drain is connected to the gate of transistor MP121 and capacitor C132. One end of capacitor C132 is connected to power line Vel, and the other end is connected to the drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the drain of transistor MP122 and the other end of capacitor C132, its source is connected to power line Vel, and its drain is connected to the sources of transistors MP123 and MP124. The gate of transistor MP123 is connected to control line AZSL, its source is connected to the drain of transistor MP121 and the source of transistor MP124, and its drain is connected to signal line 14b. The gate of transistor MP124 is connected to control line DSL, its source is connected to the drain of transistor MP121 and the source of transistor MP123, and its drain is connected to the drain of transistor MP125 and the anode of light-emitting element 130. The gate of transistor MP125 is connected to control line AZSL, its source is connected to power line Vorst, and its drain is connected to the drain of transistor MP124 and the anode of light-emitting element 130.

[0247] Using this configuration, in the pixel PIX, since transistor MP122 is set to the ON state, the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 14a, transmission gate TG72, capacitor C82, and signal line 14b. Transistor MP124 is switched on and off based on the signal of control line DSL. During the ON state of transistor MP124, transistor MP121 causes a current corresponding to the voltage across capacitor C132 to flow through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, the pixel PIX emits light with a brightness according to the pixel signal. Transistors MP123 and MP125 are switched on and off based on the signal of control line AZSL. During the ON state of transistor MP123, the drain of transistor MP121 and the source of transistor MP124 are connected to signal line 14b. During the ON state of transistor MP125, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage Vorst of the power supply line. Furthermore, transistor MP56 is turned on and off based on the signal of control line INIL, transistor MP57 is turned on and off based on the signal of control line ELL, and transistor MP73 is turned on and off based on the signal of control line REFL. When transistor MP56 is turned on, signal line 14b is set to the voltage of power line Vini, and when transistor MP57 is turned on, signal line 14b is set to the voltage of power line Vel. When transistor MP73 is turned on, one end of capacitor C82 is initialized by being set to the voltage of power line Vref.

[0248] Note that transistors MP121 to MP125, MP56, and MP57 may be transistors using low-temperature polysilicon (LTPS). Furthermore, at least one of transistors MP122 and MP125 may be a transistor using oxide semiconductor.

[0249] In circuit example 6, for example, semiconductor device 100 is applied to a node where a relatively high voltage is applied. Examples of two MOSFET element pairs using semiconductor device 100 include: a pair of transistors MP121 and MP123, a pair of transistors MP121 and MP124, a pair of transistors MP123 and MP124, and a pair of transistors MP124 and MP125.

[0250] Furthermore, as shown in the circuit diagram, a configuration in which a holding capacitor is connected to the gate of a driving transistor can also be applied to circuit example 6. This driving transistor drives the light-emitting element EL based on the signal voltage held in the holding capacitor, and a write transistor for performing writing to the holding capacitor is connected to the holding capacitor. In circuit example 6, transistors T1 and T2 correspond to a pair of transistors MP121 and MP124 or a pair of transistors MP121 and MP123, and the transistor connected to the holding capacitor and the write transistor corresponds to transistor MP121.

[0251] (Circuit Example 7)

[0252] Figure 34 is a diagram illustrating another structural example of a pixel PIX. The pixel PIX includes a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to the control line WSL, the source is connected to the signal line SGL, and the drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to the control line DSL, the source is connected to the power line VCCP, and the drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the drains of transistors MP55 and MP57 and capacitor C51, the source is connected to the drains of transistors MP52 and MP53, and the drain is connected to the sources of transistors MP58 and MP59. One end of capacitor C51 is connected to the power line VCCP, and the other end is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel with each other. The gate of transistor MP55 is connected to control line AZSL1, its source is connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and its drain is connected to the source of transistor MP56. The gate of transistor MP56 is connected to control line AZSL1, its source is connected to the drain of transistor MP55, and its drain is connected to power line VSS. The gate of transistor MP57 is connected to control line WSL, its drain is connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and its source is connected to the drain of transistor MP58. The gate of transistor MP58 is connected to control line WSL, its drain is connected to the source of transistor MP57, and its source is connected to the drain of transistor MP54 and the source of transistor MP59. The gate of transistor MP59 is connected to control line DSL, its source is connected to the drain of transistor MP54 and the source of transistor MP58, and its drain is connected to the source of transistor MP60 and the anode of light-emitting element EL. The gate of transistor MP60 is connected to the control line AZSL2, the source is connected to the drain of transistor MP59 and the anode of the light-emitting element EL, and the drain is connected to the power line VSS.

[0253] Using this configuration, in the pixel PIX, transistors MP52, MP54, MP58, and MP57 are in the ON state, thereby setting the voltage across capacitor C51 based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are switched on and off based on the signal from control line DSL. During the ON state of transistors MP53 and MP59, transistor MP54 causes current to flow through the light-emitting element EL according to the voltage across capacitor C51. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, the pixel PIX emits light with a brightness according to the pixel signal. Transistors MP55 and MP56 are switched on and off based on the signal from control line AZSL1. During the ON state of transistors MP55 and MP56, the voltage of the gate of transistor MP54 is initialized by being set to the voltage of power line VSS. Transistor MP60 is switched on and off based on the signal from control line AZSL2. During the period when transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by setting the voltage of the power supply line VSS.

[0254] Note that transistors MP52 to MP60 may be transistors using low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP55 to MP58 and MP60 may be a transistor using oxide semiconductor.

[0255] In circuit example 7, for example, semiconductor device 100 is applied to a node where a relatively high voltage is applied. Examples of two MOSFET element pairs using semiconductor device 100 include: a pair of transistors MP54 and MP58, a pair of transistors MP54 and MP59, a pair of transistors MP58 and MP59, and a pair of transistors MP59 and MP60. Alternatively, semiconductor device 100 can also be applied in cases where the silicide barrier film SLB shown in Examples 15 and 16 is not provided. Examples of two MOSFET element pairs in this case include: a pair of transistors MP52 and MP53, a pair of transistors MP53 and MP54, a pair of transistors MP52 and MP54, and a pair of transistors MP55 and MP56.

[0256] Furthermore, as shown in the circuit diagram, the holding capacitor can be connected to the gate of the light-emitting element EL driving transistor based on the signal voltage held in the holding capacitor, and the configuration of the write transistor for performing writing to the holding capacitor connected to the holding capacitor is applied to circuit example 7. In circuit example 7, transistors T1 and T2 correspond to a pair of transistors MP54 and MP59 or a pair of transistors MP54 and MP58, and the transistor connected to the holding capacitor and the write transistor corresponds to transistor MP54.

[0257] (Circuit Example 8)

[0258] Figure 35 is a diagram showing another construction example of a pixel PIX. The signals on the control line WSNL and the control line WSPL are signals that are out of phase with each other.

[0259] The pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, and MN65 through MN67, and a light-emitting element EL. Transistors MN63 and MN65 through MN67 are N-type MOSFETs, and transistor MP64 is a P-type MOSFET. The gate of transistor MN63 is connected to the control line WSNL, and its drain is connected to the signal line SGL and the source of transistor MP64, with the source connected to the drain of transistor MP64, capacitors C61 and C62, and the gate of transistor MN65. The gate of transistor MP64 is connected to the control line WSPL, and its source is connected to the signal line SGL and the drain of transistor MN63, with the drain connected to the source of transistor MN63, capacitors C61 and C62, and the gate of transistor MN65. For example, capacitor C61 is a metal-oxide-semiconductor (MOM) capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. Note that capacitor C61 can be configured using, for example, a MOS capacitor or a metal-insulator-metal (MIM) capacitor. Capacitor C62 is, for example, a MOS capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and its other end connected to power line VSS2. Note that capacitor C62 can be, for example, a MOM capacitor or a MIM capacitor. Furthermore, the other end of capacitor C62 can be connected to power line VSS3 (not shown). The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62; its drain is connected to power line VCCP; and its source is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL; its drain is connected to the source of transistor MN65 and the drain of transistor MN67; and its source is connected to power line VSS1. The gate of transistor MN67 is connected to the control line DSL, and its drain is connected to the source of transistor MN65 and the drain of transistor MN66. The source of MN67 is connected to the anode of the light-emitting element EL. Note that transistor MN67 and the control line DSL can be omitted, and the source of transistor MN65 can be connected to the drain of transistor MN66 and the anode of the light-emitting element EL.

[0260] Using this configuration, in the pixel PIX, since at least one of transistors MN63 and MP64 is set to the ON state, the voltage between capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off according to the signal of control line DSL. During the period when transistor MN67 is in the ON state, transistor MN65 causes current to flow through the light-emitting element EL according to the voltage between capacitors C61 and C62. The light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, the pixel PIX emits light with a brightness according to the pixel signal. Transistor MN66 can be turned on and off according to the signal of control line AZL. Furthermore, transistor MN66 can be used as a resistive element having a resistance value corresponding to the signal of control line AZL. In this case, transistors MN65 and MN66 constitute a so-called source follower circuit.

[0261] Note that transistors MN63, MP64, and MN65 through MN67 may be transistors using low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MN63, MP64, and MN66 may be a transistor using oxide semiconductor.

[0262] In circuit example 8, for example, semiconductor device 100 is applied to a node where a relatively high voltage is applied. Examples of two MOSFET element pairs using semiconductor device 100 include: a pair of transistors MN65 and MN66, a pair of transistors MN65 and MN67, and a pair of transistors MN66 and MN67. Alternatively, semiconductor device 100 can also be applied in cases where the silicide barrier film SLB shown in embodiments 15 and 16 is not provided. In this case, the two MOSFET element pairs to which semiconductor device 100 is applied are, for example, a pair of transistors MP63 and MP64.

[0263] Furthermore, as shown in the circuit diagram, a configuration in circuit example 8 can also be applied whereby a holding capacitor is connected to the gate of a driving transistor. This driving transistor drives the light-emitting element EL based on the signal voltage held in the holding capacitor, and a write transistor for performing writing to the holding capacitor is connected to the holding capacitor. In circuit example 8, transistors T1 and T2 correspond to a pair of transistors MP65 and MP66 or a pair of transistors MP65 and MP67, and the transistor connected to the holding capacitor and the write transistor corresponds to transistor MP65.

[0264] <3. Application Examples>

[0265] Next, application examples of the display system described in the above embodiments and variations will be explained.

[0266] (Application Example 1)

[0267] Figure 36 is an illustration showing an example of the appearance of a head-mounted display 110. The head-mounted display 110 includes, for example, ear loops 112 worn on either side of a glasses-shaped display unit 111 on the user's head. The technology described in the above embodiments, etc., can be applied to this head-mounted display 110.

[0268] (Application Example 2)

[0269] Figure 37 is an illustration showing an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a transmissive head-mounted display, comprising a main body 121, an arm 122, and a lens barrel 123. The head-mounted display 120 is mounted on glasses 128. The main body 121 includes a control panel and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light to display an image. The arm 122 connects the main body 121 and the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light provided from the main body 121 via the arm 122 onto the user's eyes through the lenses 129 of the glasses 128. The technology according to the above embodiments, etc., can be applied to this head-mounted display 120.

[0270] Note that the head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this, and can be alternatively, for example, a so-called bird-bath type head-mounted display. A bird-bath type head-mounted display includes, for example, a beam splitter and a semi-transparent reflector. The beam splitter outputs light encoded with image information toward the mirror, and the reflector reflects this light toward the user's eyes. Both the beam splitter and the semi-transparent reflector are partially transparent. Light from the surrounding environment thus reaches the user's eyes.

[0271] (Application Example 3)

[0272] Figures 38A and 38B illustrate an example of the appearance of the digital camera 130, with Figure 38A showing a front view and Figure 38B showing a rear view. The digital camera 130 is an interchangeable-lens single-lens reflex camera and includes a camera body (camera main body) 131, a camera lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The camera lens unit 132 is an interchangeable-lens unit and is located approximately near the center of the front of the camera body 131. The grip 133 is located on the left side of the front of the camera body 131, and is held by the photographer. The monitor 134 is located approximately to the left of the center of the rear of the camera body 131. The electronic viewfinder 135 is located above the monitor 14 on the rear of the camera body 131. By observing the electronic viewfinder 135, the photographer can visually identify the optical image of the object guided by the camera lens unit 132 and determine its composition. The techniques described above, such as those in the embodiments, can be applied to the electronic viewfinder 135.

[0273] (Application Example 4)

[0274] Figure 39 is an illustration showing an example of the appearance of a television device 140. The television device 140 includes a video display unit 141, which includes a front panel 142 and a filter glass 143. The technology described in the above embodiments can be applied to the video display unit 141.

[0275] (Application Example 5)

[0276] Figure 40 is an illustration showing an example of the appearance of a smartphone 150. The smartphone 150 includes a display unit 151 that displays various types of information and an operation unit 152 that includes buttons for receiving user input. The technology described in the above embodiments can be applied to the display unit 151.

[0277] (Application Example 6)

[0278] Figures 41A and 41B are diagrams illustrating examples of the construction of a vehicle to which the present disclosure is applied. Figure 41A shows an example of the interior of the vehicle as viewed from the rear of the vehicle 200, and Figure 41B shows an example of the interior of the vehicle as viewed from the left rear of the vehicle 200.

[0279] The vehicles in Figures 41A and 42B include a central display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 106.

[0280] The central display 201 is positioned on the dashboard 261, directly opposite the driver's seat 262 and the passenger seat 263. Figure 41A shows an example of the central display 201, which has a horizontally elongated shape extending from the driver's seat 262 side to the passenger seat 263 side, but the screen size and placement of the central display 201 are not limited to this. The central display 201 can display information detected by various sensors. As specific examples, the central display 201 can display images captured by an image sensor, distance images of obstacles in front of or to the side of the vehicle measured by a ToF sensor, and occupant body temperature detected by an infrared sensor, etc. The central display 201 can be used to display at least one of, for example, safety-related information, operational-related information, lifestyle logs, health-related information, authentication / identification-related information, or entertainment-related information.

[0281] Safety-related information includes detections such as drowsiness detection, gaze deviation detection, abnormal movement of children in the same passenger, seatbelt wearing detection, and occupant abandonment detection. Operational-related information includes gesture information about occupant actions detected by sensors. Gestures may include the operation of various facilities in the vehicle, such as air conditioning, navigation, audiovisual (AV) systems, lighting, etc. A occupant log includes a occupant log for all occupants. For example, the occupant log includes a record of each occupant's actions. By acquiring and storing these logs, the occupant's condition at the time of an accident can be confirmed. Health-related information includes occupant body temperature detected by temperature sensors and information on the occupant's health status estimated based on the detected body temperature. Alternatively, information on the occupant's health status may be estimated based on the occupant's face captured by an image sensor. Furthermore, information on the occupant's health status may be estimated based on the occupant's responses obtained through conversation with an automated voice system. Authentication / recognition-related information includes information such as keyless entry functions for performing facial authentication using sensors and automatic seat height and position adjustment functions in facial recognition. Entertainment-related information includes occupant operation information of the AV device detected by sensors, and information suitable for occupant content detected and identified by sensors.

[0282] For example, the console display 202 can be used to display log information. The console display 202 is located near the gear shift lever 265 in the center console 264 between the driver's seat 262 and the passenger seat 263. The console display 202 can also display information detected by various sensors. Furthermore, the console display 202 can display images of the vehicle's surroundings captured by image sensors, or it can display images of the distances to obstacles around the vehicle.

[0283] The head-up display 203 is virtually displayed behind the windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display at least one of the following: safety-related information, operational-related information, lifestyle logs, health-related information, authentication / identification-related information, or entertainment-related information. Because the head-up display 203 is typically virtually positioned in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as vehicle speed, remaining fuel, and remaining battery level.

[0284] The digital rearview mirror 204 can not only display the rear of the vehicle, but also the status of the rear seat occupants, so it can be used to display, for example, the life log information of the rear seat occupants.

[0285] The steering wheel display 205 is positioned near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of the following: safety-related information, operational-related information, daily log information, health-related information, authentication / identification-related information, or entertainment-related information. Specifically, the steering wheel display 205 is located close to the driver's hands and is therefore suitable for displaying daily log information such as the driver's body temperature, or for displaying information regarding the operation of AV devices, air conditioning systems, etc.

[0286] The rear-seat entertainment display 206 is mounted on the back side of the driver's seat 262 and the front passenger seat 263 and is for viewing by occupants in the rear seats. The rear-seat entertainment display 206 can display at least one of the following: safety-related information, operational-related information, lifestyle logs, health-related information, authentication / identification-related information, or entertainment-related information. Specifically, because the rear-seat entertainment display 206 faces the occupants in the rear seats, it displays information relevant to them. The rear-seat entertainment display 206 can display, for example, information about the operation of the AV unit or air conditioning system, or it can display the results of body temperature measurements of the occupants in the rear seats taken by the temperature sensor 5.

[0287] The technology described above can be applied to the central display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear entertainment display 206.

[0288] Note that this technology may have the following construction.

[0289] (1) A semiconductor device comprising: a semiconductor substrate having a first diffusion region; a first transistor having a first gate disposed above the semiconductor substrate; a second transistor having a second gate disposed above the semiconductor substrate, and the second transistor sharing the first diffusion region with the first transistor; and a silicide barrier film disposed above the semiconductor substrate; wherein, when viewed from a direction substantially perpendicular to the semiconductor substrate, a silicide barrier film is configured to overlap at least a portion of the first gate and at least a portion of the second gate, and when viewed from a direction substantially perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region is in contact with the outer periphery of the silicide barrier film.

[0290] (2) The semiconductor device according to (1), wherein

[0291] The semiconductor substrate also includes a second diffusion region containing a lower impurity concentration than the first diffusion region. The lower end of the second diffusion region is disposed below the lower end of the first diffusion region, and when viewed from a direction substantially perpendicular to the semiconductor substrate, the second diffusion region includes the first diffusion region. The second diffusion region is configured to extend to the first gate and the second gate.

[0292] (3) The semiconductor device according to (2), wherein at least one of the shortest path between the first transistor and the first diffusion region on the second diffusion region; and the shortest path between the second transistor and the first diffusion region on the second diffusion region has one or more corners.

[0293] (4) The semiconductor device according to (2) or (3), wherein the shortest path between the first transistor and the first diffusion region on the second diffusion region; and at least one of the shortest paths between the second transistor and the first diffusion region on the second diffusion region has a curved portion.

[0294] (5) A semiconductor device according to any one of (1) to (4), wherein, when viewed from a direction substantially perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region and the outer periphery of the silicide barrier film are in contact with each other on one side.

[0295] (6) A semiconductor device according to any one of (1) to (4), wherein, when viewed from a direction substantially perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region and the outer periphery of the silicide barrier film are in contact with each other on two or more sides.

[0296] (7) A semiconductor device according to any one of (1) to (6), wherein the first transistor and the second transistor are metal-oxide-semiconductor field-effect transistors (MOSFETs) having the same polarity.

[0297] (8) A semiconductor device according to any one of (1) to (7), wherein a first transistor and a second transistor are arranged side by side along a first direction substantially parallel to the semiconductor substrate, the width of the first transistor in a second direction substantially parallel to the semiconductor substrate and substantially perpendicular to the first direction is greater than the width of the second transistor in the second direction; and the second transistor and the first diffusion region are arranged at different locations along the second direction.

[0298] (9)

[0299] The semiconductor device according to (1) to (8) further includes a contact portion electrically connected to the first diffusion region.

[0300] (10) An electronic device comprising: a semiconductor substrate having a first diffusion region; a first transistor having a first gate disposed above the semiconductor substrate; a second transistor having a second gate disposed above the semiconductor substrate, and the second transistor sharing the first diffusion region with the first transistor; and a silicide barrier film disposed above the semiconductor substrate; wherein, when viewed from a direction substantially perpendicular to the semiconductor substrate, a silicide barrier film is configured to overlap at least a portion of the first gate and at least a portion of the second gate, and when viewed from a direction substantially perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region is in contact with the outer periphery of the silicide barrier film.

[0301] This disclosure is not limited to the individual embodiments described above, but includes various modifications that may be conceived by those skilled in the art, and the effects of this disclosure are not limited to the matters described above. In other words, various additions, modifications, and partial deletions may be made without departing from the conceptual idea and spirit of this disclosure as defined in the claims and their equivalents.

[0302] Reference Symbol List

[0303] 100 Semiconductor device; 10 Semiconductor substrate; 12 Impurity diffusion region; 20 Electrode; 21 Conductor layer; 30 Electrode; 31 Conductor layer; 50 Electrode; 51 Impurity diffusion region; C3 Contact; SLB Silicide barrier film; P1 Path; P2 Path; T1 Transistor; T2 Transistor; T3 Transistor.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a first diffusion region; A first transistor has a first gate disposed above the semiconductor substrate; The second transistor has a second gate disposed above the semiconductor substrate, and the second transistor shares the first diffusion region with the first transistor; A silicide barrier film is disposed above the semiconductor substrate. When viewed from a direction substantially perpendicular to the semiconductor substrate, the silicide barrier film is configured to overlap at least a portion of the first gate and at least a portion of the second gate, and when viewed from the direction substantially perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region is in contact with the outer periphery of the silicide barrier film.

2. The semiconductor device according to claim 1, wherein, The semiconductor substrate further includes a second diffusion region containing an impurity concentration lower than that of the first diffusion region. The lower end of the second diffusion region is disposed below the lower end of the first diffusion region, and when viewed from a direction substantially perpendicular to the semiconductor substrate, the second diffusion region includes the first diffusion region. The second diffusion region is configured to extend to the first gate and the second gate.

3. The semiconductor device according to claim 2, wherein, At least one of the following shortest paths on the second diffusion region between the first transistor and the first diffusion region: the shortest path on the second diffusion region between the second transistor and the first diffusion region has one or more corners.

4. The semiconductor device according to claim 2, wherein, At least one of the shortest path between the first transistor and the first diffusion region on the second diffusion region, and the shortest path between the second transistor and the first diffusion region on the second diffusion region, has a curved portion.

5. The semiconductor device according to claim 1, wherein, When viewed from a direction substantially perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region and the outer periphery of the silicide barrier film are in contact with each other on one side.

6. The semiconductor device according to claim 1, wherein, When viewed from a direction substantially perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region and the outer periphery of the silicide barrier film are in contact with each other on two or more sides.

7. The semiconductor device according to claim 1, wherein, The first transistor and the second transistor are metal-oxide-semiconductor field-effect transistors (MOSFETs) with the same polarity.

8. The semiconductor device according to claim 1, wherein, The first transistor and the second transistor are arranged side by side along a first direction that is substantially parallel to the semiconductor substrate. The width of the first transistor along a second direction that is substantially parallel to the semiconductor substrate and substantially perpendicular to the first direction is greater than the width of the second transistor along the second direction. The second transistor and the first diffusion region are arranged at different positions along the second direction.

9. The semiconductor device according to claim 1, further comprising a contact portion electrically connected to the first diffusion region.

10. An electronic device, comprising: A semiconductor substrate having a first diffusion region; A first transistor has a first gate disposed above the semiconductor substrate; The second transistor has a second gate disposed above the semiconductor substrate, and the second transistor shares the first diffusion region with the first transistor; A silicide barrier film is disposed above the semiconductor substrate. When viewed from a direction substantially perpendicular to the semiconductor substrate, the silicide barrier film is configured to overlap at least a portion of the first gate and at least a portion of the second gate, and when viewed from the direction substantially perpendicular to the semiconductor substrate, the outer periphery of the first diffusion region is in contact with the outer periphery of the silicide barrier film.

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