Semiconductor tube core and manufacturing method thereof

Abstract

The present disclosure relates to a semiconductor die comprising: a transistor device in an active region of the die; an electrostatic discharge (ESD) protection structure electrically connected between the load contact and the gate contact; wherein the edge termination structure comprises a field dielectric made of a field dielectric material having a first thickness t1 in a first portion of the edge termination structure and a second thickness t2 in a second portion of the edge termination structure, where the second portion is laterally arranged between the first portion and the active region and t2lt; t1, wherein the ESD protection structure at least partially overlaps the second portion.

Description

Technical Field

[0001] This application relates to a semiconductor die. Background Technology

[0002] A semiconductor die may include a semiconductor body and a semiconductor device in the active region of the semiconductor body. Summary of the Invention

[0003] Examples of this application relate to advantageous semiconductor dies.

[0004] In embodiments, this application relates to a semiconductor die according to claim 1. It may include an electrostatic discharge (ESD) protection structure electrically connected between a load contact and a gate contact of a device (e.g., a transistor device). The ESD protection structure may be disposed within or overlap with an edge-terminating structure laterally disposed between an active region and a lateral edge of the die. The edge-terminating structure may include a field dielectric material made of a field dielectric material. The field dielectric material may have a first thickness in a first portion of the edge-terminating structure and a second thickness in a second portion of the edge-terminating structure, wherein the second thickness is less than the first thickness, and the second portion is laterally disposed between the first portion and the active region. In other words, the first portion is disposed further outward than the second portion, and the dielectric material in the first portion is thicker.

[0005] The ESD protection structure can be arranged to have at least partial overlap in the second portion. As seen in a vertical cross-section, with the cross-sectional plane perpendicular to the lateral edge of the semiconductor die or body, at least the outer portion of the ESD protection structure can be arranged above the field dielectric or field dielectric material, having a first thickness thereon. Optionally, the inner portion of the ESD protection structure can overlap with the field dielectric or field dielectric material, having a second thickness thereon. Arranging the ESD protection structure to at least partially overlap with the second portion can, for example, allow for an area-saving layout.

[0006] Specific and / or alternative embodiments are provided in the remaining claims and the following description. While each feature should be disclosed independently of a particular claim class, this disclosure relates to apparatus and device aspects, but also to methods and uses. If, for example, a die manufactured in a particular manner is described, this also discloses the corresponding manufacturing process, and vice versa. Any embodiment may, for example, relate to a die, or to a method or use.

[0007] Edge-terminating structures can be arranged between the lateral edges of a die or semiconductor body and the active region of the die. In the active region, device structures, such as transistor device structures, can be formed within the semiconductor body. Typically, when discussing elements with respect to their relative positions, such as when viewed in a vertical cross-section, these elements are arranged, for example, on the same side of the active region, i.e., at the same lateral edge of the semiconductor die or body ("outward" means, for example, closer to / towards the corresponding lateral edge, and "inward" means closer to / towards the active region).

[0008] "Vertical" or "perpendicularly" can refer to a vertical direction, for example, perpendicular to the surface of the die (e.g., the surface of the semiconductor body). The first and second sides of the semiconductor body can be placed perpendicularly opposite each other. "Above" can indicate a direction that is vertically aligned and closer to the first side of the semiconductor body or the front side of the die, while "below" can indicate a direction that is vertically aligned and closer to the second side of the semiconductor body or the back side of the die. "Lateral" or "laterally" can refer to a lateral direction perpendicular to the vertical direction, where, for example, the area of ​​the semiconductor body or die can be obtained.

[0009] The semiconductor host may include a semiconductor substrate, such as one or more epitaxial layers bonded thereon. The semiconductor host may be, for example, a silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) semiconductor host.

[0010] A device structure or semiconductor device disposed in an active region may include a first load terminal disposed on a first side of a semiconductor body. Furthermore, it may include a second load terminal disposed on a vertically opposite second side of the semiconductor body. The device or device structure may be, for example, a FET having a source terminal / region and a drain terminal / region in the semiconductor body, such as a source region on the first side of the semiconductor body and a drain region on the second side of the semiconductor body.

[0011] In addition to the source and drain regions, the device may also include a body region to which the gate electrode is capacitively coupled. As an example, the device may be a superjunction transistor device. Within the semiconductor body, a first region made of a first doping type and a second region made of a second doping type may be formed. The first region may be a drift region, and the second region may be a compensation region. For example, the first doping type may be n-type, and the second doping type may be p-type.

[0012] As discussed in further detail below, the ESD protection structure may include successively alternating first and second doped type regions. At each end of the diode chain, a corresponding contact region, for example, made of a second doped type, may be arranged. When it is mentioned that the ESD protection structure “at least partially overlaps with the second portion,” this can be understood as at least the contact region and / or the doped type region being arranged over the field dielectric or field dielectric material having a first thickness thereon. The ESD protection structure, such as the first and second regions, may be formed in a material layer arranged over the field dielectric material, such as in a polysilicon layer.

[0013] In an embodiment, the field dielectric of the edge-terminating structure is arranged to be recessed into a shallow trench in the semiconductor body. The first side of the field dielectric material facing away from the semiconductor body can be planar. The perpendicularly opposite second side of the field dielectric facing the semiconductor body can have a specific morphology. The planar first side can be obtained, for example, in a planarization step by chemical mechanical polishing (CMP). Independent of these details, the planar first side may be advantageous, for example, in the fabrication of the ESD protection structure. In other words, although the ESD protection structure is arranged to have overlap at least in the first portion, where the thickness is greater, it can be formed without steps.

[0014] In this embodiment, the shallow trench has sidewalls that slope towards the active region. As seen in a vertical section perpendicular to the lateral edges, the sloped sidewalls may be arranged laterally between the bottom of the shallow trench and the active region. ESD protection structures, such as their contact areas and / or doped regions, overlap the sloped sidewalls. For example, the ESD protection structures may overlap the entire sloped sidewalls, with the ESD protection structures arranged above (overlapping) the sloped sidewalls.

[0015] As seen in the vertical cross-section, at least some of the doped regions of the ESD protection structure can be arranged above the sloping sidewalls. For example, the inner contact regions of the ESD protection structure can be arranged laterally inside the sloping sidewalls, and / or the outer contact regions of the ESD protection structure can be arranged laterally outside the sloping sidewalls. Alternatively, one or two contact regions can be arranged above the sloping sidewalls.

[0016] Typically, shallow trenches with a field dielectric can form shallow trench isolation, for example, to shield devices disposed in the active region from potentials at the lateral edges of the die (e.g., those that can be reached upwards from the back side). In other words, by arranging the ESD protection structure to at least overlap with the shallow trench / field dielectric, the area used for the isolation structure can be additionally (at least partially) used for the ESD protection structure.

[0017] In one embodiment, a well region made of a second doping type is disposed at the bottom of a shallow trench. The well region may, for example, include a non-exhaustible doped region and a exhaustible doped region, with the non-exhaustible doped region disposed, for example, laterally within the exhaustible doped region.

[0018] In an embodiment, the semiconductor die includes a gate interconnect structure that electrically connects the gate terminals of a device disposed in an active region to gate contacts. Additionally, the die may include an ESD protection structure electrically connected between a load contact and a gate contact of the device, as described above for possible details. The gate interconnect structure may extend along a first length along a first side of the active region, and the ESD protection structure may extend along a second length along the first side of the active region, wherein the gate interconnect structure is completely interrupted along the second length. In other words, the gate interconnect structure may be interrupted to allow the ESD protection structure to be arranged laterally alongside it, which may, for example, allow for a space-saving layout.

[0019] The first side of the active region can extend along the first lateral edge of the die. As seen in the first vertical section, the cross-sectional plane extends through the first length and is perpendicular to the first lateral edge of the semiconductor die, and the gate interconnect structure can extend laterally inward from the gate contact. In the second vertical section, the cross-sectional plane extends through the second length and is perpendicular to the first lateral edge of the die, and the ESD protection structure can extend laterally inward from the gate contact.

[0020] The gate contact may be, for example, a gate ring extending along the active region and / or gate pad. In other words, the gate contact may be provided for forming an electrical connection to a gate connection or pin in the package, for example, via a bonding wire or clamp. Independent of these details, the gate contact may be formed in a metallization disposed above a first side of the semiconductor body, for example, deposited on an insulating layer (interlayer dielectric).

[0021] In this embodiment, the gate interconnect structure and the ESD protection structure are formed in the same material layer, such as a polysilicon layer. Along a first length, a corresponding portion of the polysilicon layer can form a low-ohmic connection between the gate contact and the gate terminal of the device. Along a second length, the ESD protection structure can be formed in a corresponding portion of the polysilicon layer (e.g., by alternating between a first doped region and a second doped region).

[0022] In this embodiment, a second ESD protection structure is disposed on the second side of the active region (which may extend along the second side of the die towards the edge). Specifically, the second ESD protection structure may extend along the entire second side of the active region.

[0023] Alternatively or additionally, another gate interconnect structure may be disposed on the third side of the active region (which may extend along the third side of the semiconductor die towards the edge), wherein the other gate interconnect structure may extend along the entire third side of the active region. Alternatively or additionally, a third ESD protection structure may be disposed on the fourth side of the active region (which may extend along the fourth side of the die towards the edge), wherein the third ESD protection structure may extend along the entire fourth side of the active region.

[0024] In this embodiment, in addition to the gate interconnect structure and the ESD protection structure, the semiconductor die also includes an edge-terminating structure laterally located between the active region and the lateral edge of the die. Further details regarding the possible details of the edge-terminating structure are also referred to the above description. Referring to a field dielectric material having a first thickness in a first portion and a second thickness in a second portion of the edge-terminating structure, wherein the second portion is laterally disposed within the first portion and the second thickness is less than the first thickness, the ESD protection structure may overlap the first and second portions along a second length. In other words, as observed in the second vertical cross-section (see above), the ESD protection structure may be partially disposed in the first portion and partially disposed in the second portion, for example, above the sloping sidewalls, as described above.

[0025] Along the first length, the gate interconnect structure may overlap with the first and second portions. In other words, as observed in the first vertical cross-section (see above), the gate interconnect structure may be partially disposed in the first portion and partially disposed in the second portion, for example, above the sloping sidewalls of the shallow trench.

[0026] In an embodiment, the semiconductor die includes an ESD protection structure. The ESD protection structure may include a first region made of a first doping type and a second region made of a second doping type, the first and second regions being arranged alternately in succession. In an embodiment, the doping concentration of the second region is higher than that of the first region. As an example, the first type may be n-type, and the second type may be p-type; for example, a higher p-doping concentration is applied to the second region compared to the n-doping concentration of the first region.

[0027] In an embodiment, in addition to the first and second regions, the ESD protection structure also includes contact regions made of a second doping type. The first and second regions may be arranged alternately and continuously between the contact regions. In an embodiment, the doping concentration in the contact regions is higher than the doping concentration in the first and / or second regions. The doping concentration in the first region may be lower than the doping concentration in the second region, wherein the doping concentration in the contact regions may be equal to or even higher than the doping concentration in the second region.

[0028] The diode chain formed by the first and second regions can be electrically connected to the gate contact via one contact region and / or to the load contact via the other contact region, for example. Specifically, the respective contacts can be formed by respective contact plugs that may intersect perpendicularly with the insulating layer (ILD) covering the ESD protection structure.

[0029] In this embodiment, the first region and the second region are arranged alternately and continuously in the length direction. The length direction can be a lateral direction, such as a lateral direction perpendicular to the lateral edge of the semiconductor die. Independent of these details, the corresponding contact areas can have a greater extension in the length direction than the corresponding first region and / or second region.

[0030] In one embodiment, the first regions have substantially the same length relative to each other. Alternatively or additionally, the second regions may have substantially the same length relative to each other. The doping concentration of the second region may be higher than that of the first region.

[0031] As described above, the ESD protection structure can be formed in a polysilicon layer. Specifically, the first region and the second region can be formed in the polysilicon layer, for example, via corresponding first and second doping type implantation. Optionally, contact regions can also be formed in the polysilicon layer.

[0032] In this embodiment, the polysilicon layer has a thickness of no more than 400 nm, with a further upper limit, for example, no more than 300 nm, 200 nm, or 100 nm. As an example, the lower limit could be at least 50 nm or 80 nm.

[0033] In this embodiment, the ESD protection structure has a diode spacing of no more than 2.3 μm, with further upper limits such as no more than 2 μm, 1.7 μm, 1.4 μm, 1.2 μm, 1 μm, or 0.8 μm. As an example, the lower limit could be at least 0.6 μm or 0.7 μm.

[0034] As described above, the ESD protection structure can be disposed on the field dielectric, for example, having an additional layer between it and the field dielectric or directly on the field dielectric. In embodiments, the ESD protection structure is embedded in an interlayer dielectric, which can be an insulating layer made of one or more sublayers. Independent of these details, metallization can be disposed on the interlayer dielectric, for example, load contacts and / or gate contacts are formed in the metallization.

[0035] The ESD protection structure embedded in the interlayer dielectric can be covered both upwards and laterally by the interlayer dielectric. In other words, as observed in a vertical section perpendicular to the lateral edge of the die, the interlayer dielectric can not only cover the upper side of the ESD protection structure, such as the corresponding portion of the polysilicon layer, but also the lateral inner end of the corresponding portion of the polysilicon layer, and / or the lateral outer end of the corresponding portion of the polysilicon layer.

[0036] In this embodiment, the superjunction transistor device is arranged in the active region. It may include multiple superjunction transistor units, for example, each having a drift region portion and a compensation region portion.

[0037] In an embodiment, a method of manufacturing a semiconductor die may include forming a transistor device in an active region and forming an ESD protection structure, such as an electrical connection between a load contact (e.g., a source pad) and a gate contact of the device.

[0038] In this embodiment, forming an ESD protection structure may include:

[0039] Provide a polycrystalline silicon layer doped with a first type of doping;

[0040] Provide a structured mask on a doped polycrystalline silicon layer;

[0041] The second doping type is injected through the opening defined by the mask.

[0042] The opening may define a second region and / or a contact region. In an embodiment, the corresponding opening defining the corresponding contact region is larger than the corresponding opening defining the corresponding second region. Alternatively or additionally, the corresponding opening defining the corresponding second region may be smaller than the corresponding covering segment therebetween. The corresponding covering segment may cover the first doped region, for example, arranged laterally between two adjacent openings defining the second region.

[0043] In an embodiment, the corresponding opening in the corresponding second region is defined to be less than half the diode spacing, see the description of possible values ​​above.

[0044] In an embodiment, the corresponding opening defining the corresponding second region has an extension of no more than 600 nm in the length direction, with possible upper limits such as no more than 500 nm, 400 nm, 300 nm, or 200 nm. For example, a possible lower limit could be at least 100 nm or 150 nm. Attached Figure Description

[0045] The die and further details are explained below through exemplary embodiments. The various features can also be combined in different ways and are relevant to different applications.

[0046] Figure 1A vertical cross-section of a semiconductor die with an edge-termination structure is shown.

[0047] Figure 2 It shows Figure 1 Enlarged image;

[0048] Figures 3a-3c The ESD protection structure and some manufacturing details are shown.

[0049] Figure 4 A portion of the semiconductor die is shown in a vertical top view;

[0050] Figure 5 A vertical top view of a semiconductor die is shown;

[0051] Figure 6 A vertical cross-section of the active region of a semiconductor die is shown. Detailed Implementation

[0052] Figure 1 A vertical cross-section of the semiconductor die 1 is shown, specifically the vertical cross-section of the edge termination structure 10 arranged laterally between the active region 100 and the lateral edge 1.1 of the die 1. A transistor device 110 can be formed in the active region 100, as shown in the reference below. Figure 6 Detailed description. The load contact 20 can be electrically connected to the load terminal of the transistor device, such as the source region. The load contact 20 can, in particular, be a source plate connected to the source terminal or source region. Furthermore, a gate contact 30 is shown, which can be different from... Figure 1 The other section of the plane shown is connected to the gate terminal of the transistor device, see details below.

[0053] exist Figure 1 The cross-sectional view shows an electrostatic discharge (ESD) protection structure 40 connected between the load contact 20 and the gate contact 30. The ESD protection structure 40 can protect devices (e.g., the gate dielectric of a device) from electrostatic discharge events that may occur during assembly or operation.

[0054] The edge termination structure 10 may include a field dielectric 11 made of a field dielectric material 12. The field dielectric 11 can isolate the active region 100 from the edge potential at the first side 2.1 (front side) of the semiconductor body 2, for example, from the back side or drain potential extending upwards to the front side at the lateral edge 1.1. In particular, the field dielectric 11 may be recessed in a shallow trench 13, i.e., forming a shallow trench isolation.

[0055] The field dielectric material 12 has a first thickness t1 in the first portion 10.1 of the edge termination structure 10 and a second thickness t2 in the second portion 10.2 of the edge termination structure 10. For example... Figure 1As shown, the second thickness t2 is less than the first thickness t1, and the second portion 10.2 is laterally arranged inside the first portion 10.1. The ESD protection structure 40 may at least partially overlap with the second portion 10.2. Using the area above the second portion 10.2 may, for example, allow for the integration of the ESD protection structure 40 in an area-saving manner, such as for a relatively narrow high-voltage edge termination structure.

[0056] Referring to shallow trench 13, the first thickness t1 can specifically be taken from the bottom 13b of shallow trench 13. In a sense, the ESD protection structure 40 is placed in the transition between the active region 100 and the shallow trench isolation, which can specifically overlap in the inclined sidewalls 13a of shallow trench 13, see below. Load contacts, gate contacts, and field dielectrics can be arranged on a first side of the semiconductor body, and the ESD protection structure can be integrated into the stack on the first side, for example, as a polysilicon diode chain.

[0057] In the illustrated embodiment, the first side or upper side 12.1 of the field dielectric material 12, facing upwards (e.g., away from the semiconductor body 2), is planarized. In other words, the first side or upper side 12.1 can be in a horizontal plane. Planarization can, for example, allow for particularly narrow lithography, such as enabling diodes to have relatively small spacing. As detailed below, in the case of higher doping (e.g., higher n-doping), the mask openings can be only about 0.5 μm or less, and the spacing between two mask openings can be about 1.8 μm or even less.

[0058] As observed in a vertical section perpendicular to the lateral edge 1.1 of the die 1, the thickness of the dielectric material 12 above the inclined sidewall 13a decreases toward the active region 100. The ESD protection structure may only partially overlap the inclined sidewall 13a, with the inner or outer lateral end of the ESD protection structure 40 positioned above it. However, specifically, the ESD protection structure 40 may overlap the entire inclined sidewall 13a. The inner lateral end of the ESD protection structure 40 may be positioned above the field dielectric portion with a constant thickness, and the outer lateral end of the ESD protection structure may be positioned above the bottom 13b of the shallow trench 13.

[0059] In addition to the field dielectric 11, the edge termination structure 10 may include a well region 15 at the bottom of the shallow trench 13 and extending toward the active region 100. The well region 15 may be made of a second doping type, particularly p-type. It may, for example, include a non-depletable doped region and a depletable doped region, the latter being arranged laterally outside the non-depletable doped region (not mentioned in more detail). The first and second regions are shown below the well region 15; see [link to relevant documentation] for more details. Figure 6 .

[0060] Figure 2 It shows Figure 1 An enlarged view is shown. The ESD protection structure 40 is formed in the common material layer 50, particularly in the polysilicon layer 51. In the illustrated embodiment, the common material layer 50 is deposited on the field dielectric 11, and the ESD protection structure 40 is embedded in the interlayer dielectric 70 disposed on the field dielectric 11. The thickness of the interlayer dielectric 70 may exceed the thickness of the ESD protection structure 40, which is laterally embedded in and covered upwards by the interlayer dielectric 70. A gate interconnect structure 90 may also be formed in the common material layer 50, see [link to relevant documentation]. Figure 4 Compare them.

[0061] Figures 3a-3c Further details of the ESD protection structure 40 and some manufacturing processes are shown. Figure 3a A schematic cross-sectional view of a structured mask 80 on a polysilicon layer 51 is shown. Prior to the deposition and structuring of the mask 80, the polysilicon layer 51 may be doped with a first doping type, and subsequently a second doping type may be introduced through openings 82, 83 in the mask 80. Typically, in this disclosure, the first doping type may be particularly n-type and the second doping type may be particularly p-type.

[0062] The ESD protection structure 40 may include a first region 41 made of a first doping type and a second region 42 made of a second doping type, the first region 41 and the second region 42 being arranged alternately in succession. Referring to the length direction 45, the first region 41 may have substantially the same extension relative to each other, and / or the second region 42 may have substantially the same extension relative to each other. Compared to the corresponding first region 41, the corresponding second region 42 may have a larger extension in the length direction 45 (see...). Figure 3b The corresponding contact area 43 may have a larger extension than the corresponding first area 41 and / or second area 42.

[0063] Reconsidering the structured mask 80, the corresponding opening 83 defining the corresponding contact region 43 for contacting the diode chain can be larger than the corresponding opening 82 defining the corresponding second region 42. The corresponding opening 82 defining the corresponding second region 42 can be smaller than the corresponding covering segment 81 therebetween. The corresponding opening 82 can be particularly smaller than half the diode spacing.

[0064] For illustration, in absolute terms, the corresponding opening 82 may, for example, have an extension of no more than 600 nm, 500 nm, 400 nm, 300 nm, or 200 nm as measured along the length direction 45, with a possible lower limit of, for example, 100 nm or 150 nm. Along the length direction 45, the first and second regions may be arranged alternately, or, in the case of a structured mask 80, the covering segment 81 and the opening 82 may be arranged continuously and alternately.

[0065] Figure 3b The thickness tps of the polysilicon layer 51 is shown, which can be, for example, no greater than 400 nm, 300 nm, 200 nm, or 100 nm, with a possible lower limit of, for example, 50 nm or 80 nm. In the readily available ESD protection structure 40, the first and second regions 41, 42 can be arranged with a diode pitch of no greater than 2.3 μm, 2 μm, 1.7 μm, 1.4 μm, 1.2 μm, 1 μm, or 0.8 μm. A possible lower limit can be, for example, 0.6 μm or 0.7 μm.

[0066] Figure 3c The doping distribution or concentration along the contact region and the first / second regions 41, 42, 43 is shown. The doping concentration 62 of the second region 42 may be higher than the doping concentration 61 of the first region 41. The doping concentration 63 of the contact region 43 may be higher than the doping concentration 61 of the first region 41 and / or the doping concentration 62 of the second region 42.

[0067] Figure 4 A portion of die 1 is shown in a top-down vertical view. An ESD protection structure 40 is laterally arranged between the active region 100 and the lateral edge 1.1 of die 1. As described above, it can be connected between the load contact (left side) and the gate contact (right side), wherein these contacts are not in… Figure 4 As shown in the figure. In addition to the ESD protection structure 40, a gate interconnect structure 90 is also shown, which can be formed in the same common material layer, particularly in the polysilicon layer, see above.

[0068] Referring to a first side 101 of the active region 100 oriented toward a lateral edge 1.1, a gate interconnect structure 90 may extend along a first length 101.1 of the first side 101. Along a second length 101.2 of the first side 101, the gate interconnect structure 90 may be completely interrupted, and an ESD protection structure 40 may be arranged along the second length 101.2. Along the first length 101.1, the gate interconnect structure 90 may overlap with the first portion 10.1 and the second portion 10.2 (see...). Figure 1 In particular, it can overlap with the entire inclined sidewall 13a. Along the second length 101.2, the ESD protection structure 40 can overlap with the first part 10.1 and the second part 10.2 (see...). Figure 1 In particular, it can overlap with the entire inclined sidewall 13a.

[0069] Figure 5 A schematic vertical top view of the complete die is shown, for example, showing the four lateral edges 1.1-1.4 of die 1. (See reference...) Figure 4The ESD protection structure 40 and the gate interconnect structure 90 are both disposed on the first side 101. A second ESD protection structure 140 may be provided on the second side 102 of the active region 100, extending, for example, along the entire second side 102. Alternatively or additionally, another gate interconnect structure 190 may be disposed on the third side 103 of the active region 100, extending, for example, along the entire third side 103 of the active region 100. Alternatively or additionally, a third ESD protection structure 240 may be disposed on the fourth side 104 of the active region 100, extending, for example, along the entire fourth side 104 of the active region 100.

[0070] Figure 6 A schematic cross-section of the active region 100 is shown, and a semiconductor device 110, which may be, in particular, a superjunction transistor device, is illustrated. In the semiconductor body 2, a first region 211 made of a first doping type and a second region 212 made of a second doping type are formed, wherein the first region 211 may be a drift region in the semiconductor device 110. The second region 212 may be a compensation region. Reference numeral 110.1 indicates a superjunction transistor cell.

[0071] Above the first region 211 and the second region 212, a body region 112 and a source region 111 (load terminal 115) may be formed. The source region 111 is disposed on a first side 2.1 of the semiconductor body 2, and the drain region 113 of the device 110 is disposed on a vertically opposite second side 2.2 (“back side”) of the semiconductor body 2. The source region 111 and the drain region 113 may be made of a first doping type, and the body region 112 may be made of a second doping type. The first doping type may be particularly n-type, and the second doping type may be particularly p-type. From the first side 2.1, one or more gate trenches 215 extend into the semiconductor body, and gate electrodes / terminals 116 are laterally disposed next to the body region 112. In embodiments not shown, the body region may be disposed next to the source region, for example, in combination with the planar gate formed above.

Claims

1. A semiconductor die (1) having a semiconductor body (2), the semiconductor die (1) comprising: A transistor device (110) is located in the active region (100) of the die (1); An edge termination structure (10) is laterally located between the active region (100) and the lateral edge (1.1) of the die (1); The load contact (20) is electrically connected to the load terminal (115) of the transistor device (110). The gate contact (30) is electrically connected to the gate terminal (116) of the transistor device (110). An electrostatic discharge (ESD) protection structure (40) is electrically connected between the load contact (20) and the gate contact (30); The edge termination structure (10) includes a field dielectric (11) made of a field dielectric material (12). The field dielectric material (12) has a first thickness (t1) in the first part (10.1) of the edge termination structure (10) and a second thickness (t2) in the second part (10.2) of the edge termination structure (10). The second part (10.2) is arranged laterally between the first part (10.1) and the active region (100), and the second thickness (t2) is less than the first thickness (t1). The ESD protection structure (40) overlaps at least partially with the second part (10.2).

2. The semiconductor die (1) according to claim 1, wherein, The field dielectric (11) of the edge termination structure (10) is arranged in a shallow trench (13) recessed in the semiconductor body (2).

3. The semiconductor die (1) according to claim 2, wherein, The first side (12.1) of the field dielectric material (12) facing away from the semiconductor body (2) is planar.

4. The semiconductor die (1) according to claim 2 or 3, wherein, The shallow trench (13) has an inclined sidewall (13a) facing the active region (100), and the ESD protection structure (40) overlaps at least partially with the inclined sidewall (13a).

5. The semiconductor die (1) according to claim 4, wherein, In a vertical section perpendicular to the lateral edge (1.1) of the core (1), the ESD protection structure (40) overlaps with the entire inclined sidewall (13a).

6. The semiconductor die (1) according to any one of claims 2 to 5, wherein, A well region (15) made of a second doping type is arranged at the bottom of the shallow trench (13), the well region (15) including a non-depletable doped region and a depletable doped region.

7. A semiconductor die (1), comprising: A transistor device (110) is located in the active region (100) of the die (1); The load contact (20) is electrically connected to the load terminal (115) of the transistor device (110). The gate contact (30) is electrically connected to the gate terminal (116) of the transistor device (110). A gate interconnect structure (90) connects the gate terminal (116) of the transistor device (110) to the gate contact (30). An electrostatic discharge (ESD) protection structure (40) is electrically connected between the load contact (20) and the gate contact (30); The gate interconnect structure (90) extends along a first length (101.1) of a first side (101) of the active region (100). The ESD protection structure (40) extends along a second length (101.2) of the first side (101) of the active region (100). Wherein, the gate interconnect structure (90) is completely interrupted along the second length (101.2) of the first side (101) of the active region (100).

8. The semiconductor die (1) according to claim 7, wherein, The gate interconnect structure (90) and the ESD protection structure (40) are formed in a common material layer (50), particularly in a polysilicon layer (51).

9. The semiconductor die (1) according to claim 7 or 8, comprising: A second electrostatic discharge (ESD) protection structure (140) is electrically connected between the load contact (20) and the gate contact (30); The second ESD protection structure (140) extends along the entire second side (102) of the active region (100).

10. The semiconductor die (1) according to any one of claims 7 to 9, comprising: An edge termination structure (10) is laterally located between the active region (100) and the lateral edge (1.1) of the die (1); The edge termination structure (10) includes a field dielectric (11) made of a field dielectric material (12). The field dielectric material (12) has a first thickness (t1) in the first part (10.1) of the edge termination structure (10) and a second thickness (t2) in the second part (10.2) of the edge termination structure (10). The second part (10.2) is arranged laterally between the first part (10.1) and the active region (100), and the second thickness (t2) is less than the first thickness (t1). Wherein, along the first length (101.1), the gate interconnect structure (90) overlaps with the first portion (10.1) and the second portion (10.2), and Along the second length (101.2), the ESD protection structure (40) overlaps with the first portion (10.1) and the second portion (10.2).

11. The semiconductor die (1) according to claim 10, wherein, The field dielectric (11) of the edge termination structure (10) is arranged in a shallow trench (13) recessed in the semiconductor body (2), the shallow trench (13) having inclined sidewalls (13a) toward the active region (100). Along the first length (101.1), the gate interconnect structure (90) overlaps with the entire inclined sidewall (13a), and Along the second length (101.2), the ESD protection structure (40) overlaps with the entire inclined sidewall (13a).

12. A semiconductor die (1), comprising: A transistor device (110) is located in the active region (100) of the die (1); The load contact (20) is electrically connected to the load terminal (115) of the transistor device (110). The gate contact (30) is electrically connected to the gate terminal (116) of the transistor device (110). An electrostatic discharge (ESD) protection structure (40) is electrically connected between the load contact (20) and the gate contact (30); The ESD protection structure (40) includes a first region (41) made of a first doping type and a second region (42) made of a second doping type. The first region (41) and the second region (42) are arranged alternately in succession. The doping concentration (62) of the second region (42) is higher than that of the first region (41).

13. A semiconductor die (1), comprising: A transistor device (110) is located in the active region (100) of the die (1); The load contact (20) is electrically connected to the load terminal (115) of the transistor device (110). The gate contact (30) is electrically connected to the gate terminal (116) of the transistor device (110). An electrostatic discharge (ESD) protection structure (40) is electrically connected between the load contact (20) and the gate contact (30); The ESD protection structure (40) includes a first region (41) made of a first doping type, a second region (42) made of a second doping type, and a contact region (43) made of the second doping type. The first region (41) and the second region (42) are arranged alternately and continuously between the contact area (43). The doping concentration (63) in the contact area (43) is higher than the doping concentration (61, 62) in the first region (41) and / or the second region (42).

14. The semiconductor die (1) according to claim 13, wherein, The first region (41) and the second region (42) are arranged alternately in a continuous length direction (45), wherein the extension of the contact area (43) in the length direction (45) is greater than the extension of the corresponding first region (41) and / or the second region (42) in the length direction (45).

15. The semiconductor die (1) according to claim 13 or 14, wherein, The first region (41) and the second region (42) are arranged alternately in a length direction (45), wherein the first region (41) has substantially the same extension relative to each other in the length direction (45), and / or the second region (42) has substantially the same extension relative to each other in the length direction (45).

16. The semiconductor die (1) according to claim 15, wherein, The doping concentration (62) of the second region (42) is higher than that of the first region (41).

17. The semiconductor die (1) according to any one of the preceding claims, wherein, The ESD protection structure (40) is formed in the polysilicon layer (51), and in particular, the first region (41) and the second region (42) of the ESD protection structure (40) are formed in the polysilicon layer (51).

18. The semiconductor die (1) according to claim 17, wherein, The polycrystalline silicon layer (51) has a thickness (t) of no more than 400 nm, 300 nm, 200 nm or 100 nm. ps The possible lower limit of the thickness of the polycrystalline silicon layer (51) is 50 nm or 80 nm.

19. The semiconductor die (1) according to any one of the preceding claims, wherein, The ESD protection structure (40) has a diode spacing of no more than 2.3μm, 2μm, 1.7μm, 1.4μm, 1.2μm, 1μm, or 0.8μm, with the lower limit of the diode spacing being 0.6μm or 0.7μm.

20. The semiconductor die (1) according to any one of the preceding claims, comprising: Field dielectric (11), the ESD protection structure (40) is arranged on the field dielectric (11); The ESD protection structure (40) is embedded in the interlayer dielectric (70) arranged on the field dielectric (11).

21. The semiconductor die (1) according to any one of the preceding claims, wherein, The transistor device (110) includes a plurality of superjunction transistor units (110.1).

22. A method for manufacturing a semiconductor die (1), particularly a semiconductor die (1) according to any one of the preceding claims, the method comprising the following steps: A transistor device (110) is formed in the active region (100) of the die (1). An electrostatic discharge (ESD) protection structure (40) is formed between the load contact (20) and the gate contact (30).

23. The method according to claim 22, particularly a method for manufacturing a semiconductor die (1) according to any one of claims 12 to 18, in, The formation of the ESD protection structure (40) includes: A polycrystalline silicon layer doped with a first type of doping is provided (51); A structured mask (80) is provided on the doped polysilicon layer; The second doping type is injected through the opening (82) defined by the mask.

24. The method according to claim 23, wherein, The corresponding opening (83) of the corresponding contact area (43) is larger than the corresponding opening (82) of the corresponding second region (42), and / or the corresponding opening (82) of the corresponding second region (42) is smaller than the corresponding coverage segment (81) between the corresponding opening (82) of the corresponding second region (42).

25. The method according to claim 24, wherein, The corresponding opening (82) of the corresponding second region (42) is limited to less than half the diode spacing.

26. The method according to claim 24 or 25, wherein, The corresponding opening (82) of the corresponding second region (42) has an extension of no more than 600 nm, 500 nm, 400 nm, 300 nm or 200 nm measured in the length direction (45), the lower limit of which is 100 nm or 150 nm.

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