Cutting method for improving adhesive surface edge breakage of BC silicon wafer

Abstract

The invention discloses a cutting method for improving adhesive surface edge breakage of a BC silicon wafer, and relates to the technical field of linear cutting, and the method comprises the following steps: step 1, placing the BC silicon wafer on a linear cutting machine object carrying table, step 2, carrying out three-section segmentation cutting on the BC silicon wafer according to the structural composition of the BC silicon wafer, and step 3, collecting linear cutting processing data of the BC silicon wafer; 4, establishing a BC silicon wafer cutting simulation model according to data acquired during linear cutting of the BC silicon wafer; and 5, analyzing the cutting condition of the BC silicon wafer in real time according to the BC silicon wafer cutting simulation model established in the step 4, and optimizing the linear cutting processing parameters of the BC silicon wafer. According to the BC silicon wafer cutting method for improving the edge breakage of the adhesive surface, the purposes of confirming and researching the cutting depth of a cutting line contact adhesive layer, improving technological parameters, reducing the line speed in advance and preventing edge breakage output are achieved, basic cutting parameters are adjusted, simulation is conducted through a BC silicon wafer cutting simulation model, and optimized BC silicon wafer cutting parameters are obtained.

Description

Technical Field

[0001] This invention relates to the field of wire cutting technology, and in particular to a method for cutting BC silicon wafers to improve the chipping of the adhesive surface. Background Technology

[0002] BC silicon wafers are the core substrate of back-contact solar cells. Specifically, they refer to low-oxygen, high-resistivity N-type silicon wafers used in BC cells. Their most significant feature is extremely low doping concentration. By optimizing the purity, oxygen content, and crystal structure of the silicon wafer, high minority carrier lifetime and photoelectric conversion efficiency are achieved. They are the key materials that support BC cells to approach the theoretical efficiency limit.

[0003] Furthermore, cost reduction and efficiency improvement are the main themes of the photovoltaic industry, and the advancement of finer wire cutting is the mainstream technical route for continuously reducing the cost of silicon wafer cutting. Fine wire cutting is carried out in the middle or on both sides of the adhesive surface. However, during the cutting process, due to the difference in physical properties between the adhesive layer and the silicon wafer body, the stress concentration during cutting can easily lead to edge chipping of the adhesive surface, which seriously affects the product qualification rate. In addition, traditional wire cutting technology mostly adopts a single-parameter cutting mode and does not dynamically adjust parameters according to the structural characteristics of BC silicon wafers, such as the distribution and thickness variation of the adhesive layer. Moreover, traditional processes usually rely on the experience of workers to adjust parameters, lacking data-driven quantitative analysis, resulting in high trial and error costs and difficulty in balancing cutting efficiency and edge chipping risk, thus having certain defects. Summary of the Invention

[0004] The purpose of this invention is to provide a method for improving the edge chipping of BC silicon wafers during cutting, so as to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a method for improving the edge chipping of BC silicon wafers during cutting, comprising the following specific steps: Step 1: Place the BC silicon wafer on the platform of the wire cutting machine and install the detection instrument on the wire cutting machine for real-time data detection of the BC silicon wafer cutting. Step 2: Based on the structure of the BC silicon wafer, the BC silicon wafer is cut into three segments. According to the order of segment cutting, the speed of the BC silicon wafer cutting line decreases step by step, and the table speed of the wire cutting machine for conveying the BC silicon wafer also decreases step by step. Step 3: Collect data from the BC silicon wafer wire cutting process and set the BC silicon wafer segment cutting parameters from Step 2 as the basic cutting parameters; Step 4: Establish a BC silicon wafer cutting simulation model based on the data collected during BC silicon wafer wire cutting, and use the BC silicon wafer cutting simulation model to simulate BC silicon wafer cutting. Step 5: Analyze the BC silicon wafer cutting situation in real time based on the BC silicon wafer cutting simulation model established in Step 4, and optimize the BC silicon wafer wire cutting processing parameters based on the BC silicon wafer cutting analysis.

[0006] Preferably, the three-segment cutting of the BC silicon wafer in step two includes a first segment cutting, a second segment cutting, and a third segment cutting. The first segment cutting is to cut the BC silicon wafer from 0-200mm. During the first segment cutting, the wire cutting machine feeds wire at a speed between 500-2100m / min. During the first segment cutting, 10km of new wire stored on the take-up reel of the wire cutting machine is fed in the opposite direction to the feed reel of the wire cutting machine for cutting. During the first segment cutting, the feed speed of the wire cutting machine to the BC silicon wafer is between 1500-2700um / min.

[0007] Preferably, the second stage of cutting is to cut the BC silicon wafer to 200-218.8mm, and the wire feeding speed of the wire cutting machine during the second stage of cutting is between 2200-1450m / min. In the second stage of cutting, the 9km old wire on the wire feeding wheel of the wire cutting machine is fed forward to the wire taking wheel of the wire cutting machine for cutting, and the table speed of the wire cutting machine feeding the BC silicon wafer during the second stage of cutting is between 1800-150um / min.

[0008] Preferably, the third stage of cutting is performed on BC silicon wafers of 218.8-219.6mm, and the wire cutting machine feeds wire at a speed between 1400-1500m / min during the third stage of cutting. In the third stage of cutting, the 4km secondary old wire on the take-up reel of the wire cutting machine is fed in the reverse direction to the feed reel end for cutting, and the feed speed of the wire cutting machine to the BC silicon wafer is between 90-110um / min during the third stage of cutting.

[0009] Preferably, the data collected for BC silicon wafer wire cutting includes the BC silicon wafer feed position, wire speed, table speed, wire feed rate, wire return rate, coolant flow rate, BC silicon wafer and cutting wire temperature, video of the cutting wire cutting the BC silicon wafer, and tension of the cutting wire during operation. The video of the cutting wire cutting the BC silicon wafer also includes cross-sectional images of the BC silicon wafer after cutting. The basic cutting parameters include the BC silicon wafer feed position, wire speed, table speed, wire feed rate, wire return rate, and coolant flow rate. These basic cutting parameters provide foundational data for subsequent optimization of BC silicon wafer wire cutting parameters.

[0010] Preferably, the establishment of the BC silicon wafer dicing simulation model in step four includes the following steps: S4.1: Perform data processing and feature parameter extraction on the collected BC silicon wafer wire cutting data; S4.2: A geometric model is built using 3D modeling software, and the modules of the geometric model's motion are logically defined using physical fields and mathematical models. Based on the extracted feature parameters, the parameters of the defined geometric model are set to form a BC silicon wafer cutting simulation model. S4.3: Input the existing BC silicon wafer wire cutting process parameters, verify the BC silicon wafer cutting simulation model, and optimize the parameters set in the geometric model based on the verification results; S4.4: Use the BC silicon wafer cutting simulation model to simulate BC silicon wafer cutting and obtain simulation results.

[0011] Preferably, in step S4.4, when simulating BC silicon wafer wire cutting using the BC silicon wafer cutting simulation model, the basic cutting parameters are first adjusted. The adjusted basic cutting parameters are then input into the BC silicon wafer cutting simulation model, enabling the BC silicon wafer cutting simulation model to perform BC silicon wafer wire cutting simulation and output simulation results. Simultaneously, the adjusted basic cutting parameters are input into the wire cutting machine, allowing the wire cutting machine to perform wire cutting on the BC silicon wafer using the adjusted basic cutting parameters and obtain the BC silicon wafer wire cutting processing results. The simulation results are verified by processing the BC silicon wafer wire cutting results using the wire cutting machine. Based on the differences in the comparison results, the BC silicon wafer cutting simulation model is optimized again until the BC silicon wafer cutting simulation results and the BC silicon wafer wire cutting results processed by the wire cutting machine are within the allowable error range.

[0012] Preferably, after the BC silicon wafer cutting simulation model has undergone dual verification and optimization, the basic cutting parameters are adjusted to obtain multiple sets of simulated cutting parameter control groups. These multiple sets of simulated cutting parameters are then input into the BC silicon wafer cutting simulation model, enabling the BC silicon wafer cutting simulation model to perform multiple sets of BC silicon wafer wire cutting simulations and obtain multiple sets of BC silicon wafer wire cutting simulation results.

[0013] Preferably, multiple sets of BC silicon wafer wire cutting simulation results are processed. First, simulation results with edge chipping during BC silicon wafer wire cutting are removed. Then, simulation results with BC silicon wafer wire cutting efficiency lower than that of BC silicon wafer wire cutting according to basic cutting parameters are removed to obtain optimized simulation results. The optimized simulation results are packaged into files, and the files are labeled and coded. The files contain the simulation cutting parameters corresponding to the optimized simulation results. Then, the simulation cutting parameters in the files are input into the wire cutting machine to obtain the actual wire cutting results. The optimized simulation results in the files are verified, and the verification results are packaged into the corresponding labeled and coded files.

[0014] Preferably, in step five, the analysis of the BC silicon wafer cutting analysis involves comparing the optimized simulation results with the actual wire cutting results. First, it is determined whether the error between the optimized simulation results and the actual wire cutting results is within the allowable error range. If the error exceeds the allowable error range, it is considered an invalid optimized simulation result. If the error does not exceed the allowable error range, it is considered a valid optimized simulation result. The remaining valid optimized simulation results are then compared, and the valid optimized simulation results with low mechanical energy consumption and low material consumption are selected as the final optimized BC silicon wafer wire cutting processing parameters output.

[0015] The technical effects and advantages of this invention are as follows: This invention utilizes a method to improve the edge chipping of BC silicon wafers during cutting. By confirming the cutting depth of the contact layer between the cutting line and the adhesive layer, the process parameters are improved, and the line speed is reduced in advance to reduce wire mesh swaying during the cutting process, enhance liquid carrying performance, and prevent edge chipping. Furthermore, the basic cutting parameters are adjusted, and simulations are performed using a BC silicon wafer cutting simulation model to obtain optimized BC silicon wafer cutting parameters and improve BC silicon wafer production efficiency. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of the cutting method of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] This invention provides, for example Figure 1 This illustrates a method for improving the edge chipping of BC silicon wafers during cutting.

[0019] Example 1: Includes the following specific steps: Step 1: Place the BC silicon wafer on the platform of the wire cutting machine and install detection instruments on the wire cutting machine for real-time data detection of the BC silicon wafer cutting. The detection instruments include a detection camera, temperature sensor, pressure sensor, flow meter, laser interferometer, etc. The laser interferometer uses the laser ranging principle to accurately measure the displacement of the cutting line in the wire cutting machine per unit time and calculate the line speed. The temperature sensor can detect the temperature of the cutting line and the BC silicon wafer, and the flow meter can detect the coolant supply flow rate on the wire cutting machine. Step 2: Based on the structure of the BC silicon wafer, the BC silicon wafer is cut into three segments. According to the order of segment cutting, the cutting speed of the BC silicon wafer cutting line is gradually reduced, and the table speed of the wire cutting machine for feeding the BC silicon wafer is also gradually reduced. As the cutting thickness of the BC silicon wafer decreases, the cutting speed is reduced, which can effectively reduce the chipping of the BC silicon wafer adhesive surface and improve the product qualification rate. Step 3: Collect data from the BC silicon wafer wire cutting process, and set the BC silicon wafer segment cutting parameters from Step 2 as the basic cutting parameters. The basic cutting parameters can be used as the basis for subsequent adjustments to improve the efficiency and quality of BC silicon wafer wire cutting. Step 4: Establish a BC silicon wafer cutting simulation model based on the data collected during BC silicon wafer wire cutting, and use the BC silicon wafer cutting simulation model to simulate BC silicon wafer cutting, so as to adjust the basic cutting parameters in the future. Step 5: Analyze the BC silicon wafer cutting situation in real time based on the BC silicon wafer cutting simulation model established in Step 4. Based on the BC silicon wafer cutting analysis, optimize the BC silicon wafer wire cutting processing parameters and improve the BC silicon wafer production parameters.

[0020] Furthermore, in step two, the BC silicon wafer undergoes three-stage cutting, including a first-stage cutting, a second-stage cutting, and a third-stage cutting. The first-stage cutting involves cutting the BC silicon wafer from 0-200mm, and the wire cutting machine's wire feed speed during this first-stage cutting is between 500-2100m / min. During this first-stage cutting, 10km of new wire stored on the take-up reel of the wire cutting machine is fed in the reverse direction towards the feed reel. The feed speed of the wire cutting machine onto the BC silicon wafer during this first-stage cutting is between 1500-2700um / min. The parameters for wire cutting the BC silicon wafer are shown in the table below.

[0021] When the BC wafer is fed to a position of -1 to 5mm, the linear speed is 500m / min and the stage speed is 1500um / min. When the BC wafer is fed to a position of 5 to 10mm, the linear speed is 1200m / min and the stage speed is 1800um / min. When the BC wafer is fed to a position of 10 to 15mm, the linear speed is 1800m / min and the stage speed is 2200um / min. When the BC wafer is fed to a position of 15 to 200mm, the linear speed is 2100m / min. The stage speed for feeding the BC wafer is 2500 μm / min at the 15-20 mm position, 2700 μm / min at the 20-150 mm position, 2600 μm / min at the 150-170 mm position, 2500 μm / min at the 170-190 mm position, and 2400 μm / min at the 190-200 mm position.

[0022] Furthermore, the second stage of cutting involves dicing the BC silicon wafer to 200-218.8mm. During this second stage, the wire cutting machine's feed speed ranges from 2200-1450m / min. The second stage involves feeding the 9km old wire from the feed reel onto the take-up reel in a forward direction for cutting. During this second stage, the feed speed of the wire cutting machine onto the BC silicon wafer ranges from 1800-150µm / min. As shown in the table above, when the BC silicon wafer is fed to a position... At the 200-212mm position, the linear velocity is 2100m / min; at the 212-214mm position, the linear velocity is 1800m / min; at the 214-216mm position, the linear velocity is 1600m / min; at the 216-217mm position, the linear velocity is 1500m / min; and at the 217-218.8mm position, the linear velocity is 1450m / min. When the BC wafer is fed to a position of 200-208mm, the stage speed is 2200µm / min; when the BC wafer is fed to a position of 208-212mm, the stage speed is 1800µm / min; when the BC wafer is fed to a position of 212-214mm, the stage speed is 1500µm / min; and when the BC wafer is fed to a position of 214-216mm, the stage speed is 1200µm / min. When the BC silicon wafer is fed to a position of 216-217mm, the stage speed is 800um / min. When the BC silicon wafer is fed to a position of 217-218.8mm, the stage speed is 400um / min. The stage speed is reduced before the cutting line contacts the adhesive layer of the BC silicon wafer. This ensures that the cutting force is not lost and prevents the production of defective products with chipped adhesive surface. The low stage speed has a smaller impact on the adhesive surface defects caused by the cutting abnormality, increasing the versatility of the silicon wafer cutting finishing process.

[0023] Furthermore, the third stage of cutting involves cutting the BC silicon wafer to the 218.8-219.6mm range. During this third stage, the wire cutting machine feeds wire at a speed between 1400-1500 m / min. The third stage also involves feeding the 4km secondary old wire from the take-up reel to the feed reel in the reverse direction. During this third stage, the feed speed of the wire cutting machine on the BC silicon wafer ranges from 90-110 μm / min. As shown in the table above, when the BC silicon wafer is fed to the 218.8-219.6mm position, the wire speed is 1450 m / min; when it is fed to the 218.8-219mm position, the feed speed is 150 μm / min; and when it is fed to the 219-219.6mm position, the feed speed is 100 μm / min.

[0024] Example 2: Based on Example 1, the data collected for BC silicon wafer wire cutting includes the BC silicon wafer feed position, wire speed, table speed, wire feed amount, wire return amount, coolant flow rate, BC silicon wafer and cutting wire temperature, cutting wire on BC silicon wafer video, and tension during cutting wire operation. The BC silicon wafer feed position, wire speed, table speed, wire feed amount, wire return amount, coolant flow rate, BC silicon wafer and cutting wire temperature, cutting wire on BC silicon wafer video, and tension during cutting wire operation are obtained by detection instruments on the wire cutting machine. The cutting wire on BC silicon wafer video also includes cross-sectional images of the BC silicon wafer after cutting. The cross-sectional images of the BC silicon wafer after cutting can be analyzed to determine whether there is any chipping of the cut surface. The basic cutting parameters include the BC silicon wafer feed position, wire speed, table speed, wire feed amount, wire return amount, and coolant flow rate. The basic cutting parameters provide basic data for subsequent optimization of BC silicon wafer wire cutting parameters, so that subsequent optimization and adjustment of BC silicon wafer wire cutting parameters can be carried out based on the basic cutting parameters.

[0025] In particular, the establishment of the BC silicon wafer dicing simulation model in step four includes the following steps: S4.1: Data processing and feature parameter extraction are performed on the collected BC silicon wafer wire cutting data. This involves interpolating the timing data such as feed position, line speed, and table speed to generate a continuous variation curve, dividing the key intervals for adhesive layer cutting (e.g., 212mm is the starting point for line speed reduction, 218.8mm is the starting point for the third cutting segment), and marking high-risk areas for edge chipping. Then, features are extracted from the data to facilitate the judgment of the BC silicon wafer cutting surface based on the extracted features, i.e., to determine whether the BC silicon wafer cutting surface is neat and has a chipped surface. S4.2: A geometric model is built using 3D modeling software. This involves creating a simplified geometric model of the cutting mesh (including take-up / release wheels), the silicon wafer with adhesive layer, and the worktable, defining the cutting path, i.e., the reciprocating motion trajectory. 3D modeling software is a type of tool used to create, edit, and display 3D models, widely used in game development, animation production, architectural design, product design, virtual reality, and other fields. Blender, for example, is open-source and free, powerful, and supports various functions such as modeling, sculpting, animation, and rendering. It has an active community and a rich plugin ecosystem. The movement modules of the geometric model are logically defined using physical fields and mathematical models. Based on the extracted feature parameters, the defined geometric model is parameterized. The physical fields and mathematical models include kinematic models, dynamic models, and material removal models. The kinematic model is based on the collaborative control logic of line speed and table speed in the document, establishing a coupling equation between the mesh speed and the worktable feed speed. The coupling equation is as follows:

[0026] in For wire cutting force The density of the silicon wafer material reflects the relationship between the cutting force and the increase of the table speed and the decrease of the line speed. The dynamic model introduces the wire mesh vibration equation to simulate the sudden change in line speed, such as the wire mesh sway caused by the decrease from 2100m / min to 1800m / min at 212mm. The material removal model uses the finite element method to simulate the material removal rate during the cutting process, and correlates the wire feed, wire return and cutting efficiency. For example, when the wire feed in the third section is 1774m, the table speed is reduced to 100um / min to reduce the impact of the adhesive layer. The finite element method is a numerical technique used to solve approximate solutions to complex engineering and physical problems, forming the BC silicon wafer cutting simulation model. S4.3: Input the existing BC silicon wafer wire cutting process parameters, verify the BC silicon wafer cutting simulation model, thereby improving the accuracy of the BC silicon wafer cutting simulation model, and optimize the parameters set in the geometric model based on the verification results; S4.4: Use the BC silicon wafer cutting simulation model to simulate BC silicon wafer cutting and obtain simulation results. Using the BC silicon wafer cutting simulation model to simulate BC silicon wafer cutting can quickly obtain the results of BC silicon wafer wire cutting with different BC silicon wafer wire cutting process parameters. Therefore, based on the simulation results, more efficient BC silicon wafer wire cutting process parameters can be derived in reverse.

[0027] Furthermore, in step S4.4, when simulating BC silicon wafer wire cutting using the BC silicon wafer cutting simulation model, the basic cutting parameters are first adjusted. The adjusted basic cutting parameters are then input into the BC silicon wafer cutting simulation model, enabling the model to perform the BC silicon wafer wire cutting simulation and output the simulation results. Simultaneously, the adjusted basic cutting parameters are input into the wire cutting machine, allowing the machine to perform wire cutting on the BC silicon wafer using these parameters, and the BC silicon wafer wire cutting processing result is obtained. The simulation results are then verified by processing the BC silicon wafer wire cutting result using the wire cutting machine. The BC silicon wafer cutting simulation model was further optimized by comparing the results until the simulation results and the wire EDM results were within the allowable error range. The allowable error range is the error of the BC silicon wafer cutting standard set during wire EDM. By inputting the adjusted basic cutting parameters into the wire EDM machine to perform BC silicon wafer cutting, the simulation results of the BC silicon wafer cutting model were verified again. This process allows for further verification and optimization of the BC silicon wafer cutting simulation model, thereby improving its accuracy and stability.

[0028] Furthermore, after the BC silicon wafer cutting simulation model has undergone dual verification and optimization, the basic cutting parameters are adjusted. Adjusting these parameters involves modifying individual values ​​within each parameter, such as adjusting the linear speed to form a linear speed adjustment reference group, and adjusting the table speed to form a table speed adjustment reference group. Once these reference groups are established, the linear speed and table speed are simultaneously adjusted to form a linear speed and table speed adjustment reference group. Each adjustment reference group comprises at least ten parts, and the adjustment range for linear speed and table speed is based on the linear speed and table speed values ​​defined in the basic cutting parameters, with adjustments made up or down. The flow rate of the coolant on the wire EDM machine is adjusted accordingly during line speed adjustment. For example, increasing the line speed increases the coolant flow rate, and vice versa. The coolant adjustment must ensure that the temperature of the cutting wire is kept within the set range, i.e., the safe operating value of the cutting wire. Multiple sets of simulated cutting parameter control groups are obtained. These multiple sets of simulated cutting parameters are input into the BC silicon wafer cutting simulation model, which then performs multiple sets of BC silicon wafer wire cutting simulations. Multiple sets of BC silicon wafer wire cutting simulation results are obtained, including simulation results of the line speed adjustment reference group, simulation results of the table speed adjustment reference group, and simulation results of the line speed and table speed adjustment reference group.

[0029] Furthermore, multiple sets of BC silicon wafer wire cutting simulation results are processed. First, simulation results simulating edge chipping during BC silicon wafer wire cutting are removed, directly avoiding the need to adjust parameter groups for edge chipping during BC silicon wafer wire cutting, thus reducing the workload of subsequent parameter group selection. Second, simulation results simulating BC silicon wafer wire cutting efficiency being lower than that of BC silicon wafer wire cutting based on the basic cutting parameters are removed, thus avoiding the situation where the BC silicon wafer wire cutting efficiency is lower than that of BC silicon wafer wire cutting based on the basic cutting parameters after adjustment, further reducing the workload of subsequent parameter group selection. Optimized simulation results are obtained, and the optimized simulation results are packaged into files, which are then labeled and coded. The file contains simulated cutting parameters corresponding to the optimized simulation results. These parameters are then input into the wire EDM machine to obtain the actual wire EDM results. By eliminating simulation results with edge chipping and low efficiency during the simulated wire EDM of BC silicon wafers, the actual cutting workload of the wire EDM machine can be reduced, thereby improving verification efficiency and reducing resource waste. The optimized simulation results in the file are verified, and the verification results are packaged into a file with corresponding annotation codes. The annotation codes in the file include information on the adjustment parameter control groups, namely the line speed adjustment reference group, the table speed adjustment reference group, and the line speed and table speed adjustment reference group information and batch, so as to facilitate subsequent lookup of corresponding information based on the file.

[0030] In particular, step five, analyzing the BC silicon wafer cutting process, involves comparing the optimized simulation results with the actual wire cutting results. First, it's determined whether the error between the optimized simulation and actual wire cutting results is within the allowable error range. If the error exceeds this range, the optimized simulation result is considered invalid, thus ensuring the optimized simulation results contribute to production quality and reducing defective products. If the error is within the allowable error range (i.e., the error in setting the BC silicon wafer cutting standard), it is considered a valid optimized simulation result. The remaining valid optimized simulation results are then compared, and the one with the lowest mechanical energy consumption and lowest material consumption is selected as the final optimized BC silicon wafer wire cutting result. The processing parameters are output, and if the errors between all optimized simulation results and actual wire cutting results exceed the allowable error range, then there are no effective optimized simulation results, and the basic wire cutting parameters are considered the optimal BC silicon wafer wire cutting processing parameters. If there are no more than two optimized simulation results whose errors exceed the allowable error range, then the BC silicon wafer wire cutting processing parameters of these optimized simulation results are adjusted again to obtain secondary adjusted parameters. The above steps are repeated, and the secondary adjusted parameters are simulated, the results are eliminated, and compared with actual cutting until two or more effective optimized simulation results are obtained. From the two or more effective optimized simulation results, the effective optimized simulation results with low mechanical energy consumption and low material consumption are selected as the final optimized BC silicon wafer wire cutting processing parameters output.

[0031] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for improving the edge chipping of BC silicon wafers during cutting, characterized in that: The specific steps include the following: Step 1: Place the BC silicon wafer on the platform of the wire cutting machine and install the detection instrument on the wire cutting machine for real-time data detection of the BC silicon wafer cutting. Step 2: Based on the structure of the BC silicon wafer, the BC silicon wafer is cut into three segments. According to the order of segment cutting, the speed of the BC silicon wafer cutting line decreases step by step, and the table speed of the wire cutting machine for conveying the BC silicon wafer also decreases step by step. Step 3: Collect data from the BC silicon wafer wire cutting process and set the BC silicon wafer segment cutting parameters from Step 2 as the basic cutting parameters; Step 4: Establish a BC silicon wafer cutting simulation model based on the data collected during BC silicon wafer wire cutting, and use the BC silicon wafer cutting simulation model to simulate BC silicon wafer cutting. Step 5: Analyze the BC silicon wafer cutting situation in real time based on the BC silicon wafer cutting simulation model established in Step 4, and optimize the BC silicon wafer wire cutting processing parameters based on the BC silicon wafer cutting analysis.

2. The method for improving the edge chipping of BC silicon wafers according to claim 1, characterized in that: In step two, the BC silicon wafer is cut into three segments, including a first segment cut, a second segment cut, and a third segment cut. The first segment cut is to cut the BC silicon wafer from 0-200mm. During the first segment cut, the wire cutting machine feeds wire at a speed between 500-2100m / min. During the first segment cut, 10km of new wire stored on the take-up reel of the wire cutting machine is fed in the opposite direction to the feed reel of the wire cutting machine. During the first segment cut, the feed speed of the wire cutting machine to the BC silicon wafer is between 1500-2700um / min.

3. The method for improving the edge chipping of BC silicon wafers according to claim 2, characterized in that: The second stage of cutting involves cutting BC silicon wafers to 200-218.8mm. During the second stage of cutting, the wire cutting machine feeds wire at a speed between 2200-1450m / min. The second stage of cutting involves feeding 9km of old wire from the feed roller to the take-up roller on the wire cutting machine in a forward direction. During the second stage of cutting, the feed speed of the wire cutting machine to the BC silicon wafer is between 1800-150um / min.

4. The method for improving the edge chipping of BC silicon wafers according to claim 3, characterized in that: The third stage of cutting involves cutting BC silicon wafers from 218.8 to 219.6 mm. During the third stage of cutting, the wire cutting machine feeds wire at a speed between 1400 and 1500 m / min. The third stage of cutting involves feeding 4 km of secondary old wire from the take-up reel of the wire cutting machine in the reverse direction towards the feed reel. During the third stage of cutting, the feed speed of the wire cutting machine to the BC silicon wafer is between 90 and 110 μm / min.

5. The method for improving the edge chipping of BC silicon wafers according to claim 4, characterized in that: The data collected for BC silicon wafer wire cutting includes the BC silicon wafer feed position, wire speed, table speed, wire feed rate, wire return rate, coolant flow rate, BC silicon wafer and cutting wire temperature, video of the cutting wire cutting the BC silicon wafer, and tension of the cutting wire during operation. The video of the cutting wire cutting the BC silicon wafer also includes cross-sectional images of the BC silicon wafer after cutting. The basic cutting parameters include the BC silicon wafer feed position, wire speed, table speed, wire feed rate, wire return rate, and coolant flow rate. These basic cutting parameters provide foundational data for subsequent optimization of BC silicon wafer wire cutting parameters.

6. The method for improving the edge chipping of BC silicon wafers according to claim 5, characterized in that: The establishment of the BC silicon wafer dicing simulation model in step four includes the following steps: S4.1: Perform data processing and feature parameter extraction on the collected BC silicon wafer wire cutting data; S4.2: A geometric model is built using 3D modeling software, and the modules of the geometric model's motion are logically defined using physical fields and mathematical models. Based on the extracted feature parameters, the parameters of the defined geometric model are set to form a BC silicon wafer cutting simulation model. S4.3: Input the existing BC silicon wafer wire cutting process parameters, verify the BC silicon wafer cutting simulation model, and optimize the parameters set in the geometric model based on the verification results; S4.4: Use the BC silicon wafer cutting simulation model to simulate BC silicon wafer cutting and obtain simulation results.

7. The method for improving the edge chipping of BC silicon wafers according to claim 6, characterized in that: In step S4.4, when simulating BC silicon wafer wire cutting using the BC silicon wafer cutting simulation model, the basic cutting parameters are first adjusted. The adjusted basic cutting parameters are then input into the BC silicon wafer cutting simulation model, enabling the model to perform BC silicon wafer wire cutting simulation and output the simulation results. Simultaneously, the adjusted basic cutting parameters are input into the wire cutting machine, allowing the machine to perform wire cutting on the BC silicon wafer using the adjusted parameters and obtain the BC silicon wafer wire cutting processing results. The simulation results are then verified by processing the BC silicon wafer wire cutting results using the wire cutting machine. Based on the differences in the comparison results, the BC silicon wafer cutting simulation model is optimized again until the simulation results of the BC silicon wafer cutting model and the wire cutting results of the BC silicon wafer wire cutting machine are within the allowable error range.

8. The method for improving the edge chipping of BC silicon wafers according to claim 7, characterized in that: After the BC silicon wafer cutting simulation model is double-verified and optimized, the basic cutting parameters are adjusted to obtain multiple sets of simulated cutting parameter control groups. These multiple sets of simulated cutting parameters are then input into the BC silicon wafer cutting simulation model to perform multiple sets of BC silicon wafer wire cutting simulations, resulting in multiple sets of BC silicon wafer wire cutting simulation results.

9. The method for improving the edge chipping of BC silicon wafers according to claim 8, characterized in that: Multiple sets of BC silicon wafer wire cutting simulation results were processed. First, simulation results with edge chipping during BC silicon wafer wire cutting were removed. Then, simulation results where the BC silicon wafer wire cutting efficiency was lower than that of BC silicon wafer wire cutting according to the basic cutting parameters were removed. Optimized simulation results were obtained, and the optimized simulation results were packaged into files. The files were labeled and coded, and each file contained the simulation cutting parameters corresponding to the optimized simulation results. Then, the simulation cutting parameters in the files were input into the wire cutting machine to obtain the actual wire cutting results. The optimized simulation results in the files were verified, and the verification results were packaged into the corresponding labeled and coded files.

10. The method for improving the edge chipping of BC silicon wafers according to claim 9, characterized in that: Step five involves analyzing the BC silicon wafer cutting process by comparing the optimized simulation results with the actual wire cutting results. First, it is determined whether the error between the optimized simulation results and the actual wire cutting results is within the allowable error range. If the error exceeds the allowable error range, the optimized simulation results are considered invalid. If the error is within the allowable error range, the optimized simulation results are considered valid. The remaining valid optimized simulation results are then compared, and the valid optimized simulation results with low mechanical energy consumption and low material consumption are selected as the final optimized BC silicon wafer wire cutting processing parameters output.

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