Wafer reliability control method

Abstract

The invention relates to the technical field of chips, and provides a wafer reliability control method which comprises the following steps: making a test plan, and determining items, parameters and test conditions required to be tested for wafer reliability control; obtaining a target chip with the same manufacturing process as the wafer and a hierarchical structure of the target chip; determining a test target structure of each item and a level where the test target structure is located; removing the target chip layer by layer to obtain a target layer of the target chip, and positioning a target structure, needing to be tested, of the target layer and a target position of the target structure on the target layer; according to the determined target position, setting a test condition, and collecting characteristic parameters of the target structure by using a nanoprobe imaging analysis system; and obtaining a reliability control performance index of the target chip according to the characteristic parameters of the target structure, and establishing a reliability control scheme of the new wafer manufacturing process according to the reliability performance index of the target chip. According to the method provided by the invention, a wafer reliability control scheme of a new manufacturing process can be quickly established.

Description

Technical Field

[0001] This invention relates to the field of chip processing technology, and in particular to a wafer reliability control method. Background Technology

[0002] For wafer foundries, developing new process technologies requires establishing reliability control schemes for the wafer fab specifically for these new technologies. Traditionally, establishing a wafer reliability control scheme involves finalizing the new process technology and designing basic components such as the Testkey (test structure / unit device), TQV (Technology Qualification Vehicle), and PQV (Product Qualification Vehicle). After the wafers are fabricated and run, wafer-level reliability testing is performed using testing equipment to obtain the parameters for reliability test items. Based on the test results, a reliability control scheme is developed, and through repeated measurements and adjustments on numerous batches of wafers, a final reliability control scheme for the new process technology is formed.

[0003] The aforementioned methods require waiting for wafer testing equipment specific to the new process technology and for tape-out tests to be available before they can be finalized. Furthermore, multiple adjustments are needed to ultimately develop a comprehensive reliability control scheme. This entire process is time-consuming and costly, potentially impacting the production deployment of the new process technology. On the other hand, during the development of a reliability control scheme for a new process technology, oversights may occur, leading to the omission of measurements for certain critical items or incorrect measurement data. This necessitates redesigning the testing equipment, resulting in high costs, long lead times, and further impacting the production deployment of the new process. Summary of the Invention

[0004] Based on the problems existing in the prior art, this application provides a wafer reliability control method, which can help wafer foundries to quickly formulate control schemes for new process technologies during the development of new processes, and accelerate the production of new process technologies as soon as possible; at the same time, it provides a fast and low-cost solution for supplementing tests on certain important data during the formulation of new process technologies.

[0005] This application also provides a wafer reliability control method, including the following steps: S110. Develop a test plan, determine the items that need to be tested for wafer reliability control, and the parameters and test conditions that need to be obtained for each item. S120. Obtain a target chip manufactured using the same process as the wafer, and obtain the hierarchical structure of the target chip; and determine the test target structure for each item and the hierarchy in which the test target structure is located based on the items that need to be tested for reliability control. S130. Starting from one side, the target chip is removed layer by layer to obtain each target layer of the target chip. For each target layer obtained, the target structure to be tested in the target layer is located, as well as the target position of the target structure on the target layer. S140. For each target layer, set test conditions according to the determined target location, and use a nanoprobe imaging analysis system to collect characteristic parameters of the target structure. S150. Based on the characteristic parameters of the target structure, obtain the reliability control performance index of the target chip, and based on the reliability performance index of the target chip, establish a reliability control scheme for the new wafer fabrication process.

[0006] The wafer reliability control method provided in this application addresses the issue that traditional wafer process reliability testing parameters are primarily obtained through testing machines. These machines require specially designed test keys and test pads on the wafer. Probes on a chuck are then used to test nanoscale devices on the test key. The probes on the test chuck are typically larger than 1µm; therefore, the testing machine can only test the wafer and obtain reliability parameters through specially designed test pads (usually larger than 20µm*20µm). It cannot test individual chips to obtain reliability parameters. For domestic wafer foundries that are catching up, developing more advanced wafer processes often involves processes that are already mature for leading international foundries. Due to the confidentiality management of these leading wafer foundries, domestic manufacturers in the catch-up stage cannot directly obtain their advanced process technologies, nor can they obtain complete wafers or samples with complete wafer-level process reliability test structures to directly test the wafers and obtain their advanced process reliability parameters. When wafer foundries in the catch-up stage need to develop new wafer processes, completely redesigning the reliability control scheme for the new process wafers is time-consuming and costly. The wafer reliability control method provided in this application adopts a nanoprobe imaging system. Current nanoprobes can support device-level testing of 3nm and even more advanced process chips. When wafer foundries in the catch-up stage develop new wafer processes, they can legally obtain chips of the same process from other wafer foundries (e.g., through market purchase). After delamination, the target structure / device is exposed, and the nanoprobe can be used to test the electrical / electrical parameters of the target chip's nanostructure / device. This allows for the rapid acquisition of reliability performance parameters of mature wafers of the same process and provides guidance for developing reliability control schemes for new wafer process technologies. Meanwhile, in the process of developing new processes, if there are omissions in the plan or errors in the test data of certain test items, it may be impossible to collect these important parameters according to the existing Testkey design. Redesigning would be time-consuming. Alternatively, the wafer reliability control method provided in the embodiments of this application can be used to determine the items to be tested and the corresponding parameters, remove layers from a single chip, find the target structure that can be tested, and use a nanoprobe detection system to obtain the test results quickly and at low cost.

[0007] Based on the same inventive purpose, this application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer-executable program, and the processor calls the computer-executable program in the memory to implement the above-described wafer reliability control method.

[0008] Based on the same inventive purpose, this application also provides a storage medium, which is a computer-readable storage medium, and stores a computer-executable program thereon. When the computer-executable program is executed by a processor, it implements the above-described wafer reliability control method.

[0009] Based on the same inventive purpose, this application also provides a program product, which includes a computer-executable program. When the computer-executable program is run, it executes the wafer reliability control method described above. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic flowchart illustrating a new wafer process SPICE determination method provided in this application embodiment; Figure 2 A schematic diagram of the acquired packaged device; Figure 3 This is a schematic diagram of the target chip, which can be obtained by removing the package from the packaging device. Figures 4A to 4C This is a schematic diagram of the target chip's hierarchical structure obtained through SEM / FIB / TEM; Figures 5A to 5C A schematic diagram illustrating the process of removing the target chip layer by layer to obtain the target structure and determine the target location; Figures 6A to 6C A schematic diagram for circuit modification using FIB; Figure 7 This is a schematic diagram of measuring the target structure using a nanoprobe imaging system. Detailed Implementation

[0012] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0013] It is important to note that terms such as "first," "second," "symmetric," and "array" are used only to distinguish between descriptive and positional descriptions and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features specified with terms such as "first" or "symmetric" may explicitly or implicitly include one or more of that feature; similarly, when the quantity of certain features is not limited by words such as "two" or "three," it should be noted that such features also explicitly or implicitly include one or more features. In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," and "fixation" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral molding; they can refer to a mechanical connection, a direct connection, a welding connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the accompanying drawings and specific circumstances.

[0014] In recent years, as countries with advanced semiconductor technology have intensified their suppression of our semiconductor technology, particularly through strict restrictions on advanced chip foundry technology and chip processing equipment, our semiconductor industry has faced unprecedented pressure. For domestic wafer foundries, developing wafer processing technology that catches up with the world's advanced processes as soon as possible is crucial for breaking through the blockade on my country's wafer industry.

[0015] Therefore, for domestic wafer foundries, on the one hand, they need to develop advanced wafer processing technologies that can catch up with leading wafer foundries, and on the other hand, they need to establish wafer quality control and wafer reliability control schemes that can guarantee the wafer foundry process of the new process.

[0016] Traditional wafer reliability control schemes are developed after the new wafer fabrication process is finalized, and basic components such as testkeys (test structures / units), TQVs (Technology Qualification Vehicles), and PQVs (Product Qualification Vehicles) are already designed. After the wafers are fabricated and run, wafer-level reliability testing is performed using test equipment to obtain parameters for reliability test items. Based on the obtained test results, a reliability control scheme is formulated. This process involves running numerous batches of wafers, repeatedly measuring and adjusting to optimize the results, ultimately forming a reliability control scheme specifically for the new process. This method is time-consuming and costly, which may affect the production deployment of the new process.

[0017] As domestic wafer foundries are currently in a catch-up phase, their reliability control solutions for new process technologies are already mature and reliable compared to those of leading foundries. Leveraging these mature reliability control solutions, or obtaining complete wafers or samples with complete wafer-level process reliability testing structures, could significantly accelerate the R&D of related technologies for foundry followers, save R&D costs, and speed up the production of new wafer processes, possessing significant technical and engineering value. However, these advanced wafer process technologies, process information, and wafers or samples with complete wafer-level process reliability testing structures are the most important intangible assets of wafer foundries, protected by the highest level of confidentiality measures and cannot be obtained through legal means.

[0018] The inventors of this application provide a wafer reliability control method for new wafer manufacturing processes. This method attempts to legally draw on the reliability solutions of leading wafer foundries, thereby accelerating the development of reliability control solutions for new manufacturing processes and speeding up the research, development, and mass production of new wafer foundry processes.

[0019] On the other hand, since there may be oversights in the development of reliability solutions for new wafer foundry processes, one or more important items may not be measured, or the measured data may be incorrect. The wafer reliability control solution provided in this application offers a flexible and low-cost supplementary measurement solution for reliability data.

[0020] This application provides a wafer reliability control method that can legally obtain reliability test parameters for wafers manufactured using the same process technology, analyze the process reliability capability of a target chip manufactured using the same process technology, and thus formulate a reliability control scheme for a new wafer manufacturing process. Furthermore, it eliminates the need to design a dedicated testing machine.

[0021] The technical solution of this application will now be described in detail with reference to the accompanying drawings.

[0022] like Figure 1 As shown in the embodiments of this application, the wafer reliability control method includes the following steps: S110. Develop a test plan, determine the items that need to be tested for wafer reliability control, and the parameters and test conditions that need to be obtained for each item.

[0023] In step S110, a test plan is formulated, determining the items required for reliability testing of the new wafer fabrication process, as well as the characteristic parameters and test conditions required for each item. When developing a reliability solution for a new wafer foundry process, if oversights lead to the omission of measurements for one or more important items, or errors in the measured data, the test plan mainly includes the important items that need to be retested or the items with incorrect data. The wafer reliability control method provided in this application is particularly suitable for wafer-level process reliability testing. Wafer-level process reliability test items mainly include: hot carrier effect testing (HCI), gate oxide layer effect testing (GOI TDDB / Vramp), stress migration testing (SM), and width electromigration (EM), etc. In this embodiment, the Wmin width electromigration of the Metal-2 layer is used as an example. The wafer-level EM test method adopts the ISO-EM test method, and the test conditions include the stress temperature T and the stress current density J.

[0024] S120. Obtain a target chip manufactured using the same process as the wafer, and obtain the hierarchical structure of the target chip; and determine the test target structure for each item and the hierarchy in which the test target structure is located based on the items that need to be tested for reliability control.

[0025] In this step, there are two different ways to obtain target chips with the same process as the new wafer fabrication technology for two different purposes.

[0026] In the process of developing new processes, if oversights lead to the omission of measurements for one or more important items, or if measurement data is incorrect, then since the target chip is a chip diced from the wafer using the same process, it can be directly used as the target chip for testing. This avoids using pre-packaged chips, eliminating the need for depackaging and improving testing efficiency.

[0027] During the development of new wafer fabrication processes, it is necessary to obtain chip reliability test parameters from leading wafer foundries using mature processes. Since wafers and chips cannot be directly obtained, it is legal to acquire packaged devices using the same process technology through market purchases. Figure 2 As shown, the target chip is obtained by removing the package, as shown. Figure 3 As shown. There are various mature methods for removing the packaging of packaged devices, and those skilled in the art can select the appropriate removal method based on the material and structure of the packaged device.

[0028] After obtaining the target chip, its hierarchical structure can be understood through SEM / FIB / TEM analysis. For example... Figures 4A to 4CAs shown, analysis using SEM / FIB / TEM can reveal the number of metal lines / dielectric layers / gate layers in a chip, the thickness of each layer, the gate structure, and its main feature dimensions. Iso-EM typically only evaluates structures with different processes and design rules. For example, if TEM / EDX analysis reveals that the manufacturing processes for Metal-5, Metal-6, and Metal-7 are the same, then only the minimum linewidth of Metal-5 or the structure that must withstand the maximum current density during operation needs to be evaluated. Iso-EM requires selecting structures with a diameter of at least 400µm for testing to accurately reflect the performance of the EM. SEM / FIB / TEM are all commonly used detection and analysis tools in chip failure analysis, offering extremely high resolution and the ability to scan the structure of each layer of the chip.

[0029] In a preferred embodiment of this application, at least two target chips manufactured using the same process are obtained. When the target chip is a pre-packaged chip, at least two packaged devices manufactured using the same process are obtained. One of these is selected as the first target packaged device, and the package of the first target packaged device is removed to obtain the first target chip of the first target packaged device. The hierarchical structure of the first target chip is obtained. The hierarchy of each item is determined according to the items that need to be tested for wafer reliability control.

[0030] S130. Starting from one side, the target chip is removed layer by layer to obtain each target layer of the target chip. For each target layer obtained, the target structure of the item to be tested in the target layer is located, as well as the target position of the target structure on the target layer.

[0031] In the preferred embodiment provided in this application, the target chip can be removed layer by layer by mechanical polishing or laser cutting. Mechanical polishing is preferred in this application because it allows for better control and precise layer removal, and provides a more complete and clear view of the circuit structure of each layer.

[0032] For packaged devices, the packaging needs to be removed first to obtain the target chip. Then, the target chip is removed layer by layer through mechanical polishing or laser cutting. For removing the packaging, methods such as dry etching to precisely remove the upper passivation layer and dielectric layer can be used, followed by mechanical polishing to remove each layer. The first target chip obtained in step S120 is removed layer by layer starting from one side, sequentially obtaining each target layer of the first target chip. For each target layer obtained, the target structure of the items to be tested on that target layer is located, as well as the target position of the target structure on that target layer. This step is mainly to clarify the situation of the target chip, determine its structure, and identify the layer and position of the items to be tested, so as to further refine the specific testing sequence.

[0033] This application uses the evaluation of the Rs of Metal-2's Iso-EM as an example in its embodiments. Figure 5A , 5B As shown in Figure 5C, the target chip needs to be stripped down to Metal-2 to find the location of the Metal-2 layer with the smallest width. The linewidth selection for metal lines on the chip is generally based on design rules, with a minimum width, followed by X times that width (Wmin), such as 2X Wmin or 4X Wmin. Locate the feature structure to be measured in the Metal-2 layer. According to ISO-EM testing requirements, the straight-line length of the structure to be tested must be no less than 400µm. Furthermore, for each condition, at least 15 samples (target structures) need to be found, so at least 15 structures of the same type need to be found. When there are not enough suitable structures on a single chip, multiple different chips or packaged devices of the same process are needed to find suitable target structures.

[0034] Then, the width W and thickness H of Metal-2 on the target structure are measured. The width and thickness of the target structure can be measured by cutting a sample from SEM, FIB, or TEM, for later calculation of the current density of ISO-EM stress. Typically, the thickness of each metal line layer is the same on the same chip. Therefore, if the thickness H of the target structure has already been obtained in step S120, then only the width W of the ISO-EM target structure needs to be measured, which can be directly obtained using the Nanoprobe imaging analysis system.

[0035] S140. For each target layer, set test conditions according to the determined target location, and use a nanoprobe imaging analysis system to collect characteristic parameters of the target structure.

[0036] In the embodiments provided in this application, based on step S130, after obtaining each target layer, locating the target structure of the project to be tested in the target layer, and the target position of the target structure on the target layer, the nanoprobe imaging analysis system can be used immediately to perform testing and obtain the characteristic parameters of the target structure.

[0037] However, the above method requires simultaneously locating and determining the target structure and its location while performing measurements, which is chaotic and time-consuming. Furthermore, due to blind spots in understanding the specific structure of the target chip, the delamination process can damage certain structures, rendering them unmeasurable or inaccurate. Therefore, in a preferred embodiment provided in this application, in step S130, a first target chip is used to clarify the specific situation of the target chip, determine its structure, identify the layers and locations of the items to be tested, determine the specific testing sequence, and optimize the delamination process. Then, a second target chip is obtained, which can be obtained by removing the encapsulation layer from a second packaging device. The second target chip is removed layer by layer. For each target layer obtained, a nanoprobe imaging analysis system is used to test the target structure and its target location as determined in step S130, collecting the characteristic parameters of the target structure.

[0038] In a further preferred embodiment provided in this application, after obtaining the specific target structure in the target chip through delayering and determining the target location of the target structure, starting from the target location, FIB is used to repair the circuit of the target structure, so that the target structure is isolated from the target location.

[0039] With Metal-2 layer W min Taking the ISO-EM test evaluation of the structure as an example, the metal wires are usually shorted through Via / Contact in other layers below Metal-2, such as... Figures 6A to 6C As shown in the diagram. This application modifies the circuit to cut off the metal lines of Metal-2 at the target location, ensuring the isolation of the Metal-2 test structure and preventing the test results from being affected by other hierarchical structures.

[0040] Step S140 specifically includes selecting a metal wire with a length not less than a preset length for each target layer, and testing it according to the following steps: S141: Obtain the width W and length L of the metal wire; S142: Set the temperature, and under the set temperature conditions, adjust the current density and measure to obtain data sets of different current densities under the same temperature conditions; S143: Set the current density, and under the set current density condition, adjust the temperature and measure to obtain a set of temperature data under the same current density condition; In step S150, the isothermal electromigration reliability of the target chip is obtained based on the obtained data sets of different current densities under the same temperature conditions and different temperatures under the same current density conditions, and a reliability control scheme for the new wafer fabrication process is established based on the isothermal electromigration reliability of the target chip. In this embodiment of the application, the de-layered target chip is placed into the Nanoprobe imaging analysis system to locate the target structure and perform ISO-EM testing using a spot needle: For the same test item and under the same test conditions, data from at least one (usually n≥15) sample needs to be tested to calculate the lifetime.

[0041] The test conditions for samples in the same batch are identical, including width W, length L, stress temperature T, and stress current density J. For example, in this case, the structural length L = 500 μm is selected. Therefore, a segment between the two cut-off points needs to be selected, and the spacing between the two pins L = 500 μm, as shown below. Figure 7 As shown.

[0042] According to the test plan, set the Stress temperature T. T is generally ≤400°C, and the sample can be heated to the set temperature using the high-temperature sample holder configured in the Nanoprobe.

[0043] According to the test plan, set the stress current I. The current density J = I / (H*W). Set the stress parameters using the source meter and test cell. The current I is injected into the test structure through the pins at both ends.

[0044] ISO-EM testing typically requires three sets of temperature conditions to calculate the temperature acceleration factor and three sets of current density conditions to calculate the current density acceleration factor. Therefore, a complete test usually requires five sets of test conditions (T1 / J2, T2 / J2, T3 / J2, T2 / J1, T2 / J3).

[0045] S150. Based on the characteristic parameters of the target structure, obtain the reliability control performance index of the target chip, and based on the reliability performance index of the target chip, establish a reliability control scheme for the new wafer fabrication process.

[0046] Once the characteristic parameters of the target structure are obtained through testing, ISO-EM testing is completed according to the general ISO-EM testing method and the established test plan. Then, based on the general Lifetime calculation method and formula, the EM lifetime of Metal-2 is calculated, and the process reliability capabilities of competing wafer fabs are analyzed and evaluated.

[0047] The Black equation is a classic model for evaluating electromigration, and the mean time to failure is expressed as: TTF = Ao * (J – Jcrit)–n * exp(Eaa / kT); Where Ao is the linewidth constant, and the physical quantities included in Ao are the metal resistivity, the mean free time of electrons between two collisions, and the effective electron scattering cross section; n is the current density exponent, which is generally taken as 1 to 3; J is the current density; Jcrit is the current density in the specific structure being tested where no electromigration occurs; Eaa is the activation energy; k = Boltzmann constant; and T is the Kelvin temperature.

[0048] Nanoprobe's imaging system comes in two types: SEM (Scanning Electron Microscopy) and AFM (Atomic Force Microscopy). Both can measure dimensions, so they can be used to find feature structures and locate their coordinates. Furthermore, using an optical microscope (OM) in conjunction with SEM in Nanoprobe's imaging system would be even more convenient.

[0049] The testing methods of Nanoprobe differ from those of testing machines, but the testing principles are the same. For example, when testing the resistance (Rs) of a Metal-2, the testing machine requires designing the Testkey, which pre-defines the length and width of the Metal-2 within the test structure. Based on the resistance (R) obtained by placing the probes on the pads, and then calculating Rs using the length and width, the resistance can be determined. However, with Nanoprobe, its two probes can be placed at any two points along a Metal-2 segment. Because it allows for convenient dimensional measurement, the distance between the two probes is measured using SEM / AFM as the length of the feature structure, and the width is measured as the width. Therefore, Rs is calculated based on the measured resistance (R) and the previously measured length and width. When testing the threshold voltage of a MOSFET, the testing machine defines the pads corresponding to each electrode (gate, source, drain, and base) during Testkey design. For Nanoprobe, it only requires locating the contacts corresponding to each electrode and placing the probes. Then, the test is performed according to the general threshold voltage testing conditions.

[0050] The wafer reliability control method provided in this application, leveraging the flexibility of a nanoprobe imaging system, can obtain the reliability control performance indicators of a target chip by testing a single target chip or a single target chip obtained from a single packaged device. This provides a method for rapidly obtaining reliability performance parameters of mature processes within the same manufacturing process. This can serve as a reference for developing reliability control schemes for wafer fabrication processes within the same manufacturing process, accelerating the rapid development of reliability control schemes for new processes and speeding up the time to mass production. On the one hand, it accelerates the pace of catching up with advanced process technologies; on the other hand, it reduces the cost of developing new processes, demonstrating significant engineering value. Furthermore, for wafer reliability testing of new process technologies where one or more important items are not measured, or where the measured data is incorrect, the wafer reliability control scheme provided in this application offers a flexible and low-cost method for supplementing reliability data measurement.

[0051] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in the present invention, and these should all be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A wafer reliability control method, characterized in that: Includes the following steps: S110. Develop a test plan, determine the items that need to be tested for wafer reliability control, and the parameters and test conditions that need to be obtained for each item. S120. Obtain a target chip manufactured using the same process as the wafer, and obtain the hierarchical structure of the target chip; and determine the test target structure for each item and the hierarchy in which the test target structure is located based on the items that need to be tested for reliability control. S130. Starting from one side, the target chip is removed layer by layer to obtain each target layer of the target chip. For each target layer obtained, the target structure to be tested in the target layer is located, as well as the target position of the target structure on the target layer. S140. For each target layer, set test conditions according to the determined target location, and use a nanoprobe imaging analysis system to collect characteristic parameters of the target structure. S150. Based on the characteristic parameters of the target structure, obtain the reliability control performance index of the target chip, and based on the reliability performance index of the target chip, establish a reliability control scheme for the new wafer fabrication process.

2. The method as described in claim 1, characterized in that, In step S120, obtaining a target chip with the same process as the new wafer process specifically involves obtaining a target packaged device with the same process as the new wafer process, and removing the package of the target packaged device to obtain the target chip of the target packaged device.

3. The method as described in claim 2, characterized in that, In step 120, at least two target packaged devices are obtained, one of which is selected as the first target packaged device. The package of the first target packaged device is removed to obtain the first target chip of the first target packaged device. The hierarchical structure of the first target chip is obtained. And according to the items that need to be tested for reliability control, the level of each item is determined. Step 130 includes removing the first target chip layer by layer from one side to obtain each target layer of the first target chip in sequence. For each target layer obtained, the target structure of the item to be tested in the target layer is located, as well as the target position of the target structure on the target layer. Step 140 includes selecting a second target packaging device as the second target packaging device, removing the packaging of the second target packaging device to obtain a second target chip, removing the second target chip layer by layer, and for each target layer obtained, using a nanoprobe imaging analysis system to test according to the target structure determined in step S130 and the target position of the target structure, and collecting the characteristic parameters of the target structure. Step S150 includes obtaining the reliability control performance index of the target chip based on the characteristic parameters of the target structure of the second target chip, and establishing a reliability control scheme for the new wafer fabrication process based on the reliability performance index of the target chip.

4. The method according to any one of claims 1 to 3, characterized in that, After obtaining each target layer and determining the target structure and target location of the target structure, the process further includes the step of: using FIB to repair the circuit of the target structure, starting from the target location, so that the target structure is isolated from the target location.

5. The method as described in claim 4, characterized in that, In step S110, the reliability test item is the isothermal electromigration effect test, and the test conditions are temperature conditions and current density conditions. Step S140 specifically includes selecting a metal wire with a length not less than a preset length for each target layer, and testing it according to the following steps: S141: Obtain the width W and length L of the metal wire; S142: Set the temperature, and under the set temperature conditions, adjust the current density and measure to obtain data sets of different current densities under the same temperature conditions; S143: Set the current density, and under the set current density condition, adjust the temperature and measure to obtain a set of temperature data under the same current density condition; In step S150, the reliability of the isothermal electromigration effect of the target chip is obtained based on the obtained data sets of different current densities under the same temperature conditions and different temperatures under the same current density conditions, and a reliability control scheme for the new wafer fabrication process is established based on the reliability of the isothermal electromigration effect of the target chip.

6. The method as described in claim 5, characterized in that, In step S142, at least three sets of data groups with different current densities under the same temperature conditions are obtained; in step S143, at least three sets of data groups with different temperatures under the same current density conditions are obtained.

7. The method as described in claim 6, characterized in that, In step S120, the hierarchical structure of the target chip is obtained by SEM, FIB or TEM.

8. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer-executable program, and the processor invokes the computer-executable program in the memory to implement the wafer reliability control method as described in any one of claims 1 to 7.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, on which a computer-executable program is stored, and when the computer-executable program is executed by a processor, it implements the wafer reliability control method as described in any one of claims 1 to 7.

10. A program product comprising a computer-executable program, which, when run, performs the wafer reliability control method as described in any one of claims 1 to 7.

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