High-voltage-resistant secondary voltage stabilizer

Abstract

This invention relates to the field of voltage regulators, specifically to a high-voltage secondary voltage regulator, comprising a self-starting module, a bias module, and an error detection module. The error detection module includes an opening adjustment component, a regulating MOSFET P3, and an error amplification unit. Initially, the output VCC is 0V upon power-up. The self-starting module controls the bias module to start working, and the bias module outputs a static bias voltage and bias current to the error detection module. The error amplification unit samples VCC, converting voltage fluctuations into current changes that are transmitted to the regulating MOSFET P3. The drain potential of the regulating MOSFET P3 is adjusted in real time, and the amplified error signal is output from the drain of the regulating MOSFET P3 to the control terminal of the opening adjustment component. This adjusts the conduction level of the opening adjustment component, thereby controlling the magnitude of the current flowing from the high-voltage power supply VIN to VCC, achieving stable output of VCC under a wide range of high-voltage power supply VIN direct input.

Description

Technical Field

[0001] This invention relates to the field of voltage regulators, and more specifically to a high-voltage resistant secondary voltage regulator. Background Technology

[0002] A voltage regulator is a power device that automatically adjusts its output voltage to maintain stability. Its core function is to ensure the output voltage remains near a preset value through dynamic adjustments of internal circuitry when the input voltage fluctuates or the load changes, thus providing a continuous and stable power environment for electrical equipment. A secondary voltage regulator, located on the secondary side (output side) of the power supply architecture, is a voltage regulator whose core function is to ensure a stable power supply to electrical equipment even when the input voltage fluctuates or the load changes, by dynamically adjusting the output voltage. It is typically used in conjunction with a primary power converter. For example, in a switching power supply, the primary converter first converts the input voltage to an intermediate voltage, and then the secondary regulator further adjusts this intermediate voltage to the precise voltage value required by the equipment. This design improves power conversion efficiency and meets the low-voltage, high-precision power supply requirements of modern electronic equipment.

[0003] Existing high-voltage secondary regulators mostly employ "independent pre-regulator modules" to isolate the high-voltage and low-voltage domains. This leads to increased circuit losses and a larger layout area. Some solutions use high-voltage resistor voltage divider clamping bias, resulting in high static power consumption, strong noise coupling, and poor low-voltage start-up capability. Regarding error amplification and compensation, conventional solutions use standard CMOS operational amplifiers with Miller compensation to achieve error amplification and loop stability, but these suffer from limited bandwidth and slow transient response. Summary of the Invention

[0004] The purpose of this invention is to provide a high-voltage resistant secondary voltage regulator, which aims to improve the problems of existing secondary voltage regulators, such as large circuit losses and layout area, poor low-voltage start-up capability, limited bandwidth, and slow transient response.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A high-voltage resistant secondary voltage regulator includes a self-starting module, a bias module, and an error detection module. The error detection module includes an opening adjustment component, a control MOSFET P3, and an error amplification unit.

[0007] The high-voltage power supply VIN is input to the input terminals of the self-starting module, the bias module, and the opening adjustment component; the output terminal of the self-starting module is electrically connected to the input terminal of the bias module, the output terminal of the opening adjustment component is electrically connected to the input terminal of the error amplification unit and the source of the control MOS transistor P3, and outputs VCC; the output terminal of the error amplification unit is electrically connected to the gate of the control MOS transistor P3, and the drain of the control MOS transistor P3 and the output terminal of the bias module are both electrically connected to the control terminal of the opening adjustment component.

[0008] Furthermore, the error amplification unit includes transistors Q0 and Q1, MOSFETs P4 and P5, resistors R5, R6, R7, R8, R9, and R10, and capacitors C4 and C5.

[0009] The output terminal of the opening adjustment component is electrically connected to one end of resistor R5, one end of resistor R7, and one end of resistor R8. The other end of resistor R5 is electrically connected to one end of resistor R6, the base of transistor Q0, and the base of transistor Q1. The other end of resistor R7 is electrically connected to the source of MOSFET P4, and the other end of resistor R8 is electrically connected to the source of MOSFET P5. The gate and drain of MOSFET P4 are both electrically connected to the collector of transistor Q0 and the gate of MOSFET P5. The drain of MOSFET P5 is electrically connected to the collector of transistor Q1 and one end of capacitor C5, and serves as the output terminal, electrically connected to the gate of regulating MOSFET P3. The emitter of transistor Q0 is electrically connected to one end of resistor R9, and the emitter of transistor Q1 is electrically connected to the other end of resistor R9 and one end of resistor R10.

[0010] The other ends of resistor R6, resistor R10, capacitor C4, and capacitor C5 are all grounded.

[0011] Furthermore, the bias module includes MOSFETs P0, P1, P2, N1, N2, N3, HP1, HN2 and R2;

[0012] The high-voltage power supply VIN is input to the source of MOSFET P0, the source of MOSFET P1, and the source of MOSFET P2;

[0013] The output terminal of the self-starting module is electrically connected to one end of resistor R2 and the gate of MOSFET HP1. The other end of resistor R3 is electrically connected to the drain and gate of MOSFET P0, the gate of MOSFET P1, and the gate of MOSFET P2. The drain of MOSFET P1 is electrically connected to the source of MOSFET HP1. The drain of MOSFET HP1 is electrically connected to the gate of MOSFET HN2 and the gate and drain of MOSFET N1. The source of MOSFET N1 is electrically connected to the gate and drain of MOSFET N2 and the gate of MOSFET N3. The drain of MOSFET N3 is electrically connected to the drain of regulating MOSFET P3 and the source of MOSFET HN2. The drains of MOSFET HN2 and MOSFET P2 are electrically connected as output terminals to the control terminal of the opening adjustment component.

[0014] The sources of both MOS transistor N2 and MOS transistor N3 are grounded.

[0015] Furthermore, the self-starting module includes MOSFET HN1, MOSFET N0, resistor R0, resistor R1, and capacitors C0 and C1;

[0016] A high-voltage power supply VIN is input to one end of a resistor R0. The other end of the resistor R0 is electrically connected to the drain of MOSFET N0, one end of capacitor C0, and the gate of MOSFET HN1. The source of MOSFET HN1 is electrically connected to the gate of MOSFET N0, one end of resistor R1, and one end of capacitor C1. The drain of MOSFET HN1 serves as the output terminal and is electrically connected to the input terminal of the bias module.

[0017] The source of the MOS transistor N0, the other end of resistor R1, the other end of capacitor C0, and the other end of capacitor C1 are all grounded.

[0018] Furthermore, the opening adjustment component includes a MOS transistor HP2;

[0019] The high-voltage power supply VIN is input to the source of MOSFET HP2. The drain of the control MOSFET P3 and the output of the bias module are electrically connected to the gate of MOSFET HP2. The drain of MOSFET HP2 is electrically connected to the input of the error amplification unit and the source of the control MOSFET P3, and outputs VCC.

[0020] Furthermore, the error detection module also includes a surge suppression unit, which includes a MOSFET N4, a resistor R3, a resistor R4, and a capacitor C3.

[0021] The high-voltage power supply VIN is input to one end of resistor R4 and one end of capacitor C3. The other end of resistor R4 is electrically connected to the drain of MOSFET N4. The other end of capacitor C3 is electrically connected to the gate of MOSFET N4 and one end of resistor R3. The other end of resistor R3 and the source of MOSFET N4 are both electrically connected to the control terminal of the opening adjustment component.

[0022] Furthermore, the MOS transistor HP2 is a high-voltage PMOS transistor.

[0023] Furthermore, the following condition is satisfied:

[0024] (W / L) P4 (W / L) P5 =1:1;

[0025] Among them, (W / L) P4 and (W / L) P5 These are the width-to-length ratios of MOSFETs P4 and P5, respectively.

[0026] The resistance values ​​of resistors R7 and R8 are equal.

[0027] By adopting the above technical solution, the present invention has the following advantages compared with the prior art:

[0028] Upon initial power-up, the output VCC is 0V. The self-starting module controls the bias module to start working. The bias module outputs a static bias voltage and bias current to the error detection module. The error amplification unit samples VCC and converts the voltage fluctuations of VCC into current changes, which are transmitted to the regulating MOSFET P3. The drain potential of the regulating MOSFET P3 is adjusted in real time. The drain of the regulating MOSFET P3 outputs an amplified error signal to the control terminal of the opening adjustment component, adjusting the conduction degree of the opening adjustment component. When VCC is high, the transmission current is reduced; when VCC is low, the transmission current is increased. This controls the magnitude of the transmission current from the high-voltage power supply VIN to VCC, achieving a stable output of VCC under a wide range of high-voltage power supply VIN direct input. Attached Figure Description

[0029] Figure 1 This is a circuit diagram of the high-voltage secondary voltage regulator described in this invention;

[0030] Figure 2 This is a simulation diagram of the output voltage of VCC during the process of the input VIN of the high-voltage secondary regulator described in this invention rising from 0V to 36V.

[0031] Explanation of reference numerals in the attached figures:

[0032] 1. Self-starting module; 2. Bias module; 3. Error detection module. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0034] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0035] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0036] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0037] Please refer to Figure 1 As shown, this embodiment provides a high-voltage secondary regulator, including a self-starting module 1, a bias module 2, and an error detection module 3. The error detection module 3 includes an opening adjustment component, a regulating MOSFET P3, and an error amplification unit. The high-voltage power supply VIN is input to the input terminals of the self-starting module 1, the bias module 2, and the opening adjustment component. The output terminal of the self-starting module 1 is electrically connected to the input terminal of the bias module 2. The output terminal of the opening adjustment component is electrically connected to the input terminal of the error amplification unit and the source of the regulating MOSFET P3, and outputs VCC. The output terminal of the error amplification unit is electrically connected to the gate of the regulating MOSFET P3. The drain of the regulating MOSFET P3 and the output terminal of the bias module 2 are both electrically connected to the control terminal of the opening adjustment component.

[0038] Upon initial power-up, the output VCC is 0V. The self-starting module 1 controls the bias module 2 to start working. The bias module 2 outputs a static bias voltage and bias current to the error detection module 3. The error amplification unit samples VCC and converts the voltage fluctuation of VCC into current changes, which are transmitted to the regulating MOSFET P3. The drain potential of the regulating MOSFET P3 is adjusted in real time. The drain of the regulating MOSFET P3 outputs an amplified error signal to the control terminal of the opening adjustment component, which adjusts the conduction degree of the opening adjustment component. When VCC is high, the transmission current is reduced, and when VCC is low, the transmission current is increased. This controls the magnitude of the transmission current from the high voltage power supply VIN to VCC, thereby achieving a stable output of VCC under a wide range of high voltage power supply VIN direct input.

[0039] Specifically, the self-starting module 1 includes MOSFETs HN1 and N0, resistors R0 and R1, and capacitors C0 and C1. High-voltage power supply VIN is input to one end of resistor R0. The other end of resistor R0 is electrically connected to the drain of MOSFET N0, one end of capacitor C0, and the gate of MOSFET HN1. The source of MOSFET HN1 is electrically connected to the gate of MOSFET N0, one end of resistor R1, and one end of capacitor C1. The drain of MOSFET HN1 serves as the output terminal and is electrically connected to the input terminal of the bias module 2. The source of MOSFET N0, the other end of resistor R1, the other end of capacitor C0, and the other end of capacitor C1 are all grounded.

[0040] The bias module 2 includes MOSFETs P0, P1, P2, N1, N2, N3, HP1, and HN2, and resistor R2.

[0041] The high-voltage power supply VIN is input to the source of MOSFET P0, the source of MOSFET P1, and the source of MOSFET P2.

[0042] The output terminal of the self-starting module 1 is electrically connected to one end of resistor R2 and the gate of MOSFET HP1. Specifically, the drain of MOSFET HN1 is electrically connected to one end of resistor R2 and the gate of MOSFET HP1. The other end of resistor R3 is electrically connected to the drain and gate of MOSFET P0, the gate of MOSFET P1, and the gate of MOSFET P2. The drain of MOSFET P1 is electrically connected to the source of MOSFET HP1. The drain of MOSFET HP1 is electrically connected to the gate of MOSFET HN2 and the gate and drain of MOSFET N1. The source of MOSFET N1 is electrically connected to the gate and drain of MOSFET N2 and the gate of MOSFET N3. The drain of MOSFET N3 is electrically connected to the drain of the regulating MOSFET P3 and the source of MOSFET HN2. The drains of MOSFET HN2 and MOSFET P2 serve as output terminals and are electrically connected to the control terminal of the opening adjustment component.

[0043] The sources of MOSFET N2 and MOSFET N3 are both grounded.

[0044] In this circuit, MOSFETs HN1 and HN2 are high-voltage NMOS transistors, and MOSFET HP1 is a high-voltage PMOS transistor. During the initial power-on phase, VIN is connected to the high-voltage power supply. At this time, there is no bias current in the entire circuit, all MOSFETs and transistors are in the off state, VCC output is 0V, and the circuit is in the off state. VIN generates an initial startup current through resistor R0. When the gate-source voltage of MOSFET HN1 exceeds the overdrive voltage, it conducts, and current flows from the drain to the source of MOSFET HN1. The gate voltage of MOSFET N0 increases, and simultaneously, its drain voltage is pulled down. Eventually, the gate voltages of MOSFETs HN1 and N0 stabilize at an equilibrium point. The gate potential of MOSFET P0 is pulled low, MOSFET P0 conducts, and the circuit begins to work. As the power-on voltage continues to increase, the voltage division of resistor R1 also continuously increases. Eventually, the gate-source voltage of MOSFET HN1 decreases below the threshold, and MOSFET HN1 is turned off. After this, the circuit is completely controlled by bias module 2 and error detection module 3, and the startup circuit exits. Capacitors C0 and C1 stabilize the node voltage, filter out noise, and provide local decoupling during startup.

[0045] After startup, MOSFETs P0, P1, and P2 form a PMOS current mirror, and MOSFETs N2 and N3 form an NMOS current mirror, replicating the reference current image to error detection module 3. Resistor R2 is a current-limiting resistor. MOSFET HP1 operates in the saturation region after being turned on, transmitting VIN to the gate of MOSFET HN2, providing a stable gate voltage for HN2 and driving it to operate in the saturation region. MOSFET N1 is connected in a diode configuration to raise the gate voltage of MOSFET HN2.

[0046] Specifically, the error amplification unit includes transistors Q0 and Q1, MOSFETs P4 and P5, resistors R5, R6, R7, R8, R9, and R10, and capacitors C4 and C5.

[0047] The output terminal of the opening adjustment component is electrically connected to one end of resistor R5, one end of resistor R7, and one end of resistor R8. The other end of resistor R5 is electrically connected to one end of resistor R6, the base of transistor Q0, and the base of transistor Q1. The other end of resistor R7 is electrically connected to the source of MOSFET P4, and the other end of resistor R8 is electrically connected to the source of MOSFET P5. The gate and drain of MOSFET P4 are both electrically connected to the collector of transistor Q0 and the gate of MOSFET P5. The drain of MOSFET P5 is electrically connected to the collector of transistor Q1 and one end of capacitor C5, and serves as the output terminal, electrically connected to the gate of regulating MOSFET P3. The emitter of transistor Q0 is electrically connected to one end of resistor R9, and the emitter of transistor Q1 is electrically connected to the other end of resistor R9 and one end of resistor R10.

[0048] The other ends of resistor R6, resistor R10, capacitor C4, and capacitor C5 are all grounded.

[0049] The op-amp-free error amplification structure consists of transistors Q0 and Q1, and MOSFETs P4 and P5. The BJT differential pair is responsible for receiving the sampled voltage and converting voltage fluctuations into current changes, without the need for a reference voltage for comparison.

[0050] MOSFETs P4 and P5 form a PMOS current mirror, which, together with the control MOSFET P3, constitutes a hierarchical drive network based on the current mirror and error adjustment transistor. MOSFET P4 is connected as a diode, generating a reference current. MOSFET P5 mirrors this current and provides bias to the gate of MOSFET P3 via the error detection node. MOSFETs N2 and N3 form an NMOS current mirror. MOSFET N2 is connected as a diode, and MOSFET N3 mirrors its current and pulls it down from the drain of the control MOSFET P3. The pull-up current of MOSFET P3 and the pull-down current of MOSFET N3 are superimposed at the drain of P3, controlling the source potential of the second-stage amplifier transistor, i.e., controlling the source potential of MOSFET HN2, ensuring that the gate-source voltage difference of MOSFET HN2 allows it to operate in the saturation region.

[0051] In this embodiment, the opening adjustment component includes a MOSFET HP2. A high-voltage power supply VIN is input to the source of MOSFET HP2. The drain of the regulating MOSFET P3 and the output of the bias module 2 are both electrically connected to the gate of MOSFET HP2. Specifically, the drains of MOSFET P2 and MOSFET HN2 are both electrically connected to the gate of MOSFET HP2. The drain of MOSFET HP2 is electrically connected to the input of the error amplification unit and the source of the regulating MOSFET P3. Specifically, the drain of MOSFET HP2 is electrically connected to one end of resistor R3, one end of resistor R7, one end of resistor R8, one end of capacitor C4, and the source of the regulating MOSFET P3, and outputs VCC.

[0052] Furthermore, the error detection module 3 also includes a surge suppression unit, which comprises a MOSFET N4, resistor R3, resistor R4, and capacitor C3. The high-voltage power supply VIN is input to one end of resistor R4 and one end of capacitor C3. The other end of resistor R4 is electrically connected to the drain of MOSFET N4, and the other end of capacitor C3 is electrically connected to the gate of MOSFET N4 and one end of resistor R3. The other end of resistor R3 and the source of MOSFET N4 are both electrically connected to the control terminal of the opening adjustment component. Specifically, the other end of resistor R3 and the source of MOSFET N4 are both electrically connected to the gate of MOSFET HP2.

[0053] Among them, MOSFET HP2 is a high-voltage PMOS transistor; resistors R3 and R4, capacitor C3 and MOSFET N4 form a surge suppression structure. If the output voltage changes abruptly, since the voltage across capacitor C3 cannot change abruptly, the gate-source voltage of MOSFET N4 will follow suit, and MOSFET N4 will enter the saturation region. The current flowing through MOSFET N4 will automatically limit the maximum current due to the square law characteristic of NMOS current; capacitors C4 and C5 are both filter capacitors.

[0054] In this embodiment, the error amplification unit satisfies the following condition.

[0055] (W / L) P4 (W / L) P5 =1:1; where (W / L) P4 and (W / L) P5 These are the width-to-length ratios of MOSFETs P4 and P5, respectively; the resistance values ​​of resistors R7 and R8 are equal.

[0056] When the first-stage amplifier transistor is turned on, that is, when MOSFET HP2 is turned on, the current I flowing through resistor R9 can be determined from the circuit diagram. R9 It can be represented as:

[0057] I R9 =V BE1 -V BEO / R9=V T lnn / R9;

[0058] Among them, V BE0 and V BE1 V represents the base-emitter voltage of transistor Q0 and MOSFET Q1, respectively. ln is the logarithm of n to the base e, where n is the ratio of the number of transistors Q0 and Q1 connected in parallel. T It is thermal voltage.

[0059] V Y These are the base voltages of transistors Q0 and Q1, specifically:

[0060] ;

[0061] Because V Y The voltage is divided by the resistors of VCC, therefore VCC can be expressed as:

[0062] ;

[0063] Due to the process parameters V BE It is a negative temperature coefficient voltage, V T It is a positive temperature coefficient voltage. The magnitude of the positive temperature coefficient is adjusted by changing the ratio of resistor R10 to resistor R9, so that it cancels out the negative temperature coefficient, thus making VCC and V... Y It is a zero temperature coefficient voltage, thereby improving the stability of the output VCC.

[0064] Using VIN high voltage as input, a stable operating point is established through reference current mirroring of PMOS and NMOS current mirrors and precise biasing of high-voltage devices. After power-on startup, the self-starting module 1 automatically exits, and through the current mirror network of the bias module 2, a stable static bias voltage and bias current are established for all core functional devices in the circuit, ensuring that the MOS devices are turned on and operate in the saturation region. The error amplification unit performs voltage division sampling on the output voltage VCC, and directly inputs the sampled voltage into the op-amp-less error amplification structure composed of BJT differential pair transistors Q0 and Q1 and MOSFETs P4 and P5. No reference voltage is required for comparison. The BJT differential pair converts the voltage fluctuation of VCC into current change, and then through the hierarchical driving network composed of MOSFETs P4, P5 and the control MOSFET P3, the pull-up current of the control MOSFET P3 and the pull-down current of MOSFET N3 are superimposed at the drain of the control MOSFET P3, thereby controlling the source potential of MOSFET HN2 and completing the amplification of the error signal.

[0065] The amplified error signal is converted into a change in the drain potential of MOSFET HN2, which in turn drives a change in the gate potential of the high-voltage PMOS main power transistor HP2. This allows for real-time adjustment of the conduction level of HP2; when VCC is high, the transmission current is reduced, and when VCC is low, the transmission current is increased, thereby controlling the magnitude of the transmission current from VIN to VCC. Simultaneously, a surge suppression structure composed of resistors R3 and R4, capacitor C3, and MOSFET N4 suppresses sudden large fluctuations in VCC. Filtering capacitors C4 and C5 are used to decouple the core node, ultimately achieving a stable output of VCC under a wide range of high-voltage VIN input.

[0066] Please refer to the appendix. Figure 2 , attached Figure 2 The simulation diagram of the output voltage of VCC during the process of input VIN rising from 0V to 36V is attached. Figure 2It can be seen that during the process of the input VIN rising from 0V to 36V, once VIN stabilizes above the minimum operating voltage, VCC outputs a stable 2.67V. Therefore, the secondary regulator disclosed in this embodiment can be directly connected to a high-voltage input and can operate directly under a wide range of high-voltage VIN.

[0067] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A high-voltage resistant secondary voltage regulator, characterized in that, It includes a self-starting module, a bias module, and an error detection module. The error detection module includes an opening adjustment component, a control MOS transistor P3, and an error amplification unit. A high-voltage power supply VIN is input to the input terminals of the self-starting module, the bias module, and the opening adjustment component; the output terminal of the self-starting module is electrically connected to the input terminal of the bias module, the output terminal of the opening adjustment component is electrically connected to the input terminal of the error amplification unit and the source of the control MOS transistor P3, and outputs VCC; the output terminal of the error amplification unit is electrically connected to the gate of the control MOS transistor P3, and the drain of the control MOS transistor P3 and the output terminal of the bias module are both electrically connected to the control terminal of the opening adjustment component; The error amplification unit includes transistors Q0 and Q1, MOSFETs P4 and P5, resistors R5, R6, R7, R8, R9, and R10, and capacitors C4 and C5. The output terminal of the opening adjustment component is electrically connected to one end of resistor R5, one end of resistor R7, one end of resistor R8, and one end of capacitor C4. The other end of resistor R5 is electrically connected to one end of resistor R6, the base of transistor Q0, and the base of transistor Q1. The other end of resistor R7 is electrically connected to the source of MOSFET P4, and the other end of resistor R8 is electrically connected to the source of MOSFET P5. The gate and drain of MOSFET P4 are both electrically connected to the collector of transistor Q0 and the gate of MOSFET P5. The drain of MOSFET P5 is electrically connected to the collector of transistor Q1 and one end of capacitor C5, and serves as the output terminal to be electrically connected to the gate of regulating MOSFET P3. The emitter of transistor Q0 is electrically connected to one end of resistor R9, and the emitter of transistor Q1 is electrically connected to the other end of resistor R9 and one end of resistor R10. The other ends of resistor R6, resistor R10, capacitor C4, and capacitor C5 are all grounded.

2. The high-voltage resistant secondary voltage regulator according to claim 1, characterized in that: The bias module includes MOSFETs P0, P1, P2, N1, N2, N3, HP1, and HN2, and resistor R2. The high-voltage power supply VIN is input to the source of MOSFET P0, the source of MOSFET P1, and the source of MOSFET P2; The output terminal of the self-starting module is electrically connected to one end of resistor R2 and the gate of MOSFET HP1. The other end of resistor R2 is electrically connected to the drain and gate of MOSFET P0, the gate of MOSFET P1, and the gate of MOSFET P2. The drain of MOSFET P1 is electrically connected to the source of MOSFET HP1. The drain of MOSFET HP1 is electrically connected to the gate of MOSFET HN2 and the gate and drain of MOSFET N1. The source of MOSFET N1 is electrically connected to the gate and drain of MOSFET N2 and the gate of MOSFET N3. The drain of MOSFET N3 is electrically connected to the drain of regulating MOSFET P3 and the source of MOSFET HN2. The drains of MOSFET HN2 and MOSFET P2 are electrically connected as output terminals to the control terminal of the opening adjustment component. The sources of both MOS transistor N2 and MOS transistor N3 are grounded.

3. The high-voltage resistant secondary voltage regulator according to claim 1, characterized in that: The self-starting module includes MOSFET HN1, MOSFET N0, resistor R0, resistor R1, and capacitors C0 and C1; A high-voltage power supply VIN is input to one end of a resistor R0. The other end of the resistor R0 is electrically connected to the drain of MOSFET N0, one end of capacitor C0, and the gate of MOSFET HN1. The source of MOSFET HN1 is electrically connected to the gate of MOSFET N0, one end of resistor R1, and one end of capacitor C1. The drain of MOSFET HN1 serves as the output terminal and is electrically connected to the input terminal of the bias module. The source of the MOS transistor N0, the other end of resistor R1, the other end of capacitor C0, and the other end of capacitor C1 are all grounded.

4. The high-voltage resistant secondary voltage regulator according to claim 1, characterized in that: The opening adjustment component includes a MOS transistor HP2; The high-voltage power supply VIN is input to the source of MOSFET HP2. The drain of the control MOSFET P3 and the output of the bias module are electrically connected to the gate of MOSFET HP2. The drain of MOSFET HP2 is electrically connected to the input of the error amplification unit and the source of the control MOSFET P3, and outputs VCC.

5. The high-voltage resistant secondary voltage regulator according to claim 1, characterized in that: The error detection module also includes a surge suppression unit, which includes a MOSFET N4, a resistor R3, a resistor R4, and a capacitor C3. The high-voltage power supply VIN is input to one end of resistor R4 and one end of capacitor C3. The other end of resistor R4 is electrically connected to the drain of MOSFET N4. The other end of capacitor C3 is electrically connected to the gate of MOSFET N4 and one end of resistor R3. The other end of resistor R3 and the source of MOSFET N4 are both electrically connected to the control terminal of the opening adjustment component.

6. The high-voltage resistant secondary voltage regulator according to claim 4, characterized in that: The MOS transistor HP2 is a high-voltage PMOS transistor.

7. The high-voltage resistant secondary voltage regulator according to claim 3, characterized in that: The following conditions must be met. (W / L) P4 :(W / L) P5 =1:1; Among them, (W / L) P4 and (W / L) P5 These are the width-to-length ratios of MOSFETs P4 and P5, respectively. The resistance values ​​of resistors R7 and R8 are equal.

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