Chip failure repair evaluation method and electronic device
By acquiring multi-dimensional hardware status changes, calculating the overall progress score, and adjusting the reward, the problem of long repair time for inter-chip interconnect links was solved, achieving efficient fault repair and accurate fault location.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHONGHAO XINYING (HANGZHOU) TECH CO LTD
- Filing Date
- 2026-04-07
- Publication Date
- 2026-07-07
AI Technical Summary
In existing technologies, the methods for repairing inter-chip interconnection link failures lack the ability to perceive intermediate hardware states, resulting in excessively long repair times and numerous redundant operations, which affects repair efficiency.
By acquiring multi-dimensional hardware status values before and after the operation, calculating the changes in hardware status values in each dimension, determining the overall progress score, and adjusting the reward based on the overall progress score and the difficulty of equipment repair, the repair direction is guided.
It enables rapid and effective chip fault repair, reduces unnecessary operations, improves repair speed and efficiency, and enhances the accuracy of fault identification and location.
Smart Images
Figure CN121979730B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a chip fault repair and assessment method and an electronic device. Background Technology
[0002] With the explosive growth of the artificial intelligence industry, large-scale AI (Artificial Intelligence) computing chip clusters have become the infrastructure supporting core scenarios such as large model training and high-concurrency inference. In ultra-large-scale cluster deployment scenarios at the kilo- or 10,000-card level, the interconnecting links between chips carry the communication scheduling tasks of massive computing units within the cluster, and their stable operation is a key prerequisite for ensuring the overall performance of the cluster.
[0003] With the exponential expansion of cluster size, the failure modes of inter-chip interconnect links exhibit significant high complexity and strong dependency characteristics. An anomaly in a single link can trigger cascading failures across multiple nodes through topological correlation, and the causes of failures are a mixture of factors such as hardware aging, signal interference, and thermal stress fluctuations, which places extremely high demands on automated fault repair technologies.
[0004] In existing technologies, faults in inter-chip interconnect links are typically repaired using result-oriented reinforcement learning schemes, such as the Proximal Policy Optimization (PPO) algorithm. However, because these algorithms lack the ability to perceive intermediate hardware states, the reinforcement learning agent must locate the fault through numerous blind exploration steps, resulting in excessively long average repair times. Furthermore, without accurate hardware state perception, the agent frequently executes invalid global restart operations, leading to excessive redundancy and further extending the repair time, severely impacting repair efficiency. Summary of the Invention
[0005] This invention provides a chip fault repair and assessment method and an electronic device to solve existing problems.
[0006] In a first aspect, embodiments of the present invention provide a chip fault repair and assessment method, including:
[0007] Obtain multi-dimensional hardware status values before and after the operation, and calculate the changes in hardware status values in each dimension before and after the operation.
[0008] The overall progress score is determined based on the changes in hardware status values for each dimension.
[0009] The overall reward is determined based on the overall progress score.
[0010] The comprehensive reward is adjusted based on the difficulty of equipment repair to obtain a target reward, which is used to guide the direction of equipment repair.
[0011] In a second aspect, embodiments of the present invention provide an electronic device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the chip fault repair and evaluation method as described in the first aspect or any possible implementation of the first aspect.
[0012] This invention provides a chip fault repair assessment method and an electronic device. The chip fault repair assessment method includes: acquiring multi-dimensional hardware state values before and after an operation, and calculating the change in each dimension of the hardware state values before and after the operation; determining a comprehensive progress score based on the change in each dimension of the hardware state values; determining a comprehensive reward based on the comprehensive progress score; and adjusting the comprehensive reward according to the equipment repair difficulty to obtain a target reward, which is used to guide the equipment repair direction. This application quantifies the effect of repair operations based on the change in multi-dimensional hardware state, and dynamically adjusts the reward according to the equipment repair difficulty to generate a target reward. This allows the device to distinguish which operations truly advance the repair process, effectively guiding the repair process and improving repair speed and efficiency. Attached Figure Description
[0013] Figure 1 This is a flowchart illustrating the implementation of a chip fault repair and evaluation method provided in an embodiment of the present invention.
[0014] Figure 2 This is a schematic diagram of the chip fault repair and evaluation device provided in an embodiment of the present invention;
[0015] Figure 3 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation
[0016] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0017] See Figure 1 The diagram illustrates a flowchart of a chip fault repair and evaluation method provided by an embodiment of the present invention, which is described in detail below:
[0018] refer to Figure 1 The aforementioned chip fault repair and assessment method includes:
[0019] S101: Obtain multi-dimensional hardware state values before and after the operation, and calculate the changes in hardware state values of each dimension before and after the operation.
[0020] Multi-dimensional hardware status values are used to comprehensively reflect the operating status of chips and corresponding devices.
[0021] In one possible implementation, the multi-dimensional hardware status values include: device visibility, PCIe link status, inner loop initialization progress, inter-chip interconnect link synchronization, and error density.
[0022] Device visibility is used to characterize whether a TPU device node is visible, and the value range can be 0 to 1.
[0023] PCIe (Peripheral Component Interconnect Express) link status is used to characterize whether the PCIe link width and speed meet the standards, and the value range can be 0~1;
[0024] The inner loop initialization progress is used to characterize the proportion of the inner loop initialization (the chip's internal initialization process) that has been completed, and its value ranges from 0 to 1.
[0025] Inter-chip interconnection link synchronization is used to characterize the proportion of successful inter-chip interconnection link synchronization, and the value range can be 0~1;
[0026] Error density is used to characterize the weighted error density based on error type classification (the lower the better), and its value can range from 0 to 1.
[0027] The startup and fault repair process of AI chips follows a strict hardware topology dependency chain. Based on historical fault repair records, the following dependency chain is obtained:
[0028] Device visibility (system layer) → PCIe link status (bus layer) → Inner loop initialization progress (chip layer) → Inter-chip interconnect link synchronization (interconnect layer).
[0029] 1. Device Visibility → PCIe Link Status:
[0030] PCIe enumeration cannot be performed when the device node is not visible; for example, when the device visibility is 50%, the PCIe link status is only 30%.
[0031] 2. PCIe Link Status → Inner Loop Initialization Progress
[0032] When the PCIe link is not established, the chip registers cannot be accessed, and the inner loop initialization cannot be started; for example, the inner loop initialization gets stuck at a certain stage after the PCIe speed is reduced.
[0033] 3. Inner loop initialization progress → Inter-chip interconnection link synchronization
[0034] The inter-chip interconnection link training sequence cannot be sent when the inner loop is not fully initialized; for example, the inter-chip interconnection link synchronization rate is 0% when the inner loop is 60% complete.
[0035] Based on this, device visibility, PCIe link status, inner loop initialization progress, and inter-chip interconnection link synchronization are used as hardware status values to reflect the device's operating status.
[0036] Meanwhile, error density, reflecting the side effects of operations (such as cascading errors caused by reboots), complements the four parameters mentioned above. While the four parameters measure "how much was done correctly," error density measures "how much was done incorrectly." For example, on a challenging machine, the error density drops from 0.30 to 0.20 after a reboot, while the inner loop initialization progress degrades from 0.20 to 0.00. Therefore, although error density is not a hardware topology link, it is included as a global quality indicator.
[0037] As for chip temperature, power consumption data, memory / video memory status, firmware version, etc., chip temperature is an environmental parameter rather than a fault status indicator; abnormal temperature is a consequence of the fault rather than a cause, and has no direct causal relationship with the inter-chip interconnect link failure, so it is abandoned; power consumption changes lag behind status changes and are not critical observations in the fault repair process, so it is abandoned; the memory status of the computing chip cannot be read when the device is not initialized and depends on the inner loop initialization progress, so it is abandoned; static attributes do not change in a single repair process and cannot provide progress signals, so it is abandoned.
[0038] Therefore, the hardware status is divided into five dimensions: device visibility, PCIe link status, inner loop initialization progress, inter-chip interconnect link synchronization, and error density.
[0039] For example, the method for determining device visibility is as follows:
[0040] 1. Scan the device node directory and count the number of visible devices;
[0041] 2. Calculate the ratio of the number of visible devices to the total number of devices to obtain device visibility.
[0042] For example, if the number of visible devices is 6 and the total number of devices is 8, then the device visibility is 0.75.
[0043] The method for determining the PCIe link status is as follows:
[0044] 1. Read the PCIe status of each device;
[0045] 2. Calculate link health;
[0046] 3. Calculate the average link health of all devices to obtain the PCIe link status.
[0047] The method for determining the initialization progress of the inner loop is as follows:
[0048] 1. Determine the initialization completion phase;
[0049] 2. Calculate the inner loop initialization progress based on the initialization completion stage.
[0050] For example, if the initialization completion stage is in stage 5, and there are a total of 6 stages, then the inner loop initialization progress is (5-1) / (6-1)=0.8.
[0051] The method for determining the synchronization of inter-chip interconnection links is as follows:
[0052] 1. Extract the status of inter-chip interconnection links;
[0053] 2. Count the number of successfully synchronized links based on the status of inter-chip interconnection links;
[0054] 3. Divide the number of successfully synchronized links by the total number of links to obtain the inter-chip interconnection link synchronization.
[0055] For example, if 5 out of 8 inter-chip interconnect links are successfully synchronized, then the inter-chip interconnect link synchronization is 5 / 8 = 0.625.
[0056] The method for determining error density is as follows:
[0057] 1. Scan logs to count the number of errors;
[0058] 2. Normalize the error quantity to obtain the error density.
[0059] S102: Determine the overall progress score based on the changes in hardware status values for each dimension;
[0060] The difference between the hardware state value after the operation and the hardware state value before the operation is used as the change in hardware state value for this dimension.
[0061] A positive change in hardware status value indicates an improvement in the hardware status of that dimension; a zero change indicates no change in the hardware status of that dimension; and a negative change indicates a deterioration in the hardware status of that dimension. Based on this, a comprehensive progress score is determined according to the changes in hardware status values for each dimension.
[0062] In one possible implementation, S102 may include:
[0063] S1021: Determine the target weights for each dimension;
[0064] The target weights for each dimension are determined based on the degree of influence of the corresponding dimension on the overall operating status of the chip.
[0065] In one possible implementation, S1021 may include:
[0066] 1. Obtain the equipment's historical repair records;
[0067] The device history repair record covers all past fault repair data for this type of chip and devices in the same series, including but not limited to the fault type of each repair, multi-dimensional hardware status values before and after the operation, repair operation process, repair result (success / failure), repair time, and other information.
[0068] 2. Determine the conditional success rate for each dimension based on the equipment's historical repair records, and normalize the conditional success rate for each dimension to obtain the first weight for each dimension; whereby the conditional success rate is used to represent the probability that the hardware status value of a single dimension has improved.
[0069] For each dimension, the ratio of the number of repair cases in the historical repair records where the change in hardware status value of that dimension improved (greater than 0) to the total number of repair cases participating in the statistics for that dimension is the conditional success rate for that dimension, as shown in Table 1.
[0070] Table 1 First Weighting Table
[0071]
[0072] The first weight reflects the ease with which each dimension can achieve state improvement in historical repairs. The higher the success rate of the condition, the greater the first weight, indicating that the dimension is easier to improve through repair and should be given a higher weight to reflect its repair value.
[0073] 3. Using regression analysis, the correlation coefficients between the changes in hardware status values of each dimension and the success of repairs were determined based on the historical repair records of the equipment. The correlation coefficients of each dimension were then normalized to obtain the second weight of each dimension.
[0074] The second weight focuses on the degree of influence of each dimension on the successful repair result. The more significant the influence, the higher the second weight, ensuring that the weight allocation is strongly correlated with the core demand for successful repair. See Table 2 for details.
[0075] Table 2 Second Weighting Table
[0076]
[0077] 4. The first weight and the second weight of each dimension are combined to obtain the third weight of each dimension;
[0078] The fusion method can be either weighted summation or averaging, and the specific method can be set according to the actual application requirements. No restrictions are imposed here.
[0079] For example, the average weights in Tables 1 and 2 are 0.15, 0.25, 0.30, 0.20, and 0.10 for each dimension.
[0080] 5. Perform perturbation verification on the third weights of each dimension;
[0081] To ensure the accuracy and rationality of the weight determination, a perturbation is added to the third weight of each dimension. For example, refer to Table 3.
[0082] Table 3 Disturbance Verification Table
[0083]
[0084] As shown in Table 3, after perturbing the third weight of each dimension by 20%, the overall accuracy decreased, indicating that the third weight performed best in terms of overall accuracy, verifying the rationality of the third weight, and the verification was passed.
[0085] 6. If the verification passes, the third weight of each dimension will be used as the target weight of each dimension.
[0086] If the verification passes, the third weight for each dimension will be used as the target weight for that dimension. If the verification fails, the device's historical repair records can be updated, the above steps can be repeated, the third weight can be re-determined, and the verification can be performed again.
[0087] S1022: The overall progress score is obtained by weighting and summing the changes in hardware status values of each dimension with the target weights of each dimension.
[0088] For example, the weights of each dimension are 0.15, 0.25, 0.30, 0.20, and 0.10, respectively, and the changes in hardware status values for each dimension are 0.25, 0.30, 0.40, 0.625, and 0.20, respectively. The weighted summation yields a comprehensive progress score of 0.15×0.25+0.25×0.30+0.30×0.40+0.20×0.625+0.10×0.20=0.3775.
[0089] Furthermore, progress classification can be determined based on the overall progress score.
[0090] For example, if the overall progress score is >0.1, the progress is classified as "significant progress";
[0091] If 0 < overall progress score ≤ 0.1, the progress is classified as "minor progress";
[0092] If the overall progress score is 0, the progress is classified as "no change";
[0093] If the overall progress score is less than 0, the progress is classified as "state degradation".
[0094] For example, a comprehensive progress score of 0.3775 indicates that the progress is classified as "significant progress".
[0095] S103: Determine the overall reward based on the overall progress score;
[0096] In one possible implementation, S103 may include:
[0097] S1031: Obtain the type of repair operation and determine the operation cost based on the type of repair operation;
[0098] The correspondence between the types of repair operations and their costs can be preset, and the operation costs can be determined based on this correspondence.
[0099] For example, if the repair operation is an initialization, the operation cost is 0;
[0100] If the repair operation is to repair a loop exception, the operation cost is 0.5;
[0101] If the repair operation is a restart, the operation cost is 2.
[0102] S1032: Determine the base reward score based on the overall progress score;
[0103] In one possible implementation, S1032 may include:
[0104] 1. Determine the base reward score based on the overall progress score and the first formula;
[0105] The first formula may include:
[0106]
[0107] in, Basic reward points, The overall progress score.
[0108] S1033: Subtract the operating cost from the base reward score to obtain the comprehensive reward.
[0109] For example, based on the overall progress score of 0.3775, the base reward score is 10 × 0.3775 = 3.775; the repair operation type is initialization, and the operation cost is 0. Therefore, the overall reward is 3.775 + 0 = 3.775.
[0110] This application combines the cost of repair operations to optimize the reward calculation, making the overall reward more relevant to actual repair scenarios and balancing repair effectiveness with cost control.
[0111] S104: Adjust the overall reward based on the difficulty of equipment repair to obtain the target reward, which is used to guide the direction of equipment repair.
[0112] In one possible implementation, S104 may include:
[0113] S1041: Based on the difficulty of equipment repair, look up the table to obtain the expected progress score;
[0114] First, establish a table relating the difficulty of equipment repair to the expected progress score, and then look up the expected progress score in the table.
[0115] For example, if the equipment repair difficulty is "difficult", then the expected progress score is 0.1;
[0116] If the equipment repair difficulty is "moderate", the expected progress score is 0.2;
[0117] If the equipment repair difficulty is "easy", then the expected progress score is 0.3.
[0118] S1042: Calculate the ratio of the overall progress score to the expected progress score to obtain the relative performance of the repair;
[0119] S1043: Based on the relative performance of the repair, the reward adjustment value is obtained by looking up the table;
[0120] Establish a table relating the relative performance of repairs to the reward adjustment value, and then look up the reward adjustment value in the table.
[0121] For example, if the relative performance of the repair is >1.5, the reward adjustment value is 2, indicating that the completion exceeded expectations;
[0122] If 0.5 ≤ relative performance improvement ≤ 1.5, then the reward adjustment value is 0, indicating that it meets expectations;
[0123] If the relative performance of the repair is less than 0.5, the reward adjustment value is -1, indicating that it is lower than expected.
[0124] S1044: Sum the reward adjustment value with the total reward to obtain the target reward.
[0125] This application introduces relative performance in repair based on the difficulty of equipment repair, thereby achieving refined and standardized reward adjustments. This makes the target rewards more objectively reflect the actual work performance of repair personnel, while accurately adapting to repair scenarios of different difficulties.
[0126] In one possible implementation, the above method may further include:
[0127] S105: Obtain historical repair records of the equipment;
[0128] S106: Based on statistical analysis, determine the difficulty of equipment repair according to the equipment's historical repair records.
[0129] The statistical analysis method can be used to quantify each indicator in the historical repair record, assign corresponding statistical weights according to the degree of influence of each indicator on the repair difficulty, and then perform a weighted summation of each indicator to obtain the quantitative score of repair difficulty. Finally, the equipment repair difficulty can be obtained by looking up the table.
[0130] Statistical features can also be extracted from historical repair records, and the difficulty of equipment repair can be determined based on these statistical features.
[0131] In one possible implementation, the above method may further include:
[0132] S107: When three consecutive repair failures are detected, the target reward corresponding to multiple repairs continues to decrease, or the comprehensive progress score is not greater than 0, the equipment historical repair record is updated, and a step based on statistical analysis is executed to determine the equipment repair difficulty according to the equipment historical repair record.
[0133] This application quantifies the effectiveness of repair operations based on changes in multidimensional hardware states and dynamically adjusts rewards according to the difficulty of device repair to generate target rewards. This allows the device to distinguish which operations truly advance the repair process, effectively guiding the repair process. Feedback can be obtained after each operation without waiting for the final result, accelerating agent learning and improving repair speed and efficiency.
[0134] The above method will be described in detail below with reference to specific embodiments.
[0135] 1. A machine in the AI chip cluster experienced an initialization fault in the inner loop of the computing chip, which requires automatic repair.
[0136] 1. The multi-dimensional hardware status values before operation are [0.75, 0.50, 0.00, 0.00, 0.40];
[0137] 2. Perform initialization operations;
[0138] 3. After the operation, the multi-dimensional hardware status values are [1.00, 0.80, 0.60, 0.00, 0.70];
[0139] 4. The changes in hardware status values for each dimension are [+0.25, +0.30, +0.60, 0.00, +0.30];
[0140] 5. Overall progress score:
[0141] 0.15×0.25+0.25×0.30+0.30×0.60+0.20×0+0.10×0.30
[0142] =0.0375+0.075+0.18+0+0.03
[0143] =0.3225 (Significant progress)
[0144] 6. The total reward is 10 × 0.3225 + 0 = +3.225, the reward adjustment value is 0, the target reward is +3.225, which is a positive reward, and further improvements are possible;
[0145] 7. The multi-dimensional hardware status values before operation are [1.00, 0.80, 0.60, 0.00, 0.70];
[0146] 8. Perform a repair loop exception operation;
[0147] 9. After the operation, the multi-dimensional hardware status values are [1.00, 1.00, 1.00, 0.875, 0.90];
[0148] 10. The changes in hardware status values for each dimension are [0.00, +0.20, +0.40, +0.875, +0.20];
[0149] 11. The overall progress score is 0.365;
[0150] 12. The total reward is 10 × 0.365 - 0.5 = +3.15, the reward adjustment value is 0, the target reward is +3.225, a positive reward, and the repair is successful.
[0151] II. A certain machine has complex hardware characteristics, and multiple attempts to repair it have failed; the difficulty level of the equipment repair is rated as "Difficult".
[0152] 1. The multi-dimensional hardware status values before operation are [0.50, 0.30, 0.00, 0.00, 0.20];
[0153] 2. Perform initialization operations;
[0154] 3. After the operation, the multi-dimensional hardware status values are [0.50, 0.30, 0.00, 0.00, 0.20];
[0155] 4. The overall progress score is 0.0987 (slight progress);
[0156] 5. The target reward is 0.49;
[0157] 6. The multi-dimensional hardware status values before operation are [0.625, 0.40, 0.20, 0.00, 0.30];
[0158] 7. Perform a restart operation;
[0159] 8. After the operation, the multi-dimensional hardware status values are [0.50, 0.30, 0.00, 0.00, 0.20];
[0160] 9. The overall progress score is -0.0987;
[0161] 10. The target reward is -3.97, and manual intervention is initiated.
[0162] Comparative verification:
[0163] 1. The method of this application is compared with the result-oriented method (which only gives a success / failure binary reward at the end of the task) and the fixed repair number method (which sets the maximum number of retries to 5 and has no intermediate feedback) in the prior art, and the results are shown in Table 4.
[0164] Table 4 Comparison of various repair methods
[0165]
[0166] As shown in Table 4, this application achieves significant improvements in repair efficiency, success rate, resource consumption, and fault identification capability through intensive status feedback and reward mechanisms, making it the best performing of the three schemes.
[0167] 2. After adopting the dense reward mechanism of the present invention, the policy entropy of the Agent decreases under the same training rounds, indicating that the decision-making is more deterministic.
[0168] 3. During the repair process of 7 “difficult machines”, the present invention can identify invalid retry patterns after an average of 1.8 operations, saving 64% of invalid operations, while the result-oriented method requires exhausting all 5 retry opportunities to determine failure.
[0169] 4. Through the 5-dimensional state vector, maintenance personnel can clearly locate the fault stage, improving the diagnostic accuracy from 60% to 85% and reducing the root cause location time from 15 minutes to 3 minutes.
[0170] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0171] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.
[0172] Figure 2 A schematic diagram of the chip fault repair and evaluation device provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:
[0173] like Figure 2 As shown, the chip fault repair and evaluation device includes:
[0174] The hardware state change acquisition module 21 is used to acquire multi-dimensional hardware state values before and after the operation, and calculate the changes in hardware state values in each dimension before and after the operation.
[0175] Repair assessment module 22 is used to determine the overall progress score based on the changes in hardware status values in each dimension;
[0176] The reward determination module 23 is used to determine the overall reward based on the overall progress score;
[0177] The reward adjustment module 24 is used to adjust the overall reward based on the difficulty of equipment repair to obtain the target reward, which is used to guide the direction of equipment repair.
[0178] In one possible implementation, the repair evaluation module 22 includes:
[0179] The weight determination unit is used to determine the target weights for each dimension;
[0180] The score output unit is used to sum the changes in hardware status values of each dimension with the target weights of each dimension to obtain the overall progress score.
[0181] In one possible implementation, the weight determination unit can be specifically used for:
[0182] 1. Obtain the equipment's historical repair records;
[0183] 2. Determine the conditional success rate for each dimension based on the equipment's historical repair records, and normalize the conditional success rate for each dimension to obtain the first weight for each dimension; whereby the conditional success rate is used to represent the probability that the hardware status value of a single dimension has improved.
[0184] 3. Using regression analysis, the correlation coefficients between the changes in hardware status values of each dimension and the success of repairs were determined based on the historical repair records of the equipment. The correlation coefficients of each dimension were then normalized to obtain the second weight of each dimension.
[0185] 4. The first weight and the second weight of each dimension are combined to obtain the third weight of each dimension;
[0186] 5. Perform perturbation verification on the third weights of each dimension;
[0187] 6. If the verification passes, the third weight of each dimension will be used as the target weight of each dimension.
[0188] In one possible implementation, the reward determination module 23 may include:
[0189] The operation cost determination unit is used to obtain the type of repair operation and determine the operation cost based on the type of repair operation.
[0190] The basic score determination unit is used to determine the basic reward score based on the overall progress score;
[0191] The comprehensive reward determination unit is used to subtract the operating cost from the basic reward score to obtain the comprehensive reward.
[0192] In one possible implementation, the basic score determination unit can be specifically used for:
[0193] 1. Determine the base reward score based on the overall progress score and the first formula;
[0194] The first formula may include:
[0195]
[0196] in, Basic reward points, The overall progress score.
[0197] In one possible implementation, the reward correction module 24 may include:
[0198] The first lookup unit is used to look up the expected progress score based on the difficulty of equipment repair.
[0199] The relative performance calculation unit is used to calculate the ratio of the overall progress score to the expected progress score to obtain the relative performance of the repair.
[0200] The second lookup unit is used to look up the table to obtain the reward adjustment value based on the relative performance of the repair.
[0201] The adjustment unit is used to sum the reward adjustment value with the comprehensive reward to obtain the target reward.
[0202] In one possible implementation, the above-described apparatus may further include:
[0203] The record acquisition module is used to acquire the device's historical repair records;
[0204] The repair difficulty output module is used to determine the repair difficulty of the equipment based on statistical analysis and the equipment's historical repair records.
[0205] In one possible implementation, the above-described apparatus may further include:
[0206] The record update module is used to update the equipment's historical repair record when it detects three consecutive repair failures, a continuous decrease in the target reward corresponding to multiple repairs, or a comprehensive progress score that is not greater than 0. It also executes a step based on statistical analysis to determine the equipment repair difficulty according to the equipment's historical repair record.
[0207] In one possible implementation, the multi-dimensional hardware status values include: device visibility, PCIe link status, inner loop initialization progress, inter-chip interconnect link synchronization, and error density.
[0208] Figure 3 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. For example... Figure 3As shown, the electronic device 3 of this embodiment includes a processor 30 and a memory 31. The memory 31 stores a computer program 32. When the processor 30 executes the computer program 32, it implements the steps in the various method embodiments described above. Alternatively, when the processor 30 executes the computer program 32, it implements the functions of each module / unit in the various device embodiments described above.
[0209] For example, computer program 32 may be divided into one or more modules / units, which are stored in memory 31 and executed by processor 30 to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 32 in electronic device 3.
[0210] Electronic device 3 may include, but is not limited to, processor 30 and memory 31. Those skilled in the art will understand that... Figure 3 This is merely an example of electronic device 3 and does not constitute a limitation on electronic device 3. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device 3 may also include input / output devices, network access devices, buses, etc.
[0211] The processor 30 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.
[0212] The memory 31 can be an internal storage unit of the electronic device 3, such as a hard disk or memory of the electronic device 3. The memory 31 can also be an external storage device of the electronic device 3, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 3. Furthermore, the memory 31 can include both internal and external storage units of the electronic device 3. The memory 31 is used to store the computer program 32 and other programs and data required by the electronic device 3. The memory 31 can also be used to temporarily store data that has been output or will be output.
[0213] For the sake of simplicity and clarity, only the above-described functional modules / units are used as examples. In practical applications, the functions described above can be assigned to different functional modules / units as needed. These modules / units can be implemented in hardware, software, or a combination of both.
[0214] This invention also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the methods described in the above-described method embodiments.
[0215] This invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the methods described in the above-described method embodiments.
[0216] Computer programs include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.
[0217] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not detailed or described in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Unless otherwise specified or in conflict with logic, the terminology and / or descriptions between different embodiments are consistent and can be referenced interchangeably. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.
[0218] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.
Claims
1. A chip fault repair and evaluation method, characterized in that, include: Obtain multi-dimensional hardware status values before and after the operation, and calculate the changes in hardware status values in each dimension before and after the operation. The overall progress score is determined based on the changes in hardware status values for each dimension. The overall reward is determined based on the overall progress score. The comprehensive reward is adjusted based on the difficulty of equipment repair to obtain a target reward, which is used to guide the direction of equipment repair. The determination of the overall progress score based on the changes in hardware status values across each dimension includes: Determine the target weights for each dimension; The overall progress score is obtained by weighting and summing the changes in hardware status values of each dimension with the target weights of each dimension. The determination of the target weights for each dimension includes: Obtain the device's historical repair records; The conditional success rate for each dimension is determined based on the device's historical repair records, and the conditional success rate for each dimension is normalized to obtain the first weight for each dimension; wherein, the conditional success rate is used to represent the probability that a single dimension's hardware status value has improved. Regression analysis was used to determine the correlation coefficient between the changes in hardware status values of each dimension and the success of repair based on the historical repair records of the equipment. The correlation coefficients of each dimension were then normalized to obtain the second weight of each dimension. The first weights and second weights of each dimension are fused to obtain the third weights of each dimension; The third weights of each dimension are perturbed and verified. If the verification passes, the third weight of each dimension will be used as the target weight of each dimension.
2. The chip fault repair and evaluation method according to claim 1, characterized in that, The determination of the comprehensive reward based on the comprehensive progress score includes: Obtain the type of repair operation and determine the operation cost based on the type of repair operation; The base reward score is determined based on the overall progress score. The comprehensive reward is obtained by subtracting the operating cost from the basic reward score.
3. The chip fault repair and evaluation method according to claim 2, characterized in that, The determination of the base reward score based on the comprehensive progress score includes: The basic reward score is determined based on the comprehensive progress score and the first formula. The first formula includes: in, The base reward score, The overall progress score is denoted as .
4. The chip fault repair and evaluation method according to claim 1, characterized in that, The adjustment of the comprehensive reward based on the difficulty of equipment repair to obtain the target reward includes: Based on the difficulty of the equipment repair, the expected progress score is obtained by referring to the table. The ratio of the overall progress score to the expected progress score is calculated to obtain the relative performance of the repair. Based on the relative performance of the repair, the reward adjustment value is obtained by looking up the table. The target reward is obtained by summing the reward adjustment value with the comprehensive reward.
5. The chip fault repair and evaluation method according to claim 4, characterized in that, The method further includes: Obtain the device's historical repair records; Based on statistical analysis and the historical repair records of the equipment, the difficulty of repairing the equipment is determined.
6. The chip fault repair and evaluation method according to claim 5, characterized in that, The method further includes: If three consecutive repair failures are detected, the target reward corresponding to multiple repairs continues to decrease, or the comprehensive progress score is not greater than 0, then the device historical repair record is updated, and the step of determining the device repair difficulty based on the statistical analysis method and the device historical repair record is executed.
7. The chip fault repair and evaluation method according to claim 1, characterized in that, The multi-dimensional hardware status values include: device visibility, PCIe link status, inner loop initialization progress, inter-chip interconnect link synchronization, and error density.
8. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the chip fault repair and evaluation method as described in any one of claims 1 to 7.