Modeling and simulation method of dynamic random access memory

Abstract

The invention relates to a modeling and simulation method for a dynamic random access memory. According to the method, based on a target process node specified by a user, transistor and interconnection parameters are loaded from a process technical parameter database, and non-standard process node modeling is supported through an interpolation algorithm; the method comprises the following steps: performing top-down organization modeling on a dynamic random access memory by adopting a hierarchical structure, and introducing an H-type wiring network to describe address and data signal distribution; performing design space exploration on key physical parameters such as word line segmentation number, bit line segmentation number and column multiplexing degree to generate a plurality of physical implementation schemes; on the circuit level, the time delay, the power consumption and the area are accurately calculated by utilizing an analytical model, and specific time sequence parameters and refresh power consumption evaluation of the dynamic random access memory are integrated; and finally, selecting an organization scheme with the optimal comprehensive performance according to a multi-objective optimization criterion. According to the method, different architecture schemes can be quickly and accurately evaluated in an early design stage, and effective support is provided for architecture optimization of the dynamic random access memory.

Description

Technical Field

[0001] This application relates to the fields of integrated circuit design and electronic design automation, and in particular to a modeling and simulation method for dynamic random access memory. Background Technology

[0002] With the continuous evolution of advanced manufacturing processes, chip design is increasingly reliant on memory systems. Memory systems have become one of the key factors limiting overall computing performance and energy efficiency. In modern processor architectures, memory not only serves the functions of temporary data storage and fast access, but its organization, physical implementation, and access timing also directly affect the processor's effective throughput. In terms of performance, memory access latency and bandwidth limitations significantly restrict instruction execution efficiency. Especially in storage-intensive applications, performance losses caused by cache misses can exceed 50% of overall performance, severely impacting system responsiveness.

[0003] In terms of power consumption, as process nodes continue to shrink to deep submicron and even nanometer scales, transistor leakage current increases significantly, and static leakage power consumption in memory arrays shows a rapid upward trend. At the same time, frequent memory access, refresh operations, and dynamic power consumption caused by long-distance interconnects make memory systems one of the main sources of chip power consumption. In terms of area, memory usually occupies a large proportion of the chip layout. Area constraints not only directly affect chip manufacturing costs, but also indirectly affect access latency and power consumption by increasing interconnect length and load capacitance.

[0004] The performance, power consumption and area mentioned above are highly coupled. Optimization in any dimension often has an adverse effect on other dimensions, resulting in a complex and high-dimensional design space. Factors such as the word line and bit line organization of the storage system, the array partitioning strategy, the reuse structure and the hierarchical architecture configuration will all have a significant impact on the final comprehensive indicators, making it difficult for designers to make accurate trade-offs based on experience.

[0005] In traditional chip design flows, accurate evaluation of memory systems typically relies on detailed circuit-level simulation or layout-level analysis. However, these evaluation methods often can only be performed after register-transfer level design or even physical implementation is completed. If performance, power consumption, or area specifications are found to be unacceptable at this stage, architectural modifications will lead to a significant backtracking of the design flow, increasing design cycle time and development costs. In contrast, coarse-grained estimation methods used in the early stages of design, while computationally faster, often ignore the influence of process parameters, interconnect characteristics, and memory-specific timing behavior, resulting in larger prediction errors and making it difficult to provide a reliable basis for critical architectural decisions.

[0006] Regarding the aforementioned technologies, the inventors believe that existing technologies still lack an effective method for rapidly predicting performance, power consumption, and area while ensuring evaluation accuracy in the early design stage of storage systems. This makes it difficult to support the systematic exploration of various storage configurations and physical organization schemes. How to efficiently and accurately model and evaluate different storage system architectures in the early design stage has become an important technical problem restricting chip design efficiency and success rate. Summary of the Invention

[0007] To address the technical challenge of efficiently and accurately modeling and evaluating different storage system architectures in the early stages of design, this application provides a modeling and simulation method for dynamic random access memory (DRAM).

[0008] The modeling and simulation method for dynamic random access memory provided in this application adopts the following technical solution: A method for modeling and simulating dynamic random access memory includes the following steps: Step 1: Parameter loading and processing Based on the target process node input by the user, transistor and interconnect parameters are obtained from the process technology parameter database, and linear interpolation algorithm is used to process the parameters of non-standard process nodes. Step 2: Hierarchical structure modeling. A top-down approach is adopted to decompose and instantiate the dynamic random access memory model into a hierarchical structure such as unified cache access unit, memory bank, memory array block, and memory subarray, and an H-type wiring network is used for signal organization modeling. Step 3: Design Space Exploration Intelligent traversal and combined evaluation are performed on key physical organization parameters (such as word line segmentation, bit line segmentation, column reuse, etc.) to generate multiple physical implementation schemes; Step 4: Circuit-level performance analysis and calculation. Based on the parameters loaded in step 1, the delay, dynamic power consumption, static leakage power consumption and physical area of ​​all hierarchical structure components are analytically calculated and accumulated from bottom to top using the resistor-capacitor time constant model and the Horowitz delay model. Step 5: Multi-objective optimization selection, Based on the optimization target weights set by the user, the physical organization scheme with the best overall performance, power consumption, and area is selected from the results of the design space exploration.

[0009] By adopting the above technical solutions, dynamic random access memory (DRAM) can be systematically and hierarchically modeled and simulated in the early stages of chip design. This enables rapid and accurate prediction of performance, power consumption, and area metrics under different process nodes and various physical organization schemes. The method supports the modeling needs of non-standard process nodes through parameterized loading and interpolation; it achieves a fine characterization of the memory architecture and interconnect impact through hierarchical structure modeling and H-type routing network description; it comprehensively evaluates the impact of key physical parameters on overall metrics by combining design space exploration and analytical calculation; and based on a multi-objective optimization mechanism, it assists designers in making reasonable trade-offs between performance, power consumption, and area, thereby improving the efficiency of memory system architecture decision-making, shortening the design cycle, and reducing design risks.

[0010] Optionally, in the parameter loading and processing step, the process nodes for which the parameters are calculated using a linear interpolation algorithm include, but are not limited to, intermediate process nodes between two known process nodes.

[0011] By adopting the above technical solutions, it is possible to reasonably estimate the key device and interconnect parameters of non-standard or intermediate process nodes in the absence of complete process data, improve the model's adaptability and continuity to different process nodes, thereby ensuring the consistency and availability of modeling and simulation results in the process of process evolution, and providing more flexible and reliable parameter support for memory architecture design.

[0012] Optionally, in the hierarchical structure modeling step, the memory layer achieves balanced distribution and convergence of address signals and data signals among multiple memory array blocks by modeling the H-type wiring network, and incorporates the delay and power consumption contribution of the H-type wiring network into the overall index.

[0013] By adopting the above technical solutions, the distribution and convergence process of address and data signals within the memory bank among multiple memory array blocks can be accurately depicted, effectively reflecting the impact of interconnect topology on latency and power consumption. The contribution of H-type cabling networks can be incorporated into the overall evaluation, improving the accuracy and engineering reliability of memory system performance and power consumption prediction results.

[0014] Optionally, in the design space exploration step, the key physical organization parameters of the intelligent traversal include at least the number of word line partitions, the number of bit line partitions, and the column reuse, and a complete performance, power consumption, and area calculation is performed once for each combination.

[0015] By adopting the above technical solutions, we can systematically explore various combinations of key physical parameters in the memory design space, comprehensively evaluate the impact of different word line partitions, bit line partitions and column reuse on performance, power consumption and area, realize quantitative analysis and optimization guidance of memory architecture, and provide a reliable basis for designers to select the optimal physical organization scheme in the early stage.

[0016] Optionally, in the circuit-level index analysis and calculation step, the delay calculation is achieved by accurately summing and accumulating the delays of all components on the critical path, such as row decoding delay, word line delay, bit line sensing delay, and data input / output delay.

[0017] By adopting the above technical solutions, various delays on the critical path of dynamic random access memory can be accurately quantified, including row decoding, word line, bit line sensing, and data input / output delays, thereby achieving accurate prediction of the overall memory access delay, providing reliable time indicators to support performance evaluation and architecture optimization, and improving the accuracy and controllability of early design decisions.

[0018] Optionally, in the circuit-level index analysis and calculation step, the delay calculation model also integrates the calculation of timing parameters specific to the dynamic random access memory, including row-to-column command delay, row access strobe delay, and precharge delay.

[0019] By adopting the above technical solution, the timing parameters unique to dynamic random access memory, such as row-to-column command latency, row access gating latency, and precharge latency, can be considered simultaneously in latency calculation. This enables accurate modeling of the actual memory access behavior, improves the accuracy and reliability of latency prediction, and provides a comprehensive time index reference for architecture optimization and performance analysis.

[0020] Optionally, in the circuit-level index analysis and calculation step, the power consumption calculation model not only includes the sum of dynamic power consumption and static leakage power consumption, but also integrates the accurate calculation of the power consumption overhead of refresh operation unique to dynamic random access memory.

[0021] By adopting the above technical solutions, the power consumption of dynamic random access memory can be comprehensively evaluated. It can not only accurately accumulate dynamic power consumption and static leakage power consumption, but also quantify the additional power consumption brought by refresh operation, thereby achieving accurate prediction of the overall power consumption of memory. This provides a reliable basis for power consumption optimization, architecture selection and early energy efficiency analysis in design, and improves the scientificity and accuracy of design decisions.

[0022] Optionally, the power consumption calculation model can distinguish the different power consumption characteristics in the open and closed states, and model and evaluate them separately.

[0023] By adopting the above technical solutions, it is possible to distinguish and characterize the different access behaviors and power consumption characteristics of dynamic random access memory in open and closed states, realize fine-grained modeling and evaluation of power consumption differences between the two operating modes, thereby improving the accuracy of power consumption prediction and providing effective support for memory access strategy selection and low-power architecture design.

[0024] Optionally, the method further includes an evaluation of the three-dimensional stacked architecture, wherein the circuit-level metric analysis calculation step integrates the delay, power consumption, and area overhead introduced by through-silicon vias.

[0025] By adopting the above technical solutions, the additional latency, power consumption and area overhead caused by silicon vias in the three-dimensional stacked architecture can be comprehensively considered during the modeling and simulation process, so as to achieve a unified evaluation and comparative analysis of two-dimensional and three-dimensional storage architectures, thereby providing a reliable basis for the architecture selection and design optimization of three-dimensional integrated storage systems.

[0026] Optionally, the method further includes a result visualization and comparative analysis step, which outputs the simulation results of different physical organization schemes in terms of performance, power consumption, area and key timing parameters in a unified manner, and realizes intuitive comparison between multiple schemes through two-dimensional or three-dimensional charts to assist users in making design decisions.

[0027] By adopting the above technical solutions, the performance, power consumption, area, and key timing parameters of different physical organization schemes can be intuitively displayed and compared, helping users to quickly understand the differences and trade-offs between the schemes, thereby improving the efficiency of design evaluation and assisting designers in making more reasonable and efficient architectural decisions in complex design spaces.

[0028] In summary, this application includes at least one of the following beneficial technical effects: 1. It can quickly and accurately predict the performance, power consumption and area of ​​dynamic random access memory in the early stages of chip design, avoiding the high modification costs and high design risks caused by relying solely on later circuit-level simulation; 2. By introducing parameterized loading and linear interpolation mechanisms, the modeling requirements of non-standard process nodes and intermediate process nodes are effectively supported, improving the continuity and versatility of the method in the process evolution. 3. The hierarchical structure modeling and H-type wiring network description method can accurately reflect the internal hierarchical relationship of the storage system and the impact of interconnection on performance and power consumption, thereby improving the engineering credibility of the model; 4. By systematically traversing and evaluating key physical parameters such as word line segmentation, bit line segmentation, and column reuse, a comprehensive analysis of the storage system design space is achieved, assisting designers in discovering the optimal or near-optimal physical organization scheme. 5. In the circuit-level performance analysis and calculation, the modeling of DRAM-specific timing parameters, refresh power consumption, and power consumption characteristics of different page states is integrated, making the evaluation results closer to the actual working scenario; 6. By introducing the calculation of delay, power consumption and area overhead related to through-silicon vias, a unified modeling and comparative analysis of two-dimensional and three-dimensional stacked memory architectures is achieved, expanding the applicability of the method; 7. By combining multi-objective optimization selection and result visualization and comparative analysis mechanisms, designers can make intuitive trade-offs and scientific decisions between performance, power consumption and area, thereby shortening the design cycle and reducing overall design risks. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the hierarchical parsing model of an embodiment of this application.

[0030] Figure 2 This is the operational flow of the embodiments of this application. Detailed Implementation

[0031] The following is in conjunction with the appendix Figure 1-2 This application will be described in further detail.

[0032] This application discloses a modeling and simulation method for dynamic random access memory (DRAM). The method comprises the following steps: Step 1: Parameter loading and processing, and user configuration input, including capacity, process nodes, etc. Based on the target process node input by the user, transistor and interconnect parameters are obtained from the process technology parameter database, and linear interpolation algorithm is used to process the parameters of non-standard process nodes. The system performs basic parameter loading preprocessing, and at the same time, linear interpolation is used for non-standard process nodes; Step 2: Hierarchical structure modeling. Using a top-down approach, the dynamic random access memory model is decomposed and instantiated into a hierarchical structure such as unified cache access unit, memory bank, memory array block, and memory subarray, and an H-type wiring network is used for signal organization modeling. Step 3: Design Space Exploration. Intelligent design space exploration is performed for performance calculation, power consumption calculation, and area calculation. Intelligent traversal and combination evaluation are performed on key physical organization parameters (such as word line segmentation, bit line segmentation, column reuse, etc.). Through a three-dimensional stacked architecture, multiple physical implementation schemes are generated, and the generated multi-objective schemes are evaluated. The evaluation results are fed back to the intelligent design space exploration system. Step 4: Circuit-level performance analysis and calculation. Based on the parameters loaded in Step 1, the delay, dynamic power consumption, static leakage power consumption and physical area of ​​all hierarchical components are analyzed and accumulated from bottom to top using the resistor-capacitor time constant model and the Horowitz delay model. Step 5: Multi-objective optimization selection. Based on the user-defined optimization objective weights, the physical organization scheme with the optimal overall performance, power consumption, and area is selected from the results of the design space exploration. Finally, a simulation result report is generated, completing the reference. Figure 1 The hierarchical analytical model shown.

[0033] This technical solution provides a high-precision, fast simulation method for dynamic random access memory (DRAM) models, specifically designed for the accurate, rapid, and flexible evaluation of three key performance indicators—performance, power consumption, and physical area—of DRAMs, including traditional two-dimensional planar architectures and advanced three-dimensional stacked architectures, in the very early stages of integrated circuit architecture design. The core of this method lies in the deep integration of hierarchical circuit analytical modeling and intelligent design space exploration. It decomposes complex memory systems into hierarchical, computable components based on circuit physical parameters, enabling precise bottom-up accumulation of performance, power consumption, and area metrics.

[0034] 1. Simulation System Initialization and Accurate Process Parameter Loading The first step of this method is to establish an accurate computational environment and boundary conditions.

[0035] Configuration file parsing and specification definition: The system first receives all high-level specifications and design constraints of the target dynamic random access memory (DRAM) from the user through a configuration description file. These configuration parameters define the macroscopic characteristics of the simulation object, including: the total memory capacity, the minimum accessible data block size, the number of memory banks under a unified cache access unit, the burst length of data transfer, the input / output bit width of the memory's external interface, and most critically, the target process node, such as 32nm, 22nm, etc., and the basic structural type of the memory cell, such as a single-transistor single-capacitor structure. All these input parameters are parsed by the system and transformed into an internal global constraint data structure, serving as the basis for all subsequent calculations.

[0036] Precise Loading and Interpolation of Technical Parameters: To ensure circuit-level accuracy in the evaluation results, the core innovation of this method lies in the technical parameter loading submodule. This module is responsible for acquiring all necessary transistor electrical parameters and interconnect parasitic parameters. Based on the user-specified target process node, the system searches for the corresponding parameter set from a pre-established process parameter database file. These parameters form the underlying foundation for all subsequent delay and power consumption calculations, including but not limited to: transistor threshold voltage, on-state current, off-state current, gate oxide thickness, various parasitic capacitances, and the unit length resistance and unit length capacitance of interconnects.

[0037] To address the issue of missing parameters in chip design, particularly for non-standard process nodes, this method employs a linear interpolation algorithm. If a user-specified process node, such as 35nm, lacks a precise match in the database, the system intelligently identifies and retrieves the complete parameter sets of two adjacent known process nodes, such as 32nm and 45nm. Subsequently, the system performs linear interpolation on each key parameter, such as threshold voltage and on-state current, to reasonably and accurately calculate the parameter values ​​for that intermediate process node. This mechanism significantly expands the applicability of this method, ensuring the accuracy of evaluation for any process node. Furthermore, for parameters significantly affected by temperature variations, such as the leakage current of a transistor in the off-state, the system supports multi-temperature data storage and automatically selects or interpolates parameters based on the user-input operating temperature, ensuring simulation accuracy under different thermal environments. All loaded and processed parameters are encapsulated in a global technical parameter object for sharing and use by all subsequent low-level circuit calculation modules.

[0038] Hierarchical structure modeling and exploration of physical organization parameters This method employs a hierarchical modeling framework to provide a structural description of dynamic random access memory and integrates an intelligent design space exploration mechanism.

[0039] Hierarchical Instantiation: The system follows a strict top-down instantiation process, decomposing the memory into four main logical layers: Unified Cache Access Unit: The top-level interface unit, responsible for handling external access requests and coordinating multiple internal memory banks. Memory Bank: The main body of the memory, composed of multiple memory array blocks, and the basic unit for address decoding and data transmission / reception. Memory Array Block: Contains core circuit components such as row decoders, column decoders, sensing amplifiers, and multiple memory subarrays. Memory Subarray: The smallest memory cell matrix, containing memory cells with cross-connected word lines and bit lines, where actual data storage and reading / writing occur.

[0040] At the memory layer, this method models address and data routing using a highly efficient H-type routing network. This routing structure minimizes signal delay and routing resources, ensuring balanced distribution and efficient convergence of address and data signals across multiple memory array blocks. The system accurately models the length, number of stages, and driver size of the H-type routing network, incorporating its delay and power consumption contributions into the total performance-power-area metrics.

[0041] Intelligent Design Space Exploration: The physical layout parameters of dynamic random access memory (DRAM) have a crucial impact on performance, power consumption, and area metrics. This method integrates an intelligent design space exploration module, whose task is to traverse and evaluate all effective combinations of physical organization parameters to achieve multi-objective optimization. Core exploration parameters include: Word Line Segmentation: Controls the number of physical segments along the word line direction within a memory array block. Increasing the segmentation number can reduce word line length, word line capacitance, and resistance, thereby reducing row access latency, but it increases the complexity and area of ​​the driver circuitry and decoder. Bit Line Segmentation: Controls the number of segments along the bit line direction. Increasing the segmentation number can reduce bit line capacitance and reduce bit line read latency, but it also increases the complexity of column decoding and data paths. Column Multiplexing: Defines the number of sense amplifiers corresponding to each column address, determining the degree of data multiplexing. High multiplexing can reduce peripheral logic area, but may increase data path latency. Row Activation Multiplexing: Affects the design and power consumption of the row decoder. The design space exploration module generates thousands or even tens of thousands of effective combinations of parameters based on user-defined capacity and block size constraints. The system will run a complete performance, power consumption, and area calculation process for each combination, ensuring that the final selected solution meets the design specifications while achieving or approaching the optimal solution in terms of performance, power consumption, and area. This automated and intelligent exploration process reduces the manual design iteration that originally required weeks to seconds or milliseconds.

[0042] Analytical calculations of circuit-level performance, power consumption, and area All performance, power consumption, and area metrics are calculated based on analytical models and underlying circuit physical parameters, and then accumulated from the bottom up.

[0043] Performance calculation module: Delay calculation uses a high-precision circuit analytical model, strictly based on the transistor and interconnect parameters loaded in step one.

[0044] Basic Circuit Delay Calculation: At the lowest level, the system first calculates the delay of various basic circuit components: Transistor Parameter Calculation: Using the applied threshold voltage, conduction current, etc., the equivalent on-resistance of the transistor is calculated. Capacitance Calculation: The total gate capacitance of the transistor is calculated using the ideal gate capacitance, gate overlap capacitance, and edge capacitance. The total drain capacitance is calculated using junction capacitance and sidewall capacitance. These capacitances are the foundation for all subsequent delay and dynamic power consumption calculations.

[0045] Component Delay Calculation: Decoder Delay: The delay of the decoder, including row and column decoders, is modeled using the Horowitz delay model. The delay is calculated as the sum of the delay of the decoder input drivers and the delay under the large word line load driven by the decoder output. Interconnect Delay: The delay of interconnects such as word lines, bit lines, and H-type wiring networks is mainly calculated using a distributed resistor-capacitor time constant model. The system treats long interconnects as a distributed network composed of resistors and capacitors in series, and calculates their RC delay by summing or integrating. Sensing Amplifier Delay: As a key component of memory read operations, the delay of the sensing amplifier depends on the bit line capacitance at its input, the transistor driving capability, and the settling time of its internal differential amplifier circuit. The system abstracts and models the internal structure of the sensing amplifier to accurately calculate its response time to changes in bit line voltage.

[0046] Path delay accumulation and standard timing calculation: The final access delay, such as the access hit time, is the sum of the delays of all components along the critical path of the address and data signals. The critical path includes: the address propagating from the input through the H-shaped wiring network to the memory, the delays of all stages such as row decoder, word line activation, bit line sensing, sense amplifier setup, and data output drive. This method accurately accumulates all these delay terms.

[0047] Specifically for dynamic random access memory (DRAM), this method integrates a calculation model for timing parameters. These parameters are industry-standard, including row-to-column command latency: the minimum time interval between row activation and column read / write commands; precharge latency: the minimum time interval between precharge commands and row activation commands; and row access strobe latency: the minimum time interval between row activation and precharge commands. The system utilizes the word line / bit line / decoder delays calculated at the underlying level, combined with the timing logic of DRAM operations, to calculate the minimum time interval that meets reliability requirements, which serves as the final output.

[0048] Power consumption calculation module: Power consumption calculation is another key point of this method, and it is necessary to strictly distinguish between dynamic power consumption and static leakage power consumption.

[0049] Dynamic power consumption calculation: Dynamic power consumption is the energy consumed by the circuit during switching operations. Equivalent switched capacitance calculation: In each read / write operation, the system accurately identifies and accumulates the equivalent switched capacitance of all activated circuit elements. This includes the capacitance of the selected word line, the capacitance of the discharged bit line, the capacitance of the triggered sense amplifier, and the capacitance of all drivers and I / O buffers on the data path. Power consumption decomposition: The final dynamic power consumption is decomposed into multiple parts, including decoding power consumption, bit line power consumption, sense power consumption, data output power consumption, and H-network routing power consumption, facilitating designers to accurately pinpoint power bottlenecks.

[0050] Static leakage power calculation: Static leakage power is generated by the leakage current of transistors in the off state. The system uses the transistor turn-off current parameters applied in step one, and considers the effects of operating voltage and temperature, to calculate the static power consumption of each inactive component. The calculation of leakage power is particularly crucial for dynamic random access memory (DRAM): Memory cell leakage: Focus on calculating the leakage current of unselected memory cells. Peripheral logic leakage: Calculate the leakage power consumption of all decoders, drivers, and sensing amplifiers in non-switching states.

[0051] Dynamic Random Access Memory (DRAM) Specific Power Consumption Model: This method integrates accurate power consumption modeling for DRAM-specific operations: Refresh Operation Power Consumption: Since DRAM requires periodic refreshes to maintain data, the system models the additional power consumption required for refresh operations. This includes the refresh cycle, the number of rows activated during a refresh operation, and the dynamic power overhead from row activation and pre-charging in each refresh operation. Operating State Power Consumption Differences: The system can distinguish between the paging state (i.e., a row of data is held in the sensing amplifier, awaiting subsequent operations) and the page-closing state (i.e., pre-charging occurs immediately after the operation, and all rows are closed). The static leakage power consumption and dynamic operation power consumption differ significantly between these two states; this method models and evaluates these two modes separately.

[0052] Area Calculation Module: Area calculation is based on the selected process node and physical organization parameters, decomposing the memory into array area and peripheral logic area for summation. Array Area Calculation: Primarily determined by the physical size of the memory cells and the total capacity. The array area is also affected by parameters such as the number of word lines and bit lines, as these divisions introduce additional redundant circuitry and gaps. Peripheral Logic Area Calculation: Composed of the area of ​​all non-memory array circuitry. This includes: row / column decoders, sense amplifier arrays, input / output buffers, clock and control logic. The area of ​​these logic components depends on their required drive capability, i.e., fan-out load and transistor size. This method automatically calculates and determines the number and size of transistors required for each driver and buffer based on fan-out load and delay requirements, thus deriving their accurate physical area.

[0053] 4. Three-dimensional memory integration and multi-objective optimization output The final step of this method is to integrate advanced technology models and perform final optimization. 3D Memory Model Integration: This method has the capability to evaluate 3D stacked dynamic random access memory architectures. For user-configured 3D stacked scenarios, the system additionally calculates and integrates the impact of through-silicon vias (TSVs) on performance, power consumption, and area. Latency: Calculates the resistance-capacitance delay of the vertical interconnects vias and adds it to the overall access path. Power Consumption: Calculates the dynamic and static power consumption overhead of the additional driving circuitry required to drive the TSVs. Area / Volume: Calculates the physical footprint required for the TSVs themselves and their surroundings and integrates it into the total area metric. Multi-Objective Optimization and Result Output: After completing the performance, power consumption, and area calculations for all physical organization schemes, the system initiates a multi-objective optimization module. This module comprehensively scores all calculation results based on user-defined optimization objective weights, such as performance priority or power consumption / area priority, and selects the physical organization scheme that performs best in terms of the overall performance, power consumption, and area metrics. Finally, the system outputs a highly detailed simulation result report. This report not only provides overall performance, power consumption, and area metrics for the final selected solution, but also includes the following key decomposition data, greatly enhancing the transparency and analyzability of the results: Performance Decomposition: Detailed breakdown of the specific delay values ​​contributed by each critical path component, such as the H-shaped routing network, row decoder, word lines, and sense amplifiers. Power Consumption Decomposition: Detailed breakdown of the specific numerical contributions of dynamic power consumption and static leakage power consumption for each functional component, such as the array, decoder, and data path. Geometric Decomposition: Detailed breakdown of the specific area values ​​for the memory array region and various peripheral logic regions, such as the decoder region and sense amplifier region. Through this complete set of scientific, rigorous simulation processes based on underlying physical parameters, this method can provide a dynamic random access memory (DRAM) performance, power consumption, and area assessment report with circuit-level accuracy, far exceeding traditional empirical estimates, providing chip designers with precise decision-making basis to guide architecture optimization.

[0054] The technical advantages of this solution are as follows: 1. This method is based on analytical models of circuit-level transistor parameters, completely avoiding the huge errors caused by traditional early empirical estimations. By accurately loading and linearly interpolating process parameters such as interconnect resistance, capacitance, and transistor threshold voltage, this method can provide performance, power consumption, and area assessments with circuit-level accuracy during the architecture design phase. Through rigorous cross-validation and comparative testing, the prediction accuracy of this method for core memory performance indicators, such as access latency, can be stably controlled within 5% compared to detailed full-custom circuit simulation results; for the increasingly significant static leakage power consumption at advanced process nodes, the prediction accuracy of this method can achieve a matching degree of over 90%. This high-precision evaluation result gives designers strong confidence, ensuring that the architecture choices made based on simulation data are reliable, fundamentally eliminating the significant design risks and later modifications caused by low-precision estimations.

[0055] 2. This technical solution significantly improves design efficiency and shortens the design cycle while ensuring high accuracy. Traditional circuit-level simulation often requires hours or even days to calculate a single configuration, while this method achieves a leap in evaluation speed through hierarchical analytical models and efficient bottom-up cumulative calculations. In terms of computational efficiency, this method typically takes less than one second to perform a complete performance, area, and power consumption evaluation of a complete dynamic random access memory configuration, such as a 32-megabyte capacity and a 32-nanometer process. More importantly, through the integrated intelligent design space exploration module, this method can complete the traversal and evaluation of thousands of physical organization schemes, including key parameters such as word line partitioning, bit line partitioning, and column reuse, within minutes, and quickly select the optimal solution. This efficiency improvement shortens the memory architecture design cycle by at least 20% compared to traditional processes, bringing huge optimization potential to the overall chip design cycle and cost.

[0056] 3. This method comprehensively integrates precise modeling of the unique operating mechanisms of dynamic random access memory (DRAM), ensuring that simulation results closely match the operating characteristics of real chips. Regarding timing, this method can directly calculate and output key timing parameters conforming to industry standards, such as row-to-column command latency and precharge latency, allowing simulation data to be directly used for system-level timing constraints and verification. In terms of power consumption, the system accurately distinguishes different power consumption modes under open / closed page states and specifically calculates the refresh operation power consumption unique to DRAM. Data shows that at certain advanced process nodes, refresh power consumption can account for 10% to 20% of total static power consumption. The accurate modeling of this method avoids the omission of this critical power consumption, making system-level energy efficiency assessment more reliable and complete, and contributing to more precise power management.

[0057] 4. This method possesses strong process adaptability and support for future advanced architectures. Through parameterized input of configuration files and a unique linear interpolation algorithm, this method can perform parameter extrapolation and accurate evaluation for any non-standard or emerging process node, such as transitional nodes between 32nm and 22nm, greatly expanding the tool's practicality and forward-looking capabilities. Furthermore, this method has fully integrated evaluation models for 3D stacked architectures, enabling accurate modeling of latency, power consumption, and area for through-silicon vias (TSVs) used in high-bandwidth memories. When evaluating 3D memory systems, this method can accurately accumulate the vertical interconnect latency introduced by TSVs, ensuring a high degree of completeness and accuracy in evaluating next-generation memory architecture designs and providing advance guidance for 3D integration design.

[0058] The key technology of this patent lies in combining the hierarchical circuit analysis model with the exploration of intelligent physical organization parameters, thereby providing a method for evaluating the performance, power consumption, and area of ​​dynamic random access memory that combines speed and circuit-level accuracy in the early stages of chip architecture design.

[0059] This technical solution aims to address the challenge of rapidly, accurately, and flexibly evaluating the performance, power consumption, and area characteristics of dynamic random access memory (DRAM) in the early stages of integrated circuit architecture design. While there are various alternative methods for evaluating memory systems, these alternative solutions all have inherent or irreconcilable limitations in terms of evaluation cycle, accuracy, or applicability.

[0060] Alternative Option 1: Full-Custom Circuit-Level Simulation Full-custom circuit-level simulation is the gold standard for evaluating memory performance, power consumption, and area characteristics, offering the highest accuracy. It requires designers to provide complete transistor-level netlists or physical layout information for the memory array and all peripheral logic circuits. Full-custom circuit-level simulation simulates the electrical behavior of each transistor and parasitic element in the circuit by solving complex systems of nonlinear differential equations, thereby accurately calculating metrics such as delay and power consumption.

[0061] The fundamental limitations of full-custom circuit-level simulation lie in its extremely low efficiency and delayed applicability. First, simulating a memory array with millions or even billions of transistors requires hours to days of computation and enormous computing resources. This inefficiency prevents it from being used for large-scale design space exploration or for evaluating thousands of different physical organization schemes in a short period. Second, it can only be performed after the design has entered or is nearing the layout stage, at which point the architecture is already fixed. Once simulation reveals defects in the memory architecture, the cost of modification and rerouting will be astronomical.

[0062] This application's hierarchical analytical simulation method achieves near-circuit-level accuracy in predicting core performance, power consumption, and area metrics by precisely loading process parameters and employing mature circuit analytical formulas such as the Horowitz delay model, while reducing simulation time to within seconds. This means that this method can quickly and accurately eliminate a large number of suboptimal designs at the earliest stage of architecture design, without waiting for time-consuming layout completion. This application's technical solution finds an optimal balance between evaluation speed and evaluation accuracy that traditional methods cannot achieve.

[0063] Alternative Solution 2: Register-Transfer Level Synthesis and Simulation Register-transfer level (RTL) simulation and synthesis is the mainstream method for digital circuit design. Designers first need to complete the register-transfer level code for memory control logic and data paths using a hardware description language. Then, the synthesis tool maps the RTL code to the gate-level circuits of the target technology library. The synthesis tool can obtain preliminary area and timing information, while RTL simulation is used to verify the correctness of the functions. The main limitations of this approach lie in its inability to address the core physical characteristics of the memory and its delayed timing. First, register-transfer level simulation and synthesis focus on digital logic and functional verification. The performance, power consumption, and area characteristics of dynamic random access memory (DRAM) are highly dependent on analog characteristics, such as bit line capacitance, word line resistance, settling time of sense amplifiers, and static leakage current of memory cells. Register-transfer level and synthesis tools cannot accurately handle these analog / physical characteristics, so their predicted memory access latency and power consumption often deviate significantly from reality. Second, this method must wait until the complete RTL code is written, which is still in the middle of the design cycle, missing the optimal early architecture decision-making opportunity. The simulation method in this application is purely physical and circuit analysis-level. It can work before register-transfer level code is written. It directly models and calculates the most sensitive physical and analog parts of the memory, such as the RC delay of word lines and bit lines and the settling time of the sensing amplifier. It also integrates the refresh power consumption and timing parameters unique to dynamic random access memory. This method can capture the key factors that determine memory performance, power consumption and area, which are completely ignored by register-transfer level synthesis tools.

[0064] Alternative Option 3: High-Level Abstraction Model and Empirical Estimation In the very early stages of architecture design, some designers or tools use high-level abstract models or empirical formulas for rapid estimation. This method treats memory as a "black box" and estimates performance, power consumption, and area metrics using simple empirical formulas. It requires very few input parameters and runs extremely fast. The main limitations of the third alternative method are its extremely low accuracy and lack of physical guidance. Because this model lacks a direct correlation with the underlying process node, transistor characteristics and physical organization, its prediction results are often crude and unreliable. Especially when evaluating designs across different process nodes, empirical formulas cannot handle the complex nonlinear effects of changes in physical parameters such as word line splitting and column reuse, which may lead to evaluation errors exceeding 20%, thus causing designers to make suboptimal or incorrect design decisions based on incorrect prediction data.

[0065] While maintaining the speed advantage of high-level estimation, the method of this application completely abandons inaccurate empirical formulas. The method of this application uses a hierarchical analytical model and transistor parameter-driven calculation, and incorporates physical organization parameters as explicit variables into the exploration of intelligent design space. It is not only fast, but also has clear physical basis and process traceability, achieving a perfect combination between rapid evaluation and high accuracy.

[0066] In summary, traditional full-custom simulation offers the highest accuracy but is too slow and has timing delays; register-transfer level synthesis can evaluate digital logic but ignores the key analog physical characteristics of memory; while empirical estimation is fast but too coarse in accuracy. The method in this application aims to fill this technological gap. It is an innovative method based on process parameter interpolation and hierarchical circuit analysis, which can provide high-precision, fully customized, and fast performance, power consumption, and area assessment capabilities in the early stages of architecture design, realizing the key technology necessary for optimizing efficient memory system architecture.

[0067] The implementation principle of the modeling and simulation method for dynamic random access memory (DRAM) in this application is as follows: Based on process technology parameters, a unified computing environment adaptable to different process nodes is established through parameterized loading and interpolation. On this basis, a top-down hierarchical structure modeling is adopted, decomposing the DRAM into analytical circuits and interconnection units step by step. At the same time, key physical organization parameters such as word line segmentation, bit line segmentation, and column reuse are explicitly incorporated into the design variable space, and multiple candidate architecture schemes are generated by combining an intelligent design space exploration mechanism. For each scheme, circuit-level analytical calculations are performed based on the resistor-capacitor model and the Horowitz delay model, and performance, power consumption, and area indicators are accumulated from bottom to top. Furthermore, the timing constraints, refresh power consumption, and three-dimensional stacked silicon via overhead unique to DRAM are introduced to achieve accurate characterization of the actual working characteristics. Finally, through multi-objective optimization and result analysis, the memory architecture scheme that meets the design constraints and has the best comprehensive indicators is selected, thereby achieving high-speed and high-precision DRAM modeling and simulation evaluation in the early stages of design.

[0068] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A modeling and simulation method for dynamic random access memory, characterized in that: Includes the following steps: Step 1: Parameter loading and processing Based on the target process node input by the user, transistor and interconnect parameters are obtained from the process technology parameter database, and linear interpolation algorithm is used to process the parameters of non-standard process nodes. Step 2: Hierarchical structure modeling. A top-down approach is adopted to decompose and instantiate the dynamic random access memory model into a hierarchical structure such as unified cache access unit, memory bank, memory array block, and memory subarray, and an H-type wiring network is used for signal organization modeling. Step 3: Design Space Exploration Intelligent traversal and combined evaluation are performed on key physical organization parameters (such as word line segmentation, bit line segmentation, column reuse, etc.) to generate multiple physical implementation schemes; Step 4: Circuit-level performance analysis and calculation. Based on the parameters loaded in step 1, the delay, dynamic power consumption, static leakage power consumption and physical area of ​​all hierarchical structure components are analytically calculated and accumulated from bottom to top using the resistor-capacitor time constant model and the Horowitz delay model. Step 5: Multi-objective optimization selection, Based on the optimization target weights set by the user, the physical organization scheme with the best overall performance, power consumption, and area is selected from the results of the design space exploration.

2. The simulation method according to claim 1, characterized in that: In the parameter loading and processing steps, the process nodes for which parameters are calculated using a linear interpolation algorithm include, but are not limited to, intermediate process nodes between two known process nodes.

3. The simulation method according to claim 1, characterized in that: In the hierarchical structure modeling step, the storage layer achieves balanced distribution and convergence of address and data signals among multiple storage array blocks by modeling the H-type wiring network, and incorporates the delay and power consumption contribution of the H-type wiring network into the overall index.

4. The simulation method according to claim 1, characterized in that... In the design space exploration step, the key physical organization parameters of intelligent traversal include at least the number of word lines, the number of bit lines, and the column reuse degree, and a complete performance, power consumption, and area calculation is performed once for each combination.

5. The simulation method according to claim 1, characterized in that: In the circuit-level index analysis and calculation step, the delay calculation is achieved by accurately summing and accumulating the delays of all components on the critical path, such as row decoding delay, word line delay, bit line sensing delay, and data input / output delay.

6. The simulation method according to claim 1, characterized in that: In the circuit-level index analysis and calculation step, the delay calculation model also integrates the calculation of timing parameters specific to dynamic random access memory, including row-to-column command delay, row access strobe delay, and precharge delay.

7. The simulation method according to claim 1, characterized in that: In the circuit-level index analysis and calculation steps, the power consumption calculation model not only includes the sum of dynamic power consumption and static leakage power consumption, but also integrates the accurate calculation of the power consumption overhead of refresh operation unique to dynamic random access memory.

8. The simulation method according to claim 7, characterized in that: The power consumption calculation model can distinguish the different power consumption characteristics in the open and closed states, and model and evaluate them separately.

9. The simulation method according to claim 1, characterized in that: The method also includes an evaluation of the three-dimensional stacked architecture, wherein the circuit-level metric analysis calculation step integrates the delay, power consumption, and area overhead introduced by through-silicon vias.

10. The simulation method according to any one of claims 1-9, characterized in that: The method also includes a result visualization and comparative analysis step, which outputs the simulation results of different physical organization schemes in terms of performance, power consumption, area and key timing parameters in a unified manner, and realizes intuitive comparison between multiple schemes through two-dimensional or three-dimensional charts to assist users in making design decisions.

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