Display panel and display device

Abstract

The invention provides a display panel and a display device, the display panel comprises a display area and a non-display area surrounding the display area, and the non-display area comprises a fan-out area; the fan-out area comprises a plurality of fan-out data lines, the fan-out data lines comprise first fan-out data lines and second fan-out data lines which are arranged on different metal layers, and the pitch of the first fan-out data lines is different from that of the second fan-out data lines. According to the scheme, the screen-to-body ratio of the display panel can be effectively increased.

Description

Technical Field

[0001] This application relates to the field of displays, specifically to a display panel and a display device. Background Technology

[0002] Large-size displays offer advantages over small-size displays in terms of visual experience and business applications. For example, in terms of visual experience, they can enhance user immersion, display more content details, support multitasking, and provide better readability. In business applications, they can make advertising more effective and information display more efficient. Therefore, users are increasingly demanding larger display panels.

[0003] When panel display size is limited, increasing the screen-to-body ratio (STR) can improve the effective display area and enhance the user's visual experience. STR refers to the proportion of the effective display area to the total area of ​​the device's front panel. For display panels of the same size, the narrower the bezel, the higher the STR. In existing display panels, fan-out traces occupy a significant portion of the non-display area, making it difficult to achieve narrow bezel designs. Summary of the Invention

[0004] This application provides a display panel and display device to solve the problem that the fan-out traces occupy a large area of ​​the non-display area, thereby increasing the screen ratio of the display panel and realizing a narrow bezel design for the display panel.

[0005] On one hand, embodiments of this application provide a display panel, the display panel including a display area and a non-display area surrounding the display area, the non-display area including a fan-out area; The fan-out area includes multiple fan-out data lines, which include a first fan-out data line and a second fan-out data line disposed in different metal layers. The pitch of the first fan-out data line is different from that of the second fan-out data line.

[0006] On the other hand, embodiments of this application also provide a display device, including the aforementioned display panel.

[0007] The display panel and display device provided in this application embodiment, through a novel wiring design, place multiple fan-out data lines in the fan-out area on different metal layers, making full use of the pitch capability of different metal layers, reducing the wiring pressure of the data line layer, effectively increasing the number of wiring lines in the fan-out area, and further compressing the fan-out area ratio under the same panel size, thereby increasing the screen ratio of the display panel. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this application; Figure 2 yes Figure 1 A magnified structural diagram of the S1 region in the middle; Figure 3 It is along Figure 2 A schematic diagram of the cross-sectional structure along the A-A' direction; Figure 4 It is along Figure 1 A schematic diagram of the cross-sectional structure along the B-B' direction; Figure 5 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this application; Figure 6 yes Figure 5 A magnified structural diagram of region S2 in the middle; Figure 7 This is a schematic diagram of the connection between the data lines and fan-out data lines corresponding to different sub-pixels in the pixel unit in an embodiment of this application; Figure 8 This is another schematic diagram showing the connection between the data lines and fan-out data lines corresponding to different sub-pixels in the pixel unit in the embodiments of this application; Figure 9 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this application; Figure 10 yes Figure 9 A magnified structural diagram of the S3 region in the middle; Figure 11 This is a schematic diagram of a connection structure between different pixel units and fan-out data lines in the fan-out data line group in an embodiment of this application; Figure 12 This is a schematic diagram illustrating another connection structure between different pixel units and the fan-out data lines in the fan-out data line group in the embodiments of this application. Figure 13 This is a schematic diagram of several distribution structures of fan-out data lines and touch signal lines within one cycle in an embodiment of this application; Figure 14 This is a schematic diagram of a touch signal line structure in an embodiment of this application; Figure 15 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0011] Figure 1 This is a planar structural diagram of a display panel provided in an embodiment of this application. Figure 2 yes Figure 1 A magnified structural diagram of region S1 in the middle. Figure 3 It is along Figure 2 A schematic diagram of the cross-sectional structure along the A-A' direction. Figure 4 It is along Figure 1 A schematic diagram of the cross-sectional structure along the B-B' direction.

[0012] Among them, area S1 is the area where the display area and the non-display area meet. Figure 1 Taking region S1 on the left as an example, Figure 1 The location of region S1 in this application does not impose any limitations on this application.

[0013] Simultaneously refer to Figures 1 to 4 The display panel 100 includes a display area A1 and a non-display area A2 surrounding the display area A1, and the non-display area A2 includes a fan-out area A3.

[0014] Display area A1 includes multiple data lines 21, and fan-out area A3 includes multiple fan-out data lines 22. The multiple data lines 21 are arranged along a first direction D1 and extend along a second direction D2. One end of each fan-out data line 22 is electrically connected to a data line 21, and the other end is electrically connected to a driver chip 30. The driver chip 30 provides data signals to the data lines 21 through the fan-out data lines 22.

[0015] It should be noted that the electrical connection structure between the fan-out data line 22 and the driver chip 30 may vary slightly depending on the integration method of the driver chip 30. For example, in a non-limiting embodiment, a COG (Chip On Glass) package is used, and the driver chip 30 is integrated on a TFT (Thin-Film Transistor) substrate, with the fan-out data line 22 directly connected to the driver chip 30 (e.g., ...). Figure 1(as shown in the figure); or, for example, in another non-limiting embodiment, a COF (Chip OnFilm / Flex) packaging method is used, in which the driver chip 30 is integrated on an FPC (Flexible Printed Circuit), the FPC is bonded to the TFT substrate, and accordingly, the fan-out data line 22 is first connected to the FPC, and then connected to the driver chip 30 through the traces in the FPC.

[0016] It should be noted that the display panel 100 contains a large number of data cables 21 and a large number of fan-out data cables 22. Figure 1 The number of data lines 21 and fan-out data lines 22 shown is merely illustrative and is not intended to limit the scope of this application.

[0017] like Figure 1 As shown, the display area A1 also includes multiple gate lines (or scan lines) 40, which extend along the first direction D1 and are arranged along the second direction D2.

[0018] like Figure 2 As shown in the embodiment of this application, the multiple fan-out data lines 22 include a first fan-out data line 221 and a second fan-out data line 222, which are located in different metal layers. The pitch of the first fan-out data line 221 is different from that of the second fan-out data line 222.

[0019] The pitch refers to the sum of the linewidth of a signal line on the same layer and the spacing between adjacent signal lines. It directly determines the physical resolution of the display panel. A smaller data line pitch allows for more data lines to be laid out on a substrate of the same size, resulting in more column pixels and higher resolution. In advanced array substrates (especially high-resolution display panels), due to the different functions of various metal layers, their main functions, materials, thicknesses, process requirements, and design rules also differ. Consequently, the pitch capability of each metal layer for fabricating signal lines is typically different.

[0020] In some embodiments, the display panel 100 further includes a substrate and a multilayer metal layer located on one side of the substrate, with adjacent metal layers separated by an insulating layer. For example, in some embodiments, the multilayer metal layer includes a first metal layer M1 and a second metal layer M2, with the second metal layer M2 located on the side of the first metal layer M1 away from the substrate. In some embodiments, the first metal layer M1 is a gate metal layer, mainly used to form the gate line 40, requiring high thermal stability and strong adhesion, and is typically made of Mo (molybdenum), W (tungsten), or their alloys. The minimum linewidth and pitch supported are usually larger than those of dedicated wiring layers. The second metal layer M2 is a source / drain metal layer, requiring low resistivity and good ohmic contact characteristics, and is typically made of materials with better conductivity (such as Al-based alloys, copper, etc.). Design rules prioritize optimizing the data line pitch of this layer to achieve the minimum value allowed by the process. Data lines 21 are mainly disposed in the second metal layer M2.

[0021] In some embodiments, the display panel 100 may further include a third metal layer M3 or a higher metal layer, mainly used for global power lines, shielding layers or additional signal wiring layers. In display panels employing embedded touch technology, the M3 layer is also often used to fabricate touch sensing electrodes and / or related traces. The M3 layer needs to have extremely low resistance and the ability to carry large currents. It can use thick metal aluminum-based materials or copper materials with high conductivity, and its minimum pitch may be larger than that of the second metal layer M2.

[0022] The display panel provided in this application embodiment arranges multiple fan-out data lines in the fan-out area on different metal layers. For example, the multiple fan-out data lines can be distributed across three metal layers, or distributed between the second metal layer M2 and the first metal layer M1, or distributed between the second metal layer M2 and the third metal layer M3. While fully utilizing the pitch capabilities of different metal layers, the performance differences between fan-out data lines located on different metal layers are adjusted, reducing the wiring pressure of the data line layer. Compared to placing multiple fan-out data lines on the same layer, the spacing between two adjacent fan-out data lines can be reduced, thereby reducing the area occupied by the fan-out data lines in the fan-out area, effectively increasing the number of traces in the fan-out area, reducing the width of the fan-out area, and further compressing the fan-out area ratio under the same panel size, thereby increasing the screen-to-body ratio of the display panel.

[0023] It should be noted that there are multiple first fan-out data lines 221 and second fan-out data lines 222, and at least part of the second fan-out data lines 222 overlap with the first fan-out data lines 221 in a direction perpendicular to the display panel 100, but not completely. This can prevent the first fan-out data lines 221 and second fan-out data lines 222 from generating overlapping capacitance while increasing the screen ratio, thereby preventing the increased load of the first fan-out data lines 221 and second fan-out data lines 222 from affecting the data signal transmission.

[0024] Reference Figure 4 and Figure 1 For example, the display panel 100 includes a substrate 10, which includes a display area A1 and a non-display area A2. The display area A1 includes a plurality of display thin-film transistors (TFTs) DT. Each TFT DT includes a gate 51, a source 52, a drain 53, and an active layer 54. The gate 51 of the TFT DT and the plurality of gate lines 40 of the display area A1 are located in a first metal layer M1. The source 151 and drain 53 of the TFT DT and the plurality of data lines 21 of the display area A1 are located in a second metal layer M2. A common electrode 60 and a pixel electrode 61 are disposed on the side away from the substrate 10. The pixel electrode 61 is electrically connected to the source 52 (or drain 53) of the TFT DT through a via. Typically, the common electrode 60 and the pixel electrode 61 are conductors of oxide materials, such as ITO (indium tin oxide).

[0025] A first insulating layer 12 is disposed between the first metal layer M1 and the second metal layer M2, and a second insulating layer 13 is disposed between the second metal layer M2 and the third metal layer M3; a third insulating layer 14 is disposed between the first oxide conductor layer OC1 (e.g., pixel electrode 61) and the third metal layer M3. Furthermore, a fourth insulating layer 15 is disposed between the first oxide conductor layer OC1 and the second oxide conductor layer OC2.

[0026] It should be noted that, although in Figure 4 In the structural schematic diagram, the first oxide conductor layer OC1 includes a common electrode 60, and the second oxide conductor layer OC2 includes a pixel electrode 61. However, the embodiments of the present invention are not limited to this. For example, in other embodiments, the first oxide conductor layer may include the pixel electrode 61, and the second oxide conductor layer OC2 may include the common electrode 60.

[0027] In this embodiment of the invention, the common electrode 60 and the pixel electrode 61 can form a lateral electric field, which can control the liquid crystal in the liquid crystal display panel to rotate in order to achieve display.

[0028] It should be noted that the pixel electrode 61 and the common electrode 60 can also be located on the same layer and be insulated from each other. The pixel electrode 61 and the common electrode 60 can serve as the first oxide conductor layer OC1 or the second oxide conductor layer OC2.

[0029] It should be noted that, in Figure 4 In the structure shown, the thin-film transistor (TFT) is a low-temperature polycrystalline silicon (LTPS) TFT, meaning the active layer 54 of the TFT is made of LTPS. The TFT typically employs a top-gate structure, where the gate 51 is located on the side of the active layer 54 furthest from the substrate 10, and a gate insulating layer 11 is disposed between the active layer 54 and the gate 51. However, this embodiment of the invention is not limited to this. In other embodiments, the active layer 54 of the TFT can also be made of amorphous silicon or oxide semiconductor material. When the active layer 54 is an oxide semiconductor, indium gallium zinc oxide (IGZO) can be selected as the active layer. Furthermore, the TFT can also have a bottom-gate structure. For example, when the active layer of the TFT is amorphous silicon or oxide semiconductor, a bottom-gate structure is used, in which case the source and drain can be in direct contact with the active layer.

[0030] Reference Figures 2 to 4 In the structure shown, in some embodiments, the first fan-out data line 221 is located in the first metal layer M1, and the second fan-out data line 222 is located in the second metal layer M2. For example... Figure 4 As shown in (a), data line 21 is connected to the second fan-out data line 222 and both are located in the second metal layer M2, as shown in (a). Figure 4 As shown in (b), data line 21 is located in the second metal layer M2, and the first fan-out data line 221 is located in the first metal layer M1. Data line 21 can be electrically connected to the first fan-out data line 221 through a via. In some embodiments, when data line 21 and the second fan-out data line 222 are located in different metal layers, data line 21 can also be electrically connected to the second fan-out data line 222 through a via.

[0031] Since the first fan-out data line 221 and the second fan-out data line 222 are located on different metal layers, their pitch and linewidth can be different. For example, the first fan-out data line 221 can be located on the first metal layer M1, and the second fan-out data line 222 can be located on the second metal layer M2. The pitch of the first fan-out data line 221 can be greater than that of the second fan-out data line 222, and the linewidth of the first fan-out data line 221 can be greater than that of the second fan-out data line 222. (Reference) Figure 3In the structure shown, the first fan-out data line 221 is located in the first metal layer M1, the second fan-out data line 222 is located in the second metal layer M2, the pitch a1 of the first fan-out data line 221 is greater than the pitch a2 of the second fan-out data line 222, and the line width d1 of the first fan-out data line 221 is greater than the line width d2 of the second fan-out data line 222.

[0032] The first metal layer M1 typically uses metals with high melting points and relatively low resistivity, such as molybdenum (Mo), tungsten (W), molybdenum-niobium alloy (MoNb), or aluminum-based laminates (such as Al / Mo). The second metal layer M2, however, prioritizes low resistivity, often using aluminum (Al), copper (Cu), or their alloys, and is thicker than the first metal layer. This effectively reduces line resistance, RC delay, and voltage drop. By distributing some fan-out data lines across different metal layers, compared to placing them on the same layer, the pitch between the fan-out data lines can be increased. This significantly reduces inter-line parasitic capacitance, minimizes signal interference, and ensures high-quality data signal transmission. Furthermore, a larger pitch means that wider fan-out data line widths can be designed, effectively reducing their resistance and guaranteeing high-quality data signal transmission.

[0033] Additionally, the fan-out area A3 connects the dense data lines in the display area to the wider pins of the driver chip 30. Within the display area A1, the data lines 21 are typically located on the second metal layer M2 with a very small pitch. To guide these dense data lines 21 to the driver chip 30, some data lines are usually skipped, using another metal layer to cross or bypass them to avoid crossing at the exit point. By placing some of the fan-out data lines on the first metal layer M1, the connection between the skipped data lines 21 and the fan-out data lines is also facilitated. In this embodiment, a layered routing strategy is adopted for the multiple fan-out data lines in the fan-out area A3. That is, the dense fan-out data lines that originally need to be set on the same layer are distributed to two or more layers. This allows the actual routing pitch on each layer to be widened. The fan-out data lines arranged on the first metal layer M1 and the second metal layer M2 can each follow the pitch capability of their respective metal layers. Through partial overlap between layers and through vias, they can be electrically connected to the data lines in the display area. This can break through the single-layer process limit, reduce the area occupied by the fan-out data lines in the fan-out area, thereby effectively reducing the width of the fan-out area and increasing the screen ratio.

[0034] Figure 4 Using an LCD (Liquid Crystal Display) panel as an example, this is illustrated in the following way. Figure 1 The cross-sectional structure along the B-B' direction in this application is also applicable to other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels, which will not be listed here.

[0035] In some embodiments, the display panel 100 further includes a pixel array and multiple data lines located in the display area A1; the pixel array includes multiple pixel units, and the pixel units include multiple sub-pixels; the data lines are arranged corresponding to the sub-pixel columns and are connected to the fan-out data lines 22.

[0036] In one non-limiting embodiment, the multiple data lines 21 corresponding to a pixel unit may include a first data line, a second data line, and a third data line. Along the arrangement direction of the data lines 21, the second data line is located between the first and third data lines. For the three data lines corresponding to the same pixel unit, the second data line is connected to one of the first fan-out data line 221 and the second fan-out data line 222, and at least one of the first and third data lines is connected to the other of the first fan-out data line 221 and the second fan-out data line 222. (Refer to the following...) Figures 5 to 8 This needs to be explained.

[0037] Reference Figure 5 , Figure 5 This illustration shows another planar structure diagram of the display panel provided in an embodiment of this application.

[0038] In this example, the display panel 100 also includes a pixel array located in the display area A1, the pixel array comprising a plurality of pixel units 80.

[0039] In some embodiments, pixel unit 80 may include a plurality of sub-pixels, such as Figure 5 Each pixel unit 80 includes three sub-pixels: red (R), green (G), and blue (B). For ease of description, these will be referred to as R sub-pixels, G sub-pixels, and B sub-pixels below. Each color sub-pixel has an independent data line, and all sub-pixels in the same row of pixel units 80 typically share a single gate line 40. In some special application designs, the R, G, and B sub-pixels in the same row can also be controlled by two or more independent gate lines. Moreover, in some special design architectures, the R, G, and B sub-pixels can also be irregularly vertically aligned, with the same gate line controlling a row of sub-pixels of a specific color. This application does not limit the scope of this application and all are applicable. For ease of description, the following will refer to... Figure 5 The following example illustrates the arrangement of R, G, and B subpixels in a neat, vertically aligned manner.

[0040] like Figure 5As shown, data lines 21 are configured corresponding to sub-pixel columns. That is, data lines 21 extend along the column direction, with each sub-pixel in the same column corresponding to one data line 21. Each data line 21 is connected to a fan-out data line 22. Multiple data lines corresponding to a pixel unit 80 can also be considered as a single data line unit. Data lines corresponding to different pixel units 80 can be connected to fan-out data lines located on different metal layers, and multiple data lines corresponding to the same pixel unit 80 can also be connected to fan-out data lines located on different metal layers.

[0041] like Figure 6 As shown, is Figure 5 A magnified structural diagram of region S2. The multiple data lines corresponding to pixel units 801 and 802 include a first data line 211, a second data line 212, and a third data line 213. The first data line 211 connects to R sub-pixels in the same column, the second data line 212 connects to G sub-pixels in the same column, and the third data line 213 connects to B sub-pixels in the same column. Along the data line arrangement direction, i.e., the first direction D1, the second data line 212 is located between the first data line 211 and the third data line 213.

[0042] In some embodiments, the second data line 212 corresponding to each pixel unit may be connected to one of the first fan-out data line 221 or the second fan-out data line 222, and at least one of the first data line 211 and the third data line 213 may be connected to the fan-out data line located in another film layer.

[0043] for example Figure 6 As shown, the second data line 212 in the first pixel unit 801 is connected to a first fan-out data line 221-12. The first data line 211 and the third data line 213 in the first pixel unit 801 are respectively connected to second fan-out data lines 222-11 and 222-13 located in another film layer. The second data line 212 in the second pixel unit 802 is connected to a second fan-out data line 222-22. The third data line 213 in the second pixel unit 802 is connected to a second fan-out data line 222-23 in the same film layer. The first data line 211 in the second pixel unit 802 is connected to a first fan-out data line 221-21 in a different film layer.

[0044] Figure 7 and Figure 8 The diagrams show a connection diagram of the data lines and fan-out data lines corresponding to different sub-pixels in the pixel unit in the embodiments of this application.

[0045] exist Figure 7 and Figure 8In this configuration, the R sub-pixel, G sub-pixel, and B sub-pixel are respectively connected to the first data line 211, the second data line 212, and the third data line 213. Correspondingly, the first data line 211, the second data line 212, and the third data line 213 are arranged along a first direction D1 and extend along a second direction D2. The second data line 212 is located between the first data line 211 and the third data line 213. In other embodiments, the second data line may be located on the same side of the first data line 211 and the third data line 213, and the second data line may be connected to the G sub-pixel.

[0046] Of the three data lines corresponding to pixel unit 80, the second data line 212 can be connected to a first fan-out data line 221 or a second fan-out data line 222.

[0047] Furthermore, for the three data lines corresponding to the three sub-pixels R, G, and B in the same pixel unit 80, the fan-out data lines connected to the data line 212 corresponding to the G sub-pixel and the fan-out data lines connected to the data lines corresponding to other pixels (R sub-pixels and / or B sub-pixels) can be set in different metal layers with the G sub-pixel as the center, which can better ensure the uniformity of pixel display.

[0048] like Figure 7 As shown, among the three data lines corresponding to the same pixel unit 80, the second data line 212 is connected to a first fan-out data line 221, and any one or two of the first data line 211 and the third data line 213 can be connected to the second fan-out data line 222. Figure 7 In the example shown, the first data line 211 and the third data line 213 are connected to the second fan-out data lines 222-1 and 222-2, respectively.

[0049] Figure 8 In the example shown, the first data line 211 is connected to a first fan-out data line 221, and the third data line 213 is connected to a second fan-out data line 222-3.

[0050] It should be noted that the connection patterns of multiple data lines in different pixel units 80 along the arrangement direction D1 with the fan-out data lines of different metal layers may be the same or different, and this application embodiment does not limit this.

[0051] In some embodiments, referencing Figure 9 and Figure 10 , Figure 9 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this application. Figure 10 yes Figure 9 A magnified structural diagram of the S3 region.

[0052] In this example, the display panel 100 also includes a pixel array located in the display area A1, the pixel array comprising multiple pixel units, such as... Figure 9 As shown, along the arrangement direction of the data line 21, the pixel array may include a first pixel unit 81, a second pixel unit 82 and a third pixel unit 83, with the second pixel unit 82 located between the first pixel unit 81 and the third pixel unit 83.

[0053] Each pixel unit includes three sub-pixels. The second data line of the second pixel unit 82 is connected to one of the first fan-out data line 221 and the second fan-out data line 222. The second data line of at least one of the first pixel unit 81 and the third pixel unit 83 is connected to the other of the first fan-out data line 221 and the second fan-out data line 222.

[0054] like Figure 10 As shown, each pixel unit contains three sub-pixels: an R sub-pixel, a G sub-pixel, and a B sub-pixel. The R, G, and B sub-pixels in the first pixel unit 81 are connected to the first data line 811, the second data line 812, and the third data line 813, respectively. The R, G, and B sub-pixels in the second pixel unit 82 are connected to the first data line 821, the second data line 822, and the third data line 823, respectively. The R, G, and B sub-pixels in the third pixel unit 83 are connected to the first data line 831, the second data line 832, and the third data line 833, respectively.

[0055] The second data line 822 of the second pixel unit 82 is connected to a second fan-out data line 222-822, the second data line 812 of the first pixel unit 81 is connected to a first fan-out data line 221-812, and the second data line 832 of the third pixel unit 83 is connected to a second fan-out data line 222-832.

[0056] Additionally, the first data line 811 of the first pixel unit 81 is connected to a first fan-out data line 221-811, and the third data line 813 is connected to a second fan-out data line 222-813. The first data line 821 of the second pixel unit 82 is connected to a first fan-out data line 221-821, and the third data line 823 is connected to a second fan-out data line 222-823. The first data line 831 of the third pixel unit 83 is connected to a first fan-out data line 221-831, and the third data line 833 is connected to a first fan-out data line 221-833.

[0057] In the above embodiments, at least one fan-out data line corresponding to the G sub-pixel of each pixel unit is located on a different metal layer from the fan-out data lines corresponding to the G sub-pixels of the pixel units adjacent to that pixel unit. Since the human eye is more sensitive to brightness changes in green sub-pixels, when the fan-out data lines are respectively set on two metal layers, the data lines connected to the G sub-pixels are arranged alternately according to their direction of arrangement. This avoids situations where fan-out data lines connecting green sub-pixels in one region are located on the same metal layer, while fan-out data lines connecting green sub-pixels in another region are located on a different metal layer, thus preventing display mura (cloudiness).

[0058] The scheme in this application embodiment can be applied to different display panels. It can be implemented by distributing fan-out data lines connected to data lines corresponding to different pixel units across different metal layers, or by distributing fan-out data lines connected to data lines corresponding to different sub-pixels across different metal layers. Fan-out data lines located on different metal layers can have different pitches and linewidths, adapting to the process requirements of different metal layers. Compared to placing them on the same layer, increasing the pitch between fan-out data lines can significantly reduce inter-line parasitic capacitance, decrease signal interference, and ensure data signal transmission quality. Furthermore, a larger pitch means that wider fan-out data line widths can be designed, effectively reducing their resistance and ensuring data signal transmission quality.

[0059] In some embodiments, one pixel unit corresponds to one fan-out data line group; the fan-out data line group is a fan-out data line connected to the data line corresponding to one pixel unit 80; the fan-out data line group corresponding to one pixel unit 80 has a different arrangement pattern of the metal layer where the fan-out data lines are located than at least one of the fan-out data line groups corresponding to two pixel units 80 adjacent to that pixel unit in the data line arrangement direction. The following is in conjunction with... Figure 11 Here are some examples to illustrate this.

[0060] like Figure 11 As shown in the illustration, in this embodiment, each pixel unit includes three sub-pixels, each sub-pixel corresponds to a data line, and each pixel unit corresponds to a fan-out data line group. For clarity, in... Figure 11 The individual sub-pixels are not shown; only the fan-out data line groups corresponding to each sub-pixel are displayed. For example... Figure 11 As shown, pixel unit 801 corresponds to fan-out data line group 201, pixel unit 802 corresponds to fan-out data line group 202, and pixel unit 803 corresponds to fan-out data line group 203. Each fan-out data line group consists of three fan-out data lines connected to the three data lines corresponding to one pixel unit.

[0061] In some embodiments, the fan-out data line group corresponding to a pixel unit 80 has a different arrangement pattern of the metal layer where the fan-out data lines are located than at least one of the fan-out data line groups corresponding to two pixel units 80 adjacent to that pixel unit in the data line arrangement direction. For example... Figure 11 As shown, according to the arrangement order of the first data line, the second data line, and the third data line corresponding to the pixel unit, the fan-out data lines in the fan-out data line group 201 corresponding to the pixel unit 801 are set as follows: first fan-out data line 221-1, second fan-out data line 222-1, first fan-out data line 221-2; the fan-out data lines in the fan-out data line group 202 corresponding to the pixel unit 802 are set as follows: second fan-out data line 222-2, second fan-out data line 222-3, first fan-out data line 221-3; and the fan-out data lines in the fan-out data line group 203 corresponding to the pixel unit 803 are set as follows: second fan-out data line 222-4, first fan-out data line 221-4, first fan-out data line 221-5. The arrangement of the metal layers of the three fan-out data lines in the fan-out data line group 203, which is adjacent to the right side of the fan-out data line group 202, is different from that of the three fan-out data lines in the fan-out data line group 201. Specifically, the second fan-out data line 222-4 in the fan-out data line group 203 is connected to the first data line 211 in the pixel unit 803, the first fan-out data line 221-4 is connected to the second data line 212 in the pixel unit 803, and the first fan-out data line 221-5 is connected to the third data line 213 in the pixel unit 803.

[0062] It should be noted that, Figure 11 This is merely an illustrative description of the arrangement of the metal layers containing the fan-out data lines in adjacent fan-out data line groups. Other distribution patterns are also possible, and this embodiment does not limit them.

[0063] In some embodiments, multiple fan-out data line groups can be considered as a cycle. Within the same cycle, at least two fan-out data line groups have different metal layer configurations for their fan-out data lines, while adjacent cycles have the same metal layer configuration. The following is a combination of... Figure 12 This needs to be explained.

[0064] Reference Figure 12 For clarity, in Figure 12 The sub-pixels within each pixel unit are omitted. In this embodiment, one pixel unit corresponds to one fan-out data line group, and one pixel unit includes three sub-pixels. Fan-out data line groups 1-201, 1-202, 1-203, 2-201, 2-202, and 2-203 correspond to pixel units 1-801, 1-802, 1-803, 2-801, 2-802, and 2-803, respectively.

[0065] To facilitate cabling, multiple fan-out data line groups can be grouped into a single cycle. Within the same cycle, at least two groups of fan-out data lines should have different metal layer configurations, while adjacent cycles should have the same configuration for their fan-out data lines. For example... Figure 13 As shown, the three fan-out data line groups form one cycle. Figure 13 Fan-out data line groups 1-201, 1-202, and 1-203 constitute one cycle, denoted as cycle T1. Fan-out data line groups 2-201, 2-202, and 2-203 constitute another adjacent cycle, denoted as cycle T2. Within these two cycles, the metal layer arrangement pattern for each fan-out data line group is the same. However, for each cycle, the metal layer arrangement pattern for at least two fan-out data line groups within that cycle differs. For example... Figure 12 In the example shown, within period T1, the three fan-out data lines in fan-out data line group 1-201 are a second fan-out data line 222 located in the second metal layer M2 and two first fan-out data lines 221 located in the first metal layer M1, respectively. The three fan-out data lines in fan-out data line group 1-202 are two second fan-out data lines 222 located in the second metal layer M2 and one first fan-out data line 221 located in the first metal layer M1, respectively. The three fan-out data lines in fan-out data line group 1-203 are a second fan-out data line 222 located in the second metal layer M2 and two first fan-out data lines 221 located in the first metal layer M1, respectively. The metal layer configuration of fan-out data line group 2-201 within period T2 is the same as that of fan-out data line group 1-201 within period T1. Similarly, the metal layer configuration of fan-out data line group 2-202 within period T2 is the same as that of fan-out data line group 1-202 within period T1. The metal layer configuration of fan-out data line group 2-203 within period T2 is the same as that of fan-out data line group 1-203 within period T1.

[0066] By using the above-mentioned periodic and regular distribution, the design complexity can be reduced while ensuring that the data lines of each fan-out are evenly distributed in different metal layers.

[0067] It should be noted that in this embodiment, the first fan-out data line 221 and the data line 21 connected to it are located in different metal layers. For example, the first fan-out data line 221 is located in the first metal layer M1, and the data line connected to it is located in the second metal layer M2. Furthermore, within the same cycle, the number of first fan-out data lines 221 can be less than or equal to the number of second fan-out data lines 222. By placing fan-out data lines in the second metal layer M2 within a limited area, the cross-layer connections with data lines located in the second metal layer M2 can be reduced, facilitating wiring design and reducing its complexity. Additionally, since the pitch and linewidth of the first fan-out data lines located in the first metal layer M1 can be greater than those of the second fan-out data lines located in the second metal layer M2, when the number of fan-out data lines in the first metal layer M1 and the second metal layer M2 are the same, the space occupied by the same number of fan-out data lines in the first metal layer M1 is greater than the space occupied in the second metal layer M2. Therefore, by making the number of first fan-out data lines 221 less than or equal to the number of second fan-out data lines 222, the space occupied by the fan-out data lines in the first metal layer M1 can be reduced, thus reducing the width of the first metal layer M1 and consequently reducing the width of the overall border. By setting the above periodic pattern, the layered distribution of the fan-out data lines is made to cycle periodically, which can keep the pixel array display uniformity and ensure display effect; moreover, it can simplify the complexity of design and wiring process and improve design efficiency.

[0068] Reference Figure 1 and Figure 4 As shown, in some embodiments, the display panel 100 may further include touch electrodes and touch signal lines connected to the touch electrodes. The touch electrodes are located in the display area A1, and the touch signal lines extend from the display area A1 to the fan-out area A3 and are connected to the driver chip 30. The touch signal lines are used to transmit touch driving signals sent by the driver chip 30, and the touch electrodes are used to detect the touch position under the action of the touch driving signals.

[0069] like Figure 4 As shown, the touch electrode 62 can be disposed in the first oxide conductor layer OC1, and multiple touch signal lines 63 connected to the touch electrode can be disposed in the third metal layer M3. In some embodiments, the common electrode 60 can be reused as the touch electrode 62, and the touch electrode 62 is electrically connected to the touch signal lines 63 through vias.

[0070] like Figure 4 As shown, the first fan-out data line 221 and the data line 21 connected to it are located in different metal layers. The first fan-out data line 221 located in the first metal layer M1 and the data line 21 located in the second metal layer M2 are connected through vias, thereby enabling the first fan-out data line 221 in the first metal layer M1 to provide data signals to the data line 21 in the second metal layer M2.

[0071] Accordingly, the distribution structure of the fan-out data lines and touch signal lines within a period T can include various cases, for example, referring to Figure 13 As shown in the example, the distribution structure of the fan-out data lines and touch signal lines within one cycle T can include at least two of the following: (1) Along the data line arrangement direction D1, between the two data lines 21-1 and 21-2 that are respectively connected to the two adjacent first fan-out data lines 221-1 and 221-2, there is a data line 21-3 connected to the second fan-out data line 222, such as Figure 13 As shown in (a).

[0072] (2) Along the data line arrangement direction D1, the two data lines 21-1 and 21-2 that are connected to the two adjacent first fan-out data lines 221-1 and 221-2 respectively include a data line 21-3 connected to the second fan-out data line 222 and a touch line 90, such as Figure 13 As shown in (b). The connection method between the touch line 90 extending to the fan-out area A3 and the driver chip 30 is not limited in this embodiment. It should be noted that the positions of the data line 21-3 and the touch line 90 are not limited in this embodiment. Along the data line arrangement direction D1, the touch line 90 can also be located to the left of the data line 21-3.

[0073] (3) Along the data line arrangement direction D1, the two data lines 21-1 and 21-2 that are respectively connected to the two adjacent first fan-out data lines 221-1 and 221-2 include two data lines 21-3 and 21-4 that are respectively connected to the two second fan-out data lines 222-1 and 222-2, and a touch line 90, such as Figure 13 As shown in (c). It should be noted that the embodiments of this application do not limit the positions of data line 21-3, touch line 90 and data line 21-4, and the positions of the three can be arbitrarily interchanged.

[0074] like Figure 14 As shown, in some embodiments, the touch signal line 90 may include a first part 901 and a second part 902 connected to each other. The first part 901 is located in the display area A1 and is connected to the touch electrode 62 through a contact hole, and the second part 902 is located in the fan-out area A3.

[0075] The second part 9021 of the touch signal line 90 can be located on the same metal layer as the first fan-out data line 221, such as Figure 14 As shown in (a), and / or, the second part 9022 of the touch signal line 90 may be located on the same metal layer as the second fan-out data line 222, as shown in (a). Figure 14 As shown in (b).

[0076] Since touch signal lines are typically wider than data lines, placing multiple touch signal lines close together in the fan-out area A3 would create a localized, high-density, wide cluster of lines, making it extremely difficult to weave other lines between them and drastically increasing the overall width of the area. Therefore, in some embodiments, at least one fan-out data line 22 is placed between the second portions 902 of adjacent touch signal lines 90. This effectively fills the gaps between the touch lines, achieving a uniform distribution of the lines, avoiding localized congestion, and accommodating all necessary lines without increasing the total width of the fan-out area A3. Simultaneously, it improves touch performance and display quality, reducing the risk of mutual interference between the two.

[0077] Accordingly, embodiments of this application also provide a display device, such as... Figure 15 The diagram shown is a structural schematic of a display device provided in an embodiment of this application.

[0078] The display device 200 includes the aforementioned display panel 100. The display device 200 can be a mobile phone, computer, television, smart wearable device, etc., and this application embodiment does not limit it.

[0079] It should be understood that in the description of the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document indicates that the related objects before and after it have an "or" relationship.

[0080] Furthermore, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" used to indicate orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings and are only for the purpose of facilitating the description of the embodiments of this application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0081] Furthermore, the terms "first" and "second" are used for descriptive purposes only, merely to indicate and distinguish the described objects, and do not imply any order. They should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated, and do not constitute any limitation on the embodiments of this application. Therefore, a feature defined with "first" and "second" may explicitly or implicitly include at least one of those features. In the description of the embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0082] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0083] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0084] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0085] Although embodiments of this application have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting this application. Any person skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments without departing from the spirit and scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area surrounding the display area, the non-display area including a fan-out area; The fan-out area includes multiple fan-out data lines, which include a first fan-out data line and a second fan-out data line disposed in different metal layers. The pitch of the first fan-out data line is different from that of the second fan-out data line.

2. The display panel according to claim 1, characterized in that, The display panel further includes a substrate and a multilayer metal layer located on one side of the substrate, wherein adjacent metal layers of the multilayer metal layer are spaced apart by an insulating layer. The multilayer metal layer includes a first metal layer and a second metal layer, wherein the second metal layer is located on the side of the first metal layer away from the substrate; The display area includes gate lines and data lines, wherein the gate lines are located in a first metal layer and the data lines are located in a second metal layer; The first fan-out data line is located in the first metal layer, and the second fan-out data line is located in the second metal layer; The pitch of the first fan-out data line is greater than the pitch of the second fan-out data line.

3. The display panel according to claim 1, characterized in that, The line width of the first fan-out data line is different from that of the second fan-out data line.

4. The display panel according to claim 3, characterized in that, The display panel further includes a substrate and a multilayer metal layer located on one side of the substrate, wherein adjacent metal layers of the multilayer metal layer are spaced apart by an insulating layer. The multilayer metal layer includes a first metal layer and a second metal layer, wherein the second metal layer is located on the side of the first metal layer away from the substrate; The display area includes gate lines and data lines, wherein the gate lines are located in a first metal layer and the data lines are located in a second metal layer; The first fan-out data line is located in the first metal layer, and the second fan-out data line is located in the second metal layer; The width of the first fan-out data line is greater than the width of the second fan-out data line.

5. The display panel according to claim 1, characterized in that, There are multiple first fan-out data lines and multiple second fan-out data lines, and at least a portion of the second fan-out data lines overlap with the first fan-out data lines but not completely overlap in a direction perpendicular to the display panel.

6. The display panel according to claim 1, characterized in that, The display panel further includes: a pixel array and multiple data lines located in the display area; the pixel array includes multiple pixel units, and the pixel unit includes multiple sub-pixels; the data lines are arranged corresponding to the sub-pixel columns and are connected to the fan-out data lines; The multiple data lines corresponding to the pixel unit include a first data line, a second data line, and a third data line. Along the arrangement direction of the data lines, the second data line is located between the first data line and the third data line. For the same pixel unit corresponding to the data line, the second data line is connected to one of the first fan-out data line and the second fan-out data line, and at least one of the first data line and the third data line is connected to the other of the first fan-out data line and the second fan-out data line.

7. The display panel according to claim 6, characterized in that, Along the arrangement direction of the data lines, the pixel array includes a first pixel unit, a second pixel unit, and a third pixel unit, wherein the second pixel unit is located between the first pixel unit and the third pixel unit; The second data line of the second pixel unit is connected to one of the first fan-out data line and the second fan-out data line, and the second data line of at least one of the first pixel unit and the third pixel unit is connected to the other of the first fan-out data line and the second fan-out data line.

8. The display panel according to claim 6, characterized in that, One pixel unit corresponds to one fan-out data line group; the fan-out data line group is the fan-out data line connected to the data line corresponding to one pixel unit; the fan-out data line group corresponding to one pixel unit has a different arrangement pattern of the metal layer of the fan-out data line than at least one of the fan-out data line groups corresponding to two pixel units adjacent to the pixel unit in the data line arrangement direction.

9. The display panel according to claim 6, characterized in that, One pixel unit corresponds to one fan-out data line group; the fan-out data line group is the fan-out data line connected to the data line corresponding to one pixel unit; The multiple fan-out data line groups constitute a cycle. Within the same cycle, at least two fan-out data line groups have different settings for the metal layers on which their fan-out data lines are located, while adjacent cycles have the same settings for the metal layers on which their fan-out data lines are located.

10. The display panel according to claim 9, characterized in that, The display panel further includes: touch electrodes and touch signal lines connected to the touch electrodes; the touch electrodes are located in the display area, and the touch signal lines extend from the display area to the fan-out area; The first fan-out data line and the data line connected to it are located in different metal layers; The period includes at least two of the following: Along the arrangement direction of the data lines, between two data lines that are respectively connected to the two adjacent first fan-out data lines, there is a data line connected to the second fan-out data line. Along the arrangement direction of the data lines, between two data lines respectively connected to the two adjacent first fan-out data lines, there is a data line connected to the second fan-out data line and a touch signal line, and... Along the arrangement direction of the data lines, the two data lines that are respectively connected to the two adjacent first fan-out data lines include two data lines that are respectively connected to the two second fan-out data lines and one touch signal line.

11. The display panel according to claim 9, characterized in that, The first fan-out data line and the data line connected to it are located in different metal layers; In the same cycle, the number of the first fan-out data lines is less than the number of the second fan-out data lines.

12. The display panel according to any one of claims 1 to 11, characterized in that, The display panel further includes: a touch electrode and a touch signal line connected to the touch electrode; the touch electrode is located in the display area, and the touch signal line includes a first part and a second part connected to each other, the first part is located in the display area and is connected to the touch electrode through a contact hole, and the second part is located in the fan-out area; The second part of the touch signal line is located on the same metal layer as the first fan-out data line, and / or the second part of the touch signal line is located on the same metal layer as the second fan-out data line.

13. The display panel according to claim 12, characterized in that, There is at least one fan-out data line between the second portions of adjacent touch signal lines.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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