Hybrid package system and its circuit design method

Abstract

This invention relates to the field of semiconductor packaging technology, and particularly to a hybrid packaging system and its circuit design method. The system includes a substrate, at least one photonic chip, and at least two electronic chips. The electronic chips are encapsulated with a molding compound, and their pads are connected via either type I or type II circuits; wherein type I circuits have more turning points than type II circuits. The photonic chip and electronic chips are connected by a bonding structure. The system molding compound encapsulates the photonic chip, electronic chips, and bonding structure to form a system encapsulation area. This system routes the circuits onto the electronic chips, reducing the wiring burden on the photonic chips. Simultaneously, the circuit design method, for both type I and type II circuits in the hybrid packaging system, uses evaluation metrics to quantitatively analyze the pad area, dynamically matching circuit types to ensure both communication quality and consistent wiring processes, thereby reducing manufacturing complexity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a hybrid packaging system and its circuit design method. Background Technology

[0002] Semiconductor packaging commonly uses leadframes and resin PCB substrates as carrier materials. The standard process flow includes three main steps: chip mounting, wire bonding, and epoxy resin encapsulation. Wire bonding is the core step in achieving electrical connection between the chip pads and the bonding area on the substrate. Wire bonding often involves various routing methods, resulting in multiple trace paths, and different trace paths affect communication quality. Since traces are essentially signal transmission channels, path length, direction, surrounding media, and return path differences all alter communication stability. Changes in impedance, loss, crosstalk, radiated interference, timing, and grounding have a particularly significant impact on high-speed communications (USB, Ethernet, RF, differential signals, high-speed buses).

[0003] Chinese patent document CN115361787A discloses a PCB trace design method, a PCB trace design and processing method, a PCB, a PCB trace design device, a PCB trace design equipment, and a computer-readable storage medium. When a target signal line with a crosstalk value exceeding a crosstalk threshold exists in the initial PCB file, the design information of that target signal line is changed to a flip-design on the PCB surface, resulting in an optimized PCB file. However, this prior art exacerbates far-end crosstalk through stepped wave windings, degrades the signal-to-noise ratio with long parallel segments, and only applies to differential traces on the same layer, not supporting layer-switching or cross-segment trace scenarios.

[0004] Currently, when multiple optoelectronic chips are included in the same packaging system, problems such as high wiring density, poor signal integrity, and low process compatibility arise. Especially in high-integration scenarios, photonic chips, due to their stringent requirements for optical path accuracy, are unable to undertake complex electrical connection tasks. Furthermore, traditional electronic chip wiring strategies do not fully consider co-optimization with photonic devices, resulting in limited overall system performance. Summary of the Invention

[0005] The purpose of this invention is to provide a hybrid packaging system and its circuit design method, which can maintain the consistency of the process as much as possible while ensuring communication quality. That is, to balance the difficulty of wiring process (such as consistency) and the requirements of communication quality, while improving the strength of the packaging structure and the signal transmission efficiency, and reducing cost and process difficulty.

[0006] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution: A first aspect of the present invention is to provide a hybrid packaging system, including a substrate, the hybrid packaging system further comprising: At least one photonic chip; At least two electronic chips, the outer side of which is covered with chip molding compound, and the pads of the electronic chips are connected by a type I circuit or a type II circuit; wherein the type I circuit has more turning points than the type II circuit. The photonic chip and the electronic chip are connected by a bonding structure; A system molding compound, which wraps around the outside of the photonic chip, the electronic chip, and the bonding structure to form a system molding area; The system has a reinforcing layer in the encapsulation area to enhance the strength of the hybrid packaging system; The substrate is located below the encapsulation area of ​​the system.

[0007] The above technical solution involves first encapsulating the electronic chip, then setting up the circuitry to connect to the photonic chip, and finally encapsulating the entire system. This approach effectively enlarges the physical spacing of the electronic chip's circuitry, facilitating better interfacing with the photonic chip (e.g., dispersing dense connection points). Furthermore, arranging complex circuitry (e.g., RDL circuitry) on the electronic chip reduces the wiring burden on the photonic chip. Simultaneously, the introduction of a reinforcement layer enhances the strength of the electronic chip, improving the overall reliability of the packaging structure.

[0008] Preferably, the reinforcing layer is disposed between the photonic chip and the electronic chip. A first side of the reinforcing layer is connected to the photonic chip via a first bonding structure, and a second side of the reinforcing layer is connected to the electronic chip via a second bonding structure, thereby electrically connecting the photonic chip and the electronic chip. The reinforcing layer between the photonic chip and the electronic chip helps maintain the stability of the bonding interface, preventing delamination or breakage due to external forces or temperature changes during subsequent processes or use. Encapsulating them together provides external protection and, in conjunction with the reinforcing layer, further optimizes the internal stress distribution, ensuring the integrity and consistency of the signal transmission path.

[0009] Preferably, the reinforcing layer is provided with a connecting through hole, and the first bonding structure and the second bonding structure are electrically connected through the connecting through hole.

[0010] Preferably, the connecting via is a TMV via.

[0011] Preferably, the reinforcing layer is disposed on both sides of the electronic chip.

[0012] Preferably, the reinforcing layer includes a first reinforcing sheet and a second reinforcing sheet, which are respectively disposed on both sides of the electronic chip. A first heat dissipation area is formed between the first reinforcing sheet and the system molding area, and a second heat dissipation area is formed between the second reinforcing sheet and the system molding area. Correspondingly, a first type of heat dissipation portion is provided at intervals within both the first and second heat dissipation areas, and a first insulating portion is provided between the first type of heat dissipation portion and the inner surface of the system molding area. A second type of heat dissipation portion is provided on both the first and second reinforcing sheets. Providing heat dissipation portions can improve the system's heat dissipation performance, effectively reduce the temperature rise of the chip under high-frequency operating conditions, thereby improving the long-term stability and reliability of the system.

[0013] Preferably, the second type of heat dissipation part is made of insulating material or metal material; the first type of heat dissipation part is made of metal material.

[0014] Preferably, when the second type of heat dissipation part is made of metal material, the second type of heat dissipation part is disposed through the first silicon bridge and the second silicon bridge; and both ends of the second type of heat dissipation part are provided with a second insulating part.

[0015] Preferably, the metal material is a copper pillar, a gold pillar, a copper / nickel / gold alloy pillar, a titanium / copper pillar, or a copper / gold alloy pillar.

[0016] Preferably, the insulating material is photosensitive polyimide PSPI, benzocyclobutene BCB, or epoxy photosensitive medium DryFilm; the insulating material covers the sidewalls and bottom of the metal material.

[0017] Preferably, the insulating material is an inorganic passivation layer SiO2 / Si3N4, which is disposed at the bottom of the metal material.

[0018] Preferably, the metal material is copper.

[0019] Preferably, the reinforcing layer is a silicon wafer or a silicon bridge.

[0020] Preferably, the two electronic chips are a TIA electronic chip and a DRV electronic chip, both of which are arranged horizontally. That is, the TIA electronic chip and the DRV electronic chip are not stacked vertically.

[0021] A second aspect of the present invention is to provide a circuit design method applied to the hybrid packaging system described in the first aspect of the present invention, the specific steps of the method including: S1, Select at least one pad area as the current pad area; S2, calculate the pad density of the current pad area and the communication lower limit of the current pad area; S3, generate evaluation metrics based on the pad density and the communication lower limit; The formula is: I = aX + bY; Where X is the density score, a is the pad density score weighting coefficient; Y is the communication score, and b is the communication lower limit weighting coefficient. Among them, the higher the density, the smaller X is; the lower the communication lower limit, the smaller Y is. S4, when the evaluation index is less than or equal to the set first evaluation threshold, a type I line is configured for connection of the pad area; when the evaluation index is greater than or equal to the set second evaluation threshold, a type II line is configured for connection of the pad area.

[0022] The pad area can be divided according to functional areas.

[0023] The above technical solution, targeting Category I and Category II lines in hybrid packaging systems, uses evaluation metrics to quantitatively analyze pad areas and dynamically match line types. This approach balances communication quality with consistent routing processes, thereby reducing manufacturing complexity. While shorter paths offer higher communication quality, they also have shorter lifespans. Longer paths offer longer lifespans but slower communication and more complex processes. Therefore, this method effectively differentiates routing requirements for different pad areas by introducing evaluation metrics and threshold judgment mechanisms for pad density and communication lower limits. For high-density pad areas or areas with high communication quality requirements, Category II lines with shorter lines and lower signal loss are prioritized. In areas with lower density or wider communication tolerance, Category I lines with more turning points are allowed to improve routing flexibility. Furthermore, for high-density pad areas, even with limited space, if communication requirements are low, Category I lines can still be used to achieve reliable connections through their higher routing flexibility. Conversely, for low-density areas undertaking critical high-speed signal transmission tasks, Category II lines are prioritized to ensure signal integrity. This method strikes a balance between routing consistency and communication quality, selecting the optimal approach. It effectively avoids the resource waste or performance bottlenecks caused by the "one-size-fits-all" routing strategy in traditional designs, enabling refined control of the interconnect structure within the packaged system. This design method dynamically selects the routing type based on the local characteristics of the pad area, satisfying communication quality requirements while considering manufacturing feasibility and yield control, thereby reducing costs and process complexity.

[0024] Preferably, the method further includes step S5, where when the evaluation index is greater than a set first evaluation threshold and less than a set second evaluation threshold, the surrounding area is linked to assist decision-making so that the circuit type of the current pad area and the pad areas of the surrounding area remain consistent in process.

[0025] Preferably, the method further includes step S6, which calculates the evaluation index I of multiple neighboring pad areas in the surrounding area, taking the current pad area as the center point. pBased on the calculated evaluation index I p Step S4 determines whether the evaluation index for the adjacent pad area is configured as either Category I or Category II circuitry. Alternatively, step S5 can be executed to connect to surrounding areas for decision support.

[0026] In practical implementation, the coverage area (such as area or quantity) of the surrounding region can be customized. For example, when the overall chip density varies drastically (large standard deviation), the coverage area of ​​the surrounding region can be reduced. Alternatively, when the overall chip density is high, the RDL routing area should cover more of the surrounding region to avoid sporadic non-RDL via areas, i.e., expand the coverage area of ​​the surrounding region. This method supports multi-level dynamic adjustment strategies, extending from a single pad area to co-optimization of the surrounding region, further improving the signal integrity and production yield of the overall packaging system.

[0027] Preferably, the peripheral area auxiliary decision-making is as follows: the configuration of the current pad area or adjacent pad area as a Class I or Class II pad area is determined by the ratio of the number of Class I or Class II pads configured in multiple adjacent pad areas of the peripheral area. By introducing the peripheral area auxiliary decision-making mechanism, when the evaluation index is in the middle range of the evaluation threshold, the line configuration of the adjacent pad areas of the peripheral area is referenced to ensure the consistency of the process in the local area, thereby avoiding the increase in process difficulty due to frequent switching of line types.

[0028] Preferably, the method further includes step S7: if the evaluation indicators of multiple neighboring pad areas in the current pad area and the surrounding area are all greater than the set first evaluation threshold and less than the set second evaluation threshold, then the current pad area or neighboring pad area is configured as a type of circuit.

[0029] Preferably, the first type of line is an RDL line; the second type of line is an RDL line with a shorter length or fewer bends than the first type of line, or the second type of line is a TSV port. This arrangement is to further ensure that the transmission path of the second type of line is shorter than that of the first type of line.

[0030] Preferably, both Class I and Class II lines use RDL lines.

[0031] Beneficial technical effects: (1) In hybrid packaging, the electronic chip is first encapsulated, then the circuitry is set up, and after connecting the photonic chip, the system is encapsulated. This setup is equivalent to enlarging the physical spacing of the circuitry on the electronic chip to facilitate better interfacing with the photonic chip (e.g., dispersing dense connection points). Moreover, arranging complex circuitry (e.g., RDL circuitry) on the electronic chip can reduce the wiring pressure on the photonic chip. At the same time, the strength of the electronic chip is enhanced by introducing a reinforcement layer, improving the reliability of the overall packaging structure.

[0032] (2) By adopting a differentiated line configuration strategy, a balance is struck between the difficulty of wiring technology (such as consistency) and the requirements for communication quality, avoiding the simultaneous use of two different interconnect schemes (such as electroplated RDL + laser perforation) in local areas, thereby reducing the cost of photomasks and the difficulty of process control. At the same time, it effectively alleviates the stress concentration problem caused by the difference in thermal expansion coefficients between photonic chips and electronic chips, and reduces the risk of signal crosstalk in high-density interconnect areas.

[0033] (3) By introducing a decision-making mechanism for the surrounding area, when the evaluation index is in the middle range of the evaluation threshold, the circuit configuration of the adjacent pad area in the surrounding area is referenced to ensure the consistency of the process in the local area, thereby avoiding the increase in process difficulty due to frequent switching of circuit types. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0035] Figure 1 This is a schematic diagram of the hybrid packaging system according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the hybrid packaging system according to Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of the hybrid packaging system with a heat dissipation area according to Embodiment 2 of the present invention; Figure 4 This is a schematic flowchart of the circuit design method for the hybrid packaging system of the present invention; Summary of reference numerals in the attached drawings: 1-Substrate; 201-TIA electronic chip; 202-DRV electronic chip; 203-Chip molding compound; 3-Photonic chip; 4-System molding compound; 5-Reinforcing layer; 501-Connecting via; 502-First reinforcing sheet; 503-Second reinforcing sheet; 504-First heat dissipation area; 505-Second heat dissipation area; 506-First type of heat dissipation part; 507-Second type of heat dissipation part; 508-First insulating part; 509-Second insulating part. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0037] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0038] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0040] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0041] In this article, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0042] As used in this specification, the term "about" typically means + / -5% of the value, more typically + / -4%, more typically + / -3%, more typically + / -2%, even more typically + / -1%, even more typically + / -0.5%.

[0043] In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of a range should be considered as having specifically disclosed all possible subranges and the individual numerical values ​​within those ranges. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within those ranges, such as 1, 2, 3, 4, 5, and 6. This rule applies regardless of the breadth of the range.

[0044] Definitions: Optical chips (or photonic chips): Optical chips are chips that integrate optoelectronic devices and play a crucial role in communication and information processing. Their basic structure includes photoelectric conversion devices, electronic devices, and optoelectronic interconnects. The photoelectric conversion devices convert optical signals into electrical signals, the electronic devices process and control the electrical signals, and the optoelectronic interconnects enable high-speed photoelectric signal transmission. Optical chips have advantages such as small size, low power consumption, and strong anti-interference capabilities, which can greatly improve the speed and efficiency of communication and information processing, and have broad application prospects in communication, computers, fiber optic sensing, and other fields.

[0045] Electrical chips (or electronic chips): Electrical chips mainly refer to traditional integrated circuit chips, which can be composed of electronic devices such as logic gates, amplifiers, and clock circuits. The main function of these electronic devices is to process and control electrical signals. Unlike optical chips, electrical chips focus on the processing of electrical signals and are the core components for electronic devices to realize various functions.

[0046] Bonding structure: Chip bonding structure is a structural method that connects multiple chips (i.e., optical chips or electrical chips) or wafers together. It is a key technology for realizing chip stacking and interconnection. It can combine chips with different functions, improving chip integration and performance. The bonding process requires ensuring precise alignment between chips, while monitoring parameters such as surface roughness, surface cleanliness, and flatness to guarantee the quality and stability of the bonding. Common bonding methods include chip-to-wafer bonding and wafer-to-wafer bonding. In advanced packaging technologies such as TSV, the bonding structure is an indispensable part. For example, the bonding structure can be solder balls made of metal materials.

[0047] TSV (Through-Silicon Via) is a vertical interconnect structure that passes through a silicon wafer or chip. It achieves vertical electrical interconnection by creating vertical connections between chips or wafers and filling them with conductive materials such as copper, tungsten, or polysilicon. Vertical interconnection via TSVs can reduce interconnect length, signal delay, and capacitance / inductance, enabling low-power, high-speed communication between chips, increasing bandwidth, and facilitating miniaturization of device integration.

[0048] Molding (or encapsulation) refers to the process of injecting or pressing molten molding compound (such as epoxy molding compound (EMC)) into a mold cavity containing a chip, allowing it to flow, fill, and solidify to form a molding layer (or adhesive layer) on the outside of the chip. For example, molding multiple chips can encapsulate them into a single unit. Specifically, multiple dies can be repackaged into a wafer through molding.

[0049] Example 1: See Figure 1 The hybrid packaging system includes a substrate 1, and the hybrid packaging system further includes: A photonic chip 3; Two electronic chips are provided, each encapsulated in a molding compound 203 (such as molding material or plastic). The pads of the electronic chips are connected to the photonic chip 3 via either a Class I or Class II circuit. The Class I circuit has a greater number of turning points than the Class II circuit. The two electronic chips can be a TIA (transimpedance amplifier) ​​chip 201 and a DRV (driving chip) chip 202, both arranged horizontally. That is, the TIA and DRV chips are not stacked vertically. A bonding structure (such as a bonding structure connecting one or both ends of a circuit) is also provided between the photonic chip 3 and the electronic chips. System molding compound 4 (which can also be a molding material) wraps around the outside of the photonic chip 3, the electronic chip, and the bonding structure to form a system molding area; The system encapsulation area is provided with a reinforcing layer 5 to enhance the strength of the system; the reinforcing layer 5 is a silicon wafer or a silicon bridge; the substrate 1 is located below the system encapsulation area; The reinforcement layer 5 is disposed between the photonic chip 3 and the electronic chip. The first side of the reinforcement layer 5 is connected to the photonic chip 3 through a first bonding structure, and the second side of the reinforcement layer 5 is connected to the electronic chip through a second bonding structure, thereby electrically connecting the photonic chip 3 and the electronic chip.

[0050] When the strengthening layer 5 is a silicon wafer, the strengthening layer 5 is provided with a connecting via 501, and the first bonding structure and the second bonding structure are electrically connected through the connecting via 501; the connecting via 501 is a TMV via.

[0051] In some embodiments, the substrate is a base plate.

[0052] Example 2: The difference from Example 1 is that the reinforcing layer 5 is disposed on both sides of the electronic chip. Specifically, see... Figure 2 The hybrid packaging system includes a substrate 1, and the hybrid packaging system further includes: A photonic chip; Two electronic chips are included, each encapsulated in a chip molding compound 203. The pads of the electronic chips are connected via either a Class I or Class II circuit. The Class I circuit has a greater number of turning points than the Class II circuit. The two electronic chips are a TIA electronic chip 201 and a DRV electronic chip 202, both arranged horizontally. That is, the TIA electronic chip 201 and DRV electronic chip 202 are not stacked vertically. See Figure 2 As shown, a line (including Class I and / or Class II lines) can refer to a complete signal path from an electronic chip to a photonic chip, such as an RDL line (i.e., a redistribution layer).

[0053] Alternatively, the complete signal path may also include: bonding structures (such as solder balls) disposed on the surface of the photonic chip and / or electronic chip, and RDL lines disposed between the bonding structures.

[0054] The photonic chip 3 and the electronic chip will also be connected by a bonding structure; System molding compound 4, which wraps around the outside of the photonic chip 3, the electronic chip and the bonding structure to form a system molding area; The system encapsulation area is provided with a reinforcing layer 5 to enhance the strength of the system; the reinforcing layer 5 is a silicon wafer or a silicon bridge; the substrate 1 is located below the system encapsulation area; The reinforcement layer 5 is disposed on both sides of the electronic chip; the reinforcement layer 5 includes a first reinforcement sheet 502 and a second reinforcement sheet 503, the first reinforcement sheet 502 and the second reinforcement sheet 503 being disposed on both sides of the electronic chip respectively.

[0055] See Figure 3A first heat dissipation area 504 is formed between the first reinforcing sheet 502 and the system encapsulation area, and a second heat dissipation area 505 is formed between the second reinforcing sheet 503 and the system encapsulation area. Correspondingly, a first type of heat dissipation part 506 is provided at intervals in both the first heat dissipation area 504 and the second heat dissipation area 505, and a first insulating part 508 is provided between the first type of heat dissipation part 506 and the inner surface of the system encapsulation area. A second type of heat dissipation part 507 is provided on both the first reinforcing sheet 502 and the second reinforcing sheet 503.

[0056] The second type of heat dissipation part 507 is made of insulating material or metal material; the first type of heat dissipation part 506 is made of metal material.

[0057] When the second type of heat dissipation part 507 is made of metal, the second type of heat dissipation part 507 is disposed through the first reinforcing plate 502 and the second reinforcing plate 503; and the second type of heat dissipation part 507 is provided with a second insulating part 509 at both ends.

[0058] In some embodiments, the metallic material is a copper pillar or a gold pillar, or a copper / nickel / gold alloy pillar, or a titanium / copper pillar, or a copper / gold alloy pillar.

[0059] In some embodiments, the insulating material is photosensitive polyimide PSPI, benzocyclobutene BCB, or epoxy photosensitive medium Dry Film; the insulating material covers the sidewalls and bottom of the metal material.

[0060] In some embodiments, the insulating material is an inorganic passivation layer SiO2 / Si3N4, which is disposed at the bottom of the metal material.

[0061] In some embodiments, the metal material is a copper pillar.

[0062] Example 3: The purpose of this example is to balance the difficulty of wiring processes (such as consistency) and the requirements for communication quality. For example, it avoids using two different interconnect schemes (such as electroplated RDL + laser perforation) in a local area, thereby reducing photomask costs and process control difficulties.

[0063] For example, in this embodiment, a differentiated RDL circuit design is performed for photonic chips or electronic chips (or collectively referred to as chips), and the degree of difference is appropriately limited in combination with the pad distribution of the chip.

[0064] This embodiment allows for the configuration of circuits of different specifications on the chip. For example, shorter circuits with fewer bends can be selected to reduce signal loss and latency. For applications requiring high signal throughput or high-frequency, high-speed communication, shorter circuits are necessary, but shorter paths have shorter lifespans. In areas with sparse signal pads or where signal routing requirements are high, short circuits or direct connections are typically designed to control signal trace length, signal transmission path loss, and signal interference. In areas with dense signal pads, direct connections are not easily fabricated, so routing (such as RDL traces) is often required to optimize routing and facilitate signal extraction and communication.

[0065] However, short lines and routing processes differ. How to balance the difficulty of routing processes (such as consistency) and the requirements of communication quality, while ensuring communication quality and maintaining the consistency of routing processes, improving the mechanical strength of the packaging structure and signal transmission efficiency, and reducing costs and process difficulty, has become an urgent problem to be solved.

[0066] See Figure 4 The circuit design method for this hybrid packaging system includes the following specific steps: S1, Select at least one pad area as the current pad area; wherein, the pad area can be divided according to functional areas; For example, in some embodiments, taking an electronic chip as an example, its surface is typically provided with multiple pads, which can be used for circuit lead-out to achieve communication. In this embodiment, the multiple pads can be divided into different areas according to the function of different regions on the surface of the electronic chip (e.g., pads with the same or similar functions and relatively concentrated positions are grouped into one pad area). Alternatively, multiple pads that are relatively concentrated in position can be divided into one pad area according to the positional distribution of the pads.

[0067] S2, calculate the pad density of the current pad area and the communication lower limit of the current pad area; For example, the lower limit of communication for a pad area refers to its minimum requirement for signal frequency (the lowest frequency allowed to be used). This lower limit can be determined by the design specifications of the electronic chip or the application scenario.

[0068] S3, generate evaluation metrics based on the pad density and the communication lower limit; The formula is: I = aX + bY; Where X is the density score, which is generally normalized to [0,1]; a is the pad density score weighting coefficient; Y is the communication score, which is generally normalized to [0,1]; b is the communication lower limit weighting coefficient; a and b can be preset in advance, a+b=1; or, the weighting coefficients can be dynamically adjusted by the engineer based on the design application requirements (such as the focus on communication capabilities).

[0069] Among them, the higher the density, the smaller X is; the lower the communication lower limit, the smaller Y is. S4, when the evaluation index is less than or equal to the set first evaluation threshold, a type I line is configured for connection of the pad area; when the evaluation index is greater than or equal to the set second evaluation threshold, a type II line is configured for connection of the pad area. In some embodiments, the number of turning points of a Class I line is greater than that of a Class II line (or, in other words, the number of turning points allowed is greater).

[0070] Alternatively, in some embodiments, the length of a Class I line is greater than the length of a Class II line. That is to say, in this embodiment, when the density of the pad area is relatively high and the lower limit of communication is relatively low, it is permissible to configure a longer line, or to allow for more complex routing (such as setting up bends).

[0071] S5, when the evaluation index is greater than the set first evaluation threshold and less than the set second evaluation threshold, the surrounding area is linked for auxiliary decision-making so that the circuit type of the current pad area and the pad area of ​​the surrounding area are consistent with the process. S6, taking the current pad area as the center point, calculate the evaluation index I of multiple neighboring pad areas in its surrounding area. p Based on the calculated evaluation index I p Execute step S4 to determine whether the evaluation index of the adjacent pad area is to configure Category I or Category II lines in the adjacent pad area; or execute step S5 to connect the surrounding area to assist in decision-making. Specifically, the evaluation index I p Compared with the first evaluation threshold and the second evaluation threshold, if the evaluation index I p If the value is less than the set first evaluation threshold, then a type of circuit is configured for connection in the pad area; when the evaluation index I... p If the value exceeds the set second evaluation threshold, then a Class II circuit will be configured for connection in the pad area; Evaluation Index I p If the value is greater than the set first evaluation threshold but less than the set second evaluation threshold, then the surrounding area is connected to assist in decision-making; that is, the surrounding area can be evaluated in a traversal manner.

[0072] The surrounding area auxiliary decision-making is as follows: The current pad area or a neighboring pad area is configured as a Class I or Class II line based on the proportion of Class I or Class II lines configured in multiple adjacent pad areas of the surrounding area. For example, in some embodiments, if the proportion of Class I lines configured in multiple adjacent pad areas of the surrounding area is higher, it is recommended to configure the current pad area as a Class I line as well. Similarly, in some embodiments, if the proportion of Class II lines configured in multiple adjacent pad areas of the surrounding area is higher, it is recommended to configure the current pad area as a Class II line as well.

[0073] S7. If the evaluation indicators of multiple neighboring pads in the current pad area and surrounding area are all greater than the set first evaluation threshold and less than the set second evaluation threshold, then the current pad area or neighboring pad area is configured as a type of line.

[0074] The evaluation indicators and their corresponding routes are shown in Table 1.

[0075] Table 1. Correspondence between evaluation indicators and routes The higher the pad density, the longer the path can be to accommodate the high density of connections; the lower the communication threshold, the longer the path can also be.

[0076] The first type of line is an RDL line; the second type of line is an RDL line whose length or number of bends is less than that of the first type of line, or the second type of line is a TSV port. This arrangement is to further ensure that the transmission path of the second type of line is shorter than that of the first type of line.

[0077] In some embodiments, both Class I and Class II lines use RDL lines.

[0078] In some embodiments, when it is calculated that the current pad area needs to be configured with a type of circuit, at least one neighboring pad area in its surrounding area is calculated; the circuit configuration of the neighboring pad area is evaluated, for example, if the adjacent evaluation index is medium, it is recommended to configure the neighboring pad area as a type of circuit so that the area has high process consistency.

[0079] In some embodiments, when the evaluation index of a neighboring pad area is medium, the proportion of the pad area with medium evaluation index to all neighboring pad areas in the surrounding area will also be determined. For example, if the proportion of medium is particularly low (e.g., less than a set proportion threshold), it can be reassigned as a Class I circuit. If the proportion of medium is slightly high (e.g., greater than or equal to a set proportion threshold), and the surrounding area also has a certain proportion of neighboring pad areas with high evaluation index, it can be reassigned as a Class II circuit.

[0080] In some embodiments, the coverage area (e.g., area or number) of adjacent regions to be considered can be customized. For example, when the overall density of the chip varies drastically (large standard deviation), the range of the adjacent coverage area can be reduced. Alternatively, when the overall density of the chip is high, the RDL region should cover more adjacent areas to avoid sporadic non-RDL via areas, i.e., expand the adjacent coverage area.

[0081] In summary, the design method of this line is to both meet communication quality requirements and keep the surrounding pad processes as consistent as possible.

[0082] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0083] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0084] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A hybrid packaging system, comprising a substrate, characterized in that, The hybrid packaging system also includes: At least one photonic chip; At least two electronic chips, the outer side of which is covered with chip molding compound, and the pads of the electronic chips are connected by a type I circuit or a type II circuit; wherein the type I circuit has more turning points than the type II circuit. The photonic chip and the electronic chip are connected by a bonding structure; A system molding compound, which wraps around the outside of the photonic chip, the electronic chip, and the bonding structure to form a system molding area; The system has a reinforcing layer within its encapsulation area to enhance its strength. The substrate is located below the encapsulation area of ​​the system.

2. The hybrid packaging system according to claim 1, characterized in that, The reinforcement layer is disposed between the photonic chip and the electronic chip. The first side of the reinforcement layer is connected to the photonic chip through a first bonding structure, and the second side of the reinforcement layer is connected to the electronic chip through a second bonding structure, thereby electrically connecting the photonic chip and the electronic chip.

3. The hybrid packaging system according to claim 2, characterized in that, The reinforcement layer is provided with a connection through hole, and the first bonding structure and the second bonding structure are electrically connected through the connection through hole.

4. The hybrid packaging system according to claim 1, characterized in that, The reinforcement layer is disposed on both sides of the electronic chip.

5. A circuit design method applied to a hybrid packaging system as described in any one of claims 1-4, characterized in that, The specific steps of the method include: S1, Select at least one pad area as the current pad area; S2, calculate the pad density of the current pad area and the communication lower limit of the current pad area; S3, generate evaluation metrics based on the pad density and the communication lower limit; The formula is: I = aX + bY; Where X is the density score, a is the pad density score weighting coefficient; Y is the communication score, and b is the communication lower limit weighting coefficient. Among them, the higher the density, the smaller X is; the lower the communication lower limit, the smaller Y is. S4, when the evaluation index is less than or equal to the set first evaluation threshold, a type I line is configured for connection of the pad area; when the evaluation index is greater than or equal to the set second evaluation threshold, a type II line is configured for connection of the pad area.

6. The circuit design method according to claim 5, characterized in that, It also includes step S5, where when the evaluation index is greater than the set first evaluation threshold and less than the set second evaluation threshold, the surrounding area is linked to assist decision-making so that the circuit type of the current pad area and the pad area of ​​the surrounding area are kept consistent with the process.

7. The circuit design method according to claim 6, characterized in that, It also includes step S6, which calculates the evaluation index I of multiple neighboring pad areas in the surrounding area, with the current pad area as the center point. p Based on the calculated evaluation index I p Step S4 determines whether the evaluation index for the adjacent pad area is configured as either Category I or Category II circuitry. Alternatively, step S5 can be executed to connect to surrounding areas for decision support.

8. The circuit design method according to claim 7, characterized in that, The auxiliary decision-making for the surrounding area is to determine whether the current pad area or the adjacent pad area is configured as a Class I or Class II line based on the ratio of the number of Class I or Class II lines configured in the multiple adjacent pad areas of the surrounding area.

9. The circuit design method according to claim 8, characterized in that, It also includes step S7, which states that if the evaluation indicators of multiple neighboring pad areas in the current pad area and the surrounding area are all greater than the set first evaluation threshold and less than the set second evaluation threshold, then the current pad area or neighboring pad area is configured as a type of circuit.

10. The circuit design method according to claim 7, characterized in that, The first type of line is the RDL line; The second type of line is an RDL line and its length or number of turns is less than that of the first type of line, or the second type of line is a TSV port.

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