Circuit architecture, oscillator, chip and electronic equipment

Abstract

The present specification provides a circuit architecture, an oscillator, a chip, and an electronic device. The circuit architecture comprises: an oscillation circuit having at least one oscillation loop, the oscillation loop comprising at least one frequency modulation node; the at least one frequency modulation unit comprises a control subunit and an energy storage subunit; the control subunit is provided with a first end, a second end and a control end; the first end is electrically connected with the frequency modulation node, and the second end is electrically connected with the first end of the energy storage subunit; the control end is configured to receive a control voltage; the second end of the energy storage subunit is electrically connected with a reference potential end; and the control subunit is configured to respond to the control voltage and adjust the energy storage subunit so as to enable the equivalent capacitance at the frequency modulation node to change along with the control voltage. The circuit architecture has the advantages that the structure is simple, and the output frequency linearity can be kept in a wide voltage range.

Description

Technical Field

[0001] This specification relates to the field of electronic device technology, and in particular to a circuit architecture, oscillator, chip, and electronic device. Background Technology

[0002] Oscillators are fundamental modules in analog integrated circuits used to generate periodic signals, and are often used as key units in phase-locked loops, frequency synthesizers, radio frequency transceivers, and clock distribution networks.

[0003] In related technologies, to balance frequency coverage and frequency resolution, a combination of coarse and fine tuning is often used. A common method for fine tuning is to use a voltage-controlled capacitor (variable capacitor device) as a tuning element. By changing the bias voltage of the variable capacitor device, its capacitance value is changed, thereby changing the equivalent capacitance at the nodes of the oscillation loop to achieve continuous frequency adjustment.

[0004] However, voltage-controlled capacitors exhibit significant nonlinearity, characterized by a large rate of frequency change in certain voltage ranges and a small rate of change in others. Furthermore, some technologies have proposed using multiple sets of variable capacitors connected in parallel with different bias points to widen the linear range; however, such solutions are typically more complex and often require additional bias generation and calibration circuitry, increasing design and verification complexity and implementation costs. Summary of the Invention

[0005] To overcome the problems existing in related technologies, this specification provides a circuit architecture, oscillator, chip, and electronic device. This allows for controlled variation of the equivalent capacitance at the frequency modulation node with the control voltage, while maintaining a relatively simplified structure, thereby helping to maintain the linearity of the output frequency over a wider voltage range.

[0006] According to a first aspect of the embodiments of this specification, a circuit architecture is provided, the circuit architecture comprising: An oscillation circuit having at least one oscillation loop, the oscillation loop including at least one frequency modulation node; At least one frequency modulation unit includes a control subunit and an energy storage subunit; the control subunit has a first terminal, a second terminal, and a control terminal; the first terminal is electrically connected to the frequency modulation node, and the second terminal is electrically connected to the first terminal of the energy storage subunit; the control terminal is configured to receive a control voltage; the second terminal of the energy storage subunit is electrically connected to a reference potential terminal. The control subunit is configured to adjust the energy storage subunit in response to the control voltage so that the equivalent capacitance at the frequency modulation node varies with the control voltage.

[0007] In some embodiments of this disclosure, a first terminal of the energy storage subunit is configured to connect to the frequency modulation node via the control subunit when the control subunit responds to the control voltage.

[0008] In some embodiments of this disclosure, the circuit architecture includes M frequency modulation units; at least one of the oscillation loops includes N frequency modulation nodes; Where M is an integer greater than or equal to 1, and N is an integer greater than or equal to 1; the M frequency modulation units are electrically connected to at least one of the N frequency modulation nodes.

[0009] In some embodiments of this disclosure, the control subunit includes a control transistor; The drain of the control transistor is electrically connected to the frequency modulation node, the source of the control transistor is electrically connected to the first terminal of the energy storage sub-unit, and the gate of the control transistor is electrically connected to the control terminal.

[0010] In some embodiments of this disclosure, the control transistor is an N-type transistor or a P-type transistor.

[0011] In some embodiments of this disclosure, in the M frequency modulation units, the gates of the control transistors in each of the control subunits are electrically connected to each other to receive the same control voltage.

[0012] In some embodiments of this disclosure, in the M frequency modulation units, the gates of the control transistors in each control subunit are electrically isolated from each other and are respectively configured to receive independent control voltages.

[0013] In some embodiments of this disclosure, the energy storage subunit includes an energy storage capacitor; The first end of the energy storage capacitor is electrically connected to the source of the control transistor, and the second end of the energy storage capacitor is electrically connected to the reference potential terminal.

[0014] In some embodiments of this disclosure, the energy storage capacitor includes a first metal layer, a dielectric layer, and a second metal layer; The dielectric layer is sandwiched between the first metal layer and the second metal layer; Wherein, at least a portion of the first metal layer constitutes the first terminal of the energy storage capacitor, and at least a portion of the second metal layer constitutes the second terminal of the energy storage capacitor.

[0015] In some embodiments of this disclosure, the energy storage capacitor is a non-voltage-controlled capacitor.

[0016] According to a second aspect of the embodiments of this specification, an oscillator is provided, including the circuit architecture as described.

[0017] According to a third aspect of the embodiments of this specification, a chip is provided, including the aforementioned oscillator.

[0018] According to a fourth aspect of the embodiments of this specification, an electronic device is provided, including the aforementioned chip.

[0019] The technical solutions provided in the embodiments of this specification may include the following beneficial effects: In the embodiments described in this specification, the circuit architecture of this application includes an oscillation circuit and a frequency modulation unit. The oscillation circuit has at least one oscillation loop, in which a frequency modulation node is provided; the frequency modulation unit is connected to the frequency modulation node, and the frequency modulation unit consists of a control subunit and an energy storage subunit, wherein one end of the control subunit is connected to the frequency modulation node, and the other end is connected to the first end of the energy storage subunit. The control terminal of the control subunit receives a control voltage, and the second end of the energy storage subunit is connected to a reference potential terminal. During operation, the control subunit adjusts the energy storage subunit in response to the control voltage, so that the equivalent capacitance of the energy storage subunit at the frequency modulation node changes with the control voltage, thereby changing the equivalent capacitive load of the oscillation loop and achieving oscillation frequency tuning. Compared to related technologies that typically rely on the voltage-controlled capacitor's own capacitance changing with voltage for fine-tuning, which can easily lead to inconsistent frequency slopes across different voltage ranges, this application achieves more predictable tuning characteristics by controlling the equivalent capacitance of the energy storage subunit at the frequency modulation node. This simplifies the structure and improves the linearity of the output frequency changing with the control voltage over a wider control voltage range, while reducing the difficulty of system parameter design and debugging.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0022] Figure 1 This is a schematic diagram of the first type of scheme in the related technology, showing the relationship between the equivalent capacitance of a single voltage-controlled capacitor and the first voltage.

[0023] Figure 2 This is a schematic diagram of the second type of scheme in the related technology, showing the relationship between the equivalent capacitance value of multiple voltage-controlled capacitors connected in parallel under different bias conditions and the second voltage.

[0024] Figure 3 This is a schematic diagram of the circuit architecture in the embodiments of this disclosure.

[0025] Figure 4 This is a schematic diagram of the frequency modulation unit in the embodiments of this disclosure.

[0026] Figure 5This is a schematic diagram of an embodiment of the present disclosure in which multiple frequency modulation units are electrically connected to multiple frequency modulation nodes and share the same control voltage (the number of multiple frequency modulation units and multiple frequency modulation nodes are the same).

[0027] Figure 6 This is a schematic diagram of an embodiment of the present disclosure in which multiple frequency modulation units are electrically connected to multiple frequency modulation nodes and receive different control voltages respectively (the number of multiple frequency modulation units and multiple frequency modulation nodes are the same).

[0028] Figure 7 This is a schematic diagram of an embodiment of the present disclosure in which multiple frequency modulation units are electrically connected to some of the multiple frequency modulation nodes and share the same control voltage (the number of frequency modulation nodes is greater than the number of frequency modulation units).

[0029] Figure 8 This is a schematic diagram of an embodiment of the present disclosure in which multiple frequency modulation units are electrically connected to some of the multiple frequency modulation nodes and receive different control voltages respectively (the number of frequency modulation nodes is greater than the number of frequency modulation units).

[0030] Figure 9 This is a schematic diagram of the voltage waveforms of each node in the frequency modulation unit access circuit architecture and when a periodic signal is applied to the frequency modulation node in this embodiment of the present disclosure.

[0031] Explanation of reference numerals in the attached figures: VB1, First bias voltage; VB2, Second bias voltage; VB3, Third bias voltage; VB4, Fourth bias voltage; V1, First voltage; V2, Second voltage; VCtrl, Control voltage; Vth, Threshold voltage; 1, Oscillation loop; 2, Frequency modulation unit; 21, Control subunit; 211, Control transistor; 22, Energy storage subunit; 221, Energy storage capacitor; 3, Frequency modulation node. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0033] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0034] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0035] In some embodiments, to facilitate understanding of the frequency modulation unit proposed in this application and its application in an oscillator, the voltage-controlled oscillator and its fine-tuning method in related technologies are first described as follows. An oscillator is a type of analog integrated circuit module capable of spontaneously generating a periodic clock signal. A voltage-controlled oscillator is a circuit structure formed by introducing a frequency modulation circuit on the basis of an oscillator, and its output frequency can be changed with the input control voltage of the frequency modulation circuit.

[0036] In related technologies, voltage-controlled oscillators (VCOs) typically employ a combination of coarse and fine tuning to achieve a balance between wide frequency range and high resolution. Taking a VCO with an output frequency range of 5 GHz to 7 GHz as an example, coarse tuning covers a large frequency range and is usually implemented through discrete frequency points or discrete tuning increments, such as switching between multiple frequency points from 5 GHz, 5.1 GHz, 5.2 GHz to 7 GHz. Fine tuning provides a continuously adjustable frequency range within a single coarse tuning increment, such as continuous adjustment of any frequency point within the 5 GHz to 5.1 GHz range. By combining coarse and fine tuning, it is possible to achieve output at any target frequency point within the 5 GHz to 7 GHz range.

[0037] Currently, the most common methods for fine-tuning mainly fall into two categories. The first type of scheme uses a voltage-controlled capacitor as the fine-tuning element.

[0038] See Figure 1Where C1 represents the equivalent capacitance of a single voltage-controlled capacitor. In the first type of scheme, fine-tuning is usually achieved through the voltage-controlled capacitor. The capacitance of the voltage-controlled capacitor changes with the voltage across its terminals. By adjusting the first voltage V1, the equivalent capacitance in the oscillator loop can be changed, thereby achieving output frequency tuning. Since the capacitance-voltage relationship of the voltage-controlled capacitor is often non-linear, it usually only has a relatively usable near-linear response within a certain voltage range. Therefore, in engineering, the voltage-controlled capacitor is often set to operate near the first bias voltage VB1 to make the most of the "usable range" shown in the figure. However, even near this bias point, the rate of change of the capacitance with respect to the first voltage V1 will still vary significantly in different voltage ranges, showing a faster change in the middle voltage range and a slower change at both ends. This leads to inconsistent sensitivity of the oscillator output frequency to the first voltage V1, causing the slope of the frequency-voltage curve to fluctuate with voltage changes. The above characteristics increase the difficulty of matching and tuning the loop parameters with other system indicators, and may even make it difficult to select a set of loop parameters that simultaneously meet the system stability requirements.

[0039] See Figure 2 Where C2 represents the equivalent capacitance of multiple voltage-controlled capacitors connected in parallel. The second approach is an improvement on the first: it sets up multiple sets of voltage-controlled capacitors and applies different bias voltages (such as the second bias voltage VB2, the third bias voltage VB3, and the fourth bias voltage VB4) to offset the capacitance-voltage curves of each set of voltage-controlled capacitors on the second voltage V2 axis. Then, the multiple sets of voltage-controlled capacitors are connected in parallel and superimposed, so that the overall equivalent capacitance-control voltage curve presents a relatively flat and approximately linear "usable range" over a wider range, thus improving tuning linearity. However, this approach typically requires generating and stably providing multiple different bias voltages, and to obtain better linearity, the bias points and combination weights of each set of voltage-controlled capacitors need to be matched and optimized. In engineering, digital calibration circuits are often introduced for compensation; if calibration is lacking or the calibration accuracy is insufficient, the overall linearity may still be unsatisfactory. Therefore, this improved approach introduces additional complexity in terms of device quantity, bias network, and calibration logic, leading to a significant increase in the workload of design, verification, and mass production consistency control.

[0040] Based on this, see Figure 3 , Figure 4This application provides a circuit architecture including an oscillation circuit and at least one frequency modulation unit 2; wherein the oscillation circuit has at least one oscillation loop 1, and the oscillation loop 1 includes at least one frequency modulation node 3; the at least one frequency modulation unit 2 includes a control subunit 21 and an energy storage subunit 22; the control subunit 21 has a first terminal, a second terminal, and a control terminal; the first terminal is electrically connected to the frequency modulation node 3, and the second terminal is electrically connected to the first terminal of the energy storage subunit 22; the control terminal is configured to receive a control voltage VCtrl; the second terminal of the energy storage subunit 22 is electrically connected to a reference potential terminal; the control subunit 21 is configured to adjust the energy storage subunit 22 in response to the control voltage VCtrl so that the equivalent capacitance at the frequency modulation node 3 changes with the control voltage VCtrl.

[0041] It should be noted that oscillation loop 1 refers to the closed electrical signal path in the oscillation circuit used to form and maintain self-excited oscillation. This closed path is composed of multiple nodes inside the oscillation circuit and their electrical connections, ensuring that the signal in the loop meets the oscillation start-up conditions during propagation and feedback and continues to cycle in steady state, thereby forming a periodically changing voltage or current in the loop and outputting an oscillation signal. Oscillating loop 1 can be a closed path formed by a single-ended structure or a closed path formed by a differential structure. Frequency modulation node 3 refers to one or a group of electrical nodes in oscillation loop 1. During oscillation, there is a voltage or current at this electrical node that changes periodically with time, and the change in the equivalent capacitance at this electrical node will cause a change in the frequency selectivity of oscillation loop 1, thus causing a change in the oscillation frequency. Frequency modulation node 3 can be a single electrical node or a pair of differential electrical nodes in differential oscillation loop 1.

[0042] In this embodiment, during operation, after the control terminal receives the control voltage VCtrl, the control subunit 21 adjusts the conduction state or degree of conduction between the first and second terminals in response to the control voltage VCtrl, so that the energy storage subunit 22 is connected to the frequency modulation node 3 in a controlled manner. As the control voltage VCtrl changes, the equivalent capacitance presented by the energy storage subunit 22 at the frequency modulation node 3 changes accordingly through the control subunit 21, thereby changing the equivalent capacitive load of the oscillation loop 1 at the frequency modulation node 3, and thus achieving tuning and fine-tuning of the output frequency of the oscillation circuit. Compared with the fine-tuning method in related technologies that usually relies on the capacitance of the voltage-controlled capacitor itself to change with voltage, which easily leads to inconsistent slope of frequency change with control voltage VCtrl in different voltage ranges, this application achieves controlled change of equivalent capacitance through the mechanism of "control subunit 21 adjusting the connection of energy storage subunit 22 to frequency modulation node 3". Under the premise of relatively simplified structure, it helps to obtain more predictable tuning characteristics, thereby improving the linearity of output frequency change with control voltage VCtrl over a wider control voltage VCtrl range and reducing the difficulty of system parameter design and debugging.

[0043] In some embodiments of this disclosure, the first terminal of the energy storage subunit 22 is configured to be connected to the frequency modulation node 3 via the control subunit 21 when the control subunit 21 responds to the control voltage. Specifically, during oscillation operation, a periodic voltage signal exists on the frequency modulation node 3. After the control terminal receives the control voltage, the control subunit 21 forms a conduction state or degree of conduction corresponding to the control voltage between the first and second terminals. Thus, the first terminal of the energy storage subunit 22 is not always hard-connected to the frequency modulation node, but is connected in a controlled manner "via the control subunit 21": for example, when the control voltage increases, the conduction of the control subunit 21 is enhanced, the equivalent connection between the first terminal of the energy storage subunit 22 and the frequency modulation node 3 is enhanced, the participation of the energy storage subunit 22 in the charging and discharging of the frequency modulation node 3 is increased, and the equivalent capacitance presented at the frequency modulation node 3 increases; when the control voltage decreases, the conduction of the control subunit 21 is weakened, the equivalent connection of the first terminal to the frequency modulation node 3 is weakened, the participation is reduced, and the equivalent capacitance is reduced. The equivalent capacitance changes with the control voltage, thereby altering the equivalent capacitive load of the oscillation loop and achieving frequency tuning.

[0044] In some embodiments of this disclosure, see Figure 3 , Figure 5 The circuit architecture includes M frequency modulation units 2; at least one oscillation loop 1 includes N frequency modulation nodes 3. Here, M is an integer greater than or equal to 1, and N is an integer greater than or equal to 1. Each frequency modulation unit 2 is electrically connected to at least one of the N frequency modulation nodes 3, thereby enabling the frequency modulation unit 2 to adjust the equivalent capacitance at its connected frequency modulation node 3. It should be understood that the relationship between M and N is not necessarily one-to-one, and the number of frequency modulation units 2 need not be the same as the number of frequency modulation nodes 3.

[0045] As an example, see Figure 5 , Figure 6 In some circuit architectures, three frequency modulation units 2 are included, and the oscillation loop 1 includes three frequency modulation nodes 3. The three frequency modulation units 2 are electrically connected to the three frequency modulation nodes 3 respectively. In this example, the three frequency modulation units 2 are electrically connected to the three frequency modulation nodes 3 respectively, so that the equivalent capacitance at each frequency modulation node 3 can be adjusted independently. This allows for finer-grained distributed tuning of the equivalent capacitive load at different locations in the oscillation loop 1. This helps to improve the tuning resolution and the consistency of the tuning curve while ensuring the adjustable frequency range, and reduces the node swing disturbance and non-ideal coupling effects that may be caused by centralized tuning of a single frequency modulation node 3, thereby improving the stability and linearity of the oscillation frequency tuning.

[0046] As another example, in some circuit architectures, see Figure 7 , Figure 8The oscillation loop 1 includes three frequency modulation nodes 3, while the circuit architecture includes two frequency modulation units 2, which are electrically connected to any two of the three frequency modulation nodes 3. In this example, although the oscillation loop 1 has three frequency modulation nodes 3, only two frequency modulation units 2 are configured and connected to any two of the frequency modulation nodes 3. This allows the circuit to achieve distributed regulation of the equivalent capacitive load of the oscillation loop 1 while reducing the number of frequency modulation units 2, thus achieving a trade-off between area, power consumption, and implementation complexity. At the same time, by selecting two different frequency modulation nodes 3 for connection, the tuning point can be flexibly configured according to the target frequency band, phase noise, node swing distribution, or layout routing constraints. This helps to reduce implementation costs and improve adaptability while maintaining a certain tuning capability and linearity improvement effect.

[0047] As another example, in some circuit architectures, the oscillation loop 1 includes three frequency modulation nodes 3, and the circuit architecture includes one frequency modulation unit 2 (not specifically shown in the accompanying drawings), and this one frequency modulation unit 2 is electrically connected to any one of the three frequency modulation nodes 3. In this example, only one frequency modulation unit 2 is set and connected to any one of the three frequency modulation nodes 3, so that the circuit can still achieve fine-tuning of the oscillation frequency while minimizing the number of frequency modulation units 2, thereby helping to reduce circuit area, power consumption, and implementation and verification complexity; at the same time, since the frequency modulation unit 2 can be selectively connected to different frequency modulation nodes 3, the tuning point can be flexibly determined according to different oscillation structures, voltage swing distribution of different nodes, or layout routing conditions, thereby improving the versatility and engineering adaptability of the solution in different oscillation circuits.

[0048] In some implementations, see Figure 4 The control subunit 21 may include a control transistor 211. The drain of the control transistor 211 is connected to the frequency modulation node 3, the source is connected to the first terminal of the energy storage subunit 22, and the gate is connected to the control terminal to receive the control voltage VCtrl.

[0049] During operation, after the control voltage VCtrl is input to the control terminal, the conduction state or degree of conduction of the control transistor 211 changes with the control voltage VCtrl. Thus, the energy storage sub-unit 22 is adjusted through the electrical connection between the control transistor 211 and the frequency modulation node 3: when the control transistor 211 is in a strong conduction state, the equivalent capacitance of the energy storage sub-unit 22 at the frequency modulation node 3 increases; when the control transistor 211 is in a weak conduction state or tends to be off, the equivalent capacitance of the energy storage sub-unit 22 at the frequency modulation node 3 decreases. The change in the equivalent capacitance at the frequency modulation node 3 further alters the equivalent capacitive load of the oscillation loop 1, thereby achieving tuning and fine-tuning of the oscillation frequency.

[0050] The control subunit 21 is implemented using a control transistor 211, which enables the adjustment of the effective access degree of the energy storage subunit 22 with a relatively small number of components. The circuit structure is relatively simple and easy to integrate. At the same time, the conduction characteristics of the control transistor 211 are adjusted by the control voltage VCtrl, which makes the change of the equivalent capacitance at the frequency modulation node 3 more controllable and predictable, which helps to improve the consistency of the frequency tuning curve and reduce the difficulty of system parameter tuning. In addition, since the drain of the control transistor 211 is directly connected to the frequency modulation node 3 and the source is connected to the first terminal of the energy storage subunit 22, this connection method also facilitates the access of the frequency modulation function without changing the main structure of the oscillation circuit, improving the adaptability to different oscillation structures.

[0051] It should be noted that the control subunit 21 described above is not limited to being implemented using a control transistor 211. In other embodiments, the control subunit 21 can also be implemented by other switching devices or controllable conducting devices that can adjust the conduction characteristics between the first and second terminals under the action of the control voltage VCtrl, such as a switching structure or transmission structure formed by combining multiple transistors, etc. As long as the effectiveness of connecting the energy storage subunit 22 to the frequency modulation node 3 can be adjusted, a similar tuning effect can be achieved.

[0052] In some implementations, the control transistor 211 can be an N-type transistor or a P-type transistor, and the specific selection can be determined based on factors such as the process platform, the range of the control voltage VCtrl, and the common-mode potential of the frequency modulation node 3.

[0053] For example, when the control transistor 211 is an N-type transistor, the conduction level can be changed by adjusting the gate-source voltage after the control voltage VCtrl is applied to the gate, so that the effective access of the energy storage sub-unit 22 to the frequency modulation node 3 varies with the control voltage VCtrl. N-type transistors generally have better electron mobility and lower on-resistance for the same size, which is beneficial to obtain stronger conduction capability in a smaller device size, thereby reducing the introduced series loss and reducing the impact on the amplitude of the oscillation loop 1. At the same time, N-type transistors are more likely to obtain sufficient gate-source drive margin in scenarios where ground potential or a lower potential is used as the reference potential terminal, which is convenient for matching with the common low-side control voltage VCtrl range.

[0054] When the control transistor 211 is a P-type transistor, the control voltage VCtrl can also be used to adjust the conduction level, so that the effective access degree of the energy storage sub-unit 22 to the frequency modulation node 3 varies with the control voltage VCtrl. The P-type transistor is more suitable for use in scenarios where the common mode potential of the frequency modulation node 3 is high or where the power supply potential is required as a reference, which is beneficial for achieving controlled access in the higher potential region; at the same time, the P-type transistor can be used in conjunction with pull-up drive or the high-side control voltage VCtrl domain, thereby providing a more flexible implementation under different power supply architectures.

[0055] Therefore, the control transistor 211 is designed as an N-type transistor or a P-type transistor, so that the frequency modulation unit 2 can adapt to different control voltage VCtrl domains and oscillation node potential distributions, thereby improving the versatility and feasibility of the solution in different processes and different oscillation circuit structures.

[0056] In some implementations, see Figure 5 , Figure 7 The circuit architecture includes M frequency modulation units 2, and the gates of the control transistors 211 in the multiple frequency modulation units 2 are electrically connected to each other, so that they all receive the same control voltage VCtrl. That is, the same control voltage VCtrl is applied to the gates of multiple control transistors 211 simultaneously, so that multiple frequency modulation units 2 synchronously change their conduction state or conduction degree under the same control signal drive, thereby causing the equivalent capacitance presented at each frequency modulation node 3 to change in tandem with the same control voltage VCtrl.

[0057] In this implementation, since multiple frequency modulation units 2 are driven by the same control voltage VCtrl, the equivalent capacitance changes of each frequency modulation node 3 have a consistent control reference, which helps to make the frequency tuning of the oscillation loop 1 exhibit a more consistent and predictable trend. Simultaneously, compared to providing an independent control voltage VCtrl for each frequency modulation unit 2, common-gate driving can reduce the number of control voltage VCtrl channels and the corresponding bias generation and routing resources, thereby reducing implementation complexity, saving chip area, and reducing the coupling interference of the control network to the oscillation loop 1. Furthermore, in scenarios where multiple frequency modulation units 2 are distributed and connected to multiple frequency modulation nodes 3, the unified control voltage VCtrl can also keep the distributed tuning behavior synchronized, helping to reduce frequency drift or tuning errors introduced by control inconsistencies.

[0058] In some implementations, see Figure 6 , Figure 8The circuit architecture includes M frequency modulation units 2, and the gates of the control transistors 211 in each frequency modulation unit 2 are electrically isolated from each other, so that they can each receive an independent control voltage VCtrl. That is, each frequency modulation unit 2 corresponds to an independent control voltage VCtrl path, and the independent control voltage VCtrl is applied to the gate of the corresponding control transistor 211, so that different frequency modulation units 2 can independently change their conduction state or conduction degree under the drive of different control signals, thereby allowing the equivalent capacitance presented at different frequency modulation nodes 3 to be independently adjusted.

[0059] In this implementation, since each frequency modulation unit 2 has an independent control voltage VCtrl, different tuning intensities or tuning ranges can be set for different frequency modulation nodes 3 according to their voltage swing, common-mode potential, parasitic parameter distribution, or frequency tuning requirements in the oscillation loop 1. This achieves more precise segmented or distributed tuning control. For example, in some oscillation structures, some nodes are more sensitive to frequency or have larger swings. A smaller control voltage VCtrl variation range or a weaker tuning intensity can be configured for the corresponding frequency modulation unit 2 to reduce disturbances to the oscillation waveform. For other nodes, a stronger tuning intensity can be configured to expand the adjustable range. Simultaneously, the electrical isolation between gates reduces the possibility of mutual coupling between frequency modulation units 2 through the gate network, helping to suppress crosstalk and noise transmission introduced by the control network and improve the controllability and stability of frequency tuning.

[0060] In some embodiments, the circuit architecture includes M frequency modulation units 2, and in the M frequency modulation units 2, the gates of the control transistors 211 in at least two frequency modulation units 2 are electrically connected to each other to receive the same control voltage VCtrl; at the same time, the gate of the control transistor 211 in at least one frequency modulation unit 2 is electrically isolated from the gates of the control transistors 211 in at least two frequency modulation units 2, and is configured to receive an independent control voltage VCtrl. Thus, some frequency modulation units 2 can be cooperatively tuned under the same control voltage VCtrl, while other frequency modulation units 2 can be independently tuned under an independent control voltage VCtrl.

[0061] In some implementations, see Figure 4 The energy storage sub-unit 22 may include an energy storage capacitor 221. The first end of the energy storage capacitor 221 is connected to the source of the control transistor 211, and the second end of the energy storage capacitor 221 is connected to the reference potential terminal.

[0062] During operation, the signal at frequency modulation node 3 is coupled to energy storage capacitor 221 through control transistor 211. As the control voltage VCtrl input to the control terminal changes, the conduction state or degree of conduction of control transistor 211 changes, thereby altering the effective connection of energy storage capacitor 221 to frequency modulation node 3 through control transistor 211. Consequently, the equivalent capacitance at frequency modulation node 3 changes with the control voltage VCtrl, altering the equivalent capacitive load of oscillation loop 1, thus achieving tuning and fine-tuning of the oscillation frequency.

[0063] Using energy storage capacitor 221 as the energy storage sub-unit 22 has several advantages. First, it allows for the formation of the equivalent capacitance at the frequency modulation node 3 with a clearly defined capacitive energy storage and charging / discharging path, making the tuning mechanism more intuitive and stable. Second, connecting the energy storage capacitor 221 to the reference potential terminal helps provide a controllable AC capacitive load for the frequency modulation node 3 and suppresses DC operating point drift, thereby reducing the impact on the DC bias of the oscillation circuit and improving the consistency and predictability of the tuning process. Furthermore, as a common device, the energy storage capacitor 221 is easy to implement and sized on different process platforms, facilitating a design trade-off between tuning range, linearity, and power consumption / area.

[0064] In some embodiments, the energy storage capacitor 221 includes a first metal layer, a dielectric layer, and a second metal layer (not specifically shown in the accompanying drawings). The dielectric layer is sandwiched between the first and second metal layers to form a dielectric isolation structure between the capacitor's plates. At least a portion of the first metal layer constitutes a first terminal of the energy storage capacitor 221, and at least a portion of the second metal layer constitutes a second terminal of the energy storage capacitor 221. The first terminal is used to connect to the source of the control transistor 211, and the second terminal is used to connect to a reference potential terminal.

[0065] The aforementioned capacitor structure offers several advantages. First, it provides a more stable capacitance value and better process controllability, allowing the energy storage capacitor 221 to exhibit more predictable capacitive characteristics across different operating voltage ranges. This, in turn, improves the stability and consistency of the equivalent capacitance adjustment at frequency modulation node 3. Second, this structure facilitates the setting and matching of capacitance values ​​through metal layer area, interlayer dielectric thickness, or stacking method, aiding in optimization across tuning range, linearity, area, and parasitic effects. Furthermore, compared to capacitor solutions relying on semiconductor junctions or gate oxide structures, this structure makes it easier to implement two-terminal capacitor devices with clearly defined terminals, reducing uncertainties in layout implementation and parameter modeling.

[0066] In related technologies, the capacitance value of a voltage-controlled capacitor typically changes with its terminal voltage or bias voltage. This voltage dependence causes the slope of the capacitance change with voltage to be inconsistent across different voltage ranges. Consequently, the equivalent capacitance's response to the control voltage VCtrl during tuning can become nonlinear, causing the oscillator output frequency to fluctuate across different voltage ranges with the slope of the control voltage VCtrl. This increases the difficulty of system parameter design and tuning. Furthermore, voltage-controlled capacitors may be more sensitive to noise, process deviations, and temperature changes, thus affecting the consistency and predictability of frequency tuning.

[0067] In the embodiments of this application, the energy storage capacitor 221 is a non-voltage-controlled capacitor, meaning its capacitance value is not primarily regulated by changes in terminal voltage, but rather acts as a relatively fixed capacitive device to form the equivalent capacitance at the frequency modulation node 3. The tuning process is achieved by the control subunit 21 adjusting the effective connection degree of the energy storage capacitor 221. Therefore, compared to using the capacitor itself as the object of regulation, this application achieves more predictable equivalent capacitance regulation characteristics with a relatively simplified structure. This helps improve the linearity of the output frequency as a function of the control voltage VCtrl over a wider control voltage range, reduces dependence on bias and calibration, and enhances the feasibility and stability of system design and debugging.

[0068] In summary, in this application, the frequency modulation unit 2 is composed of a control subunit 21 and an energy storage subunit 22. The control subunit 21 can be specifically implemented as a control transistor 211. The drain of the control transistor 211 is connected to the frequency modulation node 3 in the oscillation loop 1, and its gate serves as the control terminal receiving the control voltage VCtrl. The source is connected to the first terminal of the energy storage subunit 22. The energy storage subunit 22 can be specifically implemented as an energy storage capacitor 221, with its second terminal connected to a reference potential terminal. During oscillation operation, a periodically changing oscillation signal exists at the frequency modulation node 3, forming a voltage swing between high and low levels. Under the action of the control voltage VCtrl, the control transistor 211 exhibits adjustable conduction characteristics, allowing the energy storage capacitor 221 to effectively connect to the frequency modulation node 3 within one oscillation cycle according to the control voltage. The voltage VCtrl changes, causing the charge amount of the energy storage capacitor 221 to change with the control voltage VCtrl during the cycle. An equivalent relationship can be established between this charge amount and the voltage swing at the frequency modulation node 3, resulting in the equivalent capacitance at the frequency modulation node 3 changing with the control voltage VCtrl. Since the tuning process is achieved by the control transistor 211 adjusting the effective connection degree of the energy storage capacitor 221, rather than relying on the capacitance value of the capacitor itself changing with the voltage, under the condition that the threshold voltage Vth basically does not change with the control voltage VCtrl, the response of the equivalent capacitance to the control voltage VCtrl has a more predictable trend. This helps to improve the linearity of the output frequency changing with the control voltage VCtrl and reduce the difficulty of system parameter design and debugging.

[0069] Further, see Figure 9 The principle of this application is explained as follows: In this scheme, the control transistor 211 acts as a switch: when the voltage between its gate and source is greater than the threshold voltage Vth, the control transistor 211 is turned on, connecting the energy storage capacitor 221 into the oscillator loop; when the voltage between its gate and source is less than the threshold voltage Vth, the control transistor 211 is turned off, disconnecting the energy storage capacitor 221 from the oscillator loop. A periodic signal is applied to the drain terminal of the control transistor 211, and the drain receives a corresponding voltage wave (…). Figure 9 In the diagram above, the source receives the corresponding voltage waveform. Figure 9 (See the image below).

[0070] Since the gate voltage is Vg (equal to the control voltage VCtrl), the highest voltage that the energy storage capacitor 221 can reach in one cycle is approximately Vg−Vth. Let the low-level voltage in this cycle be VL, then the voltage swing of the energy storage capacitor 221 in this cycle is ΔV=(Vg−Vth)−VL. Therefore, the charge / discharge amount in this cycle is Q=C·ΔV=C[(Vg−Vth)−VL], where C is the capacitance of the energy storage capacitor 221. On the other hand, the voltage swing at frequency modulation node 3 is VH−VL, where VH is the high-level voltage in this cycle. Therefore, the equivalent capacitance Cequal=Q / (VH−VL)=C[(Vg−Vth)−VL] / (VH−VL). It can be seen that as Vg increases, the equivalent capacitance increases accordingly, and the equivalent capacitance is proportional to Vg−Vth, with a rate of change of C / (VH−VL). Under relatively stable threshold voltage conditions, the equivalent capacitance exhibits a more predictable trend as the control voltage changes, which is beneficial for obtaining better linearity.

[0071] This application also provides an oscillator including the circuit architecture described above. Because the circuit architecture introduces a frequency modulation unit 2, composed of a control subunit 21 and an energy storage subunit 22, at the frequency modulation node 3 of the oscillation loop 1, the oscillator can achieve controlled changes in the equivalent capacitance at the frequency modulation node 3 under the control voltage VCtrl, thereby achieving continuous fine-tuning of the output frequency. Compared to the tuning method in related technologies that directly relies on the voltage-controlled capacitor's capacitance changing with voltage, this oscillator helps to obtain more predictable frequency tuning characteristics over a wider control voltage VCtrl range, improves the linearity and consistency of the output frequency changing with the control voltage VCtrl, and reduces the difficulty of system parameter design and debugging. Simultaneously, the frequency modulation unit 2 is modularly connected to the frequency modulation node 3, facilitating adaptation to different oscillation structures, helping to reduce implementation complexity and improve the flexibility of engineering applications.

[0072] This application also provides a chip including the aforementioned oscillator. This chip can be applied to integrated circuit scenarios requiring an on-chip adjustable clock or local oscillator signal, such as phase-locked loops and frequency synthesizers, RF transceivers and wireless communication chips, serial high-speed interfaces and clock data recovery circuits, on-chip interconnects and processors, memory clock generation modules, etc., to provide an adjustable reference clock, carrier local oscillator, or internal operating clock. Because the oscillator integrated within the chip adopts the aforementioned circuit architecture, it can achieve continuous fine-tuning of the output frequency under the control voltage VCtrl, and helps to obtain more predictable frequency tuning characteristics over a wider control voltage VCtrl range, thereby improving frequency control linearity and consistency, and reducing the difficulty of system-level loop parameter design and debugging. At the same time, this frequency modulation structure is relatively simple, which helps to reduce implementation and verification complexity, and improves integration adaptability and mass production consistency under different processes and system configurations.

[0073] This application also provides an electronic device that includes the aforementioned chip. As examples, the electronic device may be a smartphone, tablet, laptop, smartwatch, or other wearable device; wireless earphones and their charging cases; a wireless router or home gateway; a 5G small base station / micro base station; an IoT terminal (such as a smart door lock, sensor node, asset tracking tag); an in-vehicle communication and infotainment system; an industrial controller; or an industrial gateway.

[0074] In the aforementioned electronic devices, this chip can be used to provide an on-chip adjustable clock or RF local oscillator signal, applied to wireless communication links (cellular, Wi-Fi, Bluetooth, etc.), high-speed data interfaces and clock data recovery, as well as system modules requiring frequency synthesis or clock management. Because the chip-integrated oscillator can achieve continuous fine-tuning over a wide control voltage VCtrl range and improve the predictability of frequency tuning characteristics, it helps improve the clock / local oscillator consistency of the device under different operating modes, environmental conditions, and batches, reducing the complexity of system parameter tuning and calibration, thereby improving the overall communication stability, connection reliability, and mass production controllability.

[0075] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.

[0076] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.

[0077] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A circuit architecture, characterized in that: The circuit architecture includes: An oscillation circuit having at least one oscillation loop, the oscillation loop including at least one frequency modulation node; At least one frequency modulation unit includes a control subunit and an energy storage subunit; the control subunit has a first terminal, a second terminal, and a control terminal; the first terminal is electrically connected to the frequency modulation node, and the second terminal is electrically connected to the first terminal of the energy storage subunit; the control terminal is configured to receive a control voltage; the second terminal of the energy storage subunit is electrically connected to a reference potential terminal. The control subunit is configured to adjust the energy storage subunit in response to the control voltage so that the equivalent capacitance at the frequency modulation node changes with the control voltage.

2. The circuit architecture according to claim 1, characterized in that: The first end of the energy storage subunit is configured to connect to the frequency modulation node via the control subunit when the control subunit responds to the control voltage.

3. The circuit architecture according to claim 1, characterized in that: The circuit architecture includes M frequency modulation units; at least one of the oscillation loops includes N frequency modulation nodes; Where M is an integer greater than or equal to 1, and N is an integer greater than or equal to 1; the M frequency modulation units are electrically connected to at least one of the N frequency modulation nodes.

4. The circuit architecture according to claim 3, characterized in that: The control subunit includes a control transistor; The drain of the control transistor is electrically connected to the frequency modulation node, the source of the control transistor is electrically connected to the first terminal of the energy storage sub-unit, and the gate of the control transistor is electrically connected to the control terminal.

5. The circuit architecture according to claim 4, characterized in that: The control transistor is an N-type transistor or a P-type transistor.

6. The circuit architecture according to claim 4, characterized in that: In the M frequency modulation units, the gates of the control transistors in each control subunit are electrically connected to each other to receive the same control voltage.

7. The circuit architecture according to claim 4, characterized in that: In the M frequency modulation units, the gates of the control transistors in each control subunit are electrically isolated from each other and are respectively configured to receive independent control voltages.

8. The circuit architecture according to claim 4, characterized in that: The energy storage subunit includes an energy storage capacitor; The first end of the energy storage capacitor is electrically connected to the source of the control transistor, and the second end of the energy storage capacitor is electrically connected to the reference potential terminal.

9. The circuit architecture according to claim 8, characterized in that: The energy storage capacitor includes a first metal layer, a dielectric layer, and a second metal layer; The dielectric layer is sandwiched between the first metal layer and the second metal layer; Wherein, at least a portion of the first metal layer constitutes the first terminal of the energy storage capacitor, and at least a portion of the second metal layer constitutes the second terminal of the energy storage capacitor.

10. The circuit architecture according to claim 8, characterized in that: The energy storage capacitor is a non-voltage-controlled capacitor.

11. An oscillator, characterized in that: Includes the circuit architecture as described in any one of claims 1 to 10.

12. A chip, characterized in that: Including the oscillator as described in claim 11.

13. An electronic device, characterized in that: Including the chip as described in claim 12.

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