Storage array and preparation method thereof, memory and electronic equipment

Abstract

The embodiment of the invention provides a storage array and a preparation method thereof, a memory and electronic equipment, and relates to the technical field of electronic equipment. The memory array includes a stack structure, a plurality of channel layers, and a transition structure. The stacked structure comprises a plurality of electrode layers which are stacked and arranged at intervals; the stacked structure is provided with an open groove, the open groove comprises an open hole and a plurality of sub-grooves, the open hole penetrates through the multiple electrode layers, the sub-grooves are formed in the hole wall of the open hole, and the sub-grooves and the electrode layers are arranged on the same layer. A channel layer is disposed in the sub-trench. The transition structure is arranged in the sub-groove and is arranged on the surface, close to the electrode layer, of the channel layer, and the transition structure is in contact with the channel layer and the electrode layer; the conductivity of the transition structure is greater than or equal to that of the channel layer, and the conduction band height of the transition structure material is greater than that of the electrode layer material. According to the embodiment of the invention, the contact resistance between the electrode and the channel layer is reduced while the electric signal transmission capability of the electrode is not influenced.

Description

Technical Field

[0001] This application relates to the field of electronic device technology, and in particular to a storage array and its fabrication method, a memory, and an electronic device. Background Technology

[0002] Memory, such as dynamic random access memory (DRAM), enables the storage and retrieval of data. To meet the demands for high-density storage, memory with a three-dimensional stacked structure (such as 3DDRAM) has been rapidly developed.

[0003] However, compared to traditional planar memory structures, the electrical performance of three-dimensional stacked memory structures is reduced. For example, due to the large aspect ratio of the stacked structure, some doping and surface treatment processes commonly used in planar structures are no longer applicable, resulting in the inability to effectively reduce the contact resistance between the channel layer and the electrode in the three-dimensional stacked structure, thus affecting the electrical performance of the memory. Summary of the Invention

[0004] This application provides a memory array and its fabrication method, a memory, and an electronic device. The purpose is to reduce the contact resistance between the electrodes and the channel layer without affecting the electrical signal transmission capability (conductivity) of the electrodes (source and drain) themselves, thereby improving the transmission capability between the electrodes and the channel layer and optimizing the electrical performance of the memory array.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a memory array is provided, which includes a stacked structure, multiple channel layers, and a transition structure.

[0007] The stacked structure includes multiple electrode layers stacked and spaced apart. The stacked structure has slots, each slot including an opening and multiple sub-slots. The opening penetrates through the multiple electrode layers, and the multiple sub-slots are disposed on the walls of the opening, each sub-slot being located within one of the multiple electrode layers. Multiple channel layers are disposed within the multiple sub-slots. The electrode layers and channel layers are used to form transistors. A transition structure is disposed within the sub-slots, contacting both the channel layers and the electrode layers. The conductivity of the transition structure material is greater than that of the channel layer material, and the conduction band height of the transition structure material is greater than that of the electrode layer material.

[0008] In the memory array provided in this application embodiment, a transition structure is provided. The conduction band height of the transition structure is higher than that of the electrode layer, and the conductivity is higher than that of the channel layer. This makes the electron transport capability between the transition structure and the electrode layer higher than that between the electrode layer and the channel layer when the electrode layer is in direct contact with the channel layer. Furthermore, the barrier height between the transition structure and the channel layer is lower than that between the electrode layer and the channel layer when the electrode layer is in direct contact with the channel layer. This improves the overall transport capability of the electrode layer connected to the channel layer through the transition structure and optimizes the electrical performance of the memory array. For example, due to the enhanced transport capability between the electrode layer and the channel layer, the memory array provided in this application embodiment can have a larger drive current under the same driving voltage, thereby accelerating the charging speed of the capacitors in the memory array, i.e., improving the access speed of the memory array. Or, for example, when the access speed requirements of the memory array are already met (i.e., the drive current remains unchanged), due to the enhanced transport capability between the electrode layer and the channel layer, only a lower driving voltage is needed to drive the transistors in the memory array, thereby reducing the overall power consumption of the memory array and making the memory array applicable to some low-power scenarios.

[0009] Furthermore, the transition structure is disposed in the sub-slot, that is, only disposed on the part of the electrode layer directly opposite the channel layer (i.e. the part of the electrode layer exposed by the sub-slot), which will not significantly increase the resistance of the electrode layer itself. In other words, the memory array provided in this application embodiment can improve the carrier transport capability between the electrode layer and the channel layer without affecting the signal transmission capability of the electrode layer itself (e.g., the transmission capability of electrical signals transmitted from external structures to the electrode layer in the electrode layer).

[0010] In the first possible implementation, the material of the transition structure is a conductor, thereby ensuring that the conductivity of the transition structure material is greater than that of the channel layer (semiconductor material), ensuring that electrical signal transmission can be achieved between the transition structure and the electrode layer. Since both the electrode layer and the transition structure are conductors, an ohmic contact can be formed between them without overcoming potential barriers such as those between conductors and semiconductors (e.g., Schottky contact barriers). This allows the contact resistance between the electrode layer and the transition structure to be lower than the contact resistance when the electrode layer and the channel layer are in direct contact.

[0011] In one possible implementation of the first aspect, the material of the transition structure includes metal oxides. Such metal oxide transition structures have a higher conduction band height compared to metal materials, thereby reducing or eliminating the Schottky barrier height between the transition structure and the channel layer. This reduces the contact resistance between the transition structure and the channel layer, ultimately making the total parasitic resistance between the electrode layer, transition structure, and channel layer lower than the parasitic resistance when the electrode layer and channel layer are in direct contact. This increases the drive current between the electrode layer, transition structure, and channel layer, and optimizes the access speed of the memory array.

[0012] In the first possible implementation, the carrier concentration of the transition structure is relatively high, approximately 10. 18 cm -3 ~10 21 cm -3 .

[0013] In one possible implementation of the first aspect, the transition structure includes multiple sub-layers stacked along the direction from the electrode layer to the channel layer.

[0014] In one possible implementation of the first aspect, the conduction band height of the multilayer sublayer material gradually increases along the direction from the electrode layer to the channel layer. This multilayer sublayer divides the barrier height between the electrode layer and the channel layer into multiple smaller barrier heights, achieving a gradual progression of the barrier height between the electrode layer and the channel layer. This further reduces the difficulty of crossing the barrier height between the electrode layer and the channel layer, i.e., reduces the contact resistance between the electrode layer and the channel layer, improves the transmission performance between them, and further improves the electrical performance of the memory array.

[0015] In one possible implementation of the first aspect, the electrode layer includes multiple conductive layers arranged sequentially from the inside out, with the outermost conductive layer in contact with the transition structure.

[0016] In one possible implementation of the first aspect, the conduction band height of the multilayer conductive layer material gradually increases from the innermost conductive layer to the outermost conductive layer.

[0017] That is, by utilizing the multi-layer design of the electrode layer itself, the barrier height between the electrode layer and the channel layer can be further divided and decomposed, thereby further reducing the difficulty of crossing the barrier height between the electrode layer and the channel layer, i.e. reducing the contact resistance between the electrode layer and the channel layer, improving the transmission performance between the two, and further improving the electrical performance of the memory array.

[0018] In one possible implementation of the first aspect, the material of the transition structure includes InSnO, and the electrode layer includes a conductive layer of metal material and a conductive layer of InSnO material surrounding the conductive layer of metal material. The In content in the transition structure is lower than the In content in the electrode layer, so that the conduction band height gradually increases from the innermost conductive layer of the electrode layer to the outermost conductive layer of the electrode layer and then to the transition structure material, depending on the In content.

[0019] In one possible implementation of the first aspect, each channel layer includes a plurality of channel layers spaced apart along a second direction, and the plurality of channel layers corresponding to a plurality of spaced transition structures in contact; the electrode layer extends along the second direction. Specifically, at least two transition structures corresponding to at least two channel layers in the same layer are in contact with the same electrode layer.

[0020] That is, multiple transistors are arranged along the second direction, and the multiple channel layers corresponding to these multiple transistors are spaced apart from each other, and the corresponding transition structures are also spaced apart, while these multiple transistors can share an electrode layer.

[0021] When multiple transistors share a single bit line BL (e.g., the first electrode), the multiple transition structures corresponding to these transistors remain disconnected from each other, thereby preventing multiple transition structures from forming a complete loop to participate in the current transmission of the electrode layer itself and avoiding an increase in the resistance of the electrode layer.

[0022] In the first possible implementation, the material of the transition structure is a partially crystallized or fully crystallized material, so that during the preparation process, the transition structure can be correspondingly set on the part of the electrode layer that is directly opposite to the channel layer, so as to achieve a certain self-alignment effect. For example, the transition structure can be formed by inducing crystallization on the exposed part of the electrode layer, and the uncrystallized transition structure material at other locations can be removed, so that the transition structure is accurately set on the part of the electrode layer that is directly opposite to the channel layer (i.e., the exposed part of the groove), and the performance of the crystallized or fully crystallized transition structure is relatively stable and the service life is relatively long.

[0023] In one possible implementation of the first aspect, the material of the transition structure includes one or more of InO, InGaO, InZnO, InSnO, ZnAlO, InSnZnO, and InSnGaZnO. These materials can make the conduction band height of the transition structure greater than that of the electrode layer and the conductivity greater than or equal to that of the channel layer, thereby optimizing the transport performance between the electrode layer and the channel layer.

[0024] Secondly, a method for fabricating a storage array is provided, the method comprising:

[0025] A stacked structure is formed, comprising multiple electrode layers stacked and spaced apart. A slot is formed in the stacked structure; the slot includes an opening penetrating the multiple electrode layers, and the multiple sub-slots are disposed on the walls of the opening, each sub-slot being disposed within one of the multiple electrode layers. A transition structure is formed on the inner wall portion of the electrode layer belonging to the sub-slot; the conductive band height of the transition structure material is greater than the conductive band height of the electrode layer material. A channel layer is formed on the inner wall of the sub-slot; the transition structure contacts both the channel layer and the electrode layer, and the conductivity of the transition structure material is greater than or equal to the conductivity of the channel layer material.

[0026] The fabrication method provided in this application embodiment can prepare a memory array with a transition structure. By setting the transition structure, the electron transport capability between the transition structure and the electrode layer is higher than that between the electrode layer and the channel layer when the electrode layer is in direct contact with the channel layer. Moreover, the barrier height between the transition structure and the channel layer is lower than that between the electrode layer and the channel layer when the electrode layer is in direct contact with the channel layer. This improves the overall transport capability of the electrode layer connected to the channel layer through the transition structure and optimizes the electrical performance of the memory array.

[0027] In a possible implementation of the second aspect, forming a transition structure on the portion of the electrode layer belonging to the inner wall of the sub-groove includes:

[0028] An amorphous buffer film is formed on the inner wall of the groove. The portion of the amorphous buffer film located on the electrode layer is induced to crystallize, forming a transition structure. The uncrystallized portion of the amorphous buffer film is then removed.

[0029] This fabrication process facilitates accurate crystallization of the amorphous buffer film located on the electrode layer, thereby enabling selective growth of the transition structure, improving the fabrication precision of the transition structure, and reducing its fabrication difficulty.

[0030] Thirdly, a memory is provided, comprising peripheral circuitry and a memory array provided in the embodiments of the first aspect. The memory array is electrically connected to the peripheral circuitry.

[0031] Fourthly, an electronic device is provided, comprising a bus and a memory provided in the embodiments of the second aspect. The memory is electrically connected to the bus.

[0032] The technical effects of the memory in the third aspect and the electronic devices in the fourth aspect can be seen in the technical effects of the memory array design in the first aspect, and will not be repeated here. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0034] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0035] Figure 3 A schematic diagram of a storage array provided in an embodiment of this application;

[0036] Figure 4 An exploded view of a storage array structure provided in an embodiment of this application;

[0037] Figure 5 For along Figure 3 A cross-sectional view of section line A-A' in the diagram;

[0038] Figure 6 For along Figure 3 Another cross-sectional view of section line A-A' in the diagram;

[0039] Figure 7 For along Figure 3 A cross-sectional view of section line B-B' in the diagram;

[0040] Figure 8 For along Figure 3 Another cross-sectional view of section line A-A' in the diagram;

[0041] Figure 9 This is a schematic diagram of another structure of the storage array provided in an embodiment of this application;

[0042] Figure 10 A top view of a storage array provided in an embodiment of this application;

[0043] Figure 11 Other top views of the storage array provided in the embodiments of this application;

[0044] Figure 12 and Figure 13 This is a flowchart illustrating the fabrication process of the storage array provided in an embodiment of this application.

[0045] Figures 14-28 This is a schematic diagram of the structure of the storage array in each fabrication step. Detailed Implementation

[0046] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0047] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0048] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0049] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0050] Connection / linking: can refer to a mechanical or physical connection relationship, that is, A and B are connected or linked. It can mean that there are fastened components (such as screws, bolts, rivets, etc.) between A and B, or that A and B are in contact with each other and are difficult to separate. A and B can be fixed, detachable, or integrated; they can be directly connected or indirectly connected through an intermediate medium.

[0051] Coupling can be understood as direct coupling and / or indirect coupling. "Coupled connection" can be understood as a direct coupling connection and / or indirect coupling connection. Direct coupling, also known as "electrical connection," refers to components being in direct or indirect physical contact and electrically conductive. For example, in circuit construction, different components are connected through physical lines that can transmit electrical signals, such as copper foil or wires on a printed circuit board (PCB). "Indirect coupling" can be understood as two conductors conducting electricity through a gap or without contact. In one embodiment, indirect coupling can also be called capacitive coupling, for example, using the coupling between two conductive parts to form an equivalent capacitance to achieve signal transmission.

[0052] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0053] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0054] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0055] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0056] Furthermore, the scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0057] The following explains the terms mentioned in the embodiments of this application:

[0058] Conduction band height: The conduction band is the highest energy region in a semiconductor material that allows electrons to exist and move freely within it. The conduction band height is the energy difference between the lowest energy point of the conduction band and the vacuum level. A higher conduction band height means that electrons can more easily gain enough energy to transition from the valence band to the conduction band, thereby participating in the conduction process.

[0059] Electrical conductivity refers to the ease with which electric charge flows through a substance, representing the substance's ability to conduct electric current.

[0060] This application provides an electronic device, which can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, in-vehicle equipment, vehicles, and other different types of user equipment or terminal devices; the electronic device can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device.

[0061] Figure 1 This is a schematic diagram of the structure of an electronic device provided as an example of an embodiment of this application.

[0062] For example, such as Figure 1 As shown, the electronic device 1000 may include a bus 205 and a system on chip (SoC) 210 connected to the bus 205.

[0063] The system-on-chip 210 can be used to process data, such as processing application data, processing image data, and caching temporary data.

[0064] For example, the system-on-chip 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and on-chip memory 213 for caching high-speed data.

[0065] For example, the on-chip memory 213 may be static random access memory (SRAM) or embedded flash (eflash), etc.

[0066] For example, the application processor 211, the image processing unit 212 and the on-chip memory 213 described above can be integrated into a single die, or they can be disposed in multiple dies respectively.

[0067] For example, such as Figure 1As shown, the electronic device 1000 may also include an off-chip memory 220 connected to the system-on-chip 210 via a bus 205.

[0068] For example, the off-chip memory 220 may be dynamic random access memory (DRAM). The off-chip memory 220 may be used to store volatile data, such as temporary data generated by the on-chip system 210. The storage capacity of the off-chip memory 220 is typically larger than that of the on-chip memory 213, but its read speed is typically slower than that of the on-chip memory 213.

[0069] For example, the system-on-chip 210 and the off-chip memory 220 can be packaged in a single package structure, such as 2.5D or 3D packaging, to achieve faster inter-chip data transfer rates.

[0070] For example, such as Figure 1 As shown, the electronic device 1000 may also include a communication chip 230 and a power management chip 240 connected to the system-on-a-chip 210 via a bus 205.

[0071] The communication chip 230 can be used for protocol stack processing, or for amplifying and filtering analog radio frequency signals, or simultaneously perform the above functions. The power management chip 240 can be used to supply power to other chips.

[0072] Understandable Figure 1 The structure of the electronic device 1000 shown does not constitute a specific limitation on the electronic device 1000, which may include, for example... Figure 1 The components shown may have more or fewer components, or may be combined as follows: Figure 1 Some of the components shown, or those that can be used with, for example Figure 1 The component arrangements shown are different.

[0073] This application embodiment also provides a memory 100, which can be applied in the above-described electronic device 1000. For example, the memory 100 can be as follows: Figure 1 The on-chip memory 213 shown, or the memory 100, can also be as follows: Figure 1 The off-chip memory 220 is shown. This application embodiment does not limit the specific application scenarios of this memory 100.

[0074] Figure 2 This is a schematic diagram of the structure of the memory 100 provided in an embodiment of this application. Figure 2 As shown, the memory 100 includes a memory array 10 and peripheral circuitry 20.

[0075] The storage array 10 is connected to the peripheral circuit 20, which is used to control access to the storage array 10. For example, the peripheral circuit 20 can control the writing of data to the storage array 10 or control the reading of data from the storage array 10.

[0076] For example, the peripheral circuit 20 may include a word line selection circuit, a bit line selection circuit, a control circuit, and a read / write circuit, etc.

[0077] See Figure 2 For example, storage array 10 may include a plurality of array-distributed storage units G.

[0078] For example, when performing read and write operations on the memory array 10, the read and write circuit transmits control signals to the word line selection circuit and the bit line selection circuit through the control circuit. The word line selection circuit selects a column in the memory array 10, and the bit line selection circuit selects a row in the memory array 10. The word line selection circuit and the bit line selection circuit jointly determine the address of the memory cell G to be accessed.

[0079] For example, peripheral circuitry 20 may be arranged around memory array 10, see, for example, see Figure 2 The peripheral circuit 20 is disposed on at least one side of the storage array 10.

[0080] For example, the peripheral circuitry 20 may be stacked with the memory array 10, for instance, the memory array 10 may be stacked on top of the peripheral circuitry 20 (not shown in the figure).

[0081] This application also provides a storage array 10.

[0082] Figure 3 This is a schematic diagram of a storage array 10 provided in an embodiment of this application. Figure 4 This is an exploded view of a storage array 10 provided in an embodiment of this application. Figure 5 For along Figure 3 A cross-sectional view of section line A-A' in the diagram. Figure 6 For along Figure 3 Another cross-sectional view of section line A-A' in the diagram. Figure 7 For along Figure 3 The cross-sectional view of section line B-B' in the diagram.

[0083] For example, the memory array 10 may include a plurality of transistors stacked in three dimensions. For instance, the memory array 10 may be a 3D DRAM with a vertical word line (VWL) architecture (see [reference]). Figure 3 Alternatively, it can be a 3DDRAM with a vertical bit line (VBL) architecture, or the memory array 10 can be a 1T1C structure (see [reference]). Figure 6Each memory cell G in the memory array 10 includes a transistor and a capacitor, or it can be a 1TnC structure, or the memory array 10 can be a resistive random access memory (RRAM or ReRAM). It is understood that any structure that can build multiple transistors in vertical space is within the protection scope of the memory array 10 referred to in the embodiments of this application, and the embodiments of this application do not limit it.

[0084] In some embodiments, such as Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 As shown, the memory array 10 includes a stacked structure 1, a multi-channel layer 2, and a transition structure 3.

[0085] For example, see Figure 5 , Figure 6 and Figure 7 Stacked structure 1, multi-layer channel layer 2, transition structure 3 and other structures can be disposed on substrate N, which serves as a support structure for the fabrication of the aforementioned structures.

[0086] See Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 The stacked structure 1 includes multiple electrode layers 11 that are stacked and spaced apart.

[0087] See Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 The multilayer electrode layer 11 is stacked along the third direction Z.

[0088] The electrode layer 11 is used to form the electrodes of a transistor, for example, it can be used to form the source and drain of a transistor.

[0089] See Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 The multilayer electrode layers 11 are stacked so that the corresponding multiple transistors can be stacked in three dimensions, thereby increasing the storage capacity of the storage array 10.

[0090] See Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7The multiple electrode layers 11 are spaced apart, which facilitates the division between the multiple transistors corresponding to the multiple electrode layers 11. Furthermore, the spaced arrangement of the multiple electrode layers 11 facilitates the formation of sub-grooves K2 in the film layer containing the electrode layers 11 (see [reference]). Figure 5 and Figure 6 This facilitates the formation of multiple independent channel layers 2 in the sub-slot K2.

[0091] For example, the electrode layer 11 is used to form at least one electrode of a transistor.

[0092] For example, see Figure 5 and Figure 6 The electrode layer 11 may include a first electrode 111 and a second electrode 112.

[0093] The first electrode 111 and the second electrode 112 are disposed at different positions in the same channel layer 2 so that when no channel is formed in the channel layer 2, the first electrode 111 and the second electrode 112 are insulated from each other through the channel layer 2, and when a channel is formed in the channel layer 2, the first electrode 111 and the second electrode 112 are connected to each other through the channel in the channel layer 2. That is, the first electrode 111 and the second electrode 112 can serve as the source and drain of a transistor, respectively.

[0094] For example, see Figure 5 Multiple second electrodes 112 can be electrically connected, thereby enabling the simultaneous transmission of the same source signal or drain signal to multiple transistors.

[0095] Or, for example, see Figure 6 In the case where the memory array 10 includes transistors and capacitors C, the transistors and capacitors C can share the second electrode 112. That is, the second electrode 112 can be used as the source or drain of the transistor, or as an electrode plate of the capacitor C (e.g., as a memory node SN). Different second electrodes 112 are disconnected from each other.

[0096] For example, see Figure 5 The electrode layer 11 may also include a common electrode C1, which is used as another electrode plate of the capacitor C. The common electrodes C1 of multiple capacitors C can be electrically connected (e.g., they can be integrally set). A dielectric layer C2 may be provided between the common electrode C1 and the second electrode 112.

[0097] For example, the material of the electrode layer 11 is a conductor. For example, the material of the electrode layer 11 may include metals or alloys with strong conductivity such as W, Ru, Ni, Mo, and Ta, so as to ensure that the electrode layer 11 (e.g., the first electrode 111 and the second electrode 112) has good electron transport capability, thereby facilitating the transmission of signals by the electrode layer 11, such as facilitating the electrical transmission between the first electrode 111 and external electrical devices.

[0098] For example, see Figure 7 The memory array 10 may also include a gate 4 and a gate oxide layer 4A.

[0099] The gate 4 is directly opposite the channel layer 2, and the gate 4 is disposed between the first electrode 111 and the second electrode 112 (see reference). Figure 3 The gate 4 can control the channel in the channel layer 2, thereby controlling the conduction or cutoff between the first electrode 111 and the second electrode 112.

[0100] See Figure 7 Gate 4 is used to transmit gate control signals. Gate oxide layer 4A is disposed between gate 4 and channel layer 2 to prevent gate 4 and channel layer 2 from being directly electrically connected.

[0101] For example, see Figure 7 The gates 4 of multiple transistors stacked along the third direction Z can be set together as a single unit, that is, the multiple transistors can share the gate 4 in order to achieve synchronous gate control of the multiple transistors.

[0102] For example, see Figure 5 and Figure 6 The stacked structure 1 may further include multiple dielectric layers 12, which are alternately stacked with multiple electrode layers 11, so that adjacent electrode layers 11 that need to be disconnected from each other can be electrically insulated by the dielectric layers 12. For example, see [reference needed]. Figure 5 and Figure 6 A dielectric layer 12 may be sandwiched between adjacent first electrodes 111, or refer to [reference needed]. Figure 6 A dielectric layer 12 may be sandwiched between adjacent second electrodes 112.

[0103] See Figure 5 , Figure 6 and Figure 7 The stacked structure 1 is provided with a slot K, which includes an opening K1 and a plurality of sub-slots K2.

[0104] The slot K is used to penetrate the stacked structure 1 so that multiple channel layers 2 can be formed in the stacked structure 1 through the slot K, thereby forming multiple stacked transistors.

[0105] Among them, see Figure 5 , Figure 6 and Figure 7 An opening K1 is used to penetrate the multilayer electrode layer 11. Multiple sub-slots K2 are provided on the wall of the opening K1. For example, the slot opening of the sub-slot K2 is perpendicular to the wall of the opening K1. The sub-slot K2 is used to provide the channel layer 2.

[0106] See Figure 5 , Figure 6 and Figure 7 Similar to electrode layer 11, two adjacent sub-slots K2 are stacked and spaced apart, so that the two channel layers 2 disposed in the two adjacent sub-slots K2 are spaced apart from each other, thereby realizing independent control between the two adjacent transistors.

[0107] See Figure 5 , Figure 6 and Figure 7 Multiple sub-slots K2 are respectively disposed in the multilayer first collector layer 11, that is, the sub-slots K2 and the electrode layer 11 are disposed in the same layer. For example, at least a portion of the electrode layer 11 is used as part of the inner wall of the sub-slots K2, so that the channel layer 2 disposed in the sub-slots K2 can be electrically connected to the electrode layer 11.

[0108] For example, the slot K can be circular, square, elliptical, etc. This application embodiment does not limit this, and any slot K can penetrate the multilayer electrode layer 11, so that the shape of the slot K for setting multiple channel layers 2 is within the protection scope of this application embodiment.

[0109] See Figure 5 , Figure 6 and Figure 7 The multi-layer channel layer 2 is respectively set in multiple sub-slots K2.

[0110] For example, see Figure 5 , Figure 6 and Figure 7 The channel layer 2 can be laid on the inner wall of the sub-slot K2, wherein the channel layer 2 has a facing area with at least the inner wall of the far-away hole K1 of the sub-slot K2 (i.e., the electrode layer 11) so that current can be transmitted between the channel layer 2 and the electrode layer 11.

[0111] See Figure 5 , Figure 6 and Figure 7 Each sub-slot K2 has a corresponding channel layer 2.

[0112] The channel layer 2 is made of semiconductor material, which is used to form an electrically conductive channel under the control of the gate 4, thereby realizing electrical conduction between the source and drain of the transistor, that is, realizing the transistor being turned on; it is also used to realize electrical insulation between the source and drain of the transistor when the gate 4 applies a low voltage to turn off the channel, that is, realizing the transistor being turned off.

[0113] For example, see Figure 3 When the electrode layer 11 includes a first electrode 111, a second electrode 112 and a gate 4, a channel layer 2 can simultaneously contact the first electrode 111 and the second electrode 112, and contact the gate oxide layer 4A of the gate 4. Thus, under the control of the gate 4, a channel can be formed in the channel layer 2, thereby realizing the conduction between the first electrode 111 and the second electrode 112, that is, realizing the turn-on of the transistor.

[0114] For example, the material of the channel layer 2 may include at least one of the following: single-crystal silicon (Si), polycrystalline silicon (poly-Si), amorphous silicon (amorphous-Si), indium gallium zinc oxide (In-Ga-Zn-O, abbreviated as IGZO), single-crystal germanium (Ge), zinc oxide (ZnO), indium tin oxide (ITO), titanium dioxide (TiO2), molybdenum disulfide (MoS2), gallium arsenide (GaAs), indium phosphide (InP), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0115] For example, see Figure 5 , Figure 6 and Figure 7 Multiple channel layers 2 are disconnected from each other and spaced apart, so that multiple independent transistors can be formed accordingly.

[0116] For example, see Figure 5 , Figure 6 and Figure 7 Multiple sub-slots K2 are spaced apart on the sidewall of the opening K1, while the channel layer 2 is only set in the inner wall of the sub-slots K2 and not on the sidewall of the opening K1, so that adjacent channel layers 2 can be spaced apart and independent of each other.

[0117] For example, the channel layer 2 can be annular, such as square annular, or it can also be circular annular, elliptical annular, or other annular, or for example, see [reference]. Figure 3 The channel layer 2 can also be U-shaped.

[0118] The annular or U-shaped channel layer 2 facilitates simultaneous contact between the channel layer 2 and the first electrode 111, the second electrode 112, and the gate 4, while also achieving mutual spacing between the first electrode 111, the second electrode 112, and the gate 4. For example, see [reference needed]. Figure 3 The first electrode 111, the second electrode 112, and the gate 4 can be respectively disposed on different sides of the channel layer 2 (e.g., Figure 3 The first electrode 111 is disposed on the left side of the channel layer 2, thereby achieving mutual spacing between the three.

[0119] It is understood that in other embodiments, the channel layer 2 may be of other shapes, and the relative positions between the channel layer 2 and the first electrode 111, the second electrode 112 and the gate 4 may be other configurations. The embodiments of this application do not limit these features.

[0120] See Figure 5 and Figure 6 The transition structure 3 is disposed in the sub-slot K2, that is, the transition structure 3 is disposed on the surface of the channel layer 2 near the electrode layer 11, and the transition structure 3 is sandwiched between the channel layer 2 and the electrode layer 11 so that the transition structure 3 can contact the channel layer 2 and the electrode layer 11 respectively, and the channel layer 2 and the electrode layer 11 are electrically connected through the transition structure 3.

[0121] For example, see Figure 3 , Figure 4 , Figure 5 and Figure 6 At least one transition structure 3 can be provided on each channel layer 2.

[0122] For example, a transition structure 3 can be provided only on the portion of each channel layer 2 facing the first electrode 111, so that the channel layer 2 is in direct contact with the second electrode 112, thereby improving the transmission capability between the channel layer 2 and the first electrode 111.

[0123] Alternatively, for example, a transition structure 3 can be provided only on the portion of each channel layer 2 facing the second electrode 112, with the channel layer 2 in direct contact with the first electrode 111, thereby improving the transmission capability between the channel layer 2 and the second electrode 112.

[0124] Or, for example, see Figure 5 and Figure 6 Transition structures 3 can be provided on both the portion of the channel layer 2 facing the first electrode 111 and the portion of the channel layer 2 facing the second electrode 112, thereby improving not only the transmission capability between the channel layer 2 and the first electrode 111, but also the transmission capability between the channel layer 2 and the second electrode 112.

[0125] It is understood that the above embodiments of this application are only illustrative examples of some configurations of the transition structure 3, and are not intended to limit it. Other configurations of the transition structure 3 that can improve the transmission capability between the electrode layer 11 and the channel layer 2 are all within the protection scope of the embodiments of this application.

[0126] For example, see Figure 3 and Figure 4 The transition structure 3 only contacts the portion of the electrode layer 11 that is directly opposite the channel layer 2. This allows for current transmission between the channel layer 2, the transition structure 3, and the electrode layer 11, while controlling the area of ​​the electrode layer 11 occupied by the transition structure 3. This prevents the transition structure 3 from excessively affecting the conductivity of the electrode layer 11 and ensures that the current transmission capability of the electrode layer 11 itself is not affected.

[0127] From an electrical performance perspective, the conductivity of transition structure 3 is greater than or equal to that of channel layer 2; and from a band structure analysis perspective, the conduction band height of the material in transition structure 3 is greater than that in electrode layer 11. Therefore, without affecting electron transport between transition structure 3 and electrode layer 11, the contact resistance between transition structure 3 and channel layer 2 is reduced, thereby optimizing the overall transport effect between channel layer 2 and electrode layer 11. In other words, compared to direct contact between channel layer 2 and electrode layer 11, the transition structure 3 effectively optimizes the transport effect between them.

[0128] For example, the material of the transition structure 3 can be a conductor, thereby ensuring that the conductivity of the material of the transition structure 3 is greater than that of the channel layer 2 (semiconductor material), ensuring that electrical signal transmission can be achieved between the transition structure 3 and the electrode layer 11. Since both the electrode layer 11 and the transition structure 3 are conductors, an ohmic contact is formed between them, without needing to overcome potential barriers such as those between conductors and semiconductors (e.g., Schottky contact barriers). This allows the contact resistance between the electrode layer 11 and the transition structure 3 to be lower than the contact resistance when the electrode layer 11 is in direct contact with the channel layer 2.

[0129] For example, the conductivity of the material of the transition structure 3 can be lower than that of the material of the electrode layer 11 and higher than that of the material of the channel layer 2, so that the transition structure 3 can reduce the contact resistance with the channel layer 2 without adding additional series parasitic resistance, thereby taking into account both the transmission capability between the transition structure 3 and the electrode layer 11 and the transmission capability between the transition structure 3 and the channel layer 2.

[0130] For example, the material of the transition structure 3 may include a metal oxide, which can make the transition structure 3 have a higher conduction band height than the electrode layer 11 material, thereby reducing the contact resistance between the transition structure 3 and the channel layer 2 (i.e. eliminating or reducing the Schottky contact barrier), increasing the drive current between the electrode layer 11 and the channel layer 2, and optimizing the access speed of the memory array 10.

[0131] That is, the transition structure 3 can be a conductive metal oxide, so that the transition structure 3 can have both a strong electron transport capability with the electrode layer 11 and a high conduction band height to facilitate carrier transport with the channel layer 2.

[0132] For example, the transition structure 3 has a high carrier concentration, for example, a carrier concentration of approximately 10. 18 cm -3 ~10 21 cm -3 .

[0133] For example, the material of the transition structure 3 may include at least one of an oxide of In metal and an oxide of Zn metal.

[0134] For example, the material of the transition structure 3 may include one or more of InO, InGaO, InZnO, InSnO, ZnAlO, InSnZnO, and InSnGaZnO.

[0135] For example, the material of the transition structure 3 can be a monolithic material or a multi-component material, and the embodiments of this application do not limit this.

[0136] With the continuous evolution of integrated circuit technology, the logic units of processors in electronic products such as computers and mobile phones have developed rapidly. However, due to the differences in structure and process between logic units and memory units (such as DRAM), the storage density and read / write speed of memory have gradually failed to keep up with the processing speed of processors, resulting in the "memory wall" problem. Ultimately, this limits the overall performance of electronic products. In order to improve storage density, three-dimensional stacked memory arrays have emerged.

[0137] However, the electrical performance of three-dimensional stacked memory arrays is poor. For example, the transmission effect between the channel layer and the electrode layer is poor. In some other embodiments, ion implantation is used to treat the channel layer of the memory array in order to reduce the contact resistance between the channel layer and the electrode layer. However, due to the large aspect ratio of the three-dimensional stacked structure (e.g., the aperture K2 on the stacked structure 1), usually only the upper channel layer can be implanted with sufficient impurity ions, while the lower channel layer cannot be treated. As a result, the overall contact resistance between the channel layer and the electrode layer in the memory array is still high, and the transmission capabilities of different layers are different, resulting in poor electrical performance of the memory array.

[0138] In the memory array 10 provided in this application embodiment, by setting a transition structure 3, and setting the conduction band height of the transition structure 3 to be higher than that of the electrode layer 11 and the conductivity to be higher than that of the channel layer 2, the electron transport capability between the transition structure 3 and the electrode layer 11 is higher than that between the electrode layer 11 and the channel layer 2 when the electrode layer 11 is in direct contact with the channel layer 2. Furthermore, the barrier height between the transition structure 3 and the channel layer 2 is lower than that between the electrode layer 11 and the channel layer 2 when the electrode layer 11 is in direct contact with the channel layer 2. This improves the overall transport capability of the electrode layer 11 connected to the channel layer 2 through the transition structure 3, and optimizes the electrical performance of the memory array 10. For example, because the electrode layer 11... With the enhanced transmission capability between the electrode layer 11 and the channel layer 2, the memory array 10 provided in this application embodiment can have a larger drive current under the same drive voltage, thereby accelerating the charging speed of the capacitors in the memory array 10, i.e. improving the access speed of the memory array 10. Or, for example, when the access speed requirements of the memory array 10 are already met (i.e., the drive current remains unchanged), due to the enhanced transmission capability between the electrode layer 11 and the channel layer 2, only a lower drive voltage needs to be applied to the transistors of the memory array 10 to drive the transistors, thereby reducing the overall power consumption of the memory array 10, so that the memory array 10 can be applied to some low-power scenarios.

[0139] Furthermore, the transition structure 3 is disposed in the sub-slot K2, that is, the transition structure 3 is only disposed on the part of the electrode layer 11 facing the channel layer 2 (that is, the part of the electrode layer 11 exposed by the sub-slot K2), which will not significantly increase the resistance of the electrode layer 11 itself. In other words, the memory array 10 provided in this application embodiment can improve the carrier transport capability between the electrode layer 11 and the channel layer 2 without affecting the signal transmission capability of the electrode layer 11 itself (e.g., the transmission capability of electrical signals transmitted from external structures to the electrode layer 11 in the electrode layer 11).

[0140] Furthermore, the transition structure 3 has stronger oxidation resistance than the material of the electrode layer 11 (e.g., the electrode layer 11 is a metal material with high conductivity but easily oxidized and corroded, such as tungsten). This allows the electrode layer 11 to be separated from the channel layer 2 while simultaneously enabling current transmission between the electrode layer 11 and the channel layer 2. This avoids the problem that under the heat treatment conditions of chip processing, the electrode layer 11 may deprive the oxygen element in the channel layer 2, leading to an increase in oxygen vacancies in the channel layer 2 and degradation of electrical performance and reliability. Conversely, the electrode layer 11 may oxidize and its conductivity may decrease, resulting in a deterioration in the transmission effect between the electrode layer 11 and the channel layer 2. This improves the performance of the memory array 10.

[0141] Figure 8 For along Figure 3 Another cross-sectional view of section line A-A' in the diagram.

[0142] In some embodiments, see Figure 8 The transition structure 3 may include multiple sub-layers 31, which are stacked along the direction from the electrode layer 11 to the channel layer 2.

[0143] For example, the materials of the multilayer sublayers 31 may be different, or for example, the materials of the multilayer sublayers 31 may be the same, but the proportion of the same component in different layers may be different, so as to adjust the conductivity, conduction band height, etc. of the materials of the multilayer sublayers 31.

[0144] For example, along the direction from the electrode layer 11 to the channel layer 2, the conduction band height of the multilayer sublayer 31 material gradually increases.

[0145] For example, see Figure 8 The conductor strip height of the multilayer sublayer 31 material located in the slot K and disposed on the right side gradually increases from left to right, and the conductor strip height of the multilayer sublayer 31 material located in the slot K and disposed on the left side gradually increases from right to left. Thus, the barrier height between the electrode layer 11 and the channel layer 2 is divided into multiple smaller barrier heights through the multilayer sublayer 31, realizing the gradual progression of the barrier height between the electrode layer 11 and the channel layer 2. This further reduces the difficulty of crossing the barrier height between the electrode layer 11 and the channel layer 2, that is, reduces the contact resistance between the electrode layer 11 and the channel layer 2, improves the transmission performance between the two, and further improves the electrical performance of the memory array 10.

[0146] Figure 9 This is a schematic diagram of another structure of the storage array 10 provided in an embodiment of this application.

[0147] In some embodiments, see Figure 9The electrode layer 11 includes multiple conductive layers 11A, which are arranged sequentially from the inside to the outside (i.e., layer by layer), and the outermost conductive layer 11A is in contact with the transition structure 3.

[0148] For example, see Figure 9 The electrode layer 11 may include two conductive layers 11A, namely a first conductive layer A1 located on the outer layer and a second conductive layer A2 located on the inner layer, with the first conductive layer A1 sleeved on the second conductive layer A2.

[0149] For example, the multilayer conductive layers 11A can be arranged in a completely annular shape, or refer to Figure 9 The multilayer conductive layers 11A can be partially nested together, for example, see [reference]. Figure 9 The first conductive layer A1 can be disposed only around the three sides of the second conductive layer A2.

[0150] For example, the material of the multilayer conductive layer 11A can be different, for example, Figure 9 The material of the second conductive layer A2 can be a material with high conductivity, such as W, to ensure that the electrode layer 11 has good current transmission capability. Figure 9 The material of the first conductive layer A1 can be a conductive oxide or nitride, such as at least one of TaN and TiN, so as to wrap the inner conductive layer 11A, which has good conductivity but is relatively fragile and easily damaged by oxidation and corrosion, or to facilitate the adhesion strength between the electrode layer 11 and other structures through the outer conductive layer 11A, thereby improving the structural stability of the storage array 10.

[0151] For example, in the multilayer conductive layer 11A, the height of the conductive band of the material of the multilayer conductive layer 11A gradually increases from the innermost conductive layer 11A to the outermost conductive layer 11A.

[0152] That is, the memory array 10 not only reduces the difficulty of crossing the barrier height between the electrode layer 11 and the channel layer 2 through the transition structure 3, but also utilizes the multi-layer design of the electrode layer 11 itself to further divide and decompose the barrier height between the electrode layer 11 and the channel layer 2, thereby further reducing the difficulty of crossing the barrier height between the electrode layer 11 and the channel layer 2, that is, reducing the contact resistance between the electrode layer 11 and the channel layer 2, improving the transmission performance between the two, and further improving the electrical performance of the memory array 10.

[0153] In some embodiments, the height and conductivity of the conduction band can be adjusted by changing the material composition in the transition structure 3 (e.g., changing a certain component in the material), or by changing the proportion of the material composition in the transition structure 3 (e.g., increasing the proportion of a certain component in the material).

[0154] For example, the material of the transition structure 3 includes InSnO, and the electrode layer 11 includes a conductive layer 11A of metal material and a conductive layer 11A of InSnO material surrounding the conductive layer of metal material. The In content in the transition structure 3 is lower than the In content in the electrode layer 11, so that the conduction band height of the multilayer conductive layer 11A and the material of the transition structure 3 gradually increases from the innermost layer of the electrode layer 11 to the channel layer 2.

[0155] Figure 10 This is a top view of the storage array 10 provided in an embodiment of this application.

[0156] In some embodiments, the multiple transistors in the memory array 10 can not only be as Figure 3 As shown, the array can be stacked along the third direction Z, or it can be arrayed along the first direction X and the second direction Y to increase the storage capacity of the storage array 10.

[0157] Wherein, the first direction X and the second direction Y intersect, for example, are perpendicular to each other, and both the first direction X and the second direction Y are perpendicular to the third direction Z, for example, see [reference]. Figure 10 The first direction X can be the arrangement direction of the first electrode 111 and the second electrode 112 in the same transistor, and the first direction X, the second direction Y and the third direction Z are mutually perpendicular.

[0158] For example, see Figure 10 Multiple transistors (two transistors are used as an example in the figure) can be arranged along the second direction Y, that is, each channel layer 2 includes multiple channel layers 2 spaced apart along the second direction Y, and the multiple channel layers 2 are in contact with multiple transition structures 3 spaced apart; the electrode layer 11 extends along the second direction Y (for example, it can form a bit line BL), wherein at least two transition structures 3 corresponding to at least two channel layers 2 in the same layer are in contact with the same electrode layer 11.

[0159] That is, multiple transistors are arranged along the second direction Y, and the multiple channel layers 2 corresponding to these multiple transistors are arranged at intervals, and the corresponding transition structures 3 are also arranged at intervals, while these multiple transistors can share the electrode layer 11.

[0160] For example, see Figure 10 The multiple transistors can share the first electrode 111 so that the same source signal or drain signal can be transmitted to the multiple transistors.

[0161] When multiple transistors share a single bit line BL (e.g., the first electrode 111), the multiple transition structures 3 corresponding to these transistors remain disconnected from each other, thereby preventing the multiple transition structures 3 from forming a complete circuit to participate in the current transmission of the electrode layer 11 itself and avoiding an increase in the resistance of the electrode layer 11.

[0162] In some embodiments, the transition structure 3 can be partially or fully crystallized so that during the preparation process, the transition structure 3 can be correspondingly disposed on the portion of the electrode layer 11 that is directly opposite to the channel layer 2, thereby achieving a certain self-alignment effect. For example, the transition structure 3 can be formed by inducing crystallization on the portion of the electrode layer 11 exposed by the slot K, and the uncrystallized transition structure material at other locations can be removed, thereby making the transition structure 3 accurately disposed on the portion of the electrode layer 11 that is directly opposite to the channel layer 2 (i.e., the portion exposed by the slot K). The performance of the crystallized or fully crystallized transition structure 3 is relatively stable and its service life is relatively long.

[0163] Figure 11 Other top views of the storage array 10 provided in the embodiments of this application.

[0164] In some embodiments, such as Figure 11 As shown, the structure of the storage array 10 can be modified in various ways.

[0165] For example, see Figure 11 (a) and Figure 11 In (e), the gate 4 can be disposed outside the slot K, and is disposed only on one side of the slot K. Figure 3 and Figure 4 Similarly), or for example, see [link to relevant documentation]. Figure 11 (b) and Figure 11 In (f), gate 4 can be disposed on the upper and lower sides of slot K, or, for example, see [reference] Figure 11 In (c), gate 4 can also be filled in slot K to form a gate-around structure, or, for example, see [reference] Figure 11 In (d), the gate 4 can be simultaneously disposed on the inner and outer sides of the slot K, thereby increasing the facing area between the gate 4 and the channel layer 2 and improving the gate control capability.

[0166] For example, see Figure 11 (a) Figure 11 (b) Figure 11 (c) and Figure 11 In (d), the channel layer 2 can be a thin film, for example, the channel layer 2 is attached to the inner wall of the slot K (e.g., sub-slot K2). The thin film channel layer 2 facilitates the miniaturization design of the memory array 10. Or, for example, see [reference missing]. Figure 11 (e) and Figure 11 In (f), the channel layer 2 can also be filled in the slot K.

[0167] For example, see Figures 3 to 10 and Figure 11In (b), the storage array 10 may further include a filling portion 5, which fills the slot K, thereby improving the structural stability of the storage array 10.

[0168] In some embodiments, the material of the channel layer 2 includes a metal oxide semiconductor material.

[0169] For example, the material of the channel layer 2 includes one or more of In2O3, GaO, ZnO, InGaZnO, InSnZnO, InSnGaZnO, InSnO, InGaO, InMgO, InWO and InAlZnO.

[0170] That is, the material of the channel layer 2 in the memory array 10 provided in this application embodiment can be a material with excellent carrier mobility, such as indium gallium zinc oxide, thereby effectively improving the electrical performance of the memory array 10.

[0171] This application also provides a method for fabricating a storage array 10. Figure 12 and Figure 13 Some fabrication flowcharts of the storage array 10 provided in the embodiments of this application are shown. Figures 14-28 This is a schematic diagram of the structure corresponding to each fabrication step of the storage array 10.

[0172] in, Figures 14-28 Each of the figures includes a top view (i.e., a view in the XY direction) of the storage array 10 corresponding to the step, a cross-sectional view along section line C-C' in the top view, and a cross-sectional view along section line D-D' in the top view.

[0173] like Figure 12 As shown, the preparation method includes the following steps S1 to S4.

[0174] S1: See Figures 14-21 This forms a stacked structure 1.

[0175] See Figure 21 The stacked structure 1 may include multiple electrode layers 11 stacked and spaced apart.

[0176] It is understood that the embodiments of this application use the example of the electrode layer 11 including the first electrode 11 and the second electrode 12 to illustrate the structure of the stacked structure 1.

[0177] For example, see Figures 14-21 Step S1 may include the following steps S11 to S16:

[0178] S11: An initial stacked structure P is formed on the substrate N.

[0179] See Figure 14The initial stacked structure P includes a first functional layer P1 and a second functional layer P2. Both the first functional layer P1 and the second functional layer P2 can be insulating materials. For example, the first functional layer P1 can be silicon oxide and the second functional layer P2 can be silicon nitride. Alternatively, the first functional layer P1 and the second functional layer P2 can be a stack of insulating materials and semiconductor materials. For example, the first functional layer P1 can be silicon oxide and the second functional layer P2 can be polycrystalline silicon.

[0180] For example, see Figure 15 and Figure 16 After step S11, the preparation method may further include the following steps S01 and S02:

[0181] S01: See reference Figure 15 A third slot U3 is opened on the initial stacked structure P.

[0182] For example, the area where the gate 4 needs to be set can be defined by photolithography, then a deep hole can be formed by etching, and then a portion of the first functional layer P1 can be etched laterally by selective etching to form the first slot U1.

[0183] See Figure 15 The third slot U3 is set alternately with the first slot U1 and the second slot U2 to avoid unexpected electrical connections between the conductive structures formed inside the three slots.

[0184] S02: See also Figure 16 Gate 4 and gate oxide layer 4A are formed in the third slot U3.

[0185] For example, see Figure 16 The multiple gates 4 corresponding to the stacked transistors are integrated into one unit, which facilitates the synchronous gate control of multiple transistors.

[0186] For example, the material of the gate oxide layer 4A can be referenced to the dielectric layer C2, and will not be described again here. The material of the gate 4 can be referenced to the first electrode 111, and will not be described again here.

[0187] For example, steps S01 and S02 may be located after step S11 and before step S12, or steps S01 and S02 may be located after step S16. This application embodiment does not limit this.

[0188] For example, Figure 15 and Figure 16 A structure in which only one gate 4 is provided on one side of the channel layer 2 of the memory array 10 (e.g.) Figure 3The preparation method is illustrated by taking one example. In other embodiments, multiple third slots U3 can be set to form multiple gates 4. This application does not limit this.

[0189] S12: Create the first slot U1 on the initial stacked structure P.

[0190] See Figure 17 The first slot U1 is used to expose the multiple first functional layers P1 and multiple second functional layers P2 in the initial stacked structure P, so as to facilitate the subsequent formation of the first electrode 111.

[0191] For example, the area where the first electrode 111 needs to be set can be defined by photolithography, and then a deep hole / deep trench can be formed by etching. Subsequently, a portion of the second functional layer P2 can be etched laterally by selective etching to form the first groove U1.

[0192] S13: Fill the first slot U1 with conductive material to form the first electrode 111.

[0193] For example, see Figure 18 The first electrode 111 replaces at least a portion of the second functional layer P2, thereby causing a plurality of first electrodes 111 to be stacked.

[0194] For example, step S13 may include: first filling the first slot U1 with conductive material, then removing the conductive material located in the deep hole, leaving only the conductive material sandwiched between the first functional layers P1, and then filling the deep hole with insulating part P3, thereby forming a plurality of mutually insulated first electrodes 111.

[0195] For example, the material of the first electrode 111 may include metallic materials such as W, Ru, Ti, and Ta, or alloy materials such as NiPt, or conductive oxides or nitrides such as InSnO, TiN, and TaN. The material of the first electrode 111 may also be a double layer or a multilayer stack of the above materials, such as TiN / W, InSnO / W, etc.

[0196] For example, the material of the insulating part P3 may include various insulating oxides, nitrides, carbon oxides, such as SiO, SiN, SiOC, AlO, etc., or other electrically insulating materials and their stacks.

[0197] S14: Create a second slot U2 on the initial stacked structure P.

[0198] See Figure 19 The second slot U2 is used to expose the multiple first functional layers P1 and multiple second functional layers P2 in the initial stacked structure P, so as to facilitate the subsequent formation of the second electrode 112 (or capacitor C).

[0199] For example, the area where the second electrode 112 needs to be set can be defined by photolithography, and then a deep hole can be formed by etching. Subsequently, a portion of the second functional layer P2 can be etched laterally by selective etching to form the second groove U2.

[0200] S15: See also Figure 20 The second slot U2 is filled with conductive material to form the second electrode 112, see reference. Figure 20 The second electrode 112 can serve as one of the plates of the capacitor C.

[0201] For example, the material of the second electrode 112 can be the same as that of the first electrode 111, and will not be described again here.

[0202] For example, in Figure 5 In the fabrication method corresponding to the storage array 10, the conductive material completely fills the second slot U2 so that multiple second electrodes 112 can be integrally set and electrically connected to each other.

[0203] Or, for example, see Figure 20 When the second electrode 112 is also used as another plate of the capacitor C, the preparation process of the second electrode 112 refers to the preparation process of the first electrode 111, that is, the multiple second electrodes 112 are disconnected from each other.

[0204] In this embodiment, see Figure 21 The preparation method may further include:

[0205] S16: See also Figure 21 A dielectric layer C2 and a common electrode C1 are formed to form a complete capacitor C.

[0206] The material of dielectric layer C2 can include materials with high density and high dielectric constant, such as HfOx, ZrAlO, HfAlO, or other materials suitable for capacitor dielectric layers. The material of common electrode C1 can refer to the first electrode 111, and will not be described again here.

[0207] S2: A slot K is formed on the stacked structure 1.

[0208] See Figure 23 The slot K is surrounded by a first slot U1, a second slot U2 and a third slot U3 so that the channel layer 2 formed in the slot K can contact the first electrode 111, the second electrode 112 and the gate 4.

[0209] See Figure 23 The slot K includes an opening K1 and multiple sub-slots K2.

[0210] For example, see Figure 22 and Figure 23 Step S2 may include:

[0211] S21: See also Figure 22 This forms an opening K1.

[0212] See Figure 20 The opening K1 penetrates through the multilayer first electrode layer 11.

[0213] S22: See also Figure 23 By opening K1, the remaining second functional layer P2 is removed to form a sub-groove K2, so as to expose the first electrode 111, the second electrode 112 and the gate oxide layer 4A (e.g., the portion of the gate oxide layer 4A opposite to the gate 4).

[0214] For example, see Figure 23 This step also removes the first functional layer P1 that remains on the inner wall of the opening K1.

[0215] See Figure 23 Multiple sub-slots K2 are disposed on the wall of the opening K1, and the multiple sub-slots K2 are respectively disposed in the multi-layer first collector layer 11. For example, the sub-slots K2 are disposed in the same layer as the first electrode layer 11 so that the channel layer 2 formed later can have a facing area with the first electrode layer 11.

[0216] S3: See also Figures 24-26 A transition structure 3 is formed on the inner wall of the electrode layer 11 that belongs to the sub-slot K2.

[0217] The conduction band height of the transition structure 3 material is greater than that of the electrode layer 11 material, so as to reduce the Schottky barrier height between the transition structure 3 and the subsequently formed channel layer 2 (relative to the direct contact between the electrode layer 11 and the channel layer 2).

[0218] For example, see Figure 13 Step S3 includes the following steps S31 to S33:

[0219] S31: See also Figure 24 An amorphous buffer film Q1 is formed on the inner wall of the slot K.

[0220] See Figure 24 The amorphous buffer film Q1 is in contact with the first electrode 111, the second electrode 112 and the gate oxide layer 4A.

[0221] S32: See also Figure 25 The amorphous buffer film Q1 is induced to partially crystallize on the electrode layer 11 to form a transition structure 3.

[0222] For example, partial crystallization of the amorphous buffer film Q1 on the electrode layer 11 can be achieved using the electrode layer 11. For example, see... Figure 25 A portion of the amorphous buffer film Q1 is located on the crystalline conductive electrode layer 11, while another portion is located on the amorphous insulating layer (e.g., on the gate oxide layer 4A and the second functional layer P2). This allows the two portions of the amorphous buffer film Q1 to have different crystallization temperatures (due to the inductive effect of the crystalline conductor). This facilitates the accurate crystallization of the portion of the amorphous buffer film Q1 located on the electrode layer 11, i.e., achieving selective growth of the transition structure 3, improving the fabrication accuracy of the transition structure 3, and reducing its fabrication difficulty.

[0223] S33: See also Figure 26 Remove the uncrystallized portion of the amorphous buffer film Q1 to expose the area of ​​the gate 4 facing the slot K, so that the subsequently formed channel layer 2 can be controlled by the gate 4 to form a channel.

[0224] For example, a chemical etching method with an etching selectivity can be used to remove the uncrystallized portion of the amorphous buffer film Q1.

[0225] S4: See also Figure 27 A channel layer 2 is formed on the inner wall of sub-groove K2.

[0226] See Figure 27 The transition structure 3 is in contact with the channel layer 2 and the electrode layer 11, respectively.

[0227] The carrier concentration of the transition structure 3 is greater than that of the channel layer 2, and the conductivity is greater than or equal to that of the channel layer 2, thereby ensuring that an ohmic contact can be formed between the transition structure 3 and the electrode layer 11.

[0228] For example, see Figure 27 Different channel layers 2 are disconnected from each other in order to enable independent control of multiple transistors.

[0229] It is understood that different channel layers 2 can be disconnected in various ways, and the embodiments of this application do not limit this.

[0230] For example, see Figure 28 The preparation method may further include:

[0231] S5: A filling portion 5 is formed in the slot K.

[0232] The filling part 5 can be an insulating material, such as various insulating oxides, nitrides, carbon oxides, such as SiO, SiN, SiOC, AlO, GaO, etc., or other insulating materials.

[0233] The preparation method provided in this application embodiment can prepare a memory array 10 with a transition structure 3. The transition structure 3 can make the electron transport capability between the transition structure 3 and the electrode layer 11 higher than the electron transport capability between the electrode layer 11 and the channel layer 2 when the electrode layer 11 is in direct contact with the channel layer 2. Moreover, the barrier height between the transition structure 3 and the channel layer 2 is lower than the barrier height between the electrode layer 11 and the channel layer 2 when the electrode layer 11 is in direct contact with the channel layer 2. This improves the overall transport capability of the electrode layer 11 connected to the channel layer 2 through the transition structure 3 and optimizes the electrical performance of the memory array 10.

[0234] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage array, characterized in that, include: A stacked structure includes multiple electrode layers stacked and spaced apart; the stacked structure is provided with a slot, the slot including an opening and multiple sub-slots, the opening penetrating the multiple electrode layers, the multiple sub-slots being disposed on the wall of the opening, and the multiple sub-slots being respectively disposed in the multiple electrode layers; A multi-channel layer, wherein the multi-channel layer is disposed in the plurality of sub-slots; the electrode layer and the channel layer are used to form a transistor; A transition structure is disposed in the sub-slot, and the transition structure is in contact with the channel layer and the electrode layer respectively; the electrical conductivity of the material of the transition structure is greater than or equal to the electrical conductivity of the material of the channel layer, and the conduction band height of the transition structure material is greater than the conduction band height of the electrode layer material.

2. The storage array according to claim 1, characterized in that, The material of the transition structure is a conductor.

3. The storage array according to claim 1 or 2, characterized in that, The material of the transition structure includes metal oxides.

4. The storage array according to any one of claims 1 to 3, characterized in that, The transition structure includes multiple sub-layers, which are stacked along the direction from the electrode layer to the channel layer.

5. The storage array according to claim 4, characterized in that, Along the direction from the electrode layer to the channel layer, the conduction band height of the multilayer sublayer material gradually increases.

6. The storage array according to any one of claims 1 to 5, characterized in that, The electrode layer includes multiple conductive layers arranged sequentially from the inside out, with the outermost conductive layer in contact with the transition structure.

7. The storage array according to claim 6, characterized in that, In the multilayer conductive layers, the height of the conductive band gradually increases from the innermost conductive layer to the outermost conductive layer.

8. The storage array according to claim 6 or 7, characterized in that, The transition structure is made of InSnO, and the electrode layer comprises a conductive layer of metal material and a conductive layer of InSnO material surrounding the conductive layer of metal material. The In content in the transition structure is lower than the In content in the electrode layer.

9. The storage array according to any one of claims 1 to 8, characterized in that, Each of the channel layers includes a plurality of channel layers spaced apart along a second direction, the plurality of channel layers corresponding to a plurality of spaced transition structures in contact; the electrode layer extends along the second direction; In this configuration, at least two transition structures corresponding to at least two channel layers in the same layer are in contact with the same electrode layer.

10. The storage array according to any one of claims 1 to 9, characterized in that, The material of the transition structure is either partially crystallized or fully crystallized.

11. The storage array according to any one of claims 1 to 10, characterized in that, The material of the transition structure includes one or more of InO, InGaO, InZnO, InSnO, ZnAlO, InSnZnO, and InSnGaZnO.

12. A method for fabricating a memory array, characterized in that, include: A stacked structure is formed; the stacked structure includes multiple electrode layers that are stacked and spaced apart. A slot is formed on the stacked structure; the slot includes an opening and a plurality of sub-slots, the opening penetrates the multilayer electrode layer, the plurality of sub-slots are disposed on the wall of the opening, and the plurality of sub-slots are respectively disposed in the multilayer electrode layer; A transition structure is formed on the inner wall portion of the electrode layer belonging to the sub-groove; the conduction band height of the transition structure material is greater than the conduction band height of the electrode layer material. A channel layer is formed on the inner wall of the sub-slot; the transition structure is in contact with the channel layer and the electrode layer respectively, and the conductivity of the material of the transition structure is greater than or equal to the conductivity of the material of the channel layer.

13. The preparation method according to claim 12, characterized in that, The formation of a transition structure on the portion of the electrode layer belonging to the inner wall of the sub-groove includes: An amorphous buffer film is formed on the inner wall of the groove; The amorphous buffer film is induced to partially crystallize on the electrode layer to form a transition structure; Remove the uncrystallized portion of the amorphous buffer film.

14. A memory, characterized in that, include: Storage array as described in any one of claims 1 to 11; The peripheral circuitry is electrically connected to the storage array.

15. An electronic device, characterized in that, include: The memory as described in claim 14; The bus is electrically connected to the memory.

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