Capacitor structure and method of manufacturing the same

Abstract

The application relates to a capacitor structure and a manufacturing method thereof, which comprises the following steps: providing a substrate, forming a bottom metal layer on the substrate, and forming a patterned first mask layer on the bottom metal layer; performing a patterned treatment on the bottom metal layer to form a lower plate and an alignment mark; removing the first mask layer, and forming a dielectric layer on the lower plate, the alignment mark and the substrate; sequentially forming a top metal layer and a second mask layer on the dielectric layer, a part of the top metal layer located directly above the alignment mark is formed with a first alignment protrusion, and a part of the second mask layer located directly above the first alignment protrusion is formed with a second alignment protrusion; performing an alignment and patterned treatment on the second mask layer based on the second alignment protrusion, and etching the top metal layer to form an upper plate, and the orthographic projection of the upper plate towards the substrate falls into the orthographic projection of the lower plate towards the substrate. The application improves the alignment precision without increasing the mask layer, and helps to improve the performance and stability of the capacitor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a capacitor structure and a method for manufacturing the same. Background Technology

[0002] Metal-Insulator-Metal (MIM) capacitors have advantages such as low parasitic capacitance, low contact resistance, and relatively accurate capacitance values, and are widely used in semiconductor integrated circuits. Generally, an MIM capacitor consists of a top metal (CTM), a bottom metal (CBM), and an insulating dielectric layer between them. The top and bottom metals serve as the upper and lower plates of the MIM capacitor, respectively, and are typically fabricated in the back-end processes of semiconductor devices.

[0003] In copper (Cu) fabrication processes, the fabrication of MIM capacitors typically involves: first, depositing a MIM structure consisting of a bottom metal layer, an insulating dielectric layer, and a top metal layer; then, using multiple masks to progressively define the upper and lower electrodes. However, due to the complexity and thickness of the MIM structure, mask alignment becomes challenging when defining the upper and lower electrodes. Summary of the Invention

[0004] Therefore, it is necessary to provide a capacitor structure and its manufacturing method to optimize the process flow, improve the alignment accuracy of the mask used in the manufacturing process, and increase production efficiency.

[0005] This application provides a method for manufacturing a capacitor structure, including:

[0006] A substrate is provided, a bottom metal layer is formed on the substrate, and a patterned first mask layer is formed on the bottom metal layer;

[0007] The bottom metal layer is patterned to form the lower electrode plate and alignment marks;

[0008] Remove the first mask layer and form a dielectric layer on the lower electrode, the alignment mark and the substrate;

[0009] A top metal layer and a second mask layer are sequentially formed on the dielectric layer. A first alignment protrusion is formed in the portion of the top metal layer directly above the alignment mark, and a second alignment protrusion is formed in the portion of the second mask layer directly above the first alignment protrusion.

[0010] The second mask layer is aligned and patterned based on the second alignment protrusion, and the top metal layer is etched to form an upper electrode plate, wherein the orthographic projection of the upper electrode plate toward the substrate falls within the orthographic projection of the lower electrode plate toward the substrate.

[0011] In one embodiment, the orthographic projection of the alignment mark toward the substrate falls within the orthographic projection of the first alignment protrusion toward the substrate, and the orthographic projection of the first alignment protrusion toward the substrate falls within the orthographic projection of the second alignment protrusion toward the substrate.

[0012] In one embodiment, the orthographic projection of the alignment mark toward the substrate completely coincides with the orthographic projection of the first alignment protrusion toward the substrate, and the orthographic projection of the first alignment protrusion toward the substrate completely coincides with the orthographic projection of the second alignment protrusion toward the substrate.

[0013] In one embodiment, the alignment mark is formed on the substrate on one side of the lower electrode plate.

[0014] In one embodiment, after forming the upper electrode plate, the method for manufacturing the capacitor structure further includes:

[0015] Remove the second mask layer.

[0016] In one embodiment, after forming the upper electrode plate, the method for manufacturing the capacitor structure further includes:

[0017] An insulating layer is formed on the surface of the upper electrode plate and the dielectric layer;

[0018] A first connector and a second connector are formed. The first connector penetrates the insulating layer and connects to the upper electrode plate, and the second connector penetrates the insulating layer and the dielectric layer and connects to the lower electrode plate.

[0019] In one embodiment, the orthographic projection of the first connector toward the substrate falls within the orthographic projection of the upper electrode plate toward the substrate, the orthographic projection of the second connector toward the substrate is separate from the orthographic projection of the upper electrode plate toward the substrate, and both the orthographic projection of the second connector toward the substrate and the orthographic projection of the upper electrode plate toward the substrate fall within the orthographic projection of the lower electrode plate toward the substrate.

[0020] In one embodiment, the materials of the first connector and the second connector include at least one of metallic copper and metallic tungsten, and the material of the insulating layer includes silicon nitride.

[0021] In one embodiment, the top metal layer and the bottom metal layer are made of titanium nitride, and the dielectric layer is made of silicon nitride.

[0022] Accordingly, this application also provides a capacitor structure manufactured using the capacitor structure manufacturing method described above.

[0023] An unexpected effect of this application is that by using a first mask layer to pattern the bottom metal layer, an alignment mark is formed on one side of the lower electrode plate while forming the lower electrode plate. By forming a dielectric layer, a top metal layer, and a second mask layer on the lower electrode plate and the alignment mark, a first alignment protrusion is formed in the top metal layer and a second alignment protrusion is formed in the second mask layer. This allows for mask alignment during the patterning process of the second mask layer, thereby improving the alignment accuracy during the patterning process of the second mask layer without adding an additional mask layer. This, in turn, helps to improve the performance and stability of the capacitor structure, reduces production costs, shortens the production cycle, and improves production efficiency. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure corresponding to the first mark formed in the front layer in a manufacturing method of a MIM structure in a related technology.

[0026] Figure 2 This is a schematic diagram of the structure corresponding to the step of preparing a second marker based on a first marker in a manufacturing method of a MIM structure in a related technology.

[0027] Figure 3 This is a schematic diagram of the structure corresponding to the steps of forming a first metal layer, an interlayer dielectric layer, and a second metal layer on a substrate in a manufacturing method of a MIM structure in a related technology.

[0028] Figure 4 This is a schematic diagram of the structure corresponding to the step of forming the second electrode plate in the manufacturing method of a MIM structure in a related technology.

[0029] Figure 5 This is a schematic diagram of the structure corresponding to the step of forming the third photoresist layer in the manufacturing method of a MIM structure in a related technology.

[0030] Figure 6 This is a schematic diagram of the structure corresponding to the step of forming the MIM structure in the manufacturing method of the MIM structure in a related technology.

[0031] Figure 7This is a flowchart illustrating a method for manufacturing a capacitor structure according to one embodiment of this application.

[0032] Figure 8 This is a schematic diagram of the structure corresponding to the step of providing a substrate in the manufacturing method of a capacitor structure provided in one embodiment of this application.

[0033] Figure 9 This is a schematic diagram of the structure corresponding to the step of forming a bottom metal layer and a patterned first mask layer on a substrate in a method for manufacturing a capacitor structure according to one embodiment of this application.

[0034] Figure 10 This is a schematic diagram of the structure corresponding to the step of forming the lower electrode plate and alignment mark in the manufacturing method of the capacitor structure provided in one embodiment of this application.

[0035] Figure 11 This is a schematic diagram of the structure corresponding to the step of removing the first mask layer and forming a dielectric layer in the manufacturing method of the capacitor structure provided in one embodiment of this application.

[0036] Figure 12 This is a schematic diagram of the structure corresponding to the step of forming a top metal layer and a second mask layer on the dielectric layer in the manufacturing method of the capacitor structure provided in one embodiment of this application.

[0037] Figure 13 This is a schematic diagram of the structure corresponding to the step of forming the upper electrode plate in the manufacturing method of the capacitor structure provided in one embodiment of this application.

[0038] Figure 14 This is a schematic diagram of the structure corresponding to the step of forming an insulating layer in the manufacturing method of a capacitor structure provided in one embodiment of this application.

[0039] Figure 15 This is a schematic diagram of the structure corresponding to the step of forming the first connector and the second connector in the manufacturing method of the capacitor structure provided in one embodiment of this application.

[0040] The reference numerals in the figures include: 100-substrate; 101-pad oxide layer; 102-first mark; 103-first isolation layer; 104-first photoresist layer; 105-second mark; 110-first metal layer; 111-first electrode plate; 120-second isolation layer; 130-second metal layer; 131-second electrode plate; 140-third isolation layer; 150-second photoresist layer; 160-third photoresist layer; 17 0 - Electrical connector; 200 - Substrate; 201 - Front layer mark; 210 - Bottom metal layer; 211 - Lower electrode; 212 - Alignment mark; 220 - First mask layer; 230 - Dielectric layer; 240 - Top metal layer; 240a - First alignment protrusion; 241 - Upper electrode; 250 - Second mask layer; 250a - Second alignment protrusion; 260 - Insulating layer; 261 - First connector; 262 - Second connector. Detailed Implementation

[0041] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0044] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0046] To address the challenge of aligning the masks corresponding to the upper and lower electrodes during the fabrication of MIM capacitors, an additional mask layer is typically fabricated before the deposition of the lower electrode to serve as an alignment mark. For example, see [link to relevant documentation]. Figure 1 In the typical manufacturing process of a MIM structure, a pad oxide layer 101 is formed on the surface of the substrate 100, and a first mark 102 is formed within the pad oxide layer 101 to assist in the alignment between different film layers. Optionally, the material of the pad oxide layer 101 includes tetraethyl orthosilicate (TEOS). However, it should be noted that since the first mark 102 is a trench formed in the pad oxide layer 101, the size of the first mark 102 gradually decreases and is eventually filled in during the fabrication of multiple film layers, making it difficult to continue as an alignment mark for subsequent film layer alignment processes.

[0047] Therefore, refer to Figure 2 With the first mark in the pad oxide layer 101 filled in, a first isolation layer 103 and a patterned first photoresist layer 104 are sequentially formed on the pad oxide layer 101. The first isolation layer 103 is then patterned based on the first photoresist layer 104 to form a second mark 105 for alignment in subsequent processes. Optionally, the material of the first isolation layer 103 includes at least one of silicon oxide and silicon nitride. Optionally, after forming the second mark 105, the patterned first photoresist layer 104 is removed.

[0048] Next, refer to Figure 3 A first metal layer 110, a second metal layer 120, a second metal layer 130, and a third metal layer 140 are sequentially formed on the first isolation layer 103. It should be noted that since a second mark 105 is formed in the first isolation layer 103, the portions of the first metal layer 110, the second isolation layer 120, the second metal layer 130, and the third isolation layer 140 formed above the second mark 105 all inherit the morphology of the second mark 105. Optionally, the first metal layer 110 and the second metal layer 130 are made of titanium nitride (TiN), and the second isolation layer 120 and the third isolation layer 140 are made of silicon nitride (SiN).

[0049] Then refer to Figure 4 Alignment is performed based on the second mark 105, and a patterned second photoresist layer 150 is formed on the third isolation layer 140. The third isolation layer 140 and the second metal layer 130 are then etched based on the second photoresist layer 150 to form the second electrode 131. Optionally, the second photoresist layer 150 is removed after the second electrode 131 is formed.

[0050] Next, refer to Figure 5An isolation material is deposited on the third isolation layer 140 so that the thickened third isolation layer 140 at least covers the sidewalls of the second electrode 131; alignment is performed based on the second mark 105, and a patterned third photoresist layer 160 is formed on the third isolation layer 140; the third isolation layer 140, the second isolation layer 120, and the first metal layer 110 are etched based on the third photoresist layer 160 to form the first electrode 111. Optionally, the third photoresist layer 160 is removed after the second electrode 131 is formed.

[0051] Then refer to Figure 6 A insulating material is deposited again to cover the sidewalls of the first electrode 111, thereby forming a MIM structure comprising the first electrode 111, the second electrode 131, the second insulating layer 120, and the third insulating layer 140. Optionally, after forming the MIM structure, an electrical connector 170 may be formed that penetrates the insulating layers (including at least one of the third insulating layer 140 and the second insulating layer 120) and is respectively connected to the first electrode 111 and the second electrode 131.

[0052] While the manufacturing method of MIM structure described above improves the alignment accuracy in the manufacturing process of MIM structure, the above method requires the addition of a first photoresist layer process to form a second mark for alignment on the basis of the original process, which increases the number of fabrication steps of MIM structure, prolongs the production cycle, and increases the production cost.

[0053] Therefore, it is necessary to provide a capacitor structure and its manufacturing method to optimize the process flow, improve the alignment accuracy of the mask used in the manufacturing process, and increase production efficiency.

[0054] Figure 7 A flowchart illustrating a method for manufacturing a capacitor structure according to one embodiment of this application. See also... Figure 7 One embodiment of this application provides a method for manufacturing a capacitor structure, which includes steps S01 to S05.

[0055] Step S01: Provide a substrate, form a bottom metal layer on the substrate, and form a patterned first mask layer on the bottom metal layer.

[0056] Step S02: The bottom metal layer is patterned to form a lower electrode plate and alignment marks.

[0057] It should be noted that the above steps use the first mask layer to pattern the bottom metal layer, forming an alignment mark on one side of the lower electrode plate while forming the lower electrode plate. This completes the preparation of the alignment mark without adding an additional mask plate, which is beneficial for alignment in subsequent process steps.

[0058] Step S03: Remove the first mask layer and form a dielectric layer on the lower electrode, the alignment mark and the substrate.

[0059] Step S04: A top metal layer and a second mask layer are sequentially formed on the dielectric layer. A first alignment protrusion is formed in the portion of the top metal layer directly above the alignment mark, and a second alignment protrusion is formed in the portion of the second mask layer directly above the first alignment protrusion.

[0060] It should be noted that the top metal layer and the second mask layer inherit the morphology of the lower electrode and the alignment mark, thereby forming a first alignment protrusion located directly above the alignment mark and a second alignment protrusion located directly above the first alignment protrusion, which facilitates the alignment between different film layers in the next step.

[0061] Step S05: Align and pattern the second mask layer based on the second alignment protrusion, and etch the top metal layer to form an upper electrode plate, wherein the orthographic projection of the upper electrode plate toward the substrate falls within the orthographic projection of the lower electrode plate toward the substrate.

[0062] It should be noted that since the first alignment protrusion and the second alignment protrusion are formed in step S04, the upper electrode plate can be directly prepared based on the second alignment protrusion, which improves the alignment accuracy of the capacitor structure and thus helps to improve the performance and stability of the capacitor structure.

[0063] The capacitor structure manufacturing method described above utilizes a first mask layer to pattern the bottom metal layer, forming an alignment mark on one side of the bottom electrode plate while forming the bottom electrode plate. By forming a dielectric layer, a top metal layer, and a second mask layer on the bottom electrode plate and the alignment mark, a first alignment protrusion is formed in the top metal layer, and a second alignment protrusion is formed in the second mask layer. This allows for mask alignment during the patterning process of the second mask layer, thereby improving the alignment accuracy during the patterning process of the second mask layer without adding an additional mask layer. This, in turn, helps to improve the performance and stability of the capacitor structure, reduces production costs, shortens the production cycle, and improves production efficiency.

[0064] Figures 8 to 15 The diagram below shows the structural schematics corresponding to some steps in the manufacturing method of the capacitor structure provided in one embodiment of this application. Figures 8 to 15 This application provides a detailed description of a method for manufacturing a capacitor structure according to one embodiment.

[0065] First, refer to Figure 8 and Figure 9In one embodiment, step S01 includes: providing a substrate 200, forming a bottom metal layer 210 on the substrate 200, and forming a patterned first mask layer 220 on the bottom metal layer 210. Optionally, the material of the bottom metal layer 210 includes titanium nitride (TiN). Optionally, the substrate 200 includes a silicon substrate (not shown) and other semiconductor structures (not shown) formed on the surface of the silicon substrate.

[0066] It should be noted that although a groove-shaped front layer mark 201 is formed in the substrate 200, the morphology of the front layer mark 201 will gradually decrease as the number of film layers increases during the subsequent formation of multiple film layers, thus failing to play a role in film layer alignment in subsequent processes.

[0067] Next, refer to Figure 9 and Figure 10 In one embodiment, step S02 includes patterning the bottom metal layer 210 to form a lower electrode 211 and an alignment mark 212. Optionally, a dry etching process is used to etch the bottom metal layer 210 using a patterned first mask layer 220 as a mask to simultaneously form the lower electrode 211 and the alignment mark 212. Optionally, the alignment mark 212 is formed on the substrate on one side of the lower electrode.

[0068] It should be noted that during the patterning process of the bottom metal layer using the first mask layer, an alignment mark is formed on one side of the lower electrode plate at the same time as the lower electrode plate is formed. This completes the preparation of the alignment mark without adding an additional mask plate, which is beneficial for alignment in subsequent process steps.

[0069] Then refer to Figure 10 and Figure 11 Step S03 includes removing the first mask layer 220 and forming a dielectric layer 230 on the lower electrode 211, alignment mark 212, and substrate 200. Optionally, the first mask layer 220 is removed using an ashing process and a wet cleaning process. Optionally, the dielectric layer 230 is made of silicon nitride. In other embodiments of this application, the material of the dielectric layer can also be replaced with other insulating materials as needed to achieve electrical isolation between the lower electrode and the subsequently formed upper electrode, thereby ensuring the performance and stability of the final capacitor structure.

[0070] In one embodiment, chemical vapor deposition (CVD) is used to form the dielectric layer. In other embodiments of this application, other commonly used deposition processes can also be used to form the dielectric layer, and this application is not limited in this regard. It should be noted that the dielectric layer has the same thickness in different parts, exhibiting high thickness uniformity. Therefore, the dielectric layer inherits the morphology of the upper electrode and alignment mark, making the portion of the dielectric layer formed directly above the upper electrode and alignment mark higher than the remaining portion of the dielectric layer.

[0071] Next, refer to Figure 12 Step S04 includes: sequentially forming a top metal layer 240 and a second mask layer 250 on the dielectric layer 230. A first alignment protrusion 240a is formed in the portion of the top metal layer 240 directly above the alignment mark 212, and a second alignment protrusion 250a is formed in the portion of the second mask layer 250 directly above the first alignment protrusion 240a. Optionally, the material of the top metal layer 240 includes titanium nitride (TiN).

[0072] It should be noted that the top metal layer and the second mask layer both inherit the morphology of the lower electrode plate and the alignment mark, and respectively form a first alignment protrusion located directly above the alignment mark and a second alignment protrusion located directly above the first alignment protrusion, which is beneficial to improving the alignment accuracy in subsequent process manufacturing.

[0073] Continue reading Figure 12 In one embodiment, the orthographic projection of the alignment mark 212 toward the base 200 completely coincides with the orthographic projection of the first alignment protrusion 240a toward the base 200, and the orthographic projection of the first alignment protrusion 240a toward the base 200 completely coincides with the orthographic projection of the second alignment protrusion 250a toward the base 200. That is, the dimensions of the alignment mark 212, the first alignment protrusion 240a and the second alignment protrusion 250a in the direction toward the base 200 are the same and completely coincident.

[0074] In other embodiments of this application, the dimensions of the alignment mark, the first alignment protrusion, and the second alignment protrusion may also be different. In this case, the orthographic projection of the alignment mark toward the substrate falls within the orthographic projection of the first alignment protrusion toward the substrate, and the orthographic projection of the first alignment protrusion toward the substrate falls within the orthographic projection of the second alignment protrusion toward the substrate. It is only necessary to ensure that the alignment mark, the first alignment protrusion, and the second alignment protrusion are all aligned in a direction perpendicular to the substrate, so as to ensure that the second alignment protrusion can improve the alignment accuracy in subsequent process steps.

[0075] See Figure 13The process of step S05 includes: aligning and patterning the second mask layer 250 based on the second alignment protrusion 250a, and etching the top metal layer 240 based on the patterned second mask layer 250 to form the upper electrode plate 241, and the orthographic projection of the upper electrode plate 241 toward the substrate 200 falls into the orthographic projection of the lower electrode plate 211 toward the substrate 200.

[0076] It should be noted that since the first alignment protrusion 240a and the second alignment protrusion 250a are formed in step S04, the upper electrode plate 241 can be directly prepared based on the second alignment protrusion 250a, thereby improving the alignment accuracy of the final capacitor structure and helping to improve the performance and stability of the capacitor structure.

[0077] See Figure 14 and Figure 15 In one embodiment, after forming the upper electrode 241, the method for manufacturing the capacitor structure further includes: removing the second mask layer 250; forming an insulating layer 260 on the surfaces of the upper electrode 241 and the dielectric layer 230; forming a first connector 261 and a second connector 262, wherein the first connector 261 penetrates the insulating layer 260 and connects to the upper electrode 241, and the second connector 262 penetrates the insulating layer 260 and the dielectric layer 230 and connects to the lower electrode 211. Optionally, the insulating layer 260 may be made of silicon nitride (SiN). Optionally, the first connector 261 and the second connector 262 may both be made of copper, tungsten, aluminum, or other commonly used metals or alloys.

[0078] Continue reading Figure 15 In one embodiment, the orthographic projection of the first connector 261 toward the base 200 falls within the orthographic projection of the upper electrode plate 241 toward the base 200, the orthographic projection of the second connector 262 toward the base 200 is separate from the orthographic projection of the upper electrode plate 241 toward the base 200, and both the orthographic projection of the second connector 262 toward the base 200 and the orthographic projection of the upper electrode plate 241 toward the base 200 fall within the orthographic projection of the lower electrode plate 211 toward the base 200.

[0079] Accordingly, one embodiment of this application also provides a capacitor structure manufactured using the capacitor structure manufacturing method described above. It should be noted that in other embodiments of this application, other semiconductor structures with the same or similar structures can also be manufactured using the capacitor structure manufacturing method described above to solve the alignment problem between different film layers; this application does not impose any limitations on this.

[0080] An unexpected effect of this application is that by using a first mask layer to pattern the bottom metal layer, an alignment mark is formed on one side of the lower electrode plate while forming the lower electrode plate. By forming a dielectric layer, a top metal layer, and a second mask layer on the lower electrode plate and the alignment mark, a first alignment protrusion is formed in the top metal layer and a second alignment protrusion is formed in the second mask layer. This allows for mask alignment during the patterning process of the second mask layer, thereby improving the alignment accuracy during the patterning process of the second mask layer without adding an additional mask layer. This, in turn, helps to improve the performance and stability of the capacitor structure, reduces production costs, shortens the production cycle, and improves production efficiency.

[0081] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0082] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method of manufacturing a capacitor structure, characterized by, The application relates to a manufacturing method of a capacitor structure. The method comprises the following steps: providing a substrate, forming a bottom metal layer on the substrate, and forming a patterned first mask layer on the bottom metal layer; performing a patterned treatment on the bottom metal layer to form a lower plate and an alignment mark; removing the first mask layer, and forming a dielectric layer on the lower plate, the alignment mark and the substrate; sequentially forming a top metal layer and a second mask layer on the dielectric layer, a part of the top metal layer above the alignment mark is provided with a first alignment protrusion, and a part of the second mask layer above the first alignment protrusion is provided with a second alignment protrusion; performing an alignment and patterned treatment on the second mask layer based on the second alignment protrusion, and etching the top metal layer to form an upper plate, and the upper plate is projected onto the lower plate.

2. The method of manufacturing a capacitive structure according to claim 1, wherein The alignment mark is projected onto the first alignment protrusion, and the first alignment protrusion is projected onto the second alignment protrusion.

3. The method of manufacturing a capacitive structure according to claim 1, wherein The alignment mark is completely overlapped with the first alignment protrusion, and the first alignment protrusion is completely overlapped with the second alignment protrusion.

4. The method of manufacturing a capacitive structure according to claim 1, wherein The alignment mark is formed on the substrate on one side of the lower plate.

5. The method of manufacturing a capacitive structure according to claim 1, wherein After the upper plate is formed, the manufacturing method of the capacitor structure further comprises the following steps: removing the second mask layer.

6. The method of manufacturing a capacitive structure according to claim 1 or 5, wherein After the upper plate is formed, the manufacturing method of the capacitor structure further comprises the following steps: forming an insulating layer on the surface of the upper plate and the dielectric layer; forming a first connecting member and a second connecting member, the first connecting member penetrates through the insulating layer and connects the upper plate, and the second connecting member penetrates through the insulating layer and the dielectric layer and connects the lower plate.

7. The method of manufacturing a capacitive structure according to claim 6, wherein The first connecting member is projected onto the upper plate, and the second connecting member is separated from the upper plate, and both the first connecting member and the second connecting member are projected onto the lower plate.

8. The method of manufacturing a capacitive structure according to claim 6, wherein, The material of the first connecting member and the second connecting member comprises at least one of metal copper and metal tungsten, and the material of the insulating layer comprises silicon nitride.

9. The method of manufacturing a capacitive structure according to claim 1, wherein, The material of the top metal layer and the bottom metal layer comprises titanium nitride, and the material of the dielectric layer comprises silicon nitride.

10. A capacitor structure, characterized by The capacitor structure is manufactured by using the manufacturing method of the capacitor structure in any one of claims 1-9.

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