Method for manufacturing semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate which comprises a well region, and the well region comprises a top doped region; depositing a first interlayer dielectric layer on the well region; forming at least one contact through hole in the first interlayer dielectric layer; forming a first lower metal layer in the first interlayer dielectric layer; depositing a second interlayer dielectric layer on the first interlayer dielectric layer; forming at least one guide hole in the second interlayer dielectric layer; a first upper metal layer is formed on the second interlayer dielectric layer, the second thickness of the second interlayer dielectric layer is not larger than the first thickness of the first interlayer dielectric layer, and the first lower metal layer is electrically connected with the first upper metal layer through a first guide hole in the at least one guide hole.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high-voltage semiconductor device. Background Technology

[0002] Laterally diffused metal oxide semiconductor (LDMOS) transistors are now widely used in various power integrated circuits and smart power integrated circuits. The use of LDMOS in high-voltage integrated circuits (e.g., 500V to 700V) is becoming increasingly widespread. To improve the performance and reliability of ultra-high voltage LDMOS, it may be necessary to appropriately adjust and optimize the electric field distribution. For example, a thicker inter-layer dielectric (ILD) can reduce the impact of high voltage on the LDMOS conduction path, thereby reducing device degradation.

[0003] However, thicker ILD layers make the etching process with high aspect ratios more complex, which may lead to higher process costs and equipment throughput issues.

[0004] Therefore, how to effectively improve the performance and reliability of LDMOS without significantly increasing etching complexity is a problem worth solving. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes a method for manufacturing a semiconductor device to optimize the characteristics of the semiconductor device.

[0006] Embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate includes a well region and the well region includes a top-doped region; depositing a first interlayer dielectric (ILD) layer on the well region; forming at least one contact via (CT) in the first interlayer dielectric layer; forming a first lower metal layer in the first interlayer dielectric layer; depositing a second interlayer dielectric layer on the first interlayer dielectric layer; forming at least one via in the second interlayer dielectric layer; and forming a first upper metal layer on the second interlayer dielectric layer, wherein: a second thickness of the second interlayer dielectric layer is not greater than a first thickness of the first interlayer dielectric layer, and the first lower metal layer passes through the at least one via. The steps of electrically connecting a first via to the first upper metal layer and forming a first lower metal layer in the first interlayer dielectric layer include: removing a first shallow portion of the first interlayer dielectric layer by a patterning process to form a first shallow trench; depositing a conductive material on the first interlayer dielectric layer by a deposition process to form the first lower metal layer, wherein the first lower metal layer corresponds to the first shallow trench on which the conductive material is deposited; and making a top surface of the first lower metal layer and a first top surface of the first interlayer dielectric layer substantially coplanar by a planarization process.

[0007] Optionally, the first lower metal layer is not electrically connected to the well region through the at least one contact via.

[0008] Optionally, the step of forming the at least one via in the second interlayer dielectric layer includes:

[0009] A first deep portion of the second interlayer dielectric layer is removed by a patterning process to form a first deep trench; and a conductive material is deposited in the first deep trench by a deposition process to form the first via.

[0010] Optionally, the well region includes a source region and a drain region, and the method further includes: forming a second lower metal layer in the first interlayer dielectric layer, wherein the second lower metal layer is electrically connected to the source region or the drain region through a second contact via in the at least one contact via.

[0011] Optionally, the first upper metal layer is further electrically connected to the second lower metal layer through a second via in one of the at least one vias.

[0012] Optionally, the first upper metal layer is not electrically connected to the second lower metal layer through the at least one via.

[0013] An embodiment of the present invention further provides a method for manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate includes a well region and the well region includes a top-doped region; depositing a first interlayer dielectric (ILD) layer on the well region; forming at least one contact via (CT) in the first interlayer dielectric layer; forming a first lower metal layer in the first interlayer dielectric layer; depositing a second interlayer dielectric layer on the first interlayer dielectric layer; forming at least one via in the second interlayer dielectric layer; and forming a first upper metal layer on the second interlayer dielectric layer, wherein: a second thickness of the second interlayer dielectric layer is not greater than a first thickness of the first interlayer dielectric layer, and the first lower metal layer passes through a first contact via in one of the at least one contact via. The steps of electrically connecting the top doped region in the well region via a contact via and forming the first lower metal layer in the first interlayer dielectric layer include: removing a first shallow portion of the first interlayer dielectric layer by a patterning process to form a first shallow trench; depositing a conductive material on the first interlayer dielectric layer by a deposition process to form the first lower metal layer, wherein the first lower metal layer corresponds to the first shallow trench on which the conductive material is deposited; and making a top surface of the first lower metal layer and a first top surface of the first interlayer dielectric layer substantially coplanar by a planarization process.

[0014] Optionally, the first lower metal layer is not electrically connected to the first upper metal layer through the at least one via.

[0015] Optionally, the step of forming the at least one contact via in the first interlayer dielectric layer includes: removing a first deep portion of the first interlayer dielectric layer by a patterning process to form a first deep trench; and depositing a conductive material on the first interlayer dielectric layer by a deposition process to form the first contact via, wherein the first contact via corresponds to the first deep trench on which the conductive material is deposited.

[0016] Optionally, the well region includes a source region and a drain region, and the method further includes: forming a second lower metal layer in the first interlayer dielectric layer, wherein the second lower metal layer is electrically connected to the source region or the drain region through a second contact via in the at least one contact via.

[0017] Based on the above, the semiconductor device manufacturing method of the present invention employs a two-step process to form a multilayer interlayer dielectric layer structure, increasing the overall thickness of the device to avoid the influence of high voltage on the conduction path. Furthermore, the combination of metal layers and vias, as well as the combination of metal layers and contact vias, in the semiconductor device of the present invention can serve as a vertical field plate, effectively increasing the equivalent area of ​​the field plate and thereby modulating the electric field distribution. Attached Figure Description

[0018] The accompanying drawings are provided to enable those skilled in the art to further understand the invention, and are incorporated in and constitute a part of the specification of the invention. The drawings illustrate exemplary embodiments of the invention and are used together with the specification to explain the principles of the invention.

[0019] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0020] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic flowchart of the manufacturing method of the semiconductor device of the present invention;

[0022] Figures 4A to 4I For corresponding Figure 3 A cross-sectional diagram of the process;

[0023] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0024] Figure 6 This is a schematic flowchart of the manufacturing method of the semiconductor device of the present invention;

[0025] Figures 7A to 7I For corresponding Figure 6 A cross-sectional diagram of the process.

[0026] Explanation of reference numerals in the attached figures:

[0027] 10…Semiconductor device; 100…Substrate; 110…Well region; 112…Top doped region; 114…Source region; 116…Drain region; 120…First interlayer dielectric layer; 122…First lower metal layer; 124…Second lower metal layer; 126…Third lower metal layer; 1284…Second contact via; 1286…Third contact via; 130…Second interlayer dielectric layer; 1322…First via; 1324…Second via; 1326…Third via; 142…First upper metal layer; 144…Second upper metal layer; 146…Third upper metal layer; 20…Semiconductor device; 242…First upper metal layer; S302, S304, S306, S308, S310, S312, S314, S3 16. S318…Step; PR…Photoresist layer; 50…Semiconductor device; 500…Substrate; 510…Well region; 512…Top doped region; 514…Source region; 516…Drain region; 520…First interlayer dielectric layer; 522…First lower metal layer; 524…Second lower metal layer; 526…Third lower metal layer; 5222…First contact via; 5284…Second contact via; 5286…Third contact via; 530…Second interlayer dielectric layer; 5324…Second via; 5326…Third via; 542…First upper metal layer; 546…Third upper metal layer; S602, S604, S606, S608, S610, S612, S614, S616, S618…Steps Detailed Implementation

[0028] This invention provides a method for manufacturing a semiconductor device to address the problems mentioned in the background art. To make the features and advantages of this invention more apparent and understandable, specific embodiments of the invention are described in detail below with reference to the accompanying drawings. The following description contains specific information relating to exemplary embodiments of the invention. The accompanying drawings and detailed description are merely exemplary embodiments. However, the invention is not limited to these exemplary embodiments. Other variations and embodiments of the invention will occur to those skilled in the art. Unless otherwise stated, the same or corresponding components in the drawings are indicated by the same or corresponding reference numerals. Furthermore, the drawings and illustrations in this invention are generally not drawn to scale and are not intended to correspond to actual relative dimensions.

[0029] The following disclosure provides many different embodiments or examples to implement the various features of this invention. The following disclosure describes specific examples of the various components and their arrangements to simplify the explanation. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the invention describes a first feature formed on or above a second feature, it may include embodiments where the first and second feature are in direct contact, or embodiments where an additional feature is formed between the first and second feature, so that the first and second feature may not be in direct contact.

[0030] It is worth noting that additional operational steps may be performed before, during, or after the method, and in other embodiments of the method, some operational steps may be replaced or omitted.

[0031] Furthermore, spatially related terms may be used, such as "below," "lower," "above," "above," "higher," and similar terms. These spatially related terms are used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and other components or features. These spatially related terms encompass different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially related adjectives used will also be interpreted according to the orientation after the turn.

[0032] In the instruction manual, the terms "about," "approximately," and "roughly" usually indicate within 20%, 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity; that is, even without specific mention of "about," "approximately," or "roughly," the meaning of these terms is implied.

[0033] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 10 includes: a substrate 100, a well region 110, a doping region 112, a first interlayer dielectric (ILD) layer 120, a second interlayer dielectric layer 130, a first lower metal layer 122, and a first upper metal layer 142.

[0034] Please refer to Figure 1The well region 110 is located (e.g., disposed in, formed in, or covering) in (or on) the substrate 100. For example, the well region 110 may be a high-voltage N-well (HVNW) or a deep N-well (DNW), but the invention is not limited thereto. The top-doped region 112 is located in the well region 110. For example, the top-doped region 112 may be a P-top doped region. Furthermore, the well region 110 further includes a source region 114 and a drain region 116.

[0035] The first interlayer dielectric layer 120 is located on the well region 110. The first interlayer dielectric layer 120 includes at least one contact via (CT) and a first lower metal layer 122. The first lower metal layer 122 may be, for example, a metal zero (MO) layer. The at least one contact via includes a second contact via 1284 and a third contact via 1286.

[0036] The second interlayer dielectric layer 130 is located on the first interlayer dielectric layer 120. The second interlayer dielectric layer 130 includes at least one via. The at least one via includes a first via 1322, a second via 1324, and a third via 1326. The first upper metal layer 142 is located on the second interlayer dielectric layer 130. The first upper metal layer 142 may, for example, be a metal one (M1) layer. A second thickness of the second interlayer dielectric layer 130 is not greater than a first thickness of the first interlayer dielectric layer 120. For example, the second thickness of the second interlayer dielectric layer 130 can be controlled by a deposition process.

[0037] As described above, the first lower metal layer 122 is electrically connected to the first via 1322 in the at least one via. The first via 1322 is electrically connected to the first upper metal layer 142 (i.e., the first via 1322 penetrates the second interlayer dielectric layer 130). In other words, the first lower metal layer 122 is electrically connected to the first upper metal layer 142 through the first via 1322.

[0038] Based on the above description, the semiconductor device of the present invention employs a relay metal layer and a multilayer interlayer dielectric layer structure to increase the overall thickness of the device, thereby avoiding the influence of high voltage on the conduction path. Furthermore, the combination of the metal layer and vias can serve as a vertical (metal) field plate (FP) to effectively increase the equivalent area of ​​the field plate, thereby modulating the electric field distribution and increasing the breakdown voltage (or breakdown voltage, BV).

[0039] It is worth noting that, Figure 1 The structure, shape, size, and position of the components are merely illustrative and not intended to limit the invention.

[0040] In some embodiments, the first lower metal layer 122 may not be electrically connected to the well region 110 (e.g., the top doped region 112, the source region 114, or the drain region 116) through the at least one contact via, but the present invention is not limited thereto. For example, the at least one contact via may be electrically connected to the well region 110, and the first lower metal layer 122 may not be electrically connected to the at least one contact via.

[0041] In some embodiments, a top surface of the first lower metal layer 122 and a first top surface of the first interlayer dielectric layer 120 are substantially coplanar. A bottom surface of the first upper metal layer 142 and a second top surface of the second interlayer dielectric layer 130 may be substantially coplanar, but the present invention is not limited thereto.

[0042] In some embodiments, the first interlayer dielectric layer 120 may further include a second lower metal layer 124. The second lower metal layer 124 may be electrically connected to the source region 114 through the second contact via 1284 in the at least one contact via.

[0043] In some embodiments, the first interlayer dielectric layer 120 may further include a third lower metal layer 126. The third lower metal layer 126 may be electrically connected to the drain region 116 through the third contact via 1286 in the at least one contact via.

[0044] In some embodiments, the first upper metal layer 142 may not be electrically connected to the second lower metal layer 124 through the at least one via. For example, the first upper metal layer 142 may only be electrically connected to the first lower metal layer 122, and not electrically connected to other lower metal layers in the first interlayer dielectric layer 120 (e.g., the second lower metal layer 124, the third lower metal layer 126). In some embodiments, the second interlayer dielectric layer 130 may further include (e.g., be provided with) a second upper metal layer 144. The second upper metal layer 144 may be electrically connected to the second lower metal layer 124 through the second via 1324 in the at least one via. That is, at least one upper metal layer on the second interlayer dielectric layer 130 and at least one lower metal layer in the first interlayer dielectric layer 120 may have a one-to-one relationship.

[0045] In some other embodiments, the first upper metal layer 142 may be further electrically connected to the second lower metal layer 124 through the second via 1324 in the at least one via, such as... Figure 2As shown. Figure 2 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. That is, Figure 2 The first upper metal layer 242 can be regarded as Figure 1 The (electrical) combination of the first upper metal layer 142 and the second upper metal layer 144.

[0046] In some embodiments, the first interlayer dielectric layer 120 may further include another lower metal layer (not shown in the figures). The at least one via may further include another via (not shown in the figures). The first upper metal layer 142 may further be electrically connected to the other lower metal layer through the other via. That is, a plurality of lower metal layers in the first interlayer dielectric layer 120 are electrically connected to a single upper metal layer on the second interlayer dielectric layer 130, i.e., there is a many-to-one relationship.

[0047] In some embodiments, the second interlayer dielectric layer 130 may further include another upper metal layer (not shown in the figures). The at least one via may further include another via (not shown in the figures). The first lower metal layer 122 may be further electrically connected to the other metal layer through the other via. That is, a single lower metal layer in the first interlayer dielectric layer 120 is electrically connected to a plurality of upper metal layers on the second interlayer dielectric layer 130, i.e., it has a one-to-many relationship.

[0048] In some embodiments, the first lower metal layer 122, the second lower metal layer 124, and the third lower metal layer 126 may each have their own width and / or depth. The width and / or depth of the first lower metal layer 122, the second lower metal layer 124, and the third lower metal layer 126 may be substantially the same, but the present invention is not limited thereto.

[0049] In some embodiments, the at least one contact via may have its own width. The widths of the at least one contact via may be substantially the same, but this is not a limitation of the invention. The at least one guide hole may have its own width. The widths of the at least one guide hole may be substantially the same, but this is not a limitation of the invention.

[0050] In some embodiments, the substrate 100 may have a first conductivity type. The well region 110 may have a second conductivity type. The top-doped region 112 may have the first conductivity type. The source region 114 may have the second conductivity type. The drain region 116 may have the second conductivity type. In some embodiments, the well region 110 may further include a heavily doped region (not shown in the figures), which may have the first conductivity type. The source region 114 may be adjoined to the heavily doped region. The well region 110 may further include a second well region (also referred to as a body region) (not shown in the figures), which may have the first conductivity type. The source region 114 and the heavily doped region may be located in the second well region. The doping concentration of the source region 114 and the heavily doped region may be greater than the doping concentration of the second well region. The second well region, the source region 114, and the heavily doped region may be formed by a (multi-channel) ion implantation process. The source region 114, the heavily doped region, and the second well region can form a source doped region. In some embodiments, the at least one contact via may further include another contact via (not shown in the figures). The other contact via can electrically connect the second lower metal layer 124 and the heavily doped region.

[0051] In some embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type, but the present invention is not limited thereto. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the source region 114 may be referred to as the N+ region, the drain region 116 may be referred to as the N+ region, and the heavily doped region may be referred to as the P+ region. The P-type dopant may contain boron, gallium, aluminum, indium, boron trifluoride ions (BF3+), or a combination thereof. The N-type dopant may contain phosphorus, arsenic, nitrogen, antimony, or a combination thereof.

[0052] In some embodiments, the semiconductor device 10 may further include an isolation region (not shown in the figures). For example, the isolation region may contain, for example, drifting oxide (DOX) or field oxide (FOX), but the invention is not limited thereto. The isolation region may be located on the well region 110 (the top-doped region 112 therein). The isolation region may be located between the source region 114 and the drain region 116. The isolation region may cover a portion of the top-doped region 112 and the well region 110. The isolation region may be adjacent to or cover a portion of the source region 114.

[0053] In some embodiments, the semiconductor device 10 may further include a gate region (not shown in the figures). For example, the gate region comprises (e.g.) polysilicon, but the invention is not limited thereto. The gate region may be located on the isolation region. The gate region may be located between the source region 114 and the drain region 116. The gate region may cover a portion of the isolation region and a portion of the well region 110. The gate region may be adjacent to the source region 114.

[0054] In some embodiments, the semiconductor device 10 may be a laterally diffused metal oxide semiconductor (LDMOS), a metal oxide semiconductor (MOS), an insulated gate bipolar transistor (IGBT), or a diode, etc., but the present invention is not limited thereto.

[0055] Figure 3 This is a schematic flowchart of the manufacturing method of the semiconductor device of the present invention. Figures 4A to 4I For corresponding Figure 3 A cross-sectional diagram of the process. For example... Figure 3 As shown, this manufacturing method includes the following steps:

[0056] In step S302, a substrate is provided, wherein the substrate includes a well region and the well region includes a top-doped region, and then step S304 is continued.

[0057] Please refer to Figure 4A A substrate 100 is provided, wherein the substrate 100 includes a well region 110 (e.g., DNW), and the well region 110 includes a top doped region 112 (e.g., P-top), a source region 114 (e.g., N+) and a drain region 116 (e.g., N+).

[0058] In some embodiments, the well region 110 may further include a second well region (e.g., PW), and the second well region may include the source region 114. The second well region may further include a heavily doped region (e.g., P+).

[0059] In some embodiments, a gate (e.g., poly) and an isolation region (e.g., DOX) may be formed / provided on the substrate 100.

[0060] It is worth noting that although the above example uses a substrate containing a well region, a top-doped region, a source region, and a drain region as an example, the present invention is not limited thereto. For example, a well region may be formed in the substrate, and a top-doped region (e.g., formed by ion implantation of the substrate through a patterned mask), a source region, and a drain region may be formed in the well region.

[0061] In step S304, a first interlayer dielectric layer is deposited on the well region, followed by step S306.

[0062] Please refer to Figure 4B A first interlayer dielectric layer 120 is deposited on the well region 110.

[0063] In some embodiments, the first thickness of the first interlayer dielectric layer 120 can reach several micrometers (μm), but the present invention is not limited thereto.

[0064] In some embodiments, the first interlayer dielectric layer 120 may be formed by spin-on coating, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or combinations thereof.

[0065] In some embodiments, the first interlayer dielectric layer 120 may be planarized to give it a flat top surface.

[0066] In some embodiments, a first material used in the first interlayer dielectric layer 120 may include: silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitrocarbide (SiO xN yC 1-xy, where x and y are in the range of 0 to 1), tetraethyl orthosilte (TEOS), undoped silicate glass, doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials, low-k dielectric materials, or other suitable dielectric materials.

[0067] In step S306, at least one contact via is formed in the first interlayer dielectric layer, and then step S308 is continued.

[0068] Please refer to Figure 4C A second deep portion and a third deep portion of the first interlayer dielectric layer 120 are removed using a patterning process to correspondingly form a second deep trench and a third deep trench on the first interlayer dielectric layer 120. The deep trench is associated with (e.g., for) the process of contacting vias.

[0069] In some embodiments, the second deep trench may connect to the source region 114, and the third deep trench may connect to the drain region 116.

[0070] In some embodiments, the patterning process may include photolithography (e.g., photoresist coating, photoresist application (e.g., spin coating), soft baking, shielded alignment, exposure, post-exposure baking, developing, drying (e.g., hard baking), other suitable techniques, or combinations thereof), etching (e.g., wet etching (e.g., immersion etching, spray etching), dry etching (e.g., capacitively coupled plasma etching, inductively coupled plasma etching, helical plasma etching, electron cyclotron resonance plasma etching), other suitable techniques (e.g., reactive ion etching), or combinations thereof), other suitable techniques, or combinations thereof. The photolithography process may also be replaced by unshielded photolithography, electron beam writing, ion beam writing, or molecular imprinting. The etching process may also be purely chemical etching (plasma etching), purely physical etching (ion polishing), or combinations thereof.

[0071] For example, a shielding pattern (layer), such as a photoresist pattern or a hard shielding pattern, can be formed on the first interlayer dielectric layer 120 using a photolithography process. The shielding pattern may have openings to expose a portion of the first interlayer dielectric layer 120. Then, the first interlayer dielectric layer 120 corresponding to the openings can be removed using the etching process described above to form a deep trench.

[0072] In some embodiments, the shielding pattern may comprise a photoresist layer (e.g., PR in the figure), a metal layer, other suitable metallic materials, the aforementioned alloys, or combinations thereof. In some embodiments, the photoresist layer may be a positive photoresist or a negative photoresist. In some embodiments, the photoresist layer may be a single-layer or multi-layer structure, formed by, for example, deposition processes, photolithography processes, other suitable processes, or combinations thereof, but the invention is not limited thereto. In some embodiments, the metal layer may comprise a Ti / TiN / AlCu / TiN stacked structure.

[0073] After patterning, the first interlayer dielectric layer 120 has at least one deep trench.

[0074] In step S308, a first shallow portion of the first interlayer dielectric layer is removed by a patterning process to form a first shallow trench, and then step S310 is continued.

[0075] Please refer to Figure 4D A first shallow portion of the patterned first interlayer dielectric layer 120 is removed to form a first shallow trench, and a second and a third shallow portion of the first interlayer dielectric layer 120 are removed to correspondingly form a second shallow trench and a third shallow trench on the first interlayer dielectric layer 120. The shallow trenches are associated with (e.g., for) the process of an underlying metal layer.

[0076] In some embodiments, the second shallow trench may connect to the second deep trench, and the third shallow trench may connect to the third deep trench.

[0077] In some embodiments, the first shallow trench may not be connected to the at least one deep trench. The first shallow trench may not be connected to the well region 110 (e.g., the top-doped region 112).

[0078] After patterning, the first interlayer dielectric layer 120 further has at least one shallow trench.

[0079] In step S310, a conductive material is deposited on the first interlayer dielectric layer by a deposition process to form a first lower metal layer, wherein the first lower metal layer corresponds to the first shallow trench on which the conductive material is deposited, and then step S312 is continued.

[0080] Please refer to Figure 4E Conductive material is deposited on the (patterned) first interlayer dielectric layer 120 through a deposition process, thereby depositing (i.e. filling) conductive material in and on the first shallow trench, thus forming a first lower metal layer 122. It is worth noting that the top surface of the first lower metal layer 122 may not be flat at this time (for example, it may bulge due to excessive deposition of conductive material).

[0081] Furthermore, through a deposition process, conductive material is deposited on the (patterned) first interlayer dielectric layer 120, and conductive material is deposited (i.e. filled) in the second deep trench and the third deep trench, thereby correspondingly forming a second contact via 1284 and a third contact via 1286, and conductive material is deposited (i.e. filled) in and on the second shallow trench and the third shallow trench, thereby correspondingly forming a second lower metal layer 124 and a third lower metal layer 126.

[0082] In some embodiments, a suitable deposition process may include physical vapor deposition (PVD), chemical vapor deposition (CVD), coating, spin-on coating, other suitable processes, or combinations thereof, but the invention is not limited thereto. PVD processes may include sputtering, evaporation, and / or pulsed laser deposition. CVD processes may include low-pressure chemical vapor deposition (LPCVD), low-temperature chemical vapor deposition (LTCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), atomic layer deposition (ALD), electroplating, molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), other suitable processes, and / or combinations thereof, but the present invention is not limited thereto.

[0083] In some embodiments, suitable conductive materials may include aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), ruthenium (Ru), palladium (Pd), platinum (Pt), manganese (Mn), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), tungsten silicide (WSi), titanium silicide (TiSi2), other suitable conductive materials or combinations thereof, but the invention is not limited thereto.

[0084] After the deposition process, the top surface of the first interlayer dielectric layer 120 and / or the top surface of the at least one metal layer may be uneven.

[0085] In step S312, a planarization process is used to make a top surface of the first lower metal layer and a first top surface of the first interlayer dielectric layer substantially coplanar, and then step S314 is continued.

[0086] Please refer to Figure 4FThrough a planarization process, a top surface of the first lower metal layer 122 (deposited) and a first top surface of the first interlayer dielectric layer 120 (deposited) are substantially coplanar. That is, through the planarization process, excess conductive material on the first shallow trench and the first interlayer dielectric layer 120 is removed (e.g., until the original (i.e., before the photoresist layer PR is deposited) top surface of the first interlayer dielectric layer 120 is exposed).

[0087] In some embodiments, the planarization process can be replaced by an etch-back process. The planarization process can be chemical mechanical polishing (CMP).

[0088] In some embodiments, a planarization process is used to make a top surface of the second lower metal layer 124, a top surface of the third lower metal layer 126, and a first top surface of the first interlayer dielectric layer 120 substantially coplanar.

[0089] In step S314, a second interlayer dielectric layer is deposited on the first interlayer dielectric layer, wherein a second thickness of the second interlayer dielectric layer is not greater than a first thickness of the first interlayer dielectric layer, and then step S316 is continued.

[0090] Please refer to Figure 4G A second interlayer dielectric layer 130 is deposited on the first interlayer dielectric layer 120. The second thickness of the second interlayer dielectric layer 130 is not greater than the first thickness of the first interlayer dielectric layer 120.

[0091] In some embodiments, the first material and the second material may be the same. In some other embodiments, the first material and the second material may be different.

[0092] In step S316, at least one via is formed in the second interlayer dielectric layer, wherein a first via of the at least one via is electrically connected to the first lower metal layer, and then step S318 is continued.

[0093] Please refer to Figure 4H A first via 1322, a second via 1324 and a third via 1326 are formed in the second interlayer dielectric layer 130.

[0094] In detail, a first deep portion of the second interlayer dielectric layer 130 is removed by a patterning process to form a first deep trench, and a second deep portion and a third deep portion of the second interlayer dielectric layer 130 are removed to correspondingly form a second deep trench and a third deep trench on the second interlayer dielectric layer 130.

[0095] Conductive material is deposited in the first deep trench to form the first via 1322 through a deposition process, and conductive material is deposited in the second and third deep trenches to form the second via 1324 and the third via 1326 respectively. The first via 1322 is electrically connected to the first lower metal layer 122.

[0096] In some embodiments, the second via 1324 may be electrically connected to the second lower metal layer 124, and the third via 1326 may be electrically connected to the third lower metal layer 126.

[0097] In step S318, a first upper metal layer is formed on the second interlayer dielectric layer, wherein the first upper metal layer is electrically connected to the first via.

[0098] Please refer to Figure 4I A first upper metal layer 142, a second upper metal layer 144, and a third upper metal layer 146 are formed on the second interlayer dielectric layer 130. The first upper metal layer 142 is electrically connected to the first via 1322.

[0099] In some embodiments, the second upper metal layer 144 is electrically connected to the second via 1324, and the third upper metal layer 146 is electrically connected to the third via 1326.

[0100] While the above example illustrates an electrical connection between an upper metal layer (e.g., upper metal layer 142) and a single lower metal layer (e.g., lower metal layer 122), the present invention is not limited thereto. For instance, an upper metal layer may also be electrically connected to a plurality of lower metal layers (e.g., ...). Figure 2 Semiconductor device 20 in the middle.

[0101] This completes the fabrication of the semiconductor device 10 of the present invention.

[0102] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 5 As shown, the semiconductor device 50 includes: a substrate 500, a well region 510, a top doped region 512, a first interlayer dielectric layer 520, a second interlayer dielectric layer 530, a first lower metal layer 522, and a first upper metal layer 542.

[0103] Please refer to Figure 5The well region 510 is located (e.g., disposed in, formed in, or covering) in (or on) the substrate 500. For example, the well region 510 may be a high-voltage N-type well or an N-type deep well, but the invention is not limited thereto. The top-doped region 512 is located in the well region 510. For example, the top-doped region 512 may be a P-type top-doped region. Furthermore, the well region 510 further includes a source region 514 and a drain region 516.

[0104] The first interlayer dielectric layer 520 is located on the well region 510. The first interlayer dielectric layer 520 includes at least one contact via and a first lower metal layer 522. The first lower metal layer 522 may be, for example, a metal zero layer. The at least one contact via includes a first contact via 5222, a second contact via 5284, and a third contact via 5286.

[0105] The second interlayer dielectric layer 530 is located on the first interlayer dielectric layer 520. The second interlayer dielectric layer 530 includes at least one via. The at least one via includes a second via 5324 and a third via 5326. The first upper metal layer 542 is located on the second interlayer dielectric layer 530. The first upper metal layer 542 may, for example, be a metal layer. A second thickness of the second interlayer dielectric layer 530 is not greater than a first thickness of the first interlayer dielectric layer 520. For example, the second thickness of the second interlayer dielectric layer 530 can be controlled by a deposition process.

[0106] As described above, the first lower metal layer 522 is electrically connected to the first contact via 5222 in the at least one contact via. The first contact via 5222 is electrically connected to the top doped region 512 in the well region 510 (i.e., the first contact via 5222 penetrates the first interlayer dielectric layer 520). In other words, the first lower metal layer 522 is electrically connected to the top doped region 512 through the first contact via 5222.

[0107] Based on the above description, the semiconductor device of the present invention employs a relay metal layer and a multilayer interlayer dielectric layer structure to increase the overall thickness of the device, thereby avoiding the influence of high voltage on the conduction path. Furthermore, the combination of the metal layer and contact vias can serve as a vertical (metal) field plate, effectively increasing the equivalent area of ​​the field plate, thereby modulating the electric field distribution and increasing the breakdown voltage (or breakdown voltage).

[0108] It is worth noting that, Figure 5 The structure, shape, size, and position of the components are merely illustrative and not intended to limit the invention.

[0109] In some embodiments, the first lower metal layer 522 may not be electrically connected to the first upper metal layer 542 through the at least one via, but the present invention is not limited thereto. For example, the at least one via may be electrically connected to the first upper metal layer 542, and the first lower metal layer 522 may not be electrically connected to the at least one via.

[0110] In some embodiments, a top surface of the first lower metal layer 522 and a first top surface of the first interlayer dielectric layer 520 are substantially coplanar. A top surface of the top doped region 512 and a second top surface of the well region 510 may be substantially coplanar, but the present invention is not limited thereto.

[0111] In some embodiments, the first interlayer dielectric layer 520 may further include a second lower metal layer 524. The second lower metal layer 524 may be electrically connected to the source region 514 through the second contact via 5284 in the at least one contact via.

[0112] In some embodiments, the first interlayer dielectric layer 520 may further include a third lower metal layer 526. The third lower metal layer 526 may be electrically connected to the drain region 516 through the third contact via 5286 in the at least one contact via.

[0113] In some embodiments, the first lower metal layer 522, the second lower metal layer 524, and the third lower metal layer 526 may each have their own width and / or depth. The width and / or depth of the first lower metal layer 522, the second lower metal layer 524, and the third lower metal layer 526 may be substantially the same, but the present invention is not limited thereto.

[0114] In some embodiments, the at least one contact via may have its own width. The widths of the at least one contact via may be substantially the same, but this is not a limitation of the invention. The at least one guide hole may have its own width. The widths of the at least one guide hole may be substantially the same, but this is not a limitation of the invention.

[0115] In some embodiments, the substrate 500 may have a first conductivity type. The well region 510 may have a second conductivity type. The top-doped region 512 may have the first conductivity type. The source region 514 may have the second conductivity type. The drain region 516 may have the second conductivity type. In some embodiments, the well region 510 may further include a heavily doped region (not shown in the figure), which may have the first conductivity type. The source region 514 may be adjacent to the heavily doped region. The well region 510 may further include a second well region (also referred to as a substrate region) (not shown in the figure), which may have the first conductivity type. The source region 514 and the heavily doped region may be located in the second well region. The doping concentration of the source region 514 and the heavily doped region may be greater than the doping concentration of the second well region. The second well region, the source region 514, and the heavily doped region may be formed by a (multi-channel) ion implantation process. The source region 514, the heavily doped region, and the second well region may form a source doped region. In some embodiments, the at least one contact via may further include another contact via (not shown in the figures). The other contact via may electrically connect the second lower metal layer 524 and the heavily doped region.

[0116] In some embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type, but the present invention is not limited thereto. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the source region 514 may be referred to as the N+ region, the drain region 516 may be referred to as the N+ region, and the heavily doped region may be referred to as the P+ region. The P-type dopant may contain boron, gallium, aluminum, indium, boron trifluoride ions, or combinations thereof. The N-type dopant may contain phosphorus, arsenic, nitrogen, antimony, or combinations thereof.

[0117] In some embodiments, the semiconductor device 50 may further include an isolation region (not shown in the figures). For example, the isolation region comprises, for example, drift oxide or field oxide, but the invention is not limited thereto. The isolation region may be located on the well region 510 (the top-doped region 512 therein). The isolation region may be located between the source region 514 and the drain region 516. The isolation region may cover a portion of the top-doped region 512 and the well region 510. The isolation region may be adjacent to or cover a portion of the source region 514.

[0118] In some embodiments, the semiconductor device 50 may further include a gate region (not shown in the figures). For example, the gate region comprises (e.g.) polysilicon, but the invention is not limited thereto. The gate region may be located on the isolation region. The gate region may be located between the source region 514 and the drain region 516. The gate region may cover a portion of the isolation region and a portion of the well region 510. The gate region may be adjacent to the source region 514.

[0119] In some embodiments, the semiconductor device 50 may be a laterally diffused metal-oxide-semiconductor, a metal-oxide-semiconductor assembly, an insulated-gate bipolar transistor, or a diode, etc., but the present invention is not limited thereto.

[0120] Figure 6 This is a schematic flowchart of the manufacturing method of the semiconductor device of the present invention. Figures 7A to 7I For corresponding Figure 6 A cross-sectional diagram of the process. For example... Figure 6 As shown, this manufacturing method includes the following steps:

[0121] In step S602, a substrate is provided, wherein the substrate includes a well region and the well region includes a top-doped region, and then step S604 is continued.

[0122] Please refer to Figure 7A A substrate 500 is provided, wherein the substrate 500 includes a well region 510 (e.g., DNW), and the well region 510 includes a top doped region 512 (e.g., P-top), a source region 514 (e.g., N+), and a drain region 516 (e.g., N+).

[0123] In some embodiments, the well region 510 may further include a second well region (e.g., PW), and the second well region may include the source region 514. The second well region may further include a heavily doped region (e.g., P+).

[0124] In some embodiments, a gate (e.g., poly) and an isolation region (e.g., DOX) may be formed / provided on the substrate 500.

[0125] It is worth noting that although the above example uses a substrate containing a well region, a top-doped region, a source region, and a drain region as an example, the present invention is not limited thereto. For example, a well region may be formed in the substrate, and a top-doped region (e.g., formed by ion implantation of the substrate through a patterned mask), a source region, and a drain region may be formed in the well region.

[0126] In step S604, a first interlayer dielectric layer is deposited on the well region, followed by step S606.

[0127] Please refer to Figure 7B A first interlayer dielectric layer 520 is deposited on the well region 510.

[0128] In some embodiments, the first thickness of the first interlayer dielectric layer 520 can be several micrometers, but the present invention is not limited thereto.

[0129] In some embodiments, the first interlayer dielectric layer 520 may be formed by spin coating, chemical vapor deposition, high-density plasma chemical vapor deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, fluidized chemical vapor deposition, subatmospheric pressure chemical vapor deposition, other similar methods, or combinations thereof.

[0130] In some embodiments, the first interlayer dielectric layer 520 may be planarized to give it a flat top surface.

[0131] In some embodiments, a first material used in the first interlayer dielectric layer 520 may include: silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitrogen carbide, tetraethoxysilane, undoped silica glass, doped silicon oxide (such as boron-doped phosphosilicate glass, fused silica glass, phosphosilicate glass, boron-doped silica glass, or other similar materials), low dielectric constant dielectric materials, or other suitable dielectric materials.

[0132] In step S606, at least one contact via is formed in the first interlayer dielectric layer, wherein a first contact via is electrically connected to the top doped region, and then step S608 is continued.

[0133] Please refer to Figure 7C A first deep portion of the first interlayer dielectric layer 520 is removed using a patterning process to form a first deep trench on the first interlayer dielectric layer 520. A second deep portion and a third deep portion of the first interlayer dielectric layer 520 are also removed to form a second deep trench and a third deep trench on the first interlayer dielectric layer 520. The deep trenches are associated with (e.g., for) contact vias. The first deep trench connects to the top-doped region 512.

[0134] In some embodiments, the second deep trench may connect to the source region 514, and the third deep trench may connect to the drain region 516.

[0135] In some embodiments, the patterning process may include photolithography (e.g., photoresist overlay, photoresist coating (e.g., spin coating), soft baking, shielded alignment, exposure, post-exposure baking, development, drying (e.g., hard baking), other suitable techniques, or combinations thereof), etching (e.g., wet etching (e.g., immersion etching, spray etching), dry etching (e.g., capacitively coupled plasma etching, inductively coupled plasma etching, helical plasma etching, electron cyclotron resonance plasma etching), other suitable techniques (e.g., reactive ion etching), or combinations thereof), other suitable techniques, or combinations thereof. The photolithography process may also be replaced by unshielded photolithography, electron beam writing, ion beam writing, or molecular imprinting. The etching process may also be purely chemical etching (plasma etching), purely physical etching (ion polishing), or combinations thereof.

[0136] For example, a shielding pattern (layer), such as a photoresist pattern or a hard shielding pattern, can be formed on the first interlayer dielectric layer 520 using a photolithography process. The shielding pattern may have openings to expose a portion of the first interlayer dielectric layer 520. Then, the first interlayer dielectric layer 520 corresponding to the openings can be removed using the etching process described above to form a deep trench.

[0137] In some embodiments, the shielding pattern may comprise a photoresist layer (e.g., PR in the figure), a metal layer, other suitable metal materials, the alloys described above, or combinations thereof. In some embodiments, the photoresist layer may be a positive or negative photoresist. In some embodiments, the photoresist layer may be a single-layer or multi-layer structure, formed by, for example, deposition processes, photolithography processes, other suitable processes, or combinations thereof, but the invention is not limited thereto. In some embodiments, the metal layer may comprise a Ti / TiN / AlCu / TiN stacked structure.

[0138] After patterning, the first interlayer dielectric layer 520 has at least one deep trench.

[0139] In step S608, a first shallow portion of the first interlayer dielectric layer is removed by a patterning process to form a first shallow trench, and then step S610 is continued.

[0140] Please refer to Figure 7D A first shallow portion of the patterned first interlayer dielectric layer 520 is removed to form a first shallow trench, and a second and a third shallow portion of the first interlayer dielectric layer 520 are removed to correspondingly form a second shallow trench and a third shallow trench on the first interlayer dielectric layer 520. The shallow trenches are associated with (e.g., for) the process of an underlying metal layer. The first shallow trench connects to a first deep trench.

[0141] In some embodiments, the second shallow trench may connect to the second deep trench, and the third shallow trench may connect to the third deep trench.

[0142] After patterning, the first interlayer dielectric layer 520 further has at least one shallow trench.

[0143] In step S610, a conductive material is deposited on the first interlayer dielectric layer by a deposition process to form a first lower metal layer, wherein the first lower metal layer corresponds to the first shallow trench on which the conductive material is deposited, and the first lower metal layer is electrically connected to the first contact via, and then the process continues to step S612.

[0144] Please refer to Figure 7E Conductive material is deposited on the (patterned) first interlayer dielectric layer 520 through a deposition process, thereby depositing (i.e. filling) conductive material in and on the first shallow trench, thus forming a first lower metal layer 522. It is worth noting that the top surface of the first lower metal layer 522 may not be flat at this time (for example, it may bulge due to excessive deposition of conductive material).

[0145] Furthermore, through a deposition process, conductive material is deposited on the (patterned) first interlayer dielectric layer 520, thereby depositing (i.e., filling) the first deep trench with conductive material to form the first contact via 5222. Conductive material is also deposited (i.e. filled) in the second and third deep trenches to correspondingly form a second contact via 5284 and a third contact via 5286. Additionally, conductive material is deposited (i.e. filled) in the second and third shallow trenches to correspondingly form a second lower metal layer 524 and a third lower metal layer 526. The first contact via 5222 corresponds to the first deep trench where conductive material is deposited.

[0146] In some embodiments, suitable deposition processes may include physical vapor deposition (PVD), chemical vapor deposition (CVD), coating processes, spin coating, other suitable processes, or combinations thereof, but the invention is not limited thereto. PVD processes may include sputtering, evaporation, and / or pulsed laser deposition. CVD processes may include low-pressure chemical vapor deposition, low-temperature chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, rapid-rise chemical vapor deposition, metal-organic chemical vapor deposition, remote plasma chemical vapor deposition, atomic layer deposition, electroplating, molecular beam epitaxy, liquid phase epitaxy, other suitable processes, and / or combinations thereof, but the invention is not limited thereto.

[0147] In some embodiments, the (suitable) conductive material may include aluminum, copper, gold, silver, tungsten, titanium, tantalum, nickel, cobalt, ruthenium, palladium, platinum, manganese, tungsten nitride, titanium nitride, tantalum nitride, molybdenum nitride, tungsten silicide, titanium silicide, other suitable conductive materials or combinations thereof, but the invention is not limited thereto.

[0148] After the deposition process, the top surface of the first interlayer dielectric layer 520 and / or the top surface of the at least one metal layer may be uneven.

[0149] In step S612, a planarization process is used to make a top surface of the first lower metal layer and a first top surface of the first interlayer dielectric layer substantially coplanar, and then step S614 is continued.

[0150] Please refer to Figure 7F Through a planarization process, a top surface of the first lower metal layer 522 (deposited) and a first top surface of the first interlayer dielectric layer 520 (deposited) are made substantially coplanar. That is, through the planarization process, excess conductive material on the first shallow trench and the first interlayer dielectric layer 520 is removed (e.g., until the original (i.e., before the photoresist layer PR is deposited) top surface of the first interlayer dielectric layer 520 is exposed).

[0151] In some embodiments, the planarization process can be replaced by an etch-back process. The planarization process can be chemical mechanical polishing.

[0152] In some embodiments, a planarization process is used to make a top surface of the second lower metal layer 524, a top surface of the third lower metal layer 526, and a first top surface of the first interlayer dielectric layer 520 substantially coplanar.

[0153] In step S614, a second interlayer dielectric layer is deposited on the first interlayer dielectric layer, wherein a second thickness of the second interlayer dielectric layer is not greater than a first thickness of the first interlayer dielectric layer, and then step S616 is continued.

[0154] Please refer to Figure 7G A second interlayer dielectric layer 530 is deposited on the first interlayer dielectric layer 520. The second thickness of the second interlayer dielectric layer 530 is not greater than the first thickness of the first interlayer dielectric layer 520.

[0155] In some embodiments, the first material and the second material may be the same. In some other embodiments, the first material and the second material may be different.

[0156] In step S616, at least one via is formed in the second interlayer dielectric layer, and then step S618 is continued.

[0157] Please refer to Figure 7H A second via 5324 and a third via 5326 are formed in the second interlayer dielectric layer 530.

[0158] In detail, a second deep portion and a third deep portion of the second interlayer dielectric layer 530 are removed by a patterning process to form a second deep trench and a third deep trench on the second interlayer dielectric layer 530.

[0159] Conductive material is deposited in the second deep trench and the third deep trench through a deposition process to form the second via 5324 and the third via 5326 accordingly.

[0160] In some embodiments, the second via 5324 may be electrically connected to the second lower metal layer 524, and the third via 5326 may be electrically connected to the third lower metal layer 526.

[0161] In some embodiments, the at least one deep trench may not be connected to the first shallow trench.

[0162] In step S618, a first upper metal layer is formed on the second interlayer dielectric layer 130.

[0163] Please refer to Figure 7I A first upper metal layer 542 and a third upper metal layer 546 are formed on the second interlayer dielectric layer 530.

[0164] In some embodiments, the first upper metal layer 542 may be electrically connected to the first lower metal layer 522.

[0165] In some embodiments, the first upper metal layer 542 is electrically connected to the second via 5324, and the third upper metal layer 546 is electrically connected to the third via 5326.

[0166] This completes the fabrication of the semiconductor device 50 of the present invention.

[0167] In some embodiments, the substrate may comprise elemental semiconductors, such as silicon or germanium; compound semiconductors, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), or combinations thereof; alloy semiconductors, such as silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, or combinations thereof, but the embodiments of the present invention are not limited thereto. In some embodiments, the substrate may be a semiconductor-on-insulator (SOI) substrate. The aforementioned SOI substrate may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide. In some embodiments, the substrate 100 may be a semiconductor wafer (e.g., a silicon wafer or other suitable semiconductor wafer).

[0168] In some embodiments, the substrate may include various isolation features to separate different device regions within the substrate. For example, the isolation features may include shallow trench isolation (STI) features, but the invention is not limited thereto. In some embodiments, forming a shallow trench isolation may involve etching a trench in the substrate and filling the trench with an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). The filled trench may have a multilayer structure (e.g., a thermally oxidized substrate and silicon nitride filling the trench). A chemical mechanical polishing process may be performed to polish away excess insulating material and planarize the upper surface of the isolation feature.

[0169] In some embodiments, the substrate may include various conductive features (e.g., conductive lines or vias). For example, the conductive features may be formed of aluminum (Al), copper (Cu), tungsten (W), their respective alloys, other suitable conductive materials, or combinations thereof.

[0170] In summary, the semiconductor device manufacturing method of the present invention employs a two-step process to form a multilayer interlayer dielectric layer structure, increasing the overall thickness of the device to avoid the influence of high voltage on the conduction path. Furthermore, the combination of metal layers and vias, as well as the combination of metal layers and contact vias, in the semiconductor device of the present invention can serve as a vertical field plate, effectively increasing the equivalent area of ​​the field plate and thereby modulating the electric field distribution.

[0171] Although the present invention has been disclosed using the above embodiments, it is not intended to limit the present invention. Any modifications and alterations made by those skilled in the art to the above embodiments without departing from the spirit and scope of the present invention shall still fall within the technical scope protected by the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, wherein the substrate includes a well region, and the well region includes a top-doped region; A first interlayer dielectric layer is deposited on the well region; At least one contact via is formed in the first interlayer dielectric layer; A first lower metal layer is formed in the first interlayer dielectric layer; A second interlayer dielectric layer is deposited on the first interlayer dielectric layer; At least one via is formed in the second interlayer dielectric layer; as well as A first upper metal layer is formed on the second interlayer dielectric layer. in: A second thickness of the second interlayer dielectric layer is not greater than a first thickness of the first interlayer dielectric layer; The first lower metal layer is electrically connected to the first upper metal layer through a first via in one of the at least one vias; and The step of forming the first lower metal layer in the first interlayer dielectric layer includes: A first shallow portion of the first interlayer dielectric layer is removed using a patterning process to form a first shallow trench. A conductive material is deposited on the first interlayer dielectric layer using a deposition process to form the first lower metal layer, wherein the first lower metal layer corresponds to the first shallow trench on which the conductive material is deposited; and Through a planarization process, a top surface of the first lower metal layer and a first top surface of the first interlayer dielectric layer are substantially coplanar.

2. The manufacturing method as described in claim 1, characterized in that, The first lower metal layer is not electrically connected to the well region through the at least one contact via.

3. The manufacturing method as described in claim 1, characterized in that, The step of forming the at least one via in the second interlayer dielectric layer includes: A first deep portion of the second interlayer dielectric layer is removed using a patterning process to form a first deep trench; and Conductive material is deposited in the first deep trench using a deposition process to form the first via.

4. The manufacturing method as described in claim 1, characterized in that, The well region includes a source region and a drain region, and the method further includes: A second lower metal layer is formed in the first interlayer dielectric layer, characterized in that the second lower metal layer is electrically connected to the source region or the drain region through a second contact via in one of the at least one contact vias.

5. The manufacturing method as described in claim 4, characterized in that, The first upper metal layer is further electrically connected to the second lower metal layer through a second via in one of the at least one vias.

6. The manufacturing method as described in claim 4, characterized in that, The first upper metal layer is not electrically connected to the second lower metal layer through the at least one via.

7. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, wherein the substrate includes a well region, and the well region includes a top-doped region; A first interlayer dielectric layer is deposited on the well region; At least one contact via is formed in the first interlayer dielectric layer; A first lower metal layer is formed in the first interlayer dielectric layer; A second interlayer dielectric layer is deposited on the first interlayer dielectric layer; At least one via is formed in the second interlayer dielectric layer; as well as A first upper metal layer is formed on the second interlayer dielectric layer. in: A second thickness of the second interlayer dielectric layer is not greater than a first thickness of the first interlayer dielectric layer; The first lower metal layer is electrically connected to the top-doped region in the well region through a first contact via of the at least one contact via; and The step of forming the first lower metal layer in the first interlayer dielectric layer includes: A first shallow portion of the first interlayer dielectric layer is removed using a patterning process to form a first shallow trench. A conductive material is deposited on the first interlayer dielectric layer using a deposition process to form the first lower metal layer, wherein the first lower metal layer corresponds to the first shallow trench on which the conductive material is deposited; and Through a planarization process, a top surface of the first lower metal layer and a first top surface of the first interlayer dielectric layer are substantially coplanar.

8. The manufacturing method as described in claim 7, characterized in that, The first lower metal layer is not electrically connected to the first upper metal layer through the at least one via.

9. The manufacturing method as described in claim 7, characterized in that, The step of forming the at least one contact via in the first interlayer dielectric layer includes: A first deep portion of the first interlayer dielectric layer is removed using a patterning process to form a first deep trench; and Conductive material is deposited on the first interlayer dielectric layer by a deposition process to form the first contact via, wherein the first contact via corresponds to the first deep trench on which the conductive material is deposited.

10. The manufacturing method as described in claim 7, characterized in that, The well region includes a source region and a drain region, and the method further includes: A second lower metal layer is formed in the first interlayer dielectric layer, wherein the second lower metal layer is electrically connected to the source region or the drain region through a second contact via in the at least one contact via.

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