Interception filter entries using partial vectors

Abstract

The described technology provides a method including generating a complete trace vector, where each bit of the complete trace vector indicates a cache validity state of a coherency particle (cogram) in a proxy cache for an associated proxy, partitioning the trace vector into a plurality of partial vectors (PVECs), for each PVEC, generating a plurality of partial vectors (PVECs), each bit of the complete trace vector indicating a cache validity state of the coherency particle (cogram) in the proxy cache for the associated proxy. Determining whether a cache validity state of at least one bit in the PVEC is set to be valid, and in response to determining that the cache validity state of at least one bit in a given PVEC is set to be valid, storing the given PVEC and a PVEC pointer thereof in a trackinginfo field of a base snoop filter (SFT) entry for the cogran, wherein the PVEC pointer indicates the position of a given PVEC in the complete tracking vector.

Description

Background Technology

[0001] Processor-based devices may include multiple processing elements (PEs) (e.g., a processor core as a non-limiting example), each PE providing one or more local caches for storing frequently accessed data. Because multiple PEs of a processor-based device can share memory resources such as system memory, multiple copies of shared data read from a given memory address can coexist in both system memory and the PE's local cache. Therefore, to ensure that all PEs have a consistent view of the shared data, processor-based devices provide support for cache coherency protocols, enabling local changes to shared data within one PE to propagate to other PEs. Summary of the Invention

[0002] The described technique provides a method comprising: generating a complete tracking vector, wherein each bit of the complete tracking vector indicates the cache validity state of a cogran in a proxy cache for a relevant proxy; dividing the tracking vector into multiple partial vectors (PVECs); for each PVEC, determining whether the cache validity state of at least one bit in the PVEC is set to valid; and in response to determining that the cache validity state of at least one bit in a given PVEC is set to valid, storing the given PVEC and its PVEC pointer in a tracking_info field of a cogran underlying listener filter (SFT) entry, wherein the PVEC pointer indicates the position of the given PVEC in the complete tracking vector.

[0003] This summary is provided to describe in a simplified form the selection of concepts further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] This article also describes and lists other implementation methods. Attached Figure Description

[0005] Figure 1 The diagram illustrates how a system using a listener filter provides cache consistency.

[0006] Figure 2 The illustration shows an example structure of a listening filter entry that implements the techniques disclosed herein.

[0007] Figure 3 An example of a representation of the complete trace vector of the cache coherence system disclosed in this paper is illustrated.

[0008] Figure 4 The illustration shows an example entry state of the logical SFT entry of the cache coherence system disclosed in this paper.

[0009] Figure 5 The illustration shows an example tracing pattern for logical SFT entries in the cache consistency system disclosed in this paper.

[0010] Figure 6 The illustration shows an example value of the tracking_info field of the underlying SFT entry for the cache consistency system disclosed in this paper.

[0011] Figure 7 The illustration shows an example value of the tracking_info field of the underlying SFT entry for the cache consistency system disclosed in this paper.

[0012] Figure 8 The illustration shows example values ​​for the tracking_info field of the additional SFT entries in the cache consistency system disclosed in this paper.

[0013] Figure 9 The illustration shows an example operation when the agent caches a new copy of the cogran currently being tracked by SFT.

[0014] Figure 10 The illustration shows an example operation when an SFT entry determines that it cannot accurately track which agents cache the cogran that the SFT is tracking.

[0015] Figure 11 The illustration shows an example operation when an SFT entry wants to change its tracking_mode to PVEC when adding a new agent to its tracking against cogran.

[0016] Figure 12 The illustration shows an example operation for recording one or more PVECs into an SFT.

[0017] Figure 13 The illustration shows an example operation when the tracking_mode of an SFT entry is PVEC and the SFT needs to add an agent to its tracking for that SFT entry.

[0018] Figure 14 The illustration shows an example operation that forms a complete tracking vector for an SFT entry when the SFT updates the SFT entry.

[0019] Figure 15 The illustration shows an example operation when an SFT needs to update an existing logical SFT entry to remove an agent from its tracking.

[0020] Figure 16 The illustration shows an example operation when the tracking_mode of an SFT entry is PVEC and the SFT needs to remove the agent from its tracking of that SFT entry.

[0021] Figure 17 The illustration shows an example operation where cogran is accessed and an SFT lookup is performed to determine whether listening is necessary.

[0022] Figure 18 The illustration shows an example operation where a proxy might request exclusive access to cogran, rendering all other cached copies invalid.

[0023] Figure 19 The illustration shows an example system that can be used to implement the cache consistency system disclosed herein. Detailed Implementation

[0024] This paper discloses an implementation of a multiprocessor system that employs hardware-enforced cache coherence (HW). When an agent, such as a CPU or GPU, wants to access a memory location, HW automatically determines whether another agent currently holds a copy of that memory location. If the access is a read and the memory location is cached by another agent, the system memory may be outdated. In this case, the access must be satisfied by obtaining data from the other agent's cache. If the access is a write, typically other cache copies must first be written back to system memory. The memory blocks that maintain HW-enforced cache coherence are called cograns, and the system can match their cogran size to the cache line size.

[0025] In some implementations, the system may maintain a list of which agents currently cache which cograns. In other implementations, instead of maintaining a central consistency directory, all agents are queried during the processing of a requested memory access to determine if any agent holds a copy of the cogran in its cache. This query is often referred to as snooping. Over-snooping occurs when an agent is snooped to search for a cogran in its cache and that agent does not currently hold a copy of the cogran. Snooping is functionally useless and unnecessarily disturbs the agent. The system disclosed herein reveals a beneficial implementation using a Snoop Filter (SFT) to help reduce over-snooping. This implementation reduces the penalty of over-snooping in terms of the increased latency to memory access, the consumed interconnect bandwidth without functional benefit, and the energy wasted performing unnecessary cache lookups at the over-snooped agent. A Snoop Filter can be thought of as a higher-level, inclusive, set-associative cache that does not contain data and whose purpose is to track the entire set of cograns held by the lower-level cache(s) that need to maintain cache consistency.

[0026] An imprecise snooping filter is a filter that tracks whether a particular agent has cached cogran at a given point in time. This SFT is smaller than other types of SFTs, but its lack of precision means that when a snooping request is needed, all consistent caches in the system must be snooped. This lack of precision also means that the SFT typically loses the ability to detect when cogran has been evicted from all consistent caches.

[0027] A precise sniffing filter can use vectors to completely track which agents have cached copies of a cogran. Precise SFT requires a relatively large area to implement because it tracks a large amount of state, tracking one bit per agent per cogran. In this implementation, when an agent obtains a copy of a cogran to write to its cache, it sets the corresponding vector bit in the agent's SFT entry tracking that cogran. When the agent later evicts the cogran, its corresponding vector bit in the SFT entry tracking that cogran is cleared. This has several advantages over imprecise SFT: (a) only the exact agents that need to be sniffed are sniffed; (b) the sniffing range can be further reduced over time because each agent evicts a cogran from its cache, and the SFT is updated accordingly, applying only to evictions where agents communicate with the SFT.

[0028] In a hybrid implementation of SFT, SFT can precisely track (n) agents (typically 2 to 3) by recording the agent ID (AID) in the SFT's cogran tracking entry. The AID can be a unique identifier for each agent used for SFT tracking. For example, the AID can be an encoding of the SFT vector location that the agent can otherwise set. Alternatively, the AID can be the agent's interconnect address—the ID the interconnect uses to send messages to that agent. When >(n) agents have cached copies of the cogran, SFT switches from AID tracking to imprecise tracking. When the hybrid implementation is in AID tracking mode, there is no over-snogging because the SFT entry knows exactly who to listen to. On the other hand, when the hybrid implementation is in imprecise tracking mode, the SFT entry indicates that all agents need to be listened to if the cogran is currently held or tracked by SFT. When the system has many consistent agents (e.g., 128), this approach uses less hardware than precise vector SFT—recording (n) AIDs (for a sufficiently small n) requires fewer state bits than recording a large vector.

[0029] In systems with many consistent agents (e.g., 128), oversniffing due to imprecise tracking is very expensive in terms of consumed infrastructure bandwidth and wasted energy. Furthermore, the large SFT required for accurate tracking is very expensive in terms of area, which also leads to increased propagation distance for listeners (and other) messages. The workload of many agents sharing data structures or instruction pages can quickly exhaust the accurate AID tracking capabilities of a hybrid approach and may lead to more frequent use of imprecise tracking mode. While a certain degree of oversniffing is tolerable because various imprecise tracking modes generally cannot revert to accurate tracking when a cogran is evicted, listener filter management itself incurs the overhead of oversniffing. Specifically, when a listener filter cannot know which cograns are no longer cached by any agent, it may send "filter refresh" listeners more frequently to free up space in the SFT itself so that newly tracked cograns can be installed in the SFT.

[0030] An alternative implementation of SFT removes the full SFT tracking vector from each SFT entry and instead uses a separate, smaller structure (DVT) to store the full tracking vector for SFT entries that need to track more than (n) AIDs. This reduces the tracking information that each SFT entry needs to carry, but the risk is that there aren't enough entries in the DVT to cover the number of cograns shared concurrently by >n AIDs. To mitigate this risk, the system approach increases the DVT size, including the full tracking vector in each SFT entry.

[0031] Another alternative implementation of SFT removes the complete SFT tracking vector from each SFT entry and allows SFT entries to be paired with second SFT entries to form logical SFT entries consisting of two physical SFT entries; this then allows the complete tracking vector to be recorded across SFT entry pairs. This reduces the tracking information that each SFT entry needs to carry, but still requires a minimum size for the SFT entry pair to store the complete tracking vector, which can become a problem when there are a large number of agents to track, such as when the system needs to track >= 128 agents.

[0032] The SFT implementation disclosed in this paper leverages the fact that while data sharing occurs between different agents of the same virtual machine (VM), there is little (if any) data sharing between different VMs. Scheduling software attempts to improve performance and save energy by deploying VMs within a single agent cluster where possible. Typically, this cluster resides on the same die or the same non-uniform memory access (NUMA) domain, but it may also exist on other boundaries, such as half-die. Sometimes, the agents of a VM end up scattered across multiple dies or multiple NUMA domains. The technique disclosed in this paper preserves the concept of a complete trace vector for each cogran and utilizes the scheduling SW's preferences to consider the location of available agents when determining which agent set to assign a VM to. Specifically, the SFT implementation disclosed in this paper divides the complete trace vector into multiple partial vectors. If the scheduling SW has already attempted to restrict the deployment of each VM to a single set of CPUs, then the HW can use this to determine the partial vector boundaries. By enabling SFT entries to trace only a single partial vector, the size of each SFT entry can be further reduced. If the VM deployment ultimately spans multiple partial vectors, then an SFT entry can acquire an additional entry as needed to store one or more additional partial vectors to track the cogran shares tracked by that SFT entry.

[0033] For the cache coherence system disclosed herein, the term physical SFT entry (or physical entry) is used to refer to the base entry when it contains the information required to perform a cogran lookup in the SFT. When a physical SFT entry cannot be independent, it is an additional entry and contains additional information that its associated base entry cannot store. The term logical SFT entry (or logical entry) is used to refer to the base entry for the cogran, and it may also include additional SFT entries. A logical SFT entry contains all the information required to perform a cogran lookup in the SFT, as well as all known trace information about that cogran (i.e., who cached it). In the various implementations disclosed herein, a logical entry can be an aggregation of the base SFT entry and its associated additional SFT entries (if the additional entries are in use), or it can only be the base SFT entry when it has no associated additional SFT entries.

[0034] Typically, a base SFT entry contains enough information to determine whether the SFT is currently tracking the cogran of interest and provides some capability to track the listening object. A base SFT entry can be independent or not independent when tracking a cogran. Additional SFT entries provide the capacity to store more agent tracking information than the base SFT entry itself can hold. Additional SFT entries cannot be independent and are always paired with a base SFT entry.

[0035] Furthermore, as used herein, the term "full vector" (or "full trace vector") refers to a vector of one bit per agent that may be required for cogran tracing in the system. Therefore, each agent has predefined bits, and by determining which bits of the full vector stored in the SFT entry are set, it is possible to precisely determine which agent(s)(s) need to be listened to when accessing a memory location. A partial vector (PVEC or partial trace vector) refers to a portion of the full vector that the SFT entry needs to store. For example, if the full vector is divided into four parts, the resulting partial vectors can be identified as the first, second, third, or fourth part vector of the full vector. By having a partial vector and knowing its position within the full vector, it is possible to precisely determine which agent(s)(s) represented by that partial vector need to be listened to when accessing a memory location.

[0036] Figure 1 An implementation of a cache coherence system 100 using a sniffing filter is disclosed, which improves upon one or more of the above implementations. Specifically, the cache coherence system 100 can be implemented on a multi-core architecture including multiple central processing unit (CPU) cores 102 and 104, a graphics processing unit (GPU) 106, one or more input / output (I / O) agents 108, a serialization point of sale (PoS) 110, and memory 114. While this example illustrates two CPU cores and one GPU, it is to be understood that any number of CPU cores and GPUs can be used without departing from the scope of this disclosure. Examples of I / O agents 108 include, but are not limited to, Industry Standard Architecture (ISA) devices, Peripheral Component Interconnect (PCI) devices, PCI-X devices, High Speed ​​PCI devices, Universal Serial Bus (USB) devices, Advanced Technology Attachment (ATA) devices, Small Computer System Interface (SCSI) devices, and InfiniBand devices.

[0037] Processing unit cores 102, 104, 106, and I / O agents 108 can be referred to as agents 102-108, each referenced by an agent ID (AID). These agents 102-108 can have multiple levels of internal caches, such as L1, L2, and L3 caches. When agents 102-108 cache consistent memory blocks (cograns) in their internal caches, a listener filter (SFT) 150 can track these cograns and which agents 102-108 have cached each cogran. Any of the agents 102-108 can issue consistent or inconsistent requests, and the PoS 110 uses the listener filter 150 to ensure the serialization of memory access requests to provide memory consistency.

[0038] For example, PoS 110 receives a consistency request 120 from CPU 102. In response to the consistency request 120, PoS 110 issues a listen command 122 to CPU core 104, GPU 106, and I / O agent 108. CPU core 104, GPU 106, and I / O agent 108 can provide the requested consistency information back to PoS 110. When sending listen 122, PoS 110 references SFT 150.

[0039] SFT 150a illustrates an example implementation of SFT 150. SFT 150a includes data structures for tracking addresses and agents(s) 102-108, which have obtained a copy of each cogran currently cached by agents 102-108. SFT 150a can be an n-way filter, as indicated by n arrays 154. The listener filter 150a can include an array of entries 152, the contents of which are further described below. Each entry 152 can include a tag field, such as... Figure 2 The disclosed tag field 218 is used to store the tag portion of the physical address (PA) identifying the cogran. For example, for a cogran size of 64 bytes, a PA width of 48 bits, an SFT with 1024 sets, and an SFT that is a 16-way associative SFT, bits 15:6 of the PA can be used to select an SFT set, and bits 47:16 of the PA can be stored as tags in the tag field 218 of the SFT entry 152. When the SFT 150a needs to perform a lookup to see if the PA of the cogran exists in the SFT 150a, it uses the PA[15:6] of the cogran to select a set. Subsequently, for the selected set, the SFT 150a can compare PA[47:16] with the tag values ​​stored in the tag field 218 of the 16 SFT entries 152 in the selected set. If a match is found in the tag field 218 of any of the 16 SFT entries in the selected set, then its path (e.g., path 5) is currently tracking the cogran being searched.

[0040] In the implementation of SFT 150a disclosed herein, logical entry 152 can be configured to store a partial vector (PVEC) in the base SFT entry 162, and to dynamically allocate additional SFT entries 164 in the SFT set in cases where the base SFT entry 162 cannot store additional PVEC. Specifically, SFT 150a may need to track up to 128 agents; however, these 128 agents can be divided into four (4) agent clusters that need to be tracked by SFT 150a. In addition, SFT entry 152 also includes an entry_state field 166, a tracking_mode field 168, and a tracking_info field 170. According to the implementation of the cache consistency system disclosed herein, the tracking_mode field 168 can take three different values: PVEC, AID, and IMPRECISE.

[0041] For example, when a cache coherence system allocates an SFT entry (such as SFT entry 152) to track a cogran, it begins by setting the tracking_mode 168 of SFT entry 152 to AID and recording the agent's AID in the tracking_info field 170. When another agent becomes a new sharer of the cogran, the other agent needs to be added to the tracking of the cogran in SFT entry 152. In this case, if there is an available AID subfield in the tracking_info field 170 of SFT entry 152 to store the new agent's AID, then the tracking_mode 168 of SFT entry 152 will remain as AID. If more than a predetermined number of agents need to be tracked, and they all fall within a single PVEC, then the tracking_mode 168 of SFT entry 152 is changed to PVEC. For example, the predetermined number could be four (4). In this example implementation, if more than a predetermined number of agents need to be tracked, where the predetermined number of agents is four (4), and they do not fall within a single PVEC but fall within three part vectors, the cache coherence system will acquire an additional entry 164, change the entry_state 166 of the additional SFT entry 164 to EXTRA, change the tracking_mode 168 of the base SFT entry 162a to PVEC, and change the entry_state 164 of the base SFT entry 162a to SEARCHABLE_E. In the illustrated implementation, if more than four agents need to be tracked and they are spread across more than three part vectors, the tracking_mode 168 of the SFT entry 152 is changed to IMPRECISE. However, in the alternative implementation, if more than...m There are more than 10 agents, and they are distributed among more than 100 agents. n On a partial vector, the tracking_mode 168 of SFT entry 152 is changed to IMPRECISE, so if the number of agents to be tracked exceeds the ability of the SFT entry to track them, it switches to IMPRECISE.

[0042] Below Figure 2 The diagram further illustrates in detail the structure of the basic SFT entries 162 and 162a, as well as the additional SFT entry 164. Specifically, Figure 2 The diagram illustrates the structure of a logic eavesdropping filter entry 200 that implements the technology disclosed herein. Specifically, the logic eavesdropping filter entry 200 can be configured to store in the underlying SFT entry 262. n Each agent ID (AID) or partial vector (PVEC). Logical listener filter entry 200 can be configured to dynamically allocate additional SFT entries 264 in the SFT set for cases where the PVEC in the base entry 262 cannot track all agents that have obtained a copy of cogran.

[0043] Figure 2 The diagram illustrates the various components of the base SFT entry 262 when operated as a single entry without additional entries, and the base SFT entry 262a when operated using an additional SFT entry 264. The base SFT entry 262 may include an entry_state field 214, which can be set to IDLE or SEARCHABLE. The tracking_mode field 216 can be one of NA (if entry_state=IDLE), PVEC, AID, or IMPRECISE. Additionally, the base SFT entry 262 may include a tag field 218 and a miscellaneous field 220. The tracking_info field 222 and ECC field 224 of the cogran currently cached or considered to be cached entries in the base SFT entry record can store error correction bits.

[0044] The base SFT entry 262a may include a tag field 218a and an extra_entry field 221. The tracking_info field 222a may include a portion of the tracking vector of the base SFT entry, and the ECC field 224a may store error correction bits. If the logical SFT entry 200 to which the base SFT entry 262a belongs has an additional entry, the extra_entry field 221 indicates which other SFT physical entry has been assigned as an additional entry to that logical SFT entry. In one implementation, the extra_entry field 221 exists even when the logical SFT entry 200 has no associated additional entries. In an alternative implementation, when the implementation of the logical SFT entry 200 hardcodes each physical base SFT entry, the extra_entry field 221 is not present; when the state of the logical SFT entry 200 indicates that it has an additional entry, other physical entries have been pre-assigned as additional entries to that physical base SFT entry. When the entry_state 214 / 214a of logical SFT entry 200 is set to SEARCHABLE_E, it can be determined that it has an additional entry.

[0045] The entry_state field 214b of the additional SFT entry 264 can be set to EXTRA, and its tracking_mode field is (not applicable) NA. The tracking_info_E(1) field 230a and tracking_info_E(0) field 230b of the additional SFT entry 264 can be used to store additional PVEC. The ECC field 224b can store error correction bits. Therefore, the logical SFT entry 200 is either (a) simply the base SFT entry 262 when it has no associated additional SFT entry, or (b) a combination of the base SFT entry 262a and its associated additional SFT entry 264.

[0046] Figure 3The diagram illustrates a representation 300 of the complete tracking vector, where each bit of the complete tracking vector indicates the cache validity status of the cogran (cogran) in the agent cache of the relevant agent as multiple partial vectors (PVECs). When the cache coherence system determines that the tracking_mode of an SFT entry needs to be changed from AID to something else, or if the tracking_mode of an SFT entry is currently PVEC, the SFT creates an equivalent complete 128b tracking vector for the entry by decoding the AID or directing the (multiple) partial vectors to the correct positions within the complete tracking vector. The complete vector is then divided into its component PVECs. Next, the cache coherence system performs a reduction OR on the bits of each partial vector to determine which PVECs the entry needs to record. If the result of the reduction OR of a PVEC is zero, then that PVEC does not need to be recorded in the SFT entry of the cogran. If only one PVEC is needed, one PVEC is stored in the tracking_info field of the underlying SFT entry. If more than one PVEC is needed, the SFT entry requires additional SFT entries. However, if all four PVECs are required, the tracking_mode is changed to IMPRECISE.

[0047] Specifically, 302 represents vector example 1, where the complete vector is divided into four PVECs: PVEC 00 310, PVEC 01 312, PVEC 10 314, and PVEC 11 316. Specifically, the complete vector can be a 128-bit vector tracking 128 agents. Therefore, each PVEC in PVECs 310-316 is a 32-bit partial vector. For example 1 302, a given SFT entry for a cogran has five sharer agents, and each sharer agent falls into PVEC 01 312. Therefore, the reduction or operation on the bits of PVEC 01 312 returns "1", while the reduction or operation on the bits of the other PVECs returns "0". In this case, a single SFT entry with the tracking_mode of the PVEC is used to accurately track all shared agents of the cogran without using additional entries.

[0048] For vector example 2 304, the cogran of the SFT entry has 6 sharer agents, which are distributed across two PVECs, namely PVEC 01 312 and PVEC 10 314. In this case, the logical SFT entry requires an additional entry, sets the tracking_mode of the additional entry to PVEC, and records one PVEC in the tracking_info field of the base SFT entry, and the other PVEC in the tracking_info field of the additional entry. Similarly, if three PVECs in PVECs 310-316 have sharer agents, then two PVECs can be stored in the tracking_info field of the additional entry. For vector example 3 306, the cogran of the SFT entry has 8 sharer agents, which are distributed across all four PVECs 310-316. In this case, the logical SFT entry needs to store the complete tracking vector but is unable to do so. Therefore, it sets its tracking_mode to IMPRECISE.

[0049] Figure 4 The illustration shows an example entry state 400 for a logical SFT entry in the cache coherence system disclosed herein. Specifically, based on the state of the logical SFT entry, the entry_state field of the logical SFT entry can be set to four different values: IDLE, SEARCHABLE, SEARCHABLE_E, and EXTRA. When the entry state of a logical SFT entry is IDLE 402, the physical SFT entry is available for allocating new cogran as the SFT base entry, and the physical entry is available as an additional SFT entry for the logical SFT entry. When the base SFT entry is allocated to begin tracking cogran for the first time, the entry_state of the base entry is set to SEARCHABLE 404. As more agents add or evict cogran from their caches of the base SFT entry, the entry_state of the base SFT entry may be updated. If at any time the cached cogran's proxy exceeds the precise tracking capability of the underlying SFT entry, the underlying SFT entry receives an additional SFT entry and its entry_state is changed to SEARCHABLE_E 406, or the underlying SFT entry is changed to an imprecise proxy tracking mode. When the SFT no longer needs to track the cogran, the entry_state of the underlying SFT entry for that cogran is set to IDLE 402.

[0050] When an SFT entry is available (i.e., entry_state == IDLE), the available SFT entry can be used as an additional SFT entry for the logical SFT entry. In this case, the entry_state of the available SFT entry is set to EXTRA408. When the logical SFT entry no longer needs to use an additional SFT entry for cogran or the SFT evicts cogran from its tracking, the entry_state of any associated additional SFT entry is set to IDLE 402.

[0051] When the entry_state of a physical SFT entry is SEARCHABLE 404, the physical SFT entry contains information that can be used to determine whether the SFT stores cogran, and it cannot be used to allocate new cogran, nor is it an additional entry to a logical SFT entry. In this case, the logical SFT entry has no associated additional SFT entries. When the entry_state of a physical SFT entry is SEARCHABLE_E 406, the physical SFT entry contains information that can be used to determine whether the SFT stores cogran, and it cannot be used to allocate new cogran, nor is it an additional entry to a logical SFT entry. However, in this case, the logical SFT entry has associated additional SFT entries. When the entry_state of a physical SFT entry is EXTRA 408, the physical entry is an additional SFT entry containing some or all of the tracking_information representing its associated underlying SFT entry, and it cannot be used to allocate new cogran, nor is it an additional SFT entry to a underlying SFT entry.

[0052] Figure 5The illustration shows an example tracking mode 500 for a logical SFT entry in the cache consistency system disclosed herein. At allocation, an SFT entry begins in AID (502) mode and switches to PVEC (504) or IMPRECISE (506) mode if the SFT entry later exhausts its ability to add new AIDs to its tracking. When the tracking_mode of a logical SFT entry is == AID, its tracking_info contains AIDs for one or more agents that cache the cogran that the logical SFT entry is tracking. When the tracking_mode of a logical SFT entry is == PVEC, its tracking_info contains one or more partial vectors (PVECs) indicating which agents cache the cogran that the logical SFT entry is tracking. When the tracking_mode of a logical SFT entry is == IMPRECISE, its tracking_info does not fully guarantee which agents cache the cogran that the SFT entry is tracking. This typically leads to a degree of oversniffing while maintaining cache consistency.

[0053] Table I below illustrates various combinations of entry_state and tracking_mode to determine how to interpret the information stored in the tracking_info field(s) of a logical SFT entry: Table I

[0054] Figure 6 The illustration shows an example value of the tracking_info field 602 of the underlying SFT entry 600 of the cache coherence system disclosed herein when the tracking mode of the SFT entry is equal to the AID. The tracking_info field 602 can store tracking information about the AID that the SFT entry is tracking. Specifically, in AID mode, the width of the tracking_info field 602 can include four AIDs, namely AID(0)-AID(3), each AID having a width of 8 bits, including 7 bits for identifying the AID and 1 bit for indicating whether the AID is currently valid (VLD(0)-VLD(3)).

[0055] Figure 7The illustration shows example values ​​for the tracking_info field 702 of the underlying SFT entry 700 of the cache coherence system disclosed herein when the tracking mode of an SFT entry is equal to PVEC and the entry state is set to SEARCHABLE or SEARCHABLE_E. In the illustrated example, the 128-bit exact tracking vector is split into four PVECs. When the tracking_mode of an SFT entry is set to PVEC, the underlying SFT entry 700 contains a single PVEC stored by the PVECTOR subfield 704 of the tracking_info field 702. Additionally, the PVS (partial vector selection) field 706 of the tracking_info indicates which PVEC is recorded: the 1st, 2nd, 3rd, or 4th. When the entry_state of an SFT entry is set to SEARCHABLE_E, the logical SFT entry also has additional SFT entries to record the additional PVECs. The PVS field 706 of the tracking_info is also referred to herein as the PVEC pointer because it indicates which PVEC is recorded.

[0056] Figure 8 The illustration shows an example value for the tracking_info field 802 of an additional SFT entry 800 in the cache coherence system disclosed herein when the tracking_mode of an SFT entry is equal to PVEC and the entry_state is set to SEARCHABLE_E. In the illustrated example, the 128-bit exact tracking vector is split into four PVECs. When the tracking_mode of an SFT entry is set to PVEC and the entry_state of an SFT entry is set to SEARCHABLE_E, SFT entry 800 is an additional SFT entry and contains additional PVECs that its underlying SFT entry has no capacity to hold. The first PVEC is held by the tracking_info field of the underlying SFT entry. The second PVEC is held by one of the tracking_info_E fields of the additional SFT entry, for example, held in tracking_info_E0. Each tracking_info_E field has three subfields: PVECTOR 804, which stores a portion of the vector; PVS 806, also known as the PVEC pointer 806, which indicates which portion of the vector is stored by the PVECTOR field 804; and PVLD 808, which indicates whether the tracking_info_E field is currently in use. If an SFT entry is using a third PVEC, it is stored in the remaining tracking_info_E fields.

[0057] When an SFT entry is created to allow tracking of who cached cogran, SFT selects an available SFT entry. SFT sets the entry_state of the selected SFT entry to SEARCHABLE and the tracking_mode of the selected SFT entry to AID. SFT then determines which full tracking vector bit is specified to represent the agent and encodes that bit as a 7-bit value to form the agent's AID. Note that in the example system described in this paper, 7 bits are needed to uniquely identify one of the 128 agents tracked by the full vector. SFT records the AID in the AID(i) subfield of the tracking_info field of the selected SFT entry and sets the associated VLD(i) subfield bit. Additionally, the SFT entry's tag and ECC fields may be written as needed.

[0058] Figure 9 The diagram illustrates operation 900 when the agent caches a new copy of the cogran currently being tracked by SFT. Operation 902 determines the tracking_mode of the SFT entry being tracked for the cogran. If the tracking_mode of the SFT entry is currently set to AID, operation 904 determines if there is space for the SFT entry to append an AID record to the tracking_info field. If not, operation 906 determines whether the SFT is configured to enable Partial Vector Emissions (PVEC). If yes, in operation 908, control is transferred to the following steps... Figure 11 The SWITCH_TO_PVEC operation will be discussed further below. On the other hand, if operation 906 determines that the SFT is not configured to enable Partial Vector Emissions (PVEC), then in operation 910, control is transferred to the following... Figure 10 The IMPRECISE operation will be discussed further in the following section.

[0059] If operation 904 determines that the SFT entry has an additional AID recorded in the tracking_info field, then operation 912 determines the complete tracking vector bit position of the new agent. Operation 914 encodes the tracking vector bit position of the new agent as a 7b value to form the AID, operation 916 selects an available AID subfield in the tracking_info field of the entry, operation 918 records the AID of the new agent in the selected AID subfield, and operation 920 sets the VLD subfield of the selected AID field to 1.

[0060] If operation 902 determines that the tracking_mode of the SFT entry being tracked for cogran is set to IMPRECISE, then operation 922 adds an agent to the inaccurate tracking of the entry as needed. On the other hand, if operation 902 determines that the tracking_mode of the SFT entry being tracked for cogran is set to PVEC, then operation 924 transfers control to the following... Figure 13 The AddAgent_PVmode was further disclosed in the document.

[0061] Figure 10 The diagram illustrates operation 1000 when an SFT entry determines that it cannot precisely track which agents cache the cogran that the SFT is tracking. Operation 1004 sets the tracking_mode of the underlying SFT entry to IMPRECISE, operation 1006 appropriately updates the tracking_info of the underlying SFT entry for inaccurate tracking of any currently tracked agents, and operation 1008 adds the new agent to the inaccurate tracking_info field of the underlying SFT entry.

[0062] Figure 11 The illustration depicts operation 1100 when an SFT entry attempts to change its tracking_mode to PVEC when adding a new agent to its tracking for cogran. Operation 1104 initializes the full tracking vector with all bits set to zero, operation 1106 determines the full tracking vector bit positions for the new agent, and operation 1108 sets the new agent's bits in the full tracking vector. Operation 1110 decodes the AID of each agent currently being tracked by the SFT entry into the equivalent full tracking vector bit positions for each AID stored in the entry's tracking_info field, operation 1112 sets the vector bits in the full tracking vector for the currently tracked agent, and operation 1114 divides the full tracking vector into several equal-sized partial vectors, for example, four partial vectors in an exemplary embodiment. Subsequently, operation 1116 performs a reduction OR on all bits of each PVEC to form a single summary bit (called the PVEC summary bit) for each PVEC.

[0063] Operation 1118 determines whether more than one PVEC summary bit is set. If only one PVEC summary bit is set (indicating that all agents of the cogran for the cached SFT entry fall within a single PVEC), then operation 1120 sets the tracking_mode of the underlying SFT entry to PVEC, and in 1122, transfers control to the following... Figure 12The RecordPV operation is disclosed in [the documentation]. If operation 1118 determines that more than one PVEC aggregation bit is set (indicating that all agents of cogran that cache SFT entries are distributed outside a single PVEC), then operation 1124 determines whether SFT is configured to use additional SFT entries. If SFT is not configured to use additional SFT entries, then in operation 1126, control is transferred to the above [the relevant entity / entity]. Figure 10 The Switch-to-IMPRECISE operation is publicly available.

[0064] If operation 1124 determines that the SFT is configured to use additional SFT entries, then operation 1128 determines whether the number of non-zero PVECs (i.e., PVECs whose PVEC summary bit is set) exceeds the capacity of the logical SFT entry to store that number of partial vectors. For example, if the SFT base entry can store a single partial vector and the SFT additional entry can store up to two partial vectors, then a single logical SFT entry can store up to three partial vectors. If operation 1128 determines that the number of non-zero PVECs exceeds the capacity of the logical SFT entry to record that number of PVECs, then control is transferred to the above... Figure 10 The Switch-To-IMPRECISE operation is publicly available.

[0065] However, if operation 1128 determines that the number of non-zero PVECs does not exceed the logical SFT entry's capacity to record that number of PVECs, then operation 1130 acquires additional entries, operation 1132 changes the tracking_mode of the underlying SFT entry to PVEC, and operation 1134 changes the entry_state of the underlying SFT entry to SEARCHABLE_E. Subsequently, in operation 1136, control is transferred to the following... Figure 12 The RecordPV operation is further disclosed in the document.

[0066] Figure 12 The diagram illustrates operation 1200 when an SFT entry is updated due to adding or removing an agent from its tracking_info field, and the SFT entry's tracking_mode is PVEC. Operation 1200 records one or more PVECs to the SFT entry. Starting with the complete tracking vector of the SFT entry, operation 1204 selects the PVECs whose PVEC summary bit is set. Operation 1206 records the number of PVECs in the tracking_info.PVS subfield of the base entry (e.g., ...). Figure 7 The publicly disclosed PVS or PVEC pointer (706) is used, and operation 1208 records the PVEC in the tracking_info.PVECTOR subfield of the underlying entry (such as...). Figure 7In the publicly available PVECTOR 704.

[0067] Operation 1210 determines whether any other PVECs have their PVEC summary bit set. If no such PVEC exists, operation 1200 ends. If an additional PVEC has its PVEC summary bit set, operation 1212 selects the other PVEC with its PVEC summary bit set, and operation 1214 selects the available tracking_info_E field in the additional SFT entry (such as the one mentioned above). Figure 8 The publicly disclosed tracking_info_E0 field 802), operation 1218 records the number of PVECs in the tracking_info_E.PVS subfield (such as...). Figure 8 The PVS or PVEC pointer disclosed in 806 is used, and operation 1220 records the PVEC in the tracking_info_E.PVECTOR subfield of the additional SET entry (such as...). Figure 8 In the publicly disclosed PVECTOR804), operation 1222 then sets the tracking_info_E.PVLD subfield bit to 1 (such as...). Figure 8 The tracking_info_E.PVLD subfield 808 is disclosed in the documentation, and the control loop returns to the deterministic operation 1210 to check if there is another PVEC that needs to be recorded.

[0068] Figure 13 The illustration depicts operation 1300 when the tracking_mode of an SFT entry is PVEC and the SFT needs to add an agent to its tracking of that SFT entry. Operation 1304 forms a complete tracking vector, operation 1306 determines the complete tracking vector bit positions for the new agent, and operation 1308 sets the tracking vector bits of the new agent in the complete tracking vector. Operation 1310 divides the complete tracking vector into p PVECs. For example, in the illustrated implementation, p=4. Operation 1312 performs a PVEC reduction OR to form a single summary bit (PVEC summary bit) for each PVEC, where the summary bit indicates whether any bits of the PVEC are set.

[0069] Operation 1314 determines whether the number of PVEC summary bits set exceeds the logical SFT entry's capacity to store that number of PVECs. If so, operation 1316 determines whether the logical SFT entry has additional SFT entries. If so, operation 1318 sets the entry_state of the additional SFT entries to IDLE. In operation 1320, control is transferred to the above... Figure 10 The Switch-To-IMPRECISE operation is publicly available.

[0070] If operation 1314 determines that the number of PVEC summary bits set does not exceed the logical SFT entry's capacity to store that number of PVECs, then operation 1322 sets the tracking_mode of the base SFT entry to PVEC. Subsequently, operation 1324 determines whether the logical SFT entry already has additional SFT entries or only the single PVEC summary bit set. If so, control is transferred in operation 1330 to the above... Figure 12 The RecordPV operation is disclosed in the documentation. If operation 1324 determines that the SFT entry does not yet have additional SFT entries, and if more than one PVEC summary bit is set, then operation 1326 obtains the additional entries to be used for the logical SFT entry, operation 1328 changes the entry_state of the base entry to SEARCHABLE_E, and control is transferred to the above in operation 1330. Figure 12 The RecordPV operation is publicly available.

[0071] Figure 14 The diagram illustrates operation 1400, which forms the complete tracking vector for an SFT entry when the SFT updates the SFT entry by adding or removing an agent from the SFT entry's tracking_info and the SFT entry's tracking_mode is PVEC. Operation 1400 can be performed when the SFT entry's tracking_mode is set to PVEC and the SFT needs to form a complete tracking vector for the SFT entry, because it needs to add an agent to the agent tracking of the SFT entry, remove an agent from the agent tracking of the SFT entry, or send a listener.

[0072] Operation 1402 initializes the complete tracking vector by clearing all its bits, and operation 1404 uses the tracking_info.PVS subfield of the SFT base entry to guide the bits of the partial vector contained in the tracking_info.PVECTOR subfield to their equivalent bit positions in the complete tracking vector, and sets these bits in the complete tracking vector. Operation 1406 determines the entry_state of the logical SFT entry. If the entry_state of the SFT entry is SEARCHABLE, indicating that it has no additional entries, operation 1400 terminates.

[0073] If the entry_state of the SFT entry is SEARCHABLE_E, then operation 1408 selects the tracking_info_E field whose PVLD subfield is 1 from the additional entries of the logical SFT entry. Operation 1410 uses the tracking_info_E.PVS subfield to guide the PVEC bits contained in the tracking_info_E.PVECTOR subfield to the equivalent bit positions in the full tracking vector, and sets these bits in the full tracking vector. Operation 1412 determines whether there is another tracking_info_E field whose PVLD subfield is set. If so, control is transferred back to operation 1408; otherwise, operation 1400 terminates.

[0074] Figure 15 The diagram illustrates operation 1500 when an existing logical SFT entry needs to be updated to remove an agent from its tracking, such as when it is known that the agent has abandoned its cogran copy. Operation 1502 determines the tracking_mode of the SFT entry. If the tracking_mode is AID, operation 1504 determines the complete tracking vector bit position of the agent, operation 1506 encodes the agent's tracking vector bits to form its AID, and operation 1508 determines whether the underlying SFT entry has only a single valid AID remaining. If the AID to be removed is the only remaining AID in the underlying SFT entry, operation 1510 sets the entry_state of the underlying SFT entry to IDLE. Otherwise, operation 1512 removes the AID from the underlying SFT entry. Here, removing the AID means selecting the AID subfield of tracking_info whose value matches the agent's AID and clearing the corresponding VLD bit of that AID subfield.

[0075] If operation 1502 determines that the tracking_mode of the SFT entry is IMPRECISE, then operation 1514 removes the agent from imprecise tracking of the SFT as needed. If operation 1502 determines that the tracking_mode of the SFT entry is PVEC, then control is transferred to the following... Figure 16 The removeAgent_PVmode operation is publicly available.

[0076] Figure 16 The diagram illustrates operation 1600 when the tracking_mode of an SFT entry is PVEC and the SFT needs to remove the agent from its tracking of that SFT entry. Operation 1602 forms the complete tracking vector (as shown above). Figure 14(As disclosed in the document), operation 1604 determines the bit position of the agent in the complete tracking vector, and operation 1606 clears the tracking vector bits of the agent in the location tracking vector, and operation 1608 divides the complete tracking vector into p PVECs. Subsequently, operation 1610 performs a reduction OR operation on each PVEC to form a single PVEC summary bit for each PVEC, wherein the PVEC summary bit indicates whether any bit of the PVEC is set.

[0077] Operation 1612 determines the number of PVEC summary bits set. If no partial vector summary bits are set, the SFT entry no longer needs to track cogran, so operation 1614 sets the entry_state of the underlying SFT entry to IDLE. Operation 1616 determines whether the underlying SFT entry is using additional SFT entries. If so, operation 1618 sets the entry_state of the additional SFT entry to IDLE.

[0078] If operation 1612 determines that the number of PVEC summary bits set is exactly 1, then operation 1620 determines whether the entry_state of the underlying SFT entry is SEARCHABLE_E. If not, control is transferred to the above. Figure 12 The RecordPV operation is further disclosed in the documentation. However, if the entry_state of the underlying SFT entry is SEARCHABLE_E, then no additional entry is needed. In this case, operation 1622 sets the entry_state of the additional SFT entry to IDLE, operation 1624 sets the entry_state of the underlying SFT entry to SEARCHABLE, and control is transferred to the entry above. Figure 12 The RecordPV operation is further disclosed in the documentation. The illustrated example has a single PVEC field in the underlying SFT entry, with the PVEC summary bit set to 1. However, in alternative implementations with smaller PVEC values, more than one PVEC can be recorded in the underlying SFT entry. In this case, the above operation can use different values ​​of the PVEC summary bit to make one or more decisions.

[0079] On the other hand, if operation 1612 determines that the number of PVEC summary bits set is greater than 1, then control is transferred to the above. Figure 12 The RecordPV operation is further disclosed in the document.

[0080] Figure 17The diagram illustrates the whomToSnoop operation 1700 when cogran is accessed and an SFT lookup is performed to determine whether listening is necessary. Operation 1700 is used to determine which brokers need or may need to be listened to in order to maintain cache consistency. If the lookup does not find an SFT entry tracking cogran (i.e., an SFT miss), then listening is not required. If the lookup finds an SFT entry tracking cogran (i.e., an SFT hit), then SFT performs operation 1700 to determine the set of brokers that need or may need to be listened to.

[0081] Operation 1702 determines the tracking_mode of the SFT entry. If the tracking_mode is IMPRECISE, operation 1704 generates listeners for all agents indicated by the imprecise tracking. If the tracking_mode is AID, operation 1706 initializes the full tracking vector to all zeros, operation 1708 decodes the currently stored valid AID of the SFT entry to find its equivalent full tracking vector bit positions, sets these bits in the full tracking vector, and operation 1710 sends listeners for all agents whose full tracking vector bits are set. If the tracking_mode is PVEC, operation 1712 forms the full tracking vector (as described above). Figure 14 (as disclosed in the document), and Operation 1710 sends a listener to all agents that have set the full tracking vector bits.

[0082] Figure 18 The illustration shows operation 1800, which occurs when a broker might request exclusive access to the cogran, invalidating all other cached copies, for example, allowing the broker to update its cogran copy in a way that maintains cache consistency. Specifically, operation 1800 can be used when the SFT has already tracked the cogran when the broker requests exclusive access. Operation 1802 can be used... Figure 17 The whomToSnoop operation 1700 sends snooping requests to each Cogran from the cache of all Cogran's proxies.

[0083] Operation 1804 determines the complete tracking vector bit position of the agent, and operation 1806 encodes the complete tracking vector bit position of the agent to form an AID identifying the agent. Operation 1808 selects an available tracking_info AID subfield, operation 1810 sets the tracking_info.AID(i) subfield to the agent's AID, and operation 1812 sets the tracking_info.VLD(i) subfield to 1. Operation 1814 sets the tracking_mode of the underlying SFT entry to the AID, and operation 1816 sets the entry_state of the underlying SFT entry to SEARCHABLE. Operation 1818 determines whether the SFT entry currently has an additional SFT entry. If so, operation 1820 sets the entry_state of the additional SFT entry to IDLE.

[0084] The cache coherence system disclosed herein offers significant efficiency in the use of SFT. For example, for the implementation disclosed herein with 128 agents that need to be traced by a listener filter and can split the vector into 4 partial vectors, the SFT described herein is fifty (50)% smaller than the prior art SFT that carries the full trace vector in each SFT entry, and eleven (11)% smaller than the alternative SFT that carries a partial full trace vector in the base entry and the remaining full trace vector in the additional entries. The technique disclosed herein offers the advantage of reduced SFT entry bit count when the data center scheduling SW can achieve the goal of assigning CPU cores to virtual machines (VMs) in a way that makes the CPUs of virtual machines (VMs) physically close to each other. In addition, the technique disclosed herein offers an advantage over the prior art in accurately tracing all cogran-shared agent agents that a VM has when it is included in a single CPU cluster.

[85] One implementation discloses a method comprising: generating a complete tracking vector, wherein each bit of the complete tracking vector indicates the cache validity state of a cogran in a proxy cache for a related agent; dividing the tracking vector into multiple partial vectors (PVECs); for each PVEC, determining whether the cache validity state of at least one bit in the PVEC is set to valid; and in response to determining that the cache validity state of at least one bit in a given PVEC is set to valid, storing the given PVEC and its PVEC pointer in a tracking_info field of a base listener filter (SFT) entry for the cogran, wherein the PVEC pointer indicates the position of the given PVEC in the complete tracking vector.

[86] Figure 19The illustration shows an example system 1900 that can be used to implement the cache coherence system disclosed herein. This is for implementing the described techniques. Figure 19 Example hardware and operating environments include computing devices such as computers 20, mobile phones, personal data assistants (PDAs), tablet computers, smartwatches, game controllers, or other types of general-purpose computing devices. Figure 19 In some implementations, computer 20 includes a processing unit 21, system memory 22, and a system bus 23, which operably couples various system components, including the system memory 22, to the processing unit 21. There may be only one or more processing units 21, such that the processor of computer 20 includes a single central processing unit (CPU) or multiple processing units, commonly referred to as a parallel processing environment. Computer 20 can be a conventional computer, a distributed computer, or any other type of computer; however, the implementation is not limited thereto.

[87] System bus 23 can be any of several types of bus architectures, including memory buses or memory controllers using any of the various bus architectures, peripheral buses, switching structures, point-to-point connections, and local buses. System memory 22 can also be simply referred to as memory and includes read-only memory (ROM) 24 and random access memory (RAM) 25. Basic input / output system (BIOS) 26, containing basic routines that facilitate the transfer of information between components within computer 20 during startup, is stored in ROM 24. Computer 20 also includes: hard disk drive 27 for reading and writing to a hard disk (not shown); disk drive 28 for reading or writing to a removable disk 29; and optical disk drive 30 for reading or writing to a removable optical disk 31, such as a CD ROM, DVD, or other optical media.

[88] Computer 20 can be used to implement the cache coherence system disclosed herein. In one implementation, a frequency unwrapping module (including instructions for unwrapping frequencies based at least in part on the sampled reflection modulation signal) can be stored in the memory of computer 20, such as read-only memory (ROM) 24 and random access memory (RAM) 25.

[89] Furthermore, the instructions stored in the memory of the computer 20 can be used to... Figures 9 to 18 One or more operations disclosed in the document are used to generate the transformation matrix. Similarly, instructions stored in the memory of computer 20 can also be used to implement... Figures 9 to 18 One or more operations. The memory of computer 20 may also be one or more instructions to implement the cache coherence system disclosed herein.

[90] Hard disk drive 27, disk drive 28, and optical disk drive 30 are connected to system bus 23 via hard disk drive interface 32, disk drive interface 33, and optical disk drive interface 34, respectively. The drives and their associated tangible computer-readable media provide non-volatile storage for computer-readable instructions, data structures, program modules, and other data to computer 20. Those skilled in the art will understand that any type of tangible computer-readable media can be used in the example operating environment.

[91] Many program modules may be stored on a hard disk, disk 29, optical disk 31, ROM 24, or RAM 25, including an operating system 35, one or more applications 36, other program modules 37, and program data 38. Users can generate prompts on the personal computer 20 through input devices such as a keyboard 40 and pointing device 42. Other input devices (not shown) may include a microphone (e.g., for voice input), a camera (e.g., for a Natural User Interface (NUI)), a joystick, a game controller, a satellite dish, a scanner, etc. These and other input devices are typically connected to the processing unit 21 via a serial port interface 46 coupled to the system bus 23, but may be connected via other interfaces such as a parallel port, a game port, or a universal serial bus (USB). A monitor 47 or other types of display devices are also connected to the system bus 23 via an interface such as a video adapter 48. In addition to the monitor, the computer typically includes other peripheral output devices (not shown), such as speakers and printers.

[92] Computer 20 may operate in a networked environment using logical connections to one or more remote computers, such as remote computer 49. These logical connections are implemented through communication devices coupled to or part of computer 20; these implementations are not limited to a particular type of communication device. Remote computer 49 may be another computer, server, router, network PC, client, peer device, or other common network node, and typically includes many or all of the elements described above with respect to computer 20. Figure 19 The logical connections described include local area networks (LAN) 51 and wide area networks (WAN) 52. This networking environment is common in office networks, enterprise-wide computer networks, intranets, and the Internet, which are all types of networks.

[93] When used in a LAN networking environment, computer 20 is connected to local area network 51 via a network interface or adapter 53, which is a communication device. When used in a WAN networking environment, computer 20 typically includes a modem 54, a network adapter, a communication device, or any other type of communication device for establishing communication over wide area network 52. The modem 54, which may be internal or external, is connected to system bus 23 via serial port interface 46. In a networking environment, the program engine depicted relative to personal computer 20 or a portion thereof may be stored in a remote memory storage device. It should be understood that the network connection shown is an example, and other methods of communication devices for establishing communication links between computers may be used.

[94] In the example implementation, software or firmware instructions for the cache coherence system 1910 may be stored in system memory 22 and / or storage device 29 or 31 and processed by processing unit 21. Cache coherence system operations and data may be stored in system memory 22 and / or storage device 29 or 31 as a persistent data repository.

[95] In contrast to tangible computer-readable storage media, intangible computer-readable communication signals can implement computer-readable instructions, data structures, program modules, or other data residing in modulated data signals, such as carrier waves or other signal transmission mechanisms. The term “modulated data signal” refers to a signal whose one or more characteristics are set or altered in a manner that encodes information in the signal. By way of example and not limitation, intangible communication signals include wired media (such as wired networks or direct wired connections) and wireless media (such as acoustic, RF, infrared, and other wireless media).

[96] Some embodiments of a cache coherence system may include an article of manufacture. The article of manufacture may include a tangible storage medium for storing logic. Examples of storage media may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. Examples of logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application programming interfaces (APIs), instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. In one embodiment, for example, the article of manufacture may store executable computer program instructions that, when executed by a computer, cause the computer to perform methods and / or operations according to the described embodiments. Executable computer program instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Executable computer program instructions can be implemented according to predefined computer languages, methods, or syntaxes to instruct the computer to perform specific functions. Instructions can be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[97] The cache coherence system disclosed herein may include a variety of tangible computer-readable storage media and intangible computer-readable communication signals. Tangible computer-readable storage devices may be implemented by any available medium accessible by the cache coherence system disclosed herein, and include volatile and non-volatile storage media, removable and non-removable storage media. Tangible computer-readable storage media do not include intangible and transient communication signals, and include volatile and non-volatile, removable and non-removable storage media implemented by any method or technique for storing information such as computer-readable instructions, data structures, program modules or other data. Tangible computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CDROM, digital universal disc (DVD) or other optical disc storage devices, magnetic cartridges, magnetic tape, disk storage devices or other magnetic storage devices, or any other tangible medium that may be used to store desired information and is accessible by the cache coherence system disclosed herein. In contrast to tangible computer-readable storage media, intangible computer-readable communication signals may implement computer-readable instructions, data structures, program modules or other data residing in modulated data signals, such as carrier waves or other signal transmission mechanisms. The term "modulated data signal" refers to a signal whose one or more characteristics are set or altered in a way that encodes information in the signal. By way of example, and not limitation, intangible communication signals include signals that move through wired media (such as wired networks or direct wired connections) and signals that move through wireless media (such as acoustic, RF, infrared, and other wireless media).

[98] The system disclosed herein includes a memory, one or more processor units, and a cache coherence system stored in the memory and executable by one or more processor units. The cache coherence system encodes computer-executable instructions on the memory to perform a computer process on one or more processor units, the computer process including: generating a complete tracking vector, wherein each bit of the complete tracking vector indicates the cache validity state of a coherence granule (cogran) in a proxy cache for a related agent; dividing the tracking vector into multiple partial vectors (PVECs); for each PVEC, determining whether the cache validity state of at least one bit in the PVEC is set to valid; and in response to determining that the cache validity state of at least one bit in a given PVEC is set to valid, storing the given PVEC and its PVEC pointer in a tracking_info field for a base listener filter (SFT) entry for the cogran, wherein the PVEC pointer indicates the position of the given PVEC in the complete tracking vector. Alternative implementations disclose one or more physically manufactured computer-readable storage media that encode computer-executable instructions to execute a computer process on a computer system, the computer process comprising: generating a complete tracking vector, wherein each bit of the complete tracking vector indicates the cache validity state of a cogran in a proxy cache for a relevant agent; dividing the tracking vector into multiple partial vectors (PVECs); for each PVEC, determining whether the cache validity state of at least one bit in the PVEC is set to valid; and in response to determining that the cache validity state of at least one bit in a given PVEC is set to valid, storing the given PVEC and its PVEC pointer in a tracking_info field of a base listener filter (SFT) entry for the cogran, wherein the PVEC pointer indicates the position of the given PVEC in the complete tracking vector. The implementations described herein are implemented as logical steps in one or more computer systems. Logical operations can be implemented as (1) a processor-implemented sequence of steps executed in one or more computer systems and (2) interconnected machines or circuit modules within one or more computer systems. The choice of implementation depends on the performance requirements of the computer system used. Therefore, the logical operations constituting the implementations described herein are referred to differently as operations, steps, objects, or modules. Furthermore, it should be understood that logical operations can be performed in any order unless otherwise expressly claimed or the language of the claims inherently requires a specific order. The foregoing specification, examples, and data, along with the appendix, provide a complete description of the structure and use of exemplary implementations.

Claims

1. A method comprising: Generate a complete trace vector (302-306), wherein each bit of the complete trace vector indicates the cache validity status of the cogran in the agent cache for the relevant agent; The tracking vector is divided into multiple partial vectors (PVEC) (310-314). For each PVEC (310-314), determine whether the cache validity state of at least one bit in the PVEC (310-314) is set to valid; as well as In response to determining that the cache validity state of at least one bit in a given PVEC (310-314) is set to valid, the given PVEC and its PVEC pointer (806) are stored in the tracking_info field of the base listener filter (SFT) entry for the cogran, and the summary bit associated with the PVEC vector is set to one (1), wherein the PVEC pointer (806) indicates the position of the given PVEC in the complete tracking vector.

2. The method of claim 1 further includes changing the tracking_mode of the underlying SFT entry to PVEC.

3. The method according to claim 1, wherein dividing the complete tracking vector into multiple PVECs further includes dividing the complete tracking vector into four PVECs.

4. The method according to claim 1, further comprising: More than one PVEC that determines the complete tracking vector has at least one bit set to valid; as well as In response to determining that more than one partial vector of the complete tracking vector has at least one bit set to valid, Obtain available SFT entries as additional SFT entries, and The additional PVEC and its pointer are stored in the tracking_info field of the additional SFT entry.

5. The method of claim 4, further comprising changing the entry_state of the base SFT entry to SEARCHABLE_E, and changing the entry_state of the additional SFT entry to EXTRA.

6. The method according to claim 1, further comprising: It was determined that the additional SFT entries could not store any more PVEC; as well as In response to determining that the additional SFT entry cannot store any more PVEC, the tracking_mode of the underlying SFT entry is changed to IMPRECISE.

7. The method of claim 1, further comprising setting the entry_state of the underlying SFT entry to SEARCHABLE_E in response to determining that more than one PVEC has a PVEC summary bit set to one.

8. The method of claim 1, wherein the complete tracing vector tracks 128 agents, and each PVEC has 32 bits.

9. One or more physically manufactured computer-readable storage media, said computer-readable storage media encoding computer-executable instructions for performing a computer process on a computer system (1900), said computer process comprising: Generate a complete trace vector (302-306), wherein each bit of the complete trace vector indicates the cache validity status of the cogran in the agent cache for the relevant agent; The tracking vector is divided into multiple partial vectors (PVEC) (310-314). For each PVEC (310-314), determine whether the cache validity state of at least one bit in the PVEC (310-314) is set to valid; as well as In response to determining that the cache validity state of at least one bit in a given PVEC (310-314) is set to valid, the given PVEC and its PVEC pointer (806) are stored in the tracking_info field of the base listener filter (SFT) entry for the cogran, and the summary bit associated with the PVEC vector is set to one (1), wherein the PVEC pointer (806) indicates the position of the given PVEC in the complete tracking vector.

10. The computer-readable storage medium of one or more physically manufactured items according to claim 9, wherein the computer process further comprises changing the tracking_mode of the underlying SFT entry to PVEC.

11. The computer-readable storage medium of one or more physically manufactured components according to claim 9, wherein dividing the complete tracking vector into a plurality of PVECs further comprises dividing the complete tracking vector into four PVECs.

12. The computer-readable storage medium of one or more physically manufactured methods according to claim 9, wherein the computer process further comprises: More than one PVEC that determines the complete tracking vector has at least one bit set to valid; as well as In response to determining that more than one partial vector of the complete tracking vector has at least one bit set to valid, Obtain available SFT entries as additional SFT entries, and The additional PVEC and its pointer are stored in the tracking_info field of the additional SFT entry.

13. The computer-readable storage medium of one or more physically manufactured items according to claim 12, wherein the computer process further comprises changing the entry_state of the base SFT entry to SEARCHABLE_E and changing the entry_state of the additional SFT entry to EXTRA.

14. The computer-readable storage medium of one or more physically manufactured methods according to claim 9, wherein the computer process further comprises: It was determined that the additional SFT entries could not store any more PVEC; as well as In response to determining that the additional SFT entry cannot store any more PVEC, the tracking_mode of the underlying SFT entry is changed to IMPRECISE.

15. The computer-readable storage medium of one or more physically manufactured items according to claim 9, wherein the computer process further comprises setting the entry_state of the underlying SFT entry to SEARCHABLE_E in response to determining that more than one PVEC has a PVEC summary bit set to one.

16. A system (1900) comprising: Memory; One or more processor units; as well as A cache coherence system (1900) (1910) (100), wherein the cache coherence system (1900) (1910) (100) is stored in the memory and is executable by the one or more processor units, the cache coherence system (1900) (1910) (100) encoding computer-executable instructions on the memory for executing computer processes on the one or more processor units, the computer processes including: Generate a complete trace vector (302-306), wherein each bit of the complete trace vector indicates the cache validity status of the cogran in the agent cache for the relevant agent; The tracking vector is divided into multiple partial vectors (PVEC) (310-314). For each PVEC (310-314), determine whether the cache validity state of at least one bit in the PVEC (310-314) is set to valid; as well as In response to determining that the cache validity state of at least one bit in a given PVEC (310-314) is set to valid, the given PVEC and its PVEC pointer (806) are stored in the tracking_info field of the base listener filter (SFT) entry for the cogran, and the summary bit associated with the PVEC vector is set to one (1), wherein the PVEC pointer (806) indicates the position of the given PVEC in the complete tracking vector.

17. The system of claim 16, wherein the computer process further includes changing the tracking_mode of the underlying SFT entry to PVEC.

18. The system of claim 16, wherein dividing the complete tracking vector into multiple PVECs further comprises dividing the complete tracking vector into four PVECs.

19. The system of claim 18, wherein the computer process further comprises: More than one PVEC that determines the complete tracking vector has at least one bit set to valid; as well as In response to determining that more than one partial vector of the complete tracking vector has at least one bit set to valid, Obtain available SFT entries as additional SFT entries, and The additional PVEC and its pointer are stored in the tracking_info field of the additional SFT entry.

20. The system of claim 16, wherein the computer process further includes storing the one or more PVECs in the base entry in response to determining that the cache validity state of one or more PVECs in the PVECs is set to valid.

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