High-speed and region-efficient parallel read-write memory

Abstract

A memory is provided with a pair of banks including a first location unit and a second location unit. An I / O circuit for the pair of banks includes a common write path configured to couple a write driver input signal to the first location cell in response to establishment of a write enable signal for the first location cell, and couple the write driver input signal to the second location cell in response to assertion of a write enable signal for the second location cell. The I / O circuit also includes a common read path configured to couple a data bit output signal from the first location cell to a sense amplifier in response to de-assertion of the write enable signal for the first location cell, and couple a data bit output signal from the second location cell to the sense amplifier in response to de-assertion of the write enable signal for the second location cell. The common read path and the common write path are further configured to operate concurrently such that a read operation on one of the libraries may occur concurrently with a write operation on the other of the libraries.

Description

Technical Field

[0001] This application relates to integrated circuit memories, and more specifically to an integrated circuit memory having parallel write and read operations. Background Technology

[0002] Integrated circuit memories (such as static random access memory (SRAM)) consist of bit cells arranged in rows and columns. Each row is traversed by a corresponding word line. As the number of bit cells increases, it is effective to arrange the bit cells into libraries such that each library has its own row and corresponding word line. Each library will generally have its own input / output (I / O) circuitry, which includes read paths and write paths to the bit cells of that library. Summary of the Invention

[0003] According to one aspect of this disclosure, a memory is provided, the memory comprising: a first storage location unit arranged in rows and columns; a first storage column multiplexer configured to select columns from the first storage location unit; a second storage location unit arranged in rows and columns; a second storage column multiplexer configured to select columns from the second storage location unit; and input / output circuitry including a common read path coupled to the first and second storage column multiplexers, and a common write path coupled to the first and second storage column multiplexers.

[0004] According to another aspect of this disclosure, an operating method for a memory is provided, the method comprising: coupling a first data input signal via a common write path to form a first write driver input signal at a first data input terminal, the first data input terminal being shared by a first library column multiplexer of a first library unit and a second library column multiplexer of a second library unit; coupling the first write driver input signal via the first library column multiplexer to write to the first library unit during a first write operation in response to the establishment of a write enable signal for the first library unit; coupling a second data input signal via the common write path to form a second write driver input signal at the first data input terminal; and coupling the second write driver input signal via the second library column multiplexer to write to the second library unit during a second write operation in response to the establishment of a write enable signal for the second library unit.

[0005] According to another aspect of this disclosure, a memory is provided, comprising: a first storage location unit; a second storage location unit; and a common write path configured to couple a write driver input signal to the first storage location unit in response to the establishment of a write enable signal for the first storage location unit, and to couple the write driver input signal to the second storage location unit in response to the establishment of a write enable signal for the second storage location unit.

[0006] These and other advantageous features can be better understood through the detailed description below. Attached Figure Description

[0007] Figure 1 An example of an SRAM according to one aspect of the present disclosure is provided, comprising a pair of libraries accessed via a common I / O circuit, the common I / O circuit including a common read path and a common write path for the libraries.

[0008] Figure 2 An I / O portion of an SRAM according to one aspect of this disclosure is illustrated.

[0009] Figure 3 An example bit cell for SRAM according to one aspect of this disclosure is illustrated.

[0010] Figure 4 This is a flowchart of a method for operating a memory according to one aspect of this disclosure, wherein two libraries share a write path.

[0011] Figure 5 Examples of electronic systems according to one aspect of this disclosure include an integrated circuit having a memory having a pair of libraries and a common I / O circuit.

[0012] The specific embodiments of this disclosure and its advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. Detailed Implementation

[0013] SRAM can be designed so that all its bit cells form a single library / array arranged in rows and columns. Corresponding word lines pass through each row, and corresponding bit line pairs pass through each column. However, as the number of bit cells in the array increases, the row length and column length increase accordingly. The resulting word lines and bit lines can then have excessive capacitance, reducing memory speed. Therefore, bit cells are generally arranged in libraries. Each library has its own rows and columns. Word lines used for one library are not shared by another. In this way, SRAM can include a relatively large number of bit cells without the word lines and bit lines becoming excessively long.

[0014] While dividing bit cells into libraries is highly advantageous for reducing word line and bit line lengths, each library typically then has its own supporting circuitry, such as input / output (I / O) circuitry for read and write paths to the bit cells of the library. A controller (often referred to as a global library controller) controls the I / O circuitry. In this way, parallel read or write operations to the library can occur. Read and write operations are considered to be in parallel with each other because they each occur within the same memory clock cycle. To allow this simultaneous operation, each I / O circuitry typically then requires its own corresponding die space on the semiconductor die for the integrated circuit that embeds the SRAM. To reduce the semiconductor die space occupied by the memory while retaining the speed advantage of individual (per library) I / O circuitry, an SRAM in which libraries are arranged in pairs is disclosed. For each pair of libraries, shared I / O circuitry provides a shared read path and a shared write path controlled by a controller (which may also be referred to as a global library controller).

[0015] The controller manages the shared read path and shared write path, allowing both to be active simultaneously for high-speed operation. As defined herein, read and write operations are considered simultaneous when they occur within the same memory clock cycle. The shared read and write paths to each pair of libraries, controlled by the shared controller, advantageously reduce the size of the corresponding memory (semiconductor die space) while maintaining high-speed operation through the ability to read the first library in a pair while simultaneously writing to the remaining second library in that pair.

[0016] exist Figure 1The diagram shows an example SRAM 100 with a pair of libraries 105 and 110. I / O circuitry 120 includes a common read path (discussed in more detail below) for reading from one of the libraries, and a common write path (also discussed in more detail below) for writing to the remaining library. Each library 105 and 110 includes an array of bit cells arranged in rows and columns. Example column 125 of bit cells is shown in the first library 105. Similarly, example row 140 of bit cells is shown in the second library 110. Each row of bit cells may store multiple interleaved words, with each row having its own corresponding word line. A corresponding column may then exist for each word. For example, suppose each row of bit cells stores even and odd numbers. Each library 105 and 110 may then have corresponding even columns for even numbers and odd columns for odd numbers. More generally, if each row of bit cells stores multiple interleaved words, each having N bits, then each library may include N columns for each interleaved word. However, it should be noted that the portion of the shared read path used to read a single bit of a word from one of the libraries will be similar to the remainder of the shared read path used for the remaining bits in the word. Similarly, the portion of the shared write path used to write a single bit of a word to one of the libraries will be similar to the remainder of the shared write path used for the remaining bits in the word.

[0017] Since this I / O structure 200 will be similar for all the remaining bits of the word, therefore in Figure 2 The image shows a more detailed view of a single I / O portion 200 of SRAM 100. I / O circuitry 120 is represented by a single I / O circuit 215, which includes circuitry for libraries 105 and 110 (…). Figure 1 The SRAM uses a shared I / O read path 201 and a shared I / O write path 202. During a write operation to the first library 105, the first library column multiplexer (first library col. mux) 225 selects the appropriate column depending on the type of word being written to the SRAM. Similarly, during a write operation to the second library 110, the second library column multiplexer 265 selects the appropriate column. Although each column multiplexer 225 and 265 is illustrated as being common to both the read and write paths, it will be understood that separate read and write column multiplexers can be implemented. The first library column multiplexer 225 can therefore be formed by combining a first library read column multiplexer (not illustrated) and a first library write column multiplexer (not illustrated). Similarly, the second library column multiplexer 265 can be formed by combining a second library read column multiplexer (not illustrated) and a second library write column multiplexer (not illustrated).

[0018] For clarity, a shared I / O read path 201 and a shared I / O write path 202 in an I / O input circuit 215 are used for only one input / output (I / O) bit. For example, if only even and odd numbers exist with respect to word interleaving, the first library column multiplexer 225 will select from the bit cells of a pair of odd and even columns. More generally, the first library column multiplexer 225 may select from multiple columns corresponding to multiple interleaved words. The column selected to form a single output bit can be represented as a first library bit cell array 205 for one I / O. Assume the word size is 64 bits. Therefore, the first library 105 will have 64 first library bit cell arrays 205 (each bit cell array 205 serves one I / O bit) and 64 corresponding first library column multiplexers 225. More generally, if the word size is N bits (N is a complex positive integer), then the first library 105 may have N first library bit arrays 205 and N corresponding first library column multiplexers 225, each for one I / O.

[0019] During a write operation to the second library 110, a second library cell array 210 for one I / O is similarly selected from the second library 110. Column multiplexers 225 and 265 also select the appropriate column in their respective libraries during read operations. Because of this shared read and write paths, I / O circuitry 120 can read from one library while simultaneously writing to another library.

[0020] During a write operation to the first library 105, the first library column multiplexer 225 couples the write driver input signal wdin from the data input terminal 270 to the bit line in the selected column of the first library cell array 205 (discussed further below). Additionally, during the write operation, the first library column multiplexer 225 couples the complementary write driver input signal wdin_n from the complementary data input terminal 275 to the complementary bit line in the selected column of the first library cell array 205 (also discussed further below). Note that both the data input terminal 270 and the complementary data input terminal 275 are shared by column multiplexers 225 and 265. If the write operation is changed to the second library 110, the second library column multiplexer 265 couples the write driver input signal wdin from the data input terminal 270 to the bit line in the selected column of the second library cell array 210, and couples the complementary write driver input signal to the complementary bit line in the selected column of the second library cell array 210.

[0021] During a read operation on the first library 105, the first library column multiplexer 225 couples a data bit output signal (q) from a bit line in a selected column of the first library cell array 205 for one I / O to a data bit output terminal 280 shared by the first library column multiplexer 225 and the second library multiplexer 265. The data bit output terminal 280 also serves as an input terminal for a sense amplifier 240 in a shared read path 201 for one I / O. The first library column multiplexer 225 also couples a complementary data bit output signal (qb) from a complementary bit line in a selected column of the first library cell array 205 for one I / O to a complementary data bit output terminal 285 shared by the first library column multiplexer 225 and the second library column multiplexer 265 during the read operation. The complementary data bit output terminal 285 also serves as a complementary input terminal to the sense amplifier 240. Therefore, the sense amplifier 240 can perform bit decisions in response to the q and qb signals during a read operation on the first library 105. If the read operation is changed to the second library 110, the second library column multiplexer 265 couples the q signal from the bit line in the selected column of the second library cell array 210 used for one I / O to the data bit output terminal 280, and also couples the qb signal from the complementary bit line in the selected column of the second library cell array 210 to the complementary data bit output terminal 285. Therefore, the sense amplifier 240 can also perform bit decisions in response to the q and qb signals during the read operation on the second library 110.

[0022] Each column multiplexer, 225 and 265, responds to the corresponding column address (not shown). See again Figure 1 The global library controller 145 can control which library is active for read or write operations in response to a pair of low-level activation chip select signals cs_n[1] and cs_n[0]. If the chip select signal cs_n[1] is established, the first library 105 is active for read or write operations. Similarly, in response to the establishment of the chip select signal cs_n[0], the second library 110 is selected for read or write operations. As defined herein, a binary signal is considered established when it has a binary truth value, regardless of whether a high-level activation convention or a low-level activation convention is used. Thus, a high-level activation signal is established by charging to the memory power supply voltage and de-established by discharging to ground. However, a low-level activation signal is established by discharging to ground and de-established by charging to the memory power supply voltage. It will be understood that the high-level activation chip select signal may be used in alternative embodiments.

[0023] When a library is selected by establishing its chip select signal, its function for write or read operations can be controlled by the corresponding write enable signal. For example, a low-level activation of the write enable signal we_n[1] can control the first library 105 to be active for write or read operations. Similarly, a low-level activation of the write enable signal we_n[0] can control the second library 110 to be active for write or read operations. If the write enable signal we_n[1] is established in conjunction with the chip select signal cs_n[1], the first library 105 is active for write operations. Conversely, if the write enable signal we_n[1] is de-established while the chip select signal cs_n[1] is established, the first library 105 is active for read operations. Similarly, in response to the establishment of the write enable signal we_n[0] and the chip select signal cs_n[0], the second library 110 is active for write operations. Conversely, in response to deactivating the write enable signal we_n[0] and simultaneously establishing the chip select signal cs_n[0], the second library 110 is activated for read operations. It will be understood that the high-level activation convention for the write enable signal can also be used in alternative implementations.

[0024] See you again Figure 2 When the first library 105 is selected for a write operation, the first library column multiplexer 225 couples the write driver input signals wdin and wdin_n to the selected column in the first library cell array 205. Conversely, if the write enable signal we_n[1] is not established while the first library chip selection signal cs_n[1] is established, the first library column multiplexer 225 couples the q and qb signals from the selected column to the sense amplifier 240. Similar to that discussed for the first library column multiplexer 225, the second library column multiplexer 265 is configured for either a write operation or a read operation.

[0025] Although column multiplexers 225 and 265 are shown separately from the common write path 202, it will be understood that in some embodiments, the column multiplexer for write-enabled libraries in a library can be considered as part of the common write path 202. Therefore, the common write path 202 can be considered as being configured to couple the write driver input signal wdin to the first library location 105 when the first library location 105 is selected for a write operation by the establishment of the write enable signal we_n[1] and the chip select signal cs_n[1], and to couple the write driver input signal wdin to the second library location 110 in response to the establishment of the write enable signal we_n[0] and the chip select signal cs_n[0]. Similarly, in some embodiments, the column multiplexer for read-enabled libraries in a library can be considered as part of the common read path 201. Therefore, the common read path 201 can be configured to couple the data bit output signal q of the selected column from the first storage unit 105 to the sense amplifier 240 in response to the de-establishment of the we_n[1] signal combined with the establishment of the chip selection signal cs_n[1], and to couple the data bit output signal q of the selected column from the second storage unit 110 to the sense amplifier 240 in response to the de-establishment of the we_n[0] signal combined with the establishment of the chip selection signal cs_n[0].

[0026] As noted earlier, the shared I / O write path 202 generates only the wdin and wdin_n signals for the selected column during a write operation. This is only one bit of the digital word written to SRAM 100. Therefore, the shared write path 101 in I / O circuitry 120 generates the wdin and wdin_n signals for each bit in the word written to the accessed library. Similarly, the shared I / O read path 201 receives only the q and qb signals from the selected column during a read operation. The shared read path 101 in I / O circuitry 120 receives the q and qb signals for each bit in the digital word read, and thus will include a shared I / O read path 201 for each bit. The shared I / O write path 202 will now be discussed in more detail, followed by the shared I / O read path 201.

[0027] A shared I / O write path 201 includes data input memory elements (e.g., flip-flops) and a level shifter 220 for level shifting and latching the input data signal (din). In this regard, the input data signal may be generated in a core power domain (not illustrated) powered by a core power supply voltage that may not be equal to the memory power supply voltage used for SRAM 100. Therefore, the level shifter 220 levels the input data signal from the core power domain to the memory to form a level-shifted data input signal (l_din). The level-shifted data input signal is passed through a buffer and redundancy circuitry 230. If a defective column exists in the library being written to, the buffer and redundancy circuitry 230 may receive a data input signal (din_prev) from the previous column in the column being written to, such that this din_prev signal can drive one bit of the shared write path 201. In this case, the level-shifted data input signal is passed to the subsequent column in the library as a data input signal (din_next). Assuming no defective columns exist, buffer and redundancy circuitry 230 delivers the level-shifted data input signal as a buffered data input signal (gdin) and its complement (gdin_n) to write driver 235. Write driver 235 responds to the buffered data input signal by driving the buffered data input signal gdin as the write driver data input signal wdin to a column multiplexer for the appropriate library. Similarly, write driver 235 responds to the complement by driving the complement of the buffered data input signal gdin_n as the complementary write driver input signal wdin_n to the same column multiplexer.

[0028] A shared I / O read path 201 begins by sensing signals q and qb via sense amplifier 240 in response to the establishment of a sense enable (SE) signal to generate a sense amplifier output signal, which can also be represented as a bit decision signal. Depending on whether a defective column exists in the library accessed during the read operation, data output redundancy shift circuit 245 can shift the shift amplifier output signal as a latch_dout_prev signal out of subsequent column data output redundancy shift circuits (not illustrated). Similarly, if a defective column exists in the accessed library, data output redundancy shift circuit 245 can shift the sense amplifier output signal from the previous column. Assuming no defective column exists, data output redundancy shift circuit 245 can pass the sense amplifier output signal to data output (dout) latch and level shifter circuit 250. Therefore, the latched data output signal from data output latch and level shifter circuit 250 is level-shifted from the memory power domain to the core power domain.

[0029] exist Figure 3The image shows an example bit cell 300 for SRAM 100. Bit cell 300 is a portion of a bit cell column (e.g., column 125) through which bit lines BL and complementary bit lines BLB pass. Additionally, bit cell 300 is a portion of a bit cell row (e.g., row 140) through which word lines WL pass. Bit cell 300 uses a pair of cross-coupled inverters 305 to latch bits. The output terminal of the first cross-coupled inverter in the cross-coupled inverters forms a q signal that will be sensed during a read operation. During a read operation, this can also be represented as a global library controller (GBC) 145 (…). Figure 1 The controller 145 establishes the word line voltage to turn on the access transistor M1 coupled between the node used for the q signal and the bit line BL. Similarly, the controller 145 establishes the word line voltage during a write operation, causing the write driver input signal wdin (which drives the bit line BL) to... Figure 2 The output terminal of the second cross-coupled inverter in the cross-coupled inverter forms the qb signal, which will also be sensed during a read operation. During a read operation, the established word line voltage turns on the access transistor M2 coupled between the node for the qb signal and the complementary bit line BL. Similarly, the controller 145 establishes the word line voltage during a write operation such that the complementary write driver input signal wdin_n driving the complementary bit line BLB causes the qb signal to have the desired binary value. Each inverter in the cross-coupled inverter pair 305 is formed by two transistors (not illustrated). Thus, bit cell 300 is a six-transistor (6T) bit cell, but it will be understood that simultaneous read and write operations on a pair of libraries via a shared read path and a shared write path, as disclosed herein, can be practiced by an SRAM having bit cells using more than six transistors. For example, a dual-port SRAM where each bit cell is an eight-transistor (8T) bit cell can advantageously utilize the shared read path and shared write path of this disclosure.

[0030] See you again Figure 1 The controller 145 controls the timing of read and write operations. For example, during a read operation, the controller 145 may establish a sense enable signal SE after a sufficient voltage difference has been developed on the bit line pairs for the selected column, and simultaneously release the word line voltage. To determine when a sufficient voltage difference has been developed on the bit line pairs during a write operation, the controller 145 may sense the voltage difference used for copying the write column 225 (…). Figure 2 The controller 145 establishes a dummy bit line voltage for the selected column. Once a voltage difference sufficient to be developed across the bit line pair for a successful write to the accessed bit cell has been established, the controller 145 can subsequently release the word line voltage establishment during a write operation. To determine when a sufficient voltage difference has been developed across the bit line pair during a read operation, the controller 145 can sense the dummy bit line voltage used to copy the read column 260 ( Figure 2 The dummy bit line voltage.

[0031] If the first library chip select signal cs_n[1] is established, the row decoder 145 for the first library 105 decodes the (n+1)-bit wide row address addr_b1[n:0] to select the word line to be established during a read or write operation for the first library 105, where n is a complex positive integer. Similarly, if the second library chip select signal cs_n[0] is established, the row decoder 150 for the second library 110 decodes the row address addr_b0[n:0] to select the word line to be established during a read or write operation for the second library 110.

[0032] Now about Figure 4 The flowchart discusses an operational method for a memory including a shared write path according to this disclosure. The method includes an action 400 of coupling a first data input signal via the shared write path to form a first write driver input signal at a first data input terminal, the first data input terminal being shared by a first library column multiplexer of a first library unit and a second library column multiplexer of a second library unit. Coupling a data input signal via a shared write path 202 to form a write driver input signal wdin at a data input terminal 270 is an example of action 400.

[0033] Furthermore, the method includes action 405, in response to the establishment of a write enable signal for the first library unit, coupling a first write driver input signal to the first library unit via a first library column multiplexer during a first write operation to write to the first library unit. An example of action 405 is coupling the write driver input signal wdin to a selected column in the first library unit 105 via the first library column multiplexer 225 in response to the establishment of a write enable signal we_n[1] during a write operation on the first library unit 105.

[0034] The method also includes an action 410 of coupling a second data input signal via a shared write path to form a second write driver input signal at a first data input terminal. An example of action 410 is coupling a data input signal via a shared write path 102 to form a write driver input signal wdin at a data input terminal 270 in response to the establishment of a write enable signal we_n[0] during a write operation to the second storage unit 110.

[0035] Finally, the method includes action 415, in response to the establishment of a write enable signal for the second library unit, coupling a second write driver input signal to the second library unit via a second library column multiplexer during a second write operation to write to the second library unit. An example of action 415 is coupling the write driver input signal wdin to a selected column in the second library unit 110 via the second library column multiplexer 265 during a write operation to the second library unit 110.

[0036] Integrated circuits including memories with the I / O circuits disclosed herein can be advantageously used in a wide variety of electronic systems. For example, such as Figure 5 As shown, a cellular phone 500, a laptop computer 505, and a tablet PC 510 may all include an integrated circuit having a memory according to the present disclosure. Other exemplary electronic systems (such as music players, video players, communication devices, and personal computers) may also be configured to have an integrated circuit having a memory constructed according to the present disclosure.

[0037] This disclosure will now be outlined in the following series of provisions: Clause 1. A memory comprising: The first storage unit is arranged in rows and columns; A first library column multiplexer is configured to select columns from the first library location unit; The second storage unit is arranged in rows and columns; A second column multiplexer is configured to select columns from the second location unit; and The input / output circuit includes a common read path coupled to the first library column multiplexer and the second library column multiplexer, and a common write path coupled to the first library column multiplexer and the second library column multiplexer.

[0038] Clause 2. The memory according to Clause 1, the memory further includes: A controller configured to control the timing of a first read operation on the first storage unit via the shared read path and to control the timing of a first write operation on the second storage unit via the shared write path, wherein the first read operation and the first write operation are performed simultaneously.

[0039] Clause 3. The memory according to Clause 2, wherein the controller is further configured to control the timing of a second read operation on the second storage unit via the shared read path and to control the timing of a second write operation on the first storage unit via the shared write path, wherein the second read operation and the second write operation are performed simultaneously.

[0040] Clause 4. The memory according to any one of Clauses 2 to 3, wherein the memory further comprises: First copy column; and The second replication column; wherein the controller is coupled to the first replication column and the second replication column.

[0041] Clause 5. The memory according to any one of Clauses 2 to 4, wherein the common read path includes: A sensing amplifier, wherein the controller is further configured to establish a sensing enable signal to the sensing amplifier.

[0042] Clause 6. The memory according to any one of Clauses 1 to 5, wherein the shared write path includes a write driver, and wherein a data input terminal shared by the first library column multiplexer and the second library column multiplexer is coupled to the write driver, and wherein a complementary data input terminal shared by the first library column multiplexer and the second library column multiplexer is also coupled to the write driver.

[0043] Clause 7. The memory according to any one of Clauses 1 to 6, wherein each column in the first library unit includes a corresponding bit line pair, and wherein the first library column multiplexer is coupled to a bit line in the corresponding bit line pair for the selected column in the first library unit and to a complementary bit line in the corresponding bit line pair.

[0044] Clause 8. The memory pursuant to Clause 6, wherein the shared write path further comprises: A level shifter configured to level-shift a data input signal in response to a memory power supply voltage for the memory, thereby forming a level-shifted data input signal.

[0045] Clause 9. The memory pursuant to Clause 8, wherein the shared write path further comprises: A buffer, configured to buffer the level-shifted data input signal to form a buffered data input signal and a complementary buffered data input signal.

[0046] Clause 10. The memory pursuant to Clause 9, wherein the shared write path further comprises: A write driver configured to drive the data input terminal using a write driver input signal in response to the buffered data input signal, and to drive the complementary data input terminal using a complementary write driver input signal in response to the complementary buffered data input signal.

[0047] Clause 11. The memory according to Clause 5, wherein the sense amplifier includes an input terminal coupled to a data bit output terminal shared by the first quorum multiplexer and the second quorum multiplexer, and includes a complementary input terminal coupled to a complementary data bit output terminal shared by the first quorum multiplexer and the second quorum multiplexer.

[0048] Clause 12. The memory according to Clause 11, wherein the common read path further includes a data output latch and a level shifter, the data output latch and the level shifter being configured to level shift a data output signal from the sense amplifier to form a level-shifted data output signal and latch the level-shifted data output signal to form a data output signal for the common read path.

[0049] Clause 13. The memory according to any one of Clauses 1 to 12, wherein each bit cell in the first storage unit and the second storage unit is a six-transistor bit cell.

[0050] Clause 14. The memory according to any one of Clauses 1 to 13, wherein the memory is integrated into a cellular phone.

[0051] Clause 15. A method of operating a memory, the method comprising: A first data input signal is coupled by a shared write path to form a first write driver input signal at a data input terminal, the data input terminal being shared by a first library column multiplexer of a first library unit and a second library column multiplexer of a second library unit; In response to the establishment of a write enable signal for the first storage unit, during the first write operation, the first write driver input signal is coupled through the first storage column multiplexer to write to the first storage unit. The second data input signal is coupled via the shared write path to form a second write driver input signal at the data input terminal; and In response to the establishment of a write enable signal for the second library unit, during the second write operation, the second write driver input signal is coupled through the second library column multiplexer to write to the second library unit.

[0052] Clause 16. The method described in Clause 15, further comprising: In response to the de-establishment of the write enable signal for the second library unit, during the first read operation, a first data bit output signal from the second library unit is coupled via the second library column multiplexer to a data bit output terminal shared by the first library column multiplexer and the second library column multiplexer; and During the first read operation, the first data bit output signal from the data bit output terminal is coupled to a sense amplifier in a common read path, wherein the first write operation is performed simultaneously with the first read operation.

[0053] Clause 17. The method described in Clause 16, further comprising: In response to the de-establishment of the write enable signal for the first storage unit, during the second read operation, a second data bit output signal from the first storage unit is coupled to the data bit output terminal via the first storage column multiplexer; and During the second read operation, the second data bit output signal from the data bit output terminal is coupled to the sense amplifier, wherein the second write operation is performed simultaneously with the second read operation.

[0054] Clause 18. The method described in Clause 15, further comprising: During the first write operation, a first complementary data input signal is coupled via the shared write path to form a first complementary write driver input signal at a first complementary data input terminal shared by the first library multiplexer and the second library multiplexer; and During the first write operation, the first complementary write driver input signal is coupled to the first library position cell via the first library column multiplexer.

[0055] Clause 19. The method described in Clause 16, further comprising: The second library column multiplexer couples the first complementary data bit output signal from the second library location unit during the first read operation to a complementary data output terminal shared by the first library column multiplexer and the second library column multiplexer; and During the first read operation, the first complementary data bit output signal from the complementary data output terminal is coupled to the sense amplifier.

[0056] Clause 20. A memory comprising: First storage unit; Second storage unit; and A shared write path is configured to couple a write driver input signal to the first storage location in response to the establishment of a write enable signal for the first storage location, and to couple the write driver input signal to the second storage location in response to the establishment of a write enable signal for the second storage location.

[0057] Clause 21. The memory according to Clause 20, further comprising: A shared read path is configured to couple data bit signals from the first storage unit to a sense amplifier in response to the de-establishment of the write enable signal for the first storage unit, and to couple data bit signals from the second storage unit to the sense amplifier in response to the de-establishment of the write enable signal for the second storage unit.

[0058] Clause 22. The memory according to Clause 21, the memory further includes: A controller configured to control the timing of a sensing enable signal to the sensing amplifier.

[0059] Clause 23. The memory according to Clause 20, wherein each bit cell in the first and second storage units is a six-transistor bit cell.

[0060] Clause 24. The memory according to any one of Clauses 20 to 23, wherein the memory is a static random access memory.

[0061] Clause 25. The memory according to Clause 21, wherein the common read path includes a data output latch configured to latch a bit decision signal from the sense amplifier to form a data output signal.

[0062] Clause 26. The memory according to Clause 25, wherein the data output latch further includes a level shifter configured to shift the level of the data output signal.

[0063] It should be understood that many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the equipment disclosed herein without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments illustrated and described herein (as they are merely examples), but should be fully equivalent to the appended claims and their functional equivalents.

Claims

1. A memory, the memory comprising: The first storage unit is arranged in rows and columns; A first library column multiplexer is configured to select columns from the first library location unit; The second storage unit is arranged in rows and columns; A second library column multiplexer is configured to select columns from the second library location unit; and The input / output circuit includes a common read path coupled to the first library column multiplexer and the second library column multiplexer, and a common write path coupled to the first library column multiplexer and the second library column multiplexer.

2. The memory according to claim 1, further comprising: A controller configured to control the timing of a first read operation on the first storage unit via the shared read path and to control the timing of a first write operation on the second storage unit via the shared write path, wherein the first read operation and the first write operation are performed simultaneously.

3. The memory according to claim 2, wherein the controller is further configured to control the timing of a second read operation on the second storage unit via the shared read path and to control the timing of a second write operation on the first storage unit via the shared write path, wherein the second read operation and the second write operation are performed simultaneously.

4. The memory according to claim 2, further comprising: First copy column; and Second copy column; The controller is coupled to the first replication column and the second replication column.

5. The memory according to claim 2, wherein the common read path includes: A sensing amplifier, wherein the controller is further configured to establish a sensing enable signal to the sensing amplifier.

6. The memory of claim 1, wherein the shared write path includes a write driver, and wherein a data input terminal shared by the first library column multiplexer and the second library column multiplexer is coupled to the write driver, and wherein a complementary data input terminal shared by the first library column multiplexer and the second library column multiplexer is also coupled to the write driver.

7. The memory of claim 1, wherein each column in the first library unit includes a corresponding bit line pair, and wherein the first library column multiplexer is coupled to a bit line in the corresponding bit line pair for the column selected in the first library unit and to a complementary bit line in the corresponding bit line pair.

8. The memory of claim 6, wherein the shared write path further comprises: A level shifter configured to level-shift a data input signal in response to a memory power supply voltage for the memory, thereby forming a level-shifted data input signal.

9. The memory of claim 8, wherein the shared write path further comprises: A buffer, configured to buffer the level-shifted data input signal to form a buffered data input signal and a complementary buffered data input signal.

10. The memory of claim 9, wherein the shared write path further comprises: A write driver configured to drive the data input terminal using a write driver input signal in response to the buffered data input signal, and to drive the complementary data input terminal using a complementary write driver input signal in response to the complementary buffered data input signal.

11. The memory of claim 5, wherein the sense amplifier includes an input terminal coupled to a data bit output terminal shared by the first coulomb multiplexer and the second coulomb multiplexer, and includes a complementary input terminal coupled to a complementary data bit output terminal shared by the first coulomb multiplexer and the second coulomb multiplexer.

12. The memory of claim 11, wherein the common read path further comprises a data output latch and a level shifter, the data output latch and the level shifter being configured to level-shift a data output signal from the sense amplifier to form a level-shifted data output signal and latch the level-shifted data output signal to form a data output signal for the common read path.

13. The memory of claim 1, wherein each bit cell in the first storage unit and the second storage unit is a six-transistor bit cell.

14. The memory of claim 1, wherein the memory is integrated into a cellular phone.

15. A method of operating a memory, the method comprising: A first data input signal is coupled by a shared write path to form a first write driver input signal at a data input terminal, the data input terminal being shared by a first library column multiplexer of a first library unit and a second library column multiplexer of a second library unit; In response to the establishment of a write enable signal for the first storage unit, during the first write operation, the first write driver input signal is coupled through the first storage column multiplexer to write to the first storage unit. The second data input signal is coupled through the common write path to form a second write driver input signal at the data input terminal; as well as In response to the establishment of a write enable signal for the second library unit, during the second write operation, the second write driver input signal is coupled through the second library column multiplexer to write to the second library unit.

16. The method according to claim 15, further comprising: In response to the de-establishment of the write enable signal for the second library unit, during the first read operation, a first data bit output signal from the second library unit is coupled to a data bit output terminal shared by the first library multiplexer and the second library multiplexer via the second library column multiplexer. as well as During the first read operation, the first data bit output signal from the data bit output terminal is coupled to a sense amplifier in a common read path, wherein the first write operation is performed simultaneously with the first read operation.

17. The method according to claim 16, further comprising: In response to the de-establishment of the write enable signal for the first storage unit, during the second read operation, a second data bit output signal from the first storage unit is coupled to the data bit output terminal via the first storage column multiplexer. as well as During the second read operation, the second data bit output signal from the data bit output terminal is coupled to the sense amplifier, wherein the second write operation is performed simultaneously with the second read operation.

18. The method according to claim 15, further comprising: During the first write operation, a first complementary data input signal is coupled through the shared write path to form a first complementary write driver input signal at a first complementary data input terminal shared by the first library multiplexer and the second library multiplexer; as well as During the first write operation, the first complementary write driver input signal is coupled to the first library position cell via the first library column multiplexer.

19. The method according to claim 16, further comprising: The second library column multiplexer couples the first complementary data bit output signal from the second library unit during the first read operation to the complementary data output terminal shared by the first library column multiplexer and the second library column multiplexer. as well as During the first read operation, the first complementary data bit output signal from the complementary data output terminal is coupled to the sense amplifier.

20. A memory, the memory comprising: First storage unit; Second storage unit; and A shared write path is configured to couple a write driver input signal to the first storage location in response to the establishment of a write enable signal for the first storage location, and to couple the write driver input signal to the second storage location in response to the establishment of a write enable signal for the second storage location.

21. The memory according to claim 20, further comprising: A shared read path is configured to couple data bit signals from the first storage unit to a sense amplifier in response to the de-establishment of the write enable signal for the first storage unit, and to couple data bit signals from the second storage unit to the sense amplifier in response to the de-establishment of the write enable signal for the second storage unit.

22. The memory according to claim 21, further comprising: A controller configured to control the timing of a sensing enable signal to the sensing amplifier.

23. The memory of claim 20, wherein each bit cell in the first storage unit and the second storage unit is a six-transistor bit cell.

24. The memory of claim 20, wherein the memory is a static random access memory.

25. The memory of claim 21, wherein the common read path includes a data output latch configured to latch a bit decision signal from the sense amplifier to form a data output signal.

26. The memory of claim 25, wherein the data output latch further comprises a level shifter configured to shift the level of the data output signal.

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