Substrate for epitaxial growth, method for manufacturing optical semiconductor element, and optical semiconductor element

Abstract

Provided is a substrate for epitaxial growth having a buffer laminate in which cracks do not occur even when a support substrate is bonded and a substrate for initial growth is removed. A substrate for epitaxial growth, which comprises a substrate for initial growth, an etch stop layer on the substrate for initial growth, and a buffer laminate on the etch stop layer, the buffer laminate having N buffer layers having lattice constants different from each other, and an analog substrate layer on the N buffer layers and having a thickness of 300 nm or more, when the lattice constant of the initial growth substrate is ag and the lattice constant of the analog substrate layer is ap, the degree of mismatch Xp.g of the analog substrate layer with respect to the initial growth substrate is 0.7% or more, N is a natural number of 3 or more, and p is a natural number of 3 or more. The substrate for epitaxial growth has three or more buffer layers containing mismatch dislocations on the initial growth substrate side of the buffer layers.

Description

Technical Field

[0001] This invention relates to a substrate for epitaxial growth, a method for manufacturing an optical semiconductor device, and the optical semiconductor device itself. Background Technology

[0002] Most optoelectronic semiconductor devices are manufactured through a process of epitaxially growing a semiconductor stack containing an active layer on an initial growth substrate. Here, the ratio Δa / a of the difference (Δa) between the lattice constant of the initial growth substrate and the epitaxial layer formed through epitaxial growth to the lattice constant a of the initial growth substrate is called the lattice mismatch. If the lattice mismatch is small, epitaxial growth can be performed without defects. Even if the lattice mismatch is large, if the epitaxial layer is thin enough, the lattice continuity at the interface can be maintained through lattice strain in the epitaxial layer (coherent growth). The upper limit of the film thickness that allows coherent growth even with a large lattice mismatch is called the critical film thickness.

[0003] The term "lattice-matched layer growth" generally refers to epitaxial growth of a layer with a lattice mismatch within ±0.1% and close to zero. In the case of lattice-mismatched layer growth, epitaxial growth is typically performed within the range of coherent layer growth with a lattice mismatch within ±0.3%. On the other hand, regarding the epitaxial growth of a layer on an initial growth substrate with a lattice mismatch greater than 0.3% relative to the lattice constant of the initial growth substrate, a method is known to perform the growth via a buffer layer on the initial growth substrate.

[0004] For example, Patent Document 1 proposes a buffer layer formed between a substrate and a light-absorbing layer, wherein the lattice constant of the buffer layer gradually changes from the lattice constant of the substrate to the lattice constant of the light-absorbing layer. Specifically, each layer of the buffer layer is formed to a thickness below a critical film thickness to suppress the generation of crystal defects.

[0005] Furthermore, in Patent Document 2, in order to mitigate the lattice mismatch between InP and the GaInAs absorber layer, it was proposed to incorporate InAs... X P 1-X / InAs Y P 1-Y A GaInAs absorber layer with a lattice mismatch rate of more than 0.5% is formed by multi-stage insertion of a combined strained superlattice layer onto a buffer.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2001-102620

[0009] Patent Document 2: Japanese Patent Application Publication No. 6-188447 Summary of the Invention

[0010] The problem the invention aims to solve

[0011] The inventors first developed the following technique: In the conventional case where an InP substrate is used as the initial growth substrate, it is not necessary to remove the transparent initial growth substrate. Directly utilizing the thick InP initial growth substrate is beneficial for improving light extraction. In the wavelength range of 1000nm to 1700nm (e.g., 1300nm), the InP initial growth substrate is intentionally removed and a support substrate is bonded, thereby improving luminous efficiency. Furthermore, research was conducted on whether this technique can be applied to optical semiconductor devices with wavelength regions exceeding 1700nm, and optical semiconductor devices with wavelength regions of other wavelength regions. In the case of optical semiconductor devices with wavelength regions exceeding 1700nm, such as optical semiconductor devices with wavelength regions of 2000 to 3000nm, it is not possible to select an initial growth substrate with a lattice constant close to that of the semiconductor stack containing the active layer required for that wavelength. Therefore, a layer with a large lattice mismatch relative to the initial growth substrate is epitaxially grown.

[0012] In methods for growing layers with large lattice mismatches on an initial growth substrate via a buffer layer, the strain-superlattice type buffer layer stacks described in Patent Documents 1 and 2 are formed while suppressing the generation of crystal defects (dislocations). Therefore, due to lattice mismatch with the initial growth substrate, warping occurs on the substrate, or even if warping does not occur when thinning, large stresses accumulate internally. When such internal stresses accumulate, the balance of internal stresses changes drastically when bonding the support substrate using the above-described technique or when removing the initial growth substrate, which may lead to cracks.

[0013] The object of the present invention is to provide an epitaxial growth substrate having a buffer laminate that does not produce cracks even when a support substrate is bonded and an initial growth substrate is removed, and to provide a method for manufacturing an optical semiconductor device by forming a semiconductor laminate including an active layer on such an epitaxial growth substrate and performing a support substrate bond and an initial growth substrate removal, as well as an optical semiconductor device.

[0014] Solution for solving the problem

[0015] The inventors discovered that when a simulated substrate layer with a mismatch of 0.7% or more relative to the initial growth substrate is provided on an initial growth substrate via multiple buffer layers, by fabricating an epitaxial growth substrate with buffer layers formed while generating specific dislocations without coherent growth in a relaxed state of the simulated substrate layer, it is possible to reduce the warpage when forming a semiconductor stack on the simulated substrate layer in the epitaxial growth substrate. This also helps to suppress cracking in the semiconductor stack formed on the simulated substrate layer during processes such as attaching a support substrate to the semiconductor stack and removing the initial growth substrate. Thus, the present invention is completed. Here, the relaxed state can be defined as a state in which the lattice strain in the horizontal and vertical directions caused by internal stress is small and the difference between them is within a specific range; the method for determining this state will be described later.

[0016] Specifically, the buffer stack in this invention is characterized by having N (or more) buffer layers, the lattice constant of the N buffer layers generally increasing from the buffer layer closest to the initial growth substrate to the buffer layer closest to the simulated substrate layer, and in N or more of the N buffer layers, the portions in contact with other layers with different lattice constants contain mismatch dislocations.

[0017] That is, the main structure of the present invention is as follows.

[0018] [1] A substrate for epitaxial growth, comprising:

[0019] Initial growth substrate,

[0020] The etch stop layer on the aforementioned initial growth substrate, and

[0021] The buffer stack on the aforementioned etch stop layer,

[0022] The aforementioned buffer stack comprises: N buffer layers with different lattice constants, and a simulated substrate layer with a thickness of 300 nm or more on the N buffer layers.

[0023] Let the lattice constant of the aforementioned initial growth substrate be a. g Let the lattice constant of the above-mentioned simulated substrate layer be a. p In the case of the above-mentioned simulated substrate layer relative to the above-mentioned initial growth substrate, the mismatch X p·g It is above 0.7%.

[0024] The above N is a natural number greater than 3.

[0025] The aforementioned epitaxial growth substrate has three or more buffer layers containing mismatched dislocations on the initial growth substrate side of the aforementioned buffer layer.

[0026] [2] The epitaxial growth substrate according to [1], wherein,

[0027] Let q be the lattice constant in the vertical direction of the above-mentioned simulated substrate layer calculated according to the reciprocal space mapping. z Let the lattice constant in the horizontal direction be q. x Under the condition that the following equation (2) is satisfied:

[0028] -0.0002≤q z -q x ≤0.0011 (2).

[0029] [3] The epitaxial growth substrate according to [1] or [2], wherein a grid-like pattern is observed when a top view of the surface of the simulated substrate layer is taken by a metal microscope.

[0030] [4] An epitaxial growth substrate according to any one of [1] to [3], wherein,

[0031] Let a be the lattice constant of the nth buffer layer, counting from the buffer layer located closest to the aforementioned initial growth substrate. n Let the lattice constant of the (n+1)th buffer layer be a. n+1 Under the condition that the following equation (1) is satisfied:

[0032] a n <a n+1 (1),

[0033] In the above formula, n is 1 to N-1.

[0034] When n is 1, the lattice constant a1 is greater than the above a g ,

[0035] The lattice constant a when n+1 is N N Less than the above a p ,

[0036] The mismatch degree of each of the N buffer layers relative to the layer adjacent to it on the initial growth substrate side is the aforementioned mismatch degree X. p·g The value obtained by dividing by N is as follows.

[0037] [5] An epitaxial growth substrate according to any one of [1] to [4], wherein the buffer layer is composed of a single layer or multiple buffer constituent layers, and the thickness of the buffer layer is 150 nm or more.

[0038] [6] An epitaxial growth substrate according to [4] or [5], wherein,

[0039] At least one buffer layer consists of multiple buffer component layers.

[0040] Compared to buffer layer B, which is located closest to the initial growth substrate within the buffer layer, buffer layer A, located closest to the simulated substrate layer within the buffer layer, is thicker.

[0041] Here, the lattice constant of the buffer layer in equation (1) is the lattice constant of the buffer constituting layer A.

[0042] [7] The epitaxial growth substrate according to [6], wherein the thickness of the buffer constitutive layer A is 100 nm or more, and the thickness of the buffer constitutive layer B is less than half the thickness of the buffer constitutive layer A.

[0043] [8] An epitaxial growth substrate according to any one of [1] to [7], wherein the initial growth substrate is an InP substrate and the etch stop layer is an InGaAs layer.

[0044] [9] An epitaxial growth substrate according to any one of [1] to [8], wherein the initial growth substrate is an InP substrate, the buffer stack is a stack of multiple InAsP layers, and the buffer stack further has an InP window layer in contact with the etch stop layer.

[0045]

[10] A method for manufacturing an optical semiconductor device, comprising:

[0046] The process of forming a semiconductor stack containing an active layer on a simulated substrate layer of an epitaxial growth substrate in any of [1] to [9];

[0047] The process of bonding a support substrate to the aforementioned semiconductor laminate via a reflective layer; and,

[0048] The process of removing the initial growth substrate of the aforementioned epitaxial growth substrate.

[0049]

[11] In the method for manufacturing an optical semiconductor element according to

[10] , the SORI value of the surface side of the semiconductor stack on the simulated substrate layer obtained by the process of forming the semiconductor stack is less than 30 μm.

[0050]

[12] An optical semiconductor device comprising, in sequence: a support substrate, a reflective layer, a semiconductor laminate including an active layer, and a buffer laminate.

[0051] The aforementioned buffer layer stack sequentially comprises: an analog substrate layer with a thickness of 300 nm or more, N buffer layers, and a window layer, wherein the window layer is located on the light extraction side.

[0052] Let the lattice constants of the above-mentioned simulated substrate layer and the above-mentioned window layer be respectively set as a p and a t In the case of the above-mentioned simulated substrate layer relative to the above-mentioned window layer, the mismatch X p·tIt is above 0.7%.

[0053] The above N is a natural number greater than 3.

[0054] The aforementioned optical semiconductor element has three or more buffer layers containing mismatched dislocations on the window side of the aforementioned buffer layer.

[0055]

[13] According to the optical semiconductor element of

[12] , wherein,

[0056] Let a be the lattice constant of the nth buffer layer, counting from the buffer layer located closest to the aforementioned window layer. n Let the lattice constant of the (n+1)th buffer layer be a. n+1 Under the condition that the following equation (1) is satisfied:

[0057] a n <a n+1 (1),

[0058] In the above formula, n is 1 to N-1.

[0059] When n is 1, the lattice constant a1 is greater than the above a t ,

[0060] The lattice constant a when n+1 is N N Less than the above a p ,

[0061] Make the mismatch degree of each of the N buffer layers relative to the layer adjacent to it on the window layer side the aforementioned mismatch degree X. p·t The value obtained by dividing by N is as follows.

[0062]

[14] The optical semiconductor element according to

[12] or

[13] , wherein the refractive index gradually decreases from the above-mentioned analog substrate layer toward the window layer.

[0063]

[15] An optical semiconductor device according to any one of

[12] to

[14] , wherein the window layer is InP, the buffer stack is a stack of multiple InAsP layers, and the analog substrate layer is an InAsP layer.

[0064]

[16] The light semiconductor element according to any one of

[12] to

[15] , wherein the light emission center wavelength of the active layer in the above semiconductor stack is 2000 to 3000 nm.

[0065]

[17] An optical semiconductor element according to any one of

[12] to

[16] , wherein,

[0066] The aforementioned active layer has a quantum well structure, and when the lattice constant of the well layer is set to a... w hour,

[0067] The mismatch X between the aforementioned well layer and the aforementioned simulated substrate layer w·p It is above 0.1% and less than 1.2%.

[0068]

[18] According to the optical semiconductor element of

[17] , wherein, in the lattice constants of the semiconductor stack and the buffer stack, the lattice constant a of the well layer of the active layer is... w maximum.

[0069]

[19] The optical semiconductor element according to any one of

[12] to

[18] , wherein the buffer layer is composed of a single layer or multiple buffer constituent layers, and the thickness of the buffer layer is 150 nm or more.

[0070]

[20] An optical semiconductor element according to any one of

[13] to

[19] , wherein,

[0071] At least one buffer layer consists of multiple buffer component layers.

[0072] Compared to buffer layer B, which is located closest to the initial growth substrate within the buffer layer, buffer layer A, located closest to the simulated substrate layer within the buffer layer, is thicker.

[0073] Here, the lattice constant of the buffer layer in equation (1) is the lattice constant of the buffer constituting layer A.

[0074]

[21] An optical semiconductor device according to any one of

[17] to

[20] , wherein the lattice constant of the barrier layer of the above-mentioned active layer is set to a. b Let X be the degree of mismatch between the above-mentioned barrier layer and the above-mentioned simulated substrate layer. b·p In the case of mismatch X between the well layer and the simulated substrate layer, w·p And the mismatch X between the aforementioned barrier layer and the aforementioned simulated substrate layer b·p The calculated average thickness mismatch between the well layer and the barrier layer is in the range of -0.09% to 0.46%.

[0075] The effects of the invention

[0076] According to the present invention, an epitaxial growth substrate having a buffer laminate can be provided that does not produce cracks even when a support substrate is bonded and an initial growth substrate is removed. Furthermore, a method for manufacturing an optical semiconductor element in which a semiconductor laminate including an active layer is formed on such an epitaxial growth substrate and a support substrate is bonded and an initial growth substrate is removed can be provided, as well as an optical semiconductor element with high light intensity and favorable light extraction. Attached Figure Description

[0077] Figure 1This is a cross-sectional schematic diagram of an example of the substrate for epitaxial growth according to the present invention. This schematic diagram is a patterned diagram of the variation of the lattice constant, and the width of each layer in the horizontal direction relatively represents the magnitude of the lattice constant.

[0078] Figure 2 This is a cross-sectional schematic diagram of an epitaxial growth substrate in which all buffer layers are composed of two buffer constituent layers. This schematic diagram is related to... Figure 1 Similarly, the pattern of the variation in lattice constant is also presented.

[0079] Figure 3 This is a cross-sectional schematic diagram of an example of a method for manufacturing an optical semiconductor element according to the present invention.

[0080] Figure 4 This is a cross-sectional schematic diagram of an example of the optical semiconductor element of the present invention.

[0081] Figure 5 This is a schematic cross-sectional view of a substrate illustrating the definition of SORI (Slightly Increasing Warp Ratio).

[0082] Figure 6 This is a schematic cross-sectional view of the substrate illustrating the definition of (BOW).

[0083] Figure 7 This is a cross-sectional schematic diagram of an example of a buffer stack and a semiconductor stack in the optical semiconductor element of the present invention. The schematic diagram is a patterned representation of the variation in lattice constant, where the width of each semiconductor layer in the horizontal direction relatively represents the magnitude of the lattice constant.

[0084] Figure 8 This is a TEM image of a cross-section of the epitaxial growth substrate of Example 1.

[0085] Figure 9 This is a top view (3mm square) of the simulated substrate layer of the epitaxial growth substrate in Example 1, taken using a metal microscope.

[0086] Figure 10 This is a graph showing the change in the PL intensity (relative intensity) of the optical semiconductor device using the epitaxial growth substrate of Example 1 relative to the average thickness mismatch of the well layer and the barrier layer. Detailed Implementation

[0087] Before describing the embodiments of the present invention, the following aspects will be described in advance.

[0088] In this specification, the lattice constant calculated based on the composition ratio (solid-to-weight ratio) using Vigarde's law is denoted by the sign 'a', and the lattice constant of which layer is being referred to is indicated by the subscript following 'a'. For example, the lattice constant of the initial growth substrate is denoted as 'a'. g Let a denote the lattice constant of the pseudo substrate layer. p Furthermore, the lattice mismatch Δa / a is denoted by X, and the mismatch between which layer and which layer is indicated by the subscript attached to X.

[0089] For example, the mismatch between the simulated substrate layer and the initial growth substrate is denoted as X. p·g Its calculation formula <1> is set as follows:

[0090] (a p -a g ) / a g ×100…<1>.

[0091] It should be noted that the lattice constant obtained by X-ray reciprocal space determination will be distinguished by the sign q.

[0092] Regarding the composition ratios (solid-to-weight ratios) of each layer in this specification, values ​​obtained through SIMS analysis are used. For the buffer stack in this specification, the composition ratios (solid-to-weight ratios) of each layer are obtained through SIMS analysis (quadrupole type) performed along the thickness direction from a simulated substrate layer in epitaxial growth substrates. In optoelectronic semiconductor devices, values ​​obtained through SIMS analysis (quadrupole type) performed along the thickness direction from a window layer are used. It should be noted that for the SIMS analysis results, the average elemental concentration values ​​are used for half the thickness range of each layer in the central portion of the thickness direction.

[0093] During manufacturing, for a layer grown as a single film, the solid-liquid ratio is calculated using the lattice constant obtained by XRD and the value obtained by photoluminescence (PL) by converting the emission center wavelength into Eg (i.e., band gap). The growth conditions that are the target composition ratio are then determined, and a layer with the target composition ratio is stacked using these growth conditions.

[0094] Unless otherwise specified, the lattice constants in this specification are set as values ​​calculated based on the composition ratio using Vigarde's law.

[0095] First, calculate the simple lattice constant of the mixed crystal according to Vigarde's law.

[0096] Using the InGaAsP system (i.e., the general formula: (In a Ga b(P) x As y When using the example of )) for explanation, the physical property constant A abxy (Based on Vigard's law, lattice constants) Given that the proportions of each component (solid-to-solid ratio) are known, the physical property constants B of the four binary mixed crystals that form the basis of the pseudo-quaternary mixed crystals are... ax B bx B ay B by (The lattice constants of the literature values ​​in Table 1 below) are calculated by the following formula <2>.

[0097] A abxy =a×x×B ax +b×x×B bx +a×y×B ay +b×y×B by …<2>

[0098] [Table 1]

[0099]

[0100] In the case of pseudo-ternary mixed crystals, the general formula is: (In a Ga b Al c As an example, the band gap Eg and the lattice constant a based on Vigarde's law can be calculated from the following equations <3> and <4>.

[0101]

[0102] A abcy =a×B ay +b×B by +c×B cy …<4>

[0103] It should be noted that when III-V compound semiconductors are ternary, pentagonal, or hexagram systems, the formula can be transformed using the same approach to determine the constituent wavelengths and lattice constants. Furthermore, for binary systems, the values ​​described in the aforementioned literature can be used.

[0104] In this specification, when the composition ratio is not explicitly stated and the compound is abbreviated as "InGaAsP", it refers to any compound in which the chemical composition ratio of a Group III element (the sum of In and Ga) to a Group V element (As and P) is 1:1, and the ratio of In and Ga as Group III elements to the ratio of As and P as Group V elements are respectively indeterminate. This includes cases where neither In nor Ga is present in the Group III elements, and also cases where neither As nor P is present in the Group V elements. Furthermore, when expressed as "InGaP", it means that the aforementioned "InGaAsP" does not contain As except for unavoidable manufacturing contamination; when expressed as "InGaAs", it means that the aforementioned "InGaAsP" does not contain P except for unavoidable manufacturing contamination. Similarly, when described as "InAsP," it means that the aforementioned "InGaAsP" does not contain Ga except for unavoidable contamination during manufacturing. Similarly, when described as "GaAsP," it means that the aforementioned "InGaAsP" does not contain In except for unavoidable contamination during manufacturing. Furthermore, when described as "InP," it means that the aforementioned "InGaAsP" does not contain Ga or As except for unavoidable contamination during manufacturing. It should be noted that the composition ratios of InGaAsP, InGaAs, etc., can be determined using photoluminescence and X-ray diffraction methods. Additionally, the phrase "unavoidable contamination during manufacturing" refers not only to unavoidable contamination from the manufacturing apparatus using the raw material gases, but also to atomic diffusion at the interfaces of each layer during crystal growth and subsequent heat treatment.

[0105] In this specification, layers that function electrically as p-type layers are referred to as p-type layers, and layers that function electrically as n-type layers are referred to as n-type layers. On the other hand, the absence of intentionally added impurities such as Zn, S, and Sn is referred to as "undoped." Unavoidable impurities from the manufacturing process can be incorporated into undoped InGaAsP layers; specifically, impurities that are unavoidable during manufacturing can be introduced, particularly when the carrier density is low (e.g., less than 4 × 10⁻⁶). 16 / cm 3 In cases where the sample is not fully doped, it is considered "undoped" in this specification. Furthermore, the concentration values ​​for impurities such as Zn and Sn are based on SIMS analysis.

[0106] In this specification, the overall thickness of each layer can be measured using an optical interferometer. Furthermore, the thickness of each layer can be calculated separately by cross-sectional observation of the grown layer using both an optical interferometer and a transmission electron microscope. Additionally, in cases where the thickness of each layer is small, such as in a superlattice structure, TEM-EDS can be used to measure the thickness. It should be noted that in the cross-sectional view, when a specified layer has an inclined surface, the thickness of that layer is measured using the maximum height from the flat surface of the layer directly below it.

[0107] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in principle, the same reference numerals are used to denote the same constituent elements, and repeated descriptions are omitted. In the figures, for ease of explanation, the aspect ratios of the substrate and each layer are exaggerated and are independent of the actual thickness; the shapes of the electrodes, intermediate electrode portions, and mesa are also simplified. However, in… Figure 1 , 2 In 7, the width of each layer in the horizontal direction relatively represents the magnitude of the lattice constant.

[0108] <Substrate for Epitaxial Growth>

[0109] The following is for reference Figure 1 The epitaxial growth substrate of the present invention will be described, but the epitaxial growth substrate of the present invention is not limited thereto.

[0110] Here, Figure 1 This is a schematic diagram of an example of a substrate for epitaxial growth according to the present invention. In this example, the N buffer layers are all single layers. This schematic diagram is a patterned representation of the variation in lattice constant, where the width of each layer in the horizontal direction relatively represents the magnitude of the lattice constant.

[0111] The epitaxial growth substrate 1 of the present invention sequentially comprises an initial growth substrate 11, an etch stop layer 12, a buffer layer 13, and a simulated substrate layer 14 with a thickness of 300 nm or more.

[0112] (Substrate for initial growth)

[0113] The initial growth substrate 11 is not particularly limited, and can be appropriately selected from compound semiconductor substrates such as InP substrate, GaAs substrate, GaSb substrate, InAs substrate, and InSb substrate, depending on the composition of the active layer of the optical semiconductor device manufactured using the epitaxial growth substrate, with InP substrate being preferred. These substrates can be undoped or either n-type or p-type.

[0114] The substrate diameter can be selected between 2 inches and 6 inches. The thickness of the initial growth substrate also depends on the substrate diameter, and can be set to 100 μm or more, preferably 300 μm or more. It is preferred to use an initial growth substrate based on the SEMI standard.

[0115] (Etching stop layer)

[0116] The epitaxial growth substrate of the present invention has an etch stop layer 12 on the initial growth substrate 11. Alternatively, the etch stop layer may be formed after a lattice-matched initial layer is formed on the initial growth substrate 11.

[0117] The epitaxial growth substrate of the present invention is envisioned as a substrate from which the aforementioned initial growth substrate 11 is subsequently removed. The etch stop layer 12 is a layer such that, in the manufacture of an optical semiconductor device using the epitaxial growth substrate of the present invention, when the initial growth substrate 11 is removed by etching, etching is stopped only when the initial growth substrate 11 is removed, preventing the previous buffer layer stack and the semiconductor layer stack containing the active layer from being etched away as well. The etch stop layer 12 is preferably a layer whose main Group V elements differ from those of the initial growth substrate 11, so as to have etch selectivity against etchants that are difficult to etch with the etchant used to remove the initial growth substrate 11. For example, when the initial growth substrate 11 is an InP substrate, it is preferably an InGaAs layer. The etch stop layer 12 is preferably a layer with lattice matching with the initial growth substrate 11. For example, in the case of forming an InGaAs layer on an InP substrate, it is preferably an In composition (0.532) with the same lattice constant as the InP substrate. Within the thickness range described later, even if the In composition is set to 0.47 to 0.60, defect-free growth is possible. The material of the etch stop layer 12 can be appropriately selected in a manner that satisfies the above conditions, based on the material of the initial growth substrate 11 used.

[0118] The thickness of the etch stop layer 12 is only required to stop etching when the initial growth substrate 11 is removed. It can be relatively thin, preferably 100 nm or less, more preferably 50 nm or less, and even more preferably 30 nm or less. Furthermore, the thickness of the etch stop layer 12 is preferably 1 nm or more, more preferably 5 nm or more. The etch stop layer 12 can be a single layer or a composite layer (e.g., an SLS layer).

[0119] A portion of the etch stop layer 12 can be completely removed after the initial growth substrate 11 is removed, using an etchant different from the etchant used for the initial growth substrate 11, or a portion can remain and be used as a contact layer for the optical semiconductor device.

[0120] (Buffer layer)

[0121] The epitaxial growth substrate of the present invention has a buffer stack on the etch stop layer 12. The buffer stack has at least N buffer layers 13 and a simulated substrate layer 14. Furthermore, the buffer stack may have a window layer 15 between the etch stop layer 12 and the N buffer layers 13 that matches the lattice of the initial growth substrate 11.

[0122] Here, the window layer 15 is the uppermost layer on the light extraction side of the optical semiconductor element after the initial growth substrate 11 and the etch stop layer 12 have been removed, and it can be configured as a layer for roughening. Therefore, it is preferable to make a layer that is thick enough for roughening, and it can be configured to be 100 nm or more and 800 nm or less.

[0123] The buffer stack is preferably a stack of multiple InAsP layers, so that when using an InP substrate, it can be grown while increasing the lattice constant difference with the InP substrate. In this case, the window layer that matches the lattice of the InP substrate is, for example, an InP layer.

[0124] Alternatively, it is preferable to use a stack of multiple InGaSb layers so that growth can be performed while increasing the lattice constant difference with the GaSb substrate when using a GaSb substrate. In this case, the window layer that matches the lattice of the GaSb substrate is, for example, a GaSb layer.

[0125] N in the N buffer layers 13 is a natural number of 3 or more. This is because, when it is less than 2, it is difficult to achieve the effect of eliminating internal stress and to obtain the PL strength of the semiconductor stack formed thereon. Regarding the upper limit of N, although it also depends on the magnitude of the lattice mismatch between the initial growth substrate 11 and the simulated substrate layer 14, it is preferable to set it to be a number of layers suitable for generating the lattice mismatch dislocations described later, for example, 9 or less.

[0126] The N buffer layers 13 are characterized in that at least three of them contain mismatched dislocations on the initial growth substrate side of the buffer layer. When observing the cross-section of the N buffer layers 13 using a transmission electron microscope (TEM), if the number of buffer layers with mismatched dislocations observed at the interface on the initial growth substrate side is three or more, then mismatched dislocations can be observed in all N buffer layers, or the N buffer layers 13 may include buffer layers in which no mismatched dislocations are observed. Here, the initial growth substrate side of the buffer layer is preferably the interface with the layer adjacent to the initial growth substrate side (also called the lower layer).

[0127] Mismatch dislocations are dislocations caused by differences in the lattice constant in the in-plane direction of the substrate. Besides arising from the interface between adjacent buffer layers, they can also arise at the interface between the buffer layer and the aforementioned window layer. Dislocations do not propagate through the buffer layer and preferably remain within it.

[0128] Mismatched dislocations can be confirmed by exposing a cross-section in the thickness direction of the epitaxial growth substrate of this invention and observing the cross-section using a transmission electron microscope (TEM). For example... Figure 8 As shown, in observations using a transmission electron microscope (TEM), dislocations are observed as black areas. The interface between adjacent buffer layers can be discerned through contrast, and the black areas observed parallel to this interface can be identified as mismatch dislocations. A key feature of this invention is the presence of such mismatch dislocations observed parallel to the interface. Black areas observed at an angle relative to the interface are dislocations propagating in the growth direction during stress relaxation growth originating from mismatch dislocations generated at the interface, and are distinct from the aforementioned mismatch dislocations.

[0129] N buffer layers 13, with the buffer layer located closest to the initial growth substrate as the first buffer layer, and the lattice constant of the nth buffer layer counting from the buffer layer closest to the initial growth substrate set to a. n Let the lattice constant of the (n+1)th buffer layer be a. n+1 Under the condition that, the following equation (1) is satisfied.

[0130] a n <a n+1 (1)

[0131] In the above formula, n is a natural number from 1 to N-1. n+1 is a natural number from 2 to N.

[0132] When n is 1, the lattice constant a1 is the lattice constant of the buffer layer located closest to the initial growth substrate, which is greater than the lattice constant a of the initial growth substrate. g In the case of a window layer, the lattice constant a1 is greater than the lattice constant a of the window layer. t .

[0133] Furthermore, when n+1 is N, the lattice constant a N The lattice constant a of the simulated substrate layer is less than that of the substrate layer. p .

[0134] The thickness of each buffer layer is preferably set such that the difference in lattice constant between it and the layer adjacent to the initial growth substrate (hereinafter also referred to as the "lower layer") exceeds a critical film thickness, which allows for the generation of mismatched dislocations while mitigating internal stress. For example, it can be set to 150 nm or more, preferably 200 nm or more. Alternatively, it can be set to 1000 nm or less, preferably 800 nm or less, and more preferably 500 nm or less.

[0135] Here, each buffer layer can be a single layer or composed of multiple buffer constituent layers. From the viewpoint of reducing substrate warpage, each buffer layer is preferably a buffer layer comprising buffer constituent layers. It is also possible to include both single-layer buffer layers and buffer layers composed of buffer constituent layers.

[0136] The buffer layers in the buffer layer stack are divided into single-layer buffer layers and buffer layers composed of multiple buffer constituent layers. Regarding each layer constituting the buffer layer stack, when comparing the lattice constant of a single layer with the layer on the initial growth substrate side adjacent to it, if the relationship is as stated in Equation (1) above, they are considered as single-layer buffer layers. When comparing the lattice constant of a single layer with the layer on the initial growth substrate side adjacent to it, contrary to Equation (1) above, if the lattice constant of the layer on the initial growth substrate side is larger, the single layer and the layer on the initial growth substrate side adjacent to it are each considered as a buffer constituent layer. Moreover, multiple buffer constituent layers with a larger lattice constant on the initial growth substrate side are collectively considered as one buffer layer. Furthermore, the layer closest to the simulation substrate side is called buffer constituent layer A, and the layer closest to the initial growth substrate side is called buffer constituent layer B.

[0137] -Case where the buffer layer is a single layer-

[0138] When the buffer layer is a single layer, the lattice constant a of the nth buffer layer mentioned above. n It is, of course, the lattice constant of that monolayer.

[0139] The lattice constants of the multiple buffer layers in the N buffer layers 13 generally increase from the buffer layer closest to the initial growth substrate to the buffer layer closest to the simulation substrate.

[0140] Regarding the case where the buffer consists of a single-layer buffer layer, Figure 1 The diagram shown is a patterned representation of the variation in the lattice constant, where the width of each layer in the horizontal direction relatively represents the magnitude of the lattice constant.

[0141] As described above, the thickness of the single-layer buffer layer can be set to, for example, 150 nm or more.

[0142] Furthermore, in order to form mismatched dislocations and avoid threading dislocations, it is preferable to set the lattice constant of each of the N buffer layers relative to the mismatch degree of the layer (lower layer) adjacent to it on the initial growth substrate side as mismatch degree X. p·g The value obtained by dividing by N is preferably set to the mismatch degree X. p·g The value obtained by dividing by 4N is greater than or equal to the value obtained by dividing by 4N. For example, the mismatch between each buffer layer and the underlying layer is preferably in the range of 0.15% to 0.35%.

[0143] -The case where the buffer layer consists of multiple buffer layers-

[0144] When the buffer layer consists of multiple buffer constituent layers, where adjacent buffer constituent layers have different lattice constants, the lattice constant a of the nth buffer layer mentioned above is... n It is the lattice constant of the buffer constitutive layer (buffer constitutive layer A) located on the side closest to the analog substrate layer within the buffer layer. This lattice constant satisfies the above equation (1) and the relationship with other lattice constants between itself and the (n+1)th buffer layer.

[0145] The buffer layer, including the buffer constituent layer, is preferably composed of two buffer constituent layers with different lattice constants. Regarding the case where the buffer layer is composed of two layers: a buffer constituent layer (buffer constituent layer A) located on the simulation substrate side and a buffer constituent layer (buffer constituent layer B) located on the growth substrate side, in... Figure 2 The diagram shown is a patterned representation of the variation in the lattice constant, where the width of each layer in the horizontal direction relatively represents the magnitude of the lattice constant.

[0146] like Figure 2 As shown, when the lattice constant of buffer layer A is set to a and the lattice constant of buffer layer B is set to b, the lattice constant b in the nth buffer layer... n The lattice constant a of the buffer layer A is greater than that of the buffer layer A. n Furthermore, when the (n+1)th buffer layer is also composed of two buffer layers, the lattice constant b in the (n+1)th buffer layer... n+1 Greater than the lattice constant a n+1 Therefore, based on equation (1), a n+1 Greater than a n b n+1 Greater than b n .

[0147] Moreover, the buffer layer A is thicker than the buffer layer B.

[0148] In N buffer layers 13, all buffer layers are composed of two buffer layers, and each buffer layer satisfies the above relationship, such as Figure 2 As shown, the lattice constant a of the buffer layer n and b n While repeatedly increasing and decreasing, the overall value gradually increases as n increases from 1 to N-1 (and N in the (n+1)th buffer layer). Therefore, it is consistent with... Figure 1 Compared to the previous case, mismatched dislocations are more likely to occur in buffer layer B. In addition, during the overall application of compressive stress, buffer layer A is subjected to tensile stress from buffer layer B, thus increasing the mitigation effect of internal stress caused by the thickness of buffer layer A.

[0149] In the buffer layer including the buffer constituent layer, the thickness of the buffer constituent layer A located on the side closest to the analog substrate layer is preferably set to a thickness that can alleviate internal stress, which can be set to 100 nm or more, preferably 200 nm or more. Alternatively, it can be set to 1000 nm or less, preferably 800 nm or less, and more preferably 500 nm or less.

[0150] In the buffer layer including the buffer constituent layer, the thickness of the buffer constituent layer B located on the side closest to the initial growth substrate is preferably less than half the thickness of the buffer constituent layer A, and preferably the thickness that generates mismatch dislocations relative to the layer (lower layer) adjacent to the initial growth substrate side. For example, it can be set to 10 nm or more, preferably 30 nm or more. Alternatively, it can be set to 200 nm or less, preferably 100 nm or less.

[0151] The thickness of the aforementioned buffer layer A is preferably more than twice the thickness of the aforementioned buffer layer B, and more preferably more than three times.

[0152] To form mismatched dislocations and prevent through-dislocations, it is preferable to use the lattice constant of each of the N buffer layers (in the case of buffer layers including buffer constituent layers, the lattice constant b of the buffer constituent layer B closest to the initial growth substrate side). n The mismatch degree relative to the layer adjacent to the initial growth substrate (lower layer) is set as mismatch degree X. p·g The value obtained by dividing by N is more preferably set as the mismatch degree X. p·g The value obtained by dividing by 4N is greater than or equal to the value obtained by dividing by 4N. For example, the mismatch between the buffer layer B and the underlying layer is preferably in the range of 0.15% to 0.35%.

[0153] Furthermore, due to the lattice constant b of the buffer layer B n The lattice constant a of the buffer layer A is greater than that of the buffer layer A. n Therefore, the mismatch between buffer layer A and the underlying layer (buffer layer B) is negative. Its absolute value is preferably smaller than that of buffer layer B. n The absolute value of the mismatch relative to the lower layer.

[0154] (Simulated substrate layer)

[0155] The buffer layer stack in the epitaxial growth substrate of the present invention has a simulated substrate layer 14 with a thickness of 300 nm or more on the Nth buffer layer, which is the Nth buffer layer located on the side closest to the initial growth substrate.

[0156] Here, the simulated substrate layer 14 is a layer used in the fabrication of optical semiconductor devices as a substrate for epitaxially growing layers such as a semiconductor stack including the active layer 30. The semiconductor stack can be grown in a manner that matches the lattice of the simulated substrate layer.

[0157] From the viewpoint of suppressing warping due to the rapid change in the balance of internal stress during the bonding of the support substrate and the removal of the initial growth substrate, the thickness of the simulated substrate layer 14 is 300 nm or more, preferably 500 nm or more. Furthermore, from the viewpoint of avoiding excessively long growth times, it is preferably 10 μm or less.

[0158] The material of the simulated substrate layer 14 can be used to simulate the mismatch between the simulated substrate layer 14 and the initial growth substrate 11. p·g Choose the appropriate method to achieve a percentage of 0.7% or higher.

[0159] Here, the lattice constants of the simulated substrate layer and the initial growth substrate are respectively set as a. p and a g In the case of mismatch X p·g By (a p -a g ) / a g ×100 represents the degree of mismatch. p·g From the viewpoint of increasing the wavelength range that can be designed in the formed semiconductor stack, the value is preferably 0.7% or higher, and 1.0% or higher.

[0160] The material of the simulated substrate layer 14 can be appropriately selected in a manner that satisfies the above conditions.

[0161] The simulated substrate layer 14 is disposed on the aforementioned N buffer layers 13, thus allowing the simulated substrate layer 14 to be in a relaxed state. Here, a relaxed state refers to the lattice constant q in the vertical direction calculated by reciprocal space mapping (RSM) after X-ray diffraction (XRD) of the simulated substrate layer 14. z (nm) and the lattice constant q in the horizontal direction x The difference (nm) satisfies the following equation (2).

[0162] -0.0002≤q z -q x ≤0.0011 (2)

[0163] lattice constant q in the vertical direction z The lattice constant q in the horizontal direction x When the difference is zero, theoretically the lattice is in a state of complete unstrained state. The closer the value of equation (2) is to zero, the greater the reduction effect on warpage. It is preferable to set the difference to be below 0.0005 nm.

[0164] In the epitaxial growth substrate of the present invention, mismatch dislocations are present in the portions of three or more but less than N buffer layers 13 that are in contact with other layers with different lattice constants. By intentionally generating mismatch dislocations within the buffer layers, the simulated substrate layer 14 is made to be in a relaxed state, which can reduce the warpage of the substrate. Moreover, when a top view of the surface of the simulated substrate layer is taken using a metal microscope, a lattice-like pattern caused by the aforementioned mismatch dislocations in the N buffer layers 13 is sometimes observed.

[0165] Here, the simulated substrate layer 14 can be a single layer or it can be composed of multiple simulated substrate layers. In the case where it is composed of multiple simulated substrate layers, similar to the buffer layer described above, the simulated substrate layer containing the simulated substrate layer is preferably composed of two simulated substrate layers with different lattice constants, wherein the lattice constant b of the simulated substrate layer B located on the growth substrate side is greater than the lattice constant a of the simulated substrate layer A located on the simulated substrate layer B.

[0166] Furthermore, the simulated substrate constituent layer A is thicker than the simulated substrate constituent layer B. During the overall application of compressive stress, the simulated substrate constituent layer A is subjected to tensile stress from the simulated substrate constituent layer B, thus increasing the mitigation effect of internal stress caused by the thickness of the simulated substrate constituent layer A.

[0167] In the analog substrate layer including the analog substrate constituting layer, the thickness of the analog substrate constituting layer A is preferably 300 nm or more, and more preferably 400 nm or more.

[0168] In the simulated substrate layer including the simulated substrate constituent layer, the thickness of the simulated substrate constituent layer B located on the side closest to the initial growth substrate is preferably less than half the thickness of the simulated substrate constituent layer A. For example, it is preferably 50 nm or more, and more preferably 100 nm or more.

[0169] <Method for Manufacturing Substrates for Epitaxial Growth>

[0170] The method for manufacturing an epitaxial growth substrate according to the present invention includes the following steps.

[0171] The process of forming an etch stop layer on the initial growth substrate

[0172] The process of forming a buffer stack on the etch stop layer

[0173] The preferred configurations for the initial growth substrate, etch stop layer, and buffer layer stack are as described above. Their formation methods are explained below.

[0174] (Etching stop layer formation process)

[0175] The method for forming the etch stop layer 12 is not particularly limited as long as it can be epitaxially grown on the initial growth substrate. For example, metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering, etc. can be listed.

[0176] For example, if the initial growth substrate is an InP substrate and the etch stop layer 12 is an InGaAs layer, it can be formed by supplying trimethylindium (TMIn) as the In source, trimethylgallium (TMGa) as the Ga source, and hydrogen arsenide (AsH3) as the As source into the growth furnace using a carrier gas in a predetermined mixing ratio, and then performing vapor phase growth on the substrate. If it is an n-type or p-type substrate, a dopant source gas can be used further as appropriate.

[0177] The lattice constant α, calculated from the composition ratio of the etch stop layer 12, can be adjusted by changing the mixing ratio of the In source, Ga source, and As source contained in the feed gas, thereby controlling the composition ratio of the etch stop layer 12. Furthermore, the thickness of the etch stop layer 12 can be adjusted by the ratio of the amount of Group III feed gas to the amount of Group V feed gas, the growth temperature, and the growth time.

[0178] (Buffer layer formation process)

[0179] In the method for forming the buffer layer stack, at least N buffer layers 13 and a simulated substrate layer 14, as described above, are formed on the etch stop layer 12. A window layer 15 may be formed on the etch stop layer 12 before the N buffer layers 13.

[0180] These formation methods are not particularly limited as long as epitaxial growth can be performed on the etch stop layer 12, and the formation methods described above can be used.

[0181] For example, when each buffer layer and the simulated substrate layer is an InAsP layer, it can be formed by supplying trimethylindium (TMIn) as the In source, arsine (AsH3) as the As source, and phosphine (PH3) as the P source into the growth furnace using a carrier gas in a predetermined mixing ratio, and performing vapor-phase growth on the etch stop layer 12. If it is an n-type or p-type layer, a dopant source gas can be used further as appropriate.

[0182] The lattice constant α, calculated from the composition ratio of each layer, can be adjusted by changing the mixing ratio of the feed gas. Furthermore, the thickness of each layer can be adjusted by the ratio of Group III feed gas to Group V feed gas, the growth temperature, and the growth time.

[0183] Furthermore, as described above, during manufacturing, for layers grown as single films, the solid-state ratio is calculated using the lattice constant obtained by XRD and the value obtained by converting the emission center wavelength to Eg using photoluminescence (PL) measurements. This determines the growth conditions for the target composition ratio, and layers with the target composition ratio can be stacked using these growth conditions. The composition ratio of each layer can also be determined by measuring using SIMS analysis. The lattice constant α of each layer is obtained using the composition ratio (in InAs). y P 1-y In the case of layers, the solid ratio of As is y) and it is calculated using Vigarde's law.

[0184] <Manufacturing Method of Opto-Semiconductor Components>

[0185] The epitaxial growth substrate of the present invention can be used to manufacture optical semiconductor devices. Hereinafter, a method for manufacturing an optical semiconductor device using the epitaxial growth substrate of the present invention will be described, and the details of each component of the optical semiconductor device of the present invention will be explained through this method. However, the manufacturing method of the optical semiconductor device and the optical semiconductor device of the present invention are not limited thereto.

[0186] Figure 3 This is a schematic diagram illustrating an example of a method for manufacturing an optical semiconductor device using an epitaxial growth substrate according to the present invention. Figure 4 It was through Figure 3 This is an example of a photonic semiconductor device obtained by a manufacturing method. This example is one where each of the N buffer layers 13 is a single-layer buffer layer. Furthermore, the active layer 30 constitutes a multiple quantum well (MQW) structure. The photonic semiconductor device can be either a light-emitting element or a light-receiving element; the following description primarily focuses on the case where it is a light-emitting element.

[0187] It should be noted that, in Figure 3 and Figure 4 The image exaggerates the aspect ratios of the substrate and each layer relative to the actual ratios, but it is not as shown in the image. Figure 1 and Figure 2 That is, a pattern that visualizes the changes in the lattice constant.

[0188] The method for manufacturing the optical semiconductor element of the present invention includes the following steps.

[0189] The process of forming a semiconductor stack including an active layer on a simulated substrate layer of an epitaxial growth substrate of the present invention (semiconductor stack formation process);

[0190] The process of bonding a support substrate to a semiconductor laminate via a reflective layer (support substrate bonding process); and,

[0191] The process of removing the initial growth substrate from the epitaxial growth substrate (initial growth substrate removal process).

[0192] (Semiconductor laminate formation process)

[0193] In this process, firstly, as Figure 3 As shown in Figure A, an epitaxial growth substrate 1 having the aforementioned N buffer layers 13 and a simulated substrate layer 14 is prepared. Next, a semiconductor stack including an active layer 30 is formed on the simulated substrate layer 14 of the epitaxial growth substrate 1. Figure 3 B is a diagram of the semiconductor stack after it has been formed.

[0194] The semiconductor stack is preferably formed by sandwiching an active layer 30 between an n-type layer and a p-type layer 37, and the active layer 30 is preferably composed of a multiple quantum well (MQW) structure. From the viewpoint of improving light output by suppressing crystal defects, the MQW structure is advantageous. Figure 3 In Figure B, the active layer 30 constitutes an MQW structure having a structure formed by alternating well layers 35W and barrier layers 35B. Additionally, in this figure, the analog substrate layer 14 is n-type (e.g., doped Si) and also serves as an n-type layer, forming a semiconductor stack structure including the active layer 30 together with the p-type layer 37. However, the method for manufacturing the optical semiconductor device of the present invention is not limited to this embodiment; other n-type layers can be formed on the analog substrate layer 14, and known semiconductor layers suitable for optical semiconductor devices can be added. For example, to suppress impurity diffusion, undoped spacer layers can be provided between the n-type layer and the active layer 30, and between the p-type layer 37 and the active layer 30; co-doped layers can also be provided. The n-type layer and p-type layer 37 can also function as barrier layers, cladding layers, or contact layers.

[0195] The active layer 30 can be composed of elements selected based on the emission center wavelength. For example, the emission center wavelength can be set to 2000-3000 nm. In this case, the well layer 35W of the multiple quantum well (MQW) structure can be formed from a combination of 2 to 6 elements selected from group III elements (Al, Ga, In) and group V elements (P, As, Sb), such as InGaAs. It can also be InAs, InGaAlAs, or InGaAsP.

[0196] According to the present invention, even if the growth substrate is GaAs, a wavelength range longer than the possible wavelength range of the GaAs lattice-matched system can be selected as the emission center wavelength by means of the buffer stack 13 and the simulated substrate layer 14. Similarly, even if the growth substrate is InP, a wavelength range longer than the possible wavelength range of the InP lattice-matched system can be selected as the emission center wavelength by means of the buffer stack 13 and the simulated substrate layer 14. The growth substrate can also be InAs or GaSb, and a wavelength range longer than the possible wavelength range of the InAs and GaSb lattice-matched systems can be selected as the emission center wavelength by means of the buffer stack 13 and the simulated substrate layer 14.

[0197] The band gap of the barrier layer 35B is larger than that of the well layer 35W. The composition of the barrier layer 35B can be formed from a group III-V compound semiconductor composed of a combination of 2 to 6 elements selected from group III elements (Al, Ga, In) and group V elements (P, As, Sb). For example, if the well layer 35W is InGaAs, the barrier layer 35B can be InAsP. It can also be InGaAlAs or InGaAsP.

[0198] The wavelength of light emission can also be adjusted by applying strain to the well layer 35W and the barrier layer 35B by adjusting the compositional difference between the well layer 35W and the barrier layer 35B.

[0199] The barrier layer 35B is preferably a layer whose lattice matches that of the analog substrate layer 14. For example, if the analog substrate layer 14 is an n-type InAsP layer, it is preferable to set the barrier layer 35B as an InAsP layer. In this case, the p-type layer 37 is more preferably a p-type InAsP layer. In addition, the lattice constant (α) of the barrier layer 35B is... b It can also be compared to the lattice constant (a) of the simulated substrate layer 14. p The stress is small, and the tensile stress is applied based on the simulated substrate layer 14.

[0200] The lattice constant of the well layer at 35 W (a w Preferably, the lattice constant (α) is greater than that of the simulated substrate layer 14. p Therefore, compressive strain is applied to the well layer 35W. Applying compressive strain to the well layer 35W improves luminous efficiency compared to applying tensile strain, and is therefore preferred.

[0201] The overall thickness of the semiconductor stack including the active layer 30 is not particularly limited, for example, it can be set to 2~15μm. The thickness of the active layer 30 is also not particularly limited, for example, it can be set to 100~1000nm.

[0202] The active layer 30 has an MQW structure, which allows the thickness of the well layer 35W to be set to 3~15nm, the thickness of the barrier layer 35B to be set to 5~15nm, and the number of the two layers to be set to 3~50.

[0203] After a semiconductor laminate including an active layer 30 is formed on the simulated substrate layer 14, the SORI value of the surface of the laminate is preferably less than 30 μm, and more preferably less than 24 μm. This enables bonding to the support substrate and reduces defects such as poor bonding and cracking. The SORI value is the value when the initial growth substrate is set to a diameter of 3 inches.

[0204] Here, the SORI value is the SORI (μm) specified in SEMI M1-0302. SORI is the difference between the maximum and minimum values ​​of all measurement points under non-adsorption conditions when the measurement is performed under non-forced conditions. For example... Figure 5 As shown, if the reference plane is set as an imaginary plane obtained by the least squares method, then the SORI value is represented by the sum of the absolute values ​​of the maximum value A and the minimum value B.

[0205] After a semiconductor laminate including an active layer 30 is formed on the simulated substrate layer 14, the BOW value of the laminate surface is preferably less than 40 μm, more preferably less than 30 μm. This enables bonding to the support substrate and reduces defects such as poor bonding and cracking. The BOW value is the value when the initial growth substrate is set to a diameter of 3 inches.

[0206] Here, as Figure 6 As shown, the BOW value is as follows: for the center measurement value (measurement surface) of the workpiece under non-adsorption, the sum of the absolute values ​​of the largest absolute values ​​among the measurement values ​​with different signs from the center, and the sign of the center measurement value is attached.

[0207] The thickness of the p-type layer 37 is not particularly limited, but is preferably set to 100~9000nm, and more preferably 400~4000nm.

[0208] Alternatively, a spacer layer can be provided between the active layer 30 and the analog substrate layer 14, or between the active layer 30 and the p-type layer 37. By providing a spacer layer, the diffusion of dopants can be prevented. The thickness of the spacer layer is not particularly limited, for example, it can be set to 50~400nm.

[0209] When the analog substrate layer 14 is an n-type InAsP layer and the p-type layer is a p-type InAsP layer, the spacer layer can be, for example, an i-type InAsP layer. They are preferably lattice-matched with the analog substrate layer.

[0210] The p-type layer 37 can also have a p-type contact layer. The thickness of the p-type contact layer is not particularly limited, for example, it can be set to 50~400nm.

[0211] Each layer of the semiconductor stack including the active layer 30 can be formed by epitaxial growth. The above description applies to epitaxial growth. These stack formation processes are one example of this embodiment, and the method for manufacturing the optical semiconductor device of the present invention is not limited to this embodiment.

[0212] (Support substrate bonding process)

[0213] Next, a support substrate 16 is bonded to the semiconductor stack containing the active layer 30 of the epitaxial growth substrate 1 via a reflective layer. If a portion of the etch stop layer remains on the semiconductor stack containing the active layer 30 as an island-shaped contact layer, the support substrate 16 is bonded over it via a reflective layer 17.

[0214] Except where the reflective layer 17 has a transparent electrode such as ITO and also functions as an intermediate electrode, an island-shaped intermediate electrode portion 38 and a dielectric layer 39 surrounding the intermediate electrode portion 38 in the horizontal direction can be provided between the semiconductor stack containing the active layer 30 and the reflective layer 17.

[0215] exist Figure 3 In C, the epitaxial growth substrate 1 has a p-type layer 37 on a semiconductor stack including an active layer 30, an island-shaped intermediate electrode portion 38 and a dielectric layer 39 surrounding the intermediate electrode portion 38 in the horizontal direction on the p-type layer 37, and a reflective layer 17 is formed thereon.

[0216] The reflective layer 17 is a layer that reflects light emitted from the semiconductor stack containing the active layer 30. The reflective layer 17 is not particularly limited, but a metal reflective layer is preferred. Examples of metals used for the metal reflective layer include Au, Pt, Ti, and Ag, with Au being particularly preferred. The thickness of the reflective layer 17 is not particularly limited, and can be, for example, set to 400-2000 nm. The method of forming the reflective layer 17 is not particularly limited, and examples include vapor deposition and sputtering.

[0217] The support substrate 16 is not particularly limited as long as it is a different type of substrate from the initial growth substrate 11 in the epitaxial growth substrate 1. Examples include substrates using semiconductor substrates such as Si and Ge, metal substrates such as Mo and Cu-W, and ceramic substrates such as AlN. The thickness of the support substrate 16 can be set to 100 μm or more, or 500 μm or less.

[0218] Alternatively, a metal bonding layer 18 can be provided on one side of the support substrate 16. By integrating the support substrate 16 with the metal bonding layer 18 onto the semiconductor laminate including the active layer 30 of the epitaxial growth substrate 1 via the reflective layer 17, reliable bonding can be achieved. In this case, the metal reflective layer and the metal bonding layer can be arranged opposite each other and bonded together, and then heat-compression bonding can be performed. The above-described support substrate bonding process is one example of this embodiment, and the method for manufacturing the optical semiconductor element of the present invention is not limited to this embodiment.

[0219] (Removal process of the substrate used for initial growth)

[0220] Next, as Figure 3 As shown in D, the initial growth substrate 11 is removed. For example, if the initial growth substrate 11 is an InP growth substrate, it can be removed by wet etching using hydrochloric acid. The epitaxial growth substrate 1 has an etch stop layer 12, so etching can be stopped at the etch stop layer 12. The hydrochloric acid is preferably hydrochloric acid with a concentration of 0.1% to 36%, but other chemicals can also be mixed in within a range that does not affect the etch selectivity.

[0221] The etch stop layer 12 can be removed by wet etching based on an etchant with a composition corresponding to that of the etch stop layer 12. For example, in the case where the etch stop layer 12 is an n-type InGaAs layer, it can be removed using a sulfuric acid-hydrogen peroxide based etchant.

[0222] Figure 4 This is part of the etch stop layer 12 remaining on the epitaxial growth substrate 1, and is an example of an optical semiconductor device used as the contact layer 12 for the upper surface electrode 40 of the optical semiconductor device. The etch stop layer 12 can also be removed without leaving any residue.

[0223] In addition, such as Figure 4 As shown, the light extraction surface of the window layer 15 of the optical semiconductor element can also be roughened by setting unevenness.

[0224] In this way, optical semiconductor devices can be obtained. For example... Figure 4 As shown, an upper surface electrode 40 can be formed on the contact layer 12 of the optical semiconductor element, and a back electrode 50 can be formed on the back side of the support substrate 16. The method for forming the upper surface electrode 40 and the back electrode 50 is not particularly limited, and for example, sputtering, vapor deposition, or resistance heating can be used.

[0225] In the method for manufacturing the optical semiconductor device of the present invention, a buffer is formed in the epitaxial growth substrate used for manufacturing, in a manner simulating a relaxed state of the substrate layer, thereby reducing the warpage of the initial growth substrate. Therefore, during the bonding of the support substrate to the epitaxial growth substrate and the removal of the initial growth substrate after bonding, crack formation in the laminate can be suppressed. The above-described initial growth substrate removal process is one example in this embodiment, and the method for manufacturing the optical semiconductor device of the present invention is not limited to this embodiment.

[0226] <Optical Semiconductor Components>

[0227] The following is for reference Figure 4 and Figure 7 The optical semiconductor element of the present invention is described herein, but the optical semiconductor element of the present invention is not limited thereto.

[0228] Here, Figure 7 Is Figure 4 The diagram shown illustrates a portion of the semiconductor stack and buffer stack extracted from an example of the semiconductor light-emitting element of the present invention. This diagram is a pattern illustrating the variation of the lattice constant of the semiconductor layers, where the width of each semiconductor layer in the horizontal direction relatively represents the magnitude of the lattice constant.

[0229] Figure 4 The optical semiconductor element 2 shown comprises, in sequence: a support substrate 16, a metal bonding layer 18, a reflective layer 17, an intermediate electrode portion 38, a dielectric layer 39, a p-type layer 37, an active layer 30, a simulated substrate layer 14, N buffer layers 13, a window layer 15, and a contact layer 12. Regarding each component, the description relating to the components marked with the same reference numerals in the description of the epitaxial growth substrate and its manufacturing method applies. Furthermore, the description of components not shown also applies to those described in the description of the epitaxial growth substrate and its manufacturing method.

[0230] The window layer 15 of the optical semiconductor element 2 is lattice matched with the initial growth substrate 11 of the epitaxial growth substrate 1, and the lattice constants are consistent. Therefore, the relationship between the optical semiconductor element and other components is the same as the relationship between the initial growth substrate 11 and other components in the epitaxial growth substrate 1.

[0231] The lattice constants of the simulated substrate layer 14 and window layer 15 are set to a, respectively. p and a t In the case of (a) p -a t ) / a t ×100 represents the mismatch between the simulated substrate layer 14 and the window layer 15. p·t It is 0.7% or more. From the viewpoint of increasing the wavelength range that can be designed in the formed semiconductor stack, it is preferably 1.0% or more.

[0232] Furthermore, the N buffer layers 13 are characterized by having 3 or more buffer layers containing mismatched dislocations on the window layer 15 side of the buffer layer.

[0233] Furthermore, the lattice constant of the nth buffer layer, counting from the buffer layer closest to the aforementioned window layer 15, is set to a. n Let the lattice constant of the (n+1)th buffer layer be a. n+1 Under the condition that, the following equation (1) is satisfied.

[0234] Satisfy a n <a n+1 (1),

[0235] In the above formula, n is a natural number from 1 to N-1, and n+1 is a natural number from 2 to N. When n is 1, the lattice constant a1 is greater than a. t When n+1 is N, it is related to a. n+1 The corresponding lattice constant a N The lattice constant a of the simulated substrate layer is less than that of the substrate layer. p .

[0236] Furthermore, in order to form mismatched dislocations and prevent through-dislocations, it is preferable to set the lattice constant of each of the N buffer layers relative to the mismatch degree of the layer (lower layer) adjacent to the window layer 15 as mismatch degree X. p·t The value obtained by dividing by N is more preferably set as the mismatch degree X. p·t The value obtained by dividing by 4N is greater than or equal to the value obtained by dividing by 4N. For example, the mismatch between each buffer layer and the underlying layer is preferably in the range of 0.15% to 0.35%.

[0237] In the optical semiconductor element of the present invention, by having a buffer layer stack as described above, the refractive index can be gradually reduced from the simulated substrate layer toward the window layer. In the N buffer layers 13, the refractive index varies depending on the composition ratio of each layer. Therefore, by using a semiconductor (e.g., InAsP) with a high refractive index on the simulated substrate side and the lowest refractive index in the window layer, which serves as the light extraction side, in the N buffer layers 13, the refractive index can be reduced toward the light extraction side, thereby improving light extraction efficiency.

[0238] As a constituent material in optical semiconductor devices, any compound semiconductor that meets the above conditions can be selected. For example, such a configuration can be configured as a stack of InP window layer, InAsP buffer layer, and InAsP simulation substrate layer.

[0239] In the optical semiconductor device of the present invention, the active layer 30 is a multiple quantum well (MQW) structure formed by alternately and repeatedly stacking well layers 35W and barrier layers 35B, wherein the lattice constant of the well layer 35W is set to a. wIn the case of a, a is preferred w The lattice constant a is greater than 15 for the window layer. t Among all the lattice constants of the semiconductor laminate and the buffer laminate, the lattice constant α of the well layer 35W is preferred. w Maximum. As a result, it is possible to improve photoluminescence (output).

[0240] Furthermore, the mismatch X between the well layer and the simulated substrate layer w·p Preferably, the concentration is 0.1% or more and less than 1.2%, more preferably less than 1.1%. By setting it within this range, the effect of improving photoluminescence (output) can be increased.

[0241] Furthermore, compressive strain is applied to the well layer 35W as described above. Compared to applying tensile strain, applying compressive strain to the well layer 35W improves photoluminescence (output) and luminous efficiency.

[0242] Furthermore, the mismatch X between the well layer and the simulated substrate layer is used. w·p and the values ​​of the well layer thickness, and the mismatch X between the barrier layer and the simulated substrate layer. b·p The values ​​of the barrier layer thickness are given by the following formula (3):

[0243] (X w·p × well layer thickness + X b·p (×barrier layer thickness) / (well layer thickness + barrier layer thickness)

[0244] The calculated average thickness mismatch value relative to the combined thickness of the well layer and barrier layer of the simulated substrate is preferably in the range of -0.09% to 0.46%, more preferably in the range of -0.02% to 0.36%. By subjecting the well layer to compressive stress from the simulated substrate and the barrier layer to tensile stress from the simulated substrate, the stresses are partially offset, thereby adjusting the aforementioned average thickness mismatch to this range, thereby increasing the improvement effect of photoluminescence (output).

[0245] Example

[0246] The present invention will be further described in detail below using examples, but the present invention is not limited to the following examples.

[0247] [First Trial]

[0248] <Example 1>

[0249] (Manufacturing of substrate 1 for epitaxial growth)

[0250] On the (100) surface of a Si-doped n-type InP substrate (3 inches, substrate thickness: 625 μm, lattice constant: 0.5869 nm), a Si-InP layer (initial growth layer) and a Si-In layer were sequentially formed using MOCVD with the film thicknesses shown in Table 2. 0.532 Ga 0.468 As layer (etch stop layer), Si-InP layer (n-type window layer for roughening). The composition of the etch stop layer matches the InP lattice.

[0251] Next, using trimethylindium (TMIn) as the In source, arsine (AsH3) as the As source, and phosphine (PH3) as the P source as the P source, a Si-InAsP layer was grown in the vapor phase using MOCVD while varying the amount of P in the raw material gas relative to the sum of As and P (P gas ratio). This process was repeated until the film thicknesses shown in Table 2 were achieved, forming buffer layers 1-1 to 1-7 and a simulated substrate layer. Each buffer layer consists of two buffer constituent layers (buffer constituent layers A1 to A7 and buffer constituent layers B1 to B7).

[0252] InAs in each buffer layer and analog substrate layer y P 1-y The As solid-state ratio y was determined by SIMS analysis after the buffer layer was formed, and the lattice constant a was calculated from the As solid-state ratio. The film thickness was confirmed by TEM.

[0253] For the obtained epitaxial growth substrate 1, the refractive indices of buffer layers 1-1 to 1-7 were calculated based on Corona Corporation's "III-V Semiconductor Mixed Crystals" formula P88 (2.108). Additionally, the mismatch X relative to the initial growth substrate was calculated. n·g And the mismatch relative to the lower layer on the substrate side of the initial growth. These are shown in Table 2.

[0254] [Table 2]

[0255]

[0256] XRD measurements were performed on the obtained epitaxial growth substrate 1, and the lattice constant q in the vertical direction was determined by reciprocal space mapping (RSM). z Horizontal lattice constant q x The simulation substrate layer was confirmed to be in a relaxed state. The (206) direction was determined using a Bruker X-ray diffraction apparatus D8, from which q was calculated. z q x The results are shown in Table 6.

[0257] In addition, the cross-section of the obtained epitaxial growth substrate 1 was exposed in the thickness direction and observed using a transmission electron microscope (TEM) (60kx magnification, 4.5μm×4.5μm field of view). Figure 8 The image shows a cross-section. In this image, black lines representing mismatch dislocations are identified at the interfaces between the roughening n-type window layer and the buffer layer 1-1, specifically on the initial growth substrate side of buffer layer 1-1, the initial growth substrate side of buffer layer 1-2, the initial growth substrate side of buffer layer 1-4, the initial growth substrate side of buffer layer 1-5, the initial growth substrate side of buffer layer 1-6, and the initial growth substrate side of buffer layer 1-7, at the portions where they connect to other layers with different lattice constants. On the other hand, no dislocations penetrating the buffer layers are identified. It should be noted that... Figure 8 Within the field of view, no black lines representing mismatched dislocations were identified on the initial growth substrate side of buffer layers 1-3.

[0258] Furthermore, for the epitaxial growth substrate 1, the surface of the simulated substrate layer was photographed using a metal microscope (magnification 5x, field of view 3mm×3mm). Figure 9 This image shows a top-down view. The image confirms a lattice-like pattern based on mismatch dislocations.

[0259] (Photoluminescence (PL) measurement and support substrate bonding test based on the fabrication of semiconductor laminate 1 and fabrication of opto-semiconductor devices)

[0260] First, in order to investigate which type of epitaxial growth substrate is preferred, a semiconductor stack 1 was formed on the epitaxial growth substrate 1, and PL measurement and SORI and support substrate bonding tests were performed for evaluation. Examples of such semiconductor stacks 1 formed on the epitaxial growth substrate 1 shown in Table 2 are shown in Table 3.

[0261] [Table 3]

[0262]

[0263] Then, a 980nm wavelength, 100mW laser was used to irradiate the light using a photoluminescence measuring device (RPMBlue manufactured by Onto Innovation), and the intensity and wavelength of the excited light were measured. Additionally, the SORI (μm) specified in SEMI M1-0302 was determined. Next, an Au reflective layer was formed across the entire surface by sputtering. An Au layer was pre-formed on the upper surface of the support substrate by sputtering as a metal bonding layer. Pressure was applied while heating at 315°C to test whether the support substrate could be bonded via Au-Au bonding. The results are shown in Table 6.

[0264] The evaluation of the support substrate bonding process in Table 6 is as follows.

[0265] A… achieves a bonding rate of over 90% (approximately 100%) without cracking.

[0266] B…sometimes a bond can be formed without cracking, but this occurs in less than 90% of cases.

[0267] C… cannot be joined without causing cracks.

[0268] (Manufacturing of Opto-Semiconductor Component 1)

[0269] Next, an experiment was conducted to obtain the optical semiconductor element 1 through the manufacturing method of the optical semiconductor element. An example in which a semiconductor stack 1 for forming the optical semiconductor element 1 is formed on the epitaxial growth substrate shown in Table 2 is also shown in Table 3. Table 3 also shows the state after the removal process of the initial growth substrate, and the bottom of the table shows the light extraction direction.

[0270] Specifically, after forming the semiconductor stack as described in Table 3, an intermediate electrode layer (AuZn) is formed on the p-type second contact layer described in Table 3 by sputtering. Patterning is then performed by photolithography to create an intermediate electrode portion consisting of island-shaped p-type second contact layers and an intermediate electrode layer. Next, after patterning by photolithography, a dielectric layer composed of SiO2 is formed by plasma CVD. Only the dielectric layer covering the intermediate electrode portion is removed, and an Au reflective layer is formed over the entire surface by sputtering. An Au layer is pre-formed on the upper surface of the support substrate as a metal bonding layer by sputtering. Pressure is applied while heating at 315°C to bond the support substrate via Au-Au bonding. Then, after etching away the initial growth substrate using a hydrochloric acid-based etchant, an etch stop layer is removed except for the area forming the upper surface electrode using a photolithography-based patterning and phosphoric acid-hydrogen peroxide-based etchant. The remaining island-shaped etch stop layer is used as a contact layer, and an upper surface electrode (AuGe) is formed on this contact layer. After forming a mesa shape by etching the buffer laminate and semiconductor laminate along a predetermined cutting line, the support substrate is cut off, thereby obtaining the optical semiconductor element 1 of Example 1.

[0271] When using the epitaxial growth substrate 1 in Example 1, no bonding defects or cracks are generated during the support substrate bonding process, and no cracks are generated during the subsequent initial growth substrate removal process.

[0272] The lattice constant α of the window layer of the obtained optical semiconductor device 1 t The lattice constant a of the well layer is 0.5869 nm. w It is 0.5977nm.

[0273] <Example 2>

[0274] In Example 1, instead of the N=7 buffer layers consisting of buffer layers 1-1 to 1-7, N=7 buffer layers consisting of single-layer buffer layers 2-1 to 2-7 were used. A simulated substrate layer was formed under the conditions shown in Table 4. Otherwise, an epitaxial growth substrate 2 was fabricated in the same manner as in Example 1, and a semiconductor stack 1 was formed on the epitaxial growth substrate. PL measurement and SORI and support substrate bonding tests were performed for evaluation. The results are shown in Table 6.

[0275] It should be noted that in Table 6, the excitation light intensity of PL in Example 1 is set to 1.00, and the excitation light intensities of other examples and comparative examples are recorded as relative values ​​to Example 1.

[0276] The buffer layers 2-1 to 2-7 are obtained by using the In source, P source and As source described in Example 1, setting the P gas phase ratio to the values ​​shown in Table 4, and performing vapor phase growth by MOCVD until the film thickness shown in Table 4 is reached.

[0277] Determine the lattice constant q in the perpendicular direction as calculated by reciprocal space mapping (RSM). z Horizontal lattice constant q x The simulation substrate layer was confirmed to be in a relaxed state. In cross-sectional TEM observation, black lines representing mismatch dislocations were identified between the roughening n-type window layer and buffer layer 2-1, and between each buffer layer. Specifically, black lines representing mismatch dislocations were identified at the junctions with other layers having different lattice constants on the initial growth substrate side of N=7 buffer layers. On the other hand, no dislocations penetrating the buffer layers were identified.

[0278] In this example, although the SORI is larger compared to Example 1, the support substrate bonds well, and crack formation in the laminate is suppressed. Therefore, subsequent fabrication of optical semiconductor devices is also possible.

[0279] [Table 4]

[0280]

[0281] <Example 3>

[0282] In Example 1, instead of the buffer composed of buffer layers 1-1 to 1-7, a buffer composed of single-layer buffer layers 3-1 to 3-4 was used. A simulated substrate layer was formed under the conditions shown in Table 5. Otherwise, an epitaxial growth substrate 3 was fabricated in the same manner as in Example 1, and a semiconductor stack 1 was formed on the epitaxial growth substrate. PL measurement and SORI and support substrate bonding tests were performed for evaluation. The results are shown in Table 6.

[0283] The buffer layers 3-1 to 3-4 are obtained by using the In source, P source and As source described in Example 1, setting the P gas phase ratio to the value shown in Table 5, and performing vapor phase growth by MOCVD until the film thickness shown in Table 5 is reached.

[0284] Determine the lattice constant q in the perpendicular direction as calculated by reciprocal space mapping (RSM). z Horizontal lattice constant q x The simulation substrate layer was confirmed to be in a relaxed state. In cross-sectional TEM observation, black lines representing mismatch dislocations were identified between the roughening n-type window layer and buffer layer 3-1, and between each buffer layer. Specifically, black lines representing mismatch dislocations were identified in the portions where the N=4 buffer layers connect to other layers with different lattice constants on the initial growth substrate side.

[0285] In this example, although SORI is larger compared to Example 1, the support substrate is well bonded, and crack generation in the laminate is also suppressed.

[0286] Therefore, it is also possible to manufacture subsequent optical semiconductor devices.

[0287] [Table 5]

[0288]

[0289] <Comparative Example 1>

[0290] Without forming N buffer layers, the epitaxial growth substrate 1' was obtained in the same manner as in Example 1. Since cracks were observed visually in the simulated substrate layer, reciprocal space mapping measurement and cross-sectional observation using TEM were not performed. A semiconductor stack 1 was formed on the epitaxial growth substrate and evaluated. In this example, SORI was too large to be measured, and the support substrate could not be bonded. Furthermore, cracks were also observed in the semiconductor stack 1, PL did not emit light, and the fabrication of the optical semiconductor device was not carried out. The results are shown in Table 6.

[0291] <Comparative Example 2>

[0292] In Example 2, instead of the buffer composed of buffer layers 2-1 to 2-7, a raw material gas was supplied in a manner that continuously varied from the initial growth substrate side to the simulated substrate layer side in terms of the P-gas ratio, forming a buffer with a film thickness of 1645 nm. The simulated substrate layer was formed under the same conditions as in Table 4. Otherwise, an epitaxial growth substrate 2' was obtained in the same manner as in Example 2. A semiconductor stack 1 was formed on the epitaxial growth substrate, and PL measurements and SORI and support substrate bonding tests were performed in the same manner as in Example 2. The results are shown in Table 6.

[0293] Determine the lattice constant q in the perpendicular direction as calculated by reciprocal space mapping (RSM).z Horizontal lattice constant q x The lattice constant difference was greater than in Examples 1-3. In cross-sectional TEM observation, no layer boundaries were observed, and no black lines representing mismatched dislocations were identified. However, dislocations penetrating the entire buffer were confirmed. In this example, SORI increased significantly compared to Example 1, and poor bonding was observed in approximately half of the bonding attempts with the support substrate. Therefore, the fabrication of the optoelectronic semiconductor device was not carried out.

[0294] [Table 6]

[0295]

[0296] [Second Test]

[0297] In the first experiment above, in order to find an epitaxial growth substrate that could support substrate bonding and substrate removal, the composition ratio of the simulated substrate was fixed, and the N buffer layers were changed.

[0298] In the second experiment below, using the epitaxial growth substrate of Example 1 as a reference, a semiconductor stack 2 as shown in Table 7 was grown on the epitaxial growth substrate, and the PL intensity was measured. The relationship between the simulated substrate and the well layer in the semiconductor stack was investigated by changing the amount of N and the composition ratio of the simulated substrate. The variations in the amount of N and the composition ratio of the simulated substrate are illustrated in Table 8, and the results of the investigation on the effects of the mismatch caused by the difference in the lattice constants of the simulated substrate and the well layer, and the variations in the type of stress on the well layer, on SORI, BOW, and PL intensity are shown in Table 9. For N=3 and N=9, which are not shown in Table 8, the variations in the amount of N and the composition ratio of the simulated substrate shown in Table 8 were also applied.

[0299] [Table 7]

[0300]

[0301] [Table 8]

[0302]

[0303] [Table 9]

[0304]

[0305] Table 9 shows the experimental results for two cases: one with the design wavelength of the well layer set to 2100 nm and the other with 2300 nm. In both experiments, the excitation light intensity of PL was set to 1.00 when N=7, and the excitation light intensity for other N values ​​was recorded as a relative value. Table 9 shows that the SORI of the epitaxial growth substrate after forming the semiconductor stack 2 is generally low, and the evaluation of the substrate bonding process is A (the proportion of bonding without cracking is over 90% (approximately 100%)). However, the PL intensity of the well layer decreases under tensile stress. Furthermore, based on the magnitude of the PL intensity, it is preferable for the well layer to be subjected to compressive stress, and thus, the mismatch X between the well layer and the simulated substrate layer is... w·p Preferably, it is 0.1% or more and less than 1.2%, more preferably less than 1.1%.

[0306] [Third Trial]

[0307] Next, using the epitaxial growth substrate of Example 1, the composition of the well layer was changed to alter the design wavelength in the semiconductor stack 2 shown in Table 7. The As solid-state ratio and lattice constant of the barrier layer were also changed to alter the stress between the well layer and the barrier layer. Otherwise, the investigation was conducted in the same manner as in the second experiment. In the semiconductor stack 2 of Table 7, the barrier layer used the same composition as the simulated substrate layer. In the third experiment, on the simulated substrate layer listed in Table 7 with N=7, the composition of the well layer was changed accordingly to the wavelength, as shown in Table 10. A 10.5-pair quantum well structure was formed while changing the As solid-state ratio y of the barrier layer. Based on this, the same p-type layer as in Table 7 was formed, resulting in semiconductor stacks with wavelengths of 2450 nm, 2600 nm, and 2700 nm. At a wavelength of 2450 nm, the well layer composition used was In... 0.90 Ga 0.10 As, at 2600nm, the well layer composition uses In 0.92 Ga 0.08 As, the composition of the well layer at 2700nm uses In 0.94 Ga 0.06 As shown in Table 10, the PL intensity, SORI, and BOW were measured, and the results confirming the bonding with the support substrate are presented together with the lattice constants of the formed well and barrier layers and the mismatch of these layers relative to the simulated substrate layers. It should be noted that the well layer thickness was 10 nm and the barrier layer thickness was 10 nm.

[0308] [Table 10]

[0309]

[0310] As shown in Table 10, the relative intensity of the PL (Power Point) when the barrier layer and the simulated substrate layer have no lattice constant difference (assumed to have the same composition) is set to 1, using the mismatch X between the well layer and the simulated substrate layer. w·p and the values ​​of the well layer thickness, and the mismatch X between the barrier layer and the simulated substrate layer. b·p The values ​​of the barrier layer thickness are given by the following formula (3):

[0311] (X w·p × well layer thickness + X b·p (×barrier layer thickness) / (well layer thickness + barrier layer thickness)

[0312] The calculated average thickness mismatch of the well layer and barrier layer relative to the simulated substrate layer is preferably in the range of -0.09% to 0.46%, more preferably in the range of -0.02% to 0.36%. This is because, as shown in Table 9, the mismatch X of the well layer relative to the simulated substrate layer... w·p The compressive stress is set to be greater than 0.1% and less than 1.2%, and the lattice constant of the barrier layer is set so that the tensile stress is offset by the compressive stress on the well layer. This improves the crystallinity within the quantum well structure and enables a large PL strength.

[0313] Figure 10 This represents the change in PL intensity (relative intensity) relative to the average thickness mismatch of the combined well and barrier layers.

[0314] Explanation of reference numerals in the attached figures

[0315] 1. Substrate for epitaxial growth

[0316] 2 Optical semiconductor components

[0317] 11. Substrate for initial growth

[0318] 12. Etching stop layer (contact layer)

[0319] 13 N buffer layers

[0320] 14 Simulated substrate layer

[0321] 15 Other layers (window layers)

[0322] 16 Supporting substrate

[0323] 17. Reflective layer

[0324] 18 Metal bonding layer

[0325] 30 Active layer

[0326] 35B barrier layer

[0327] 35W well layer

[0328] 37 p-type layer

[0329] 38 Intermediate electrode section

[0330] 39 Dielectric layer

[0331] 40 Upper surface electrode

[0332] 50 Back electrode

Claims

1. A substrate for epitaxial growth, comprising: Initial growth substrate, The etch stop layer on the initial growth substrate, and The buffer stack on the etch stop layer The buffer stack comprises: N buffer layers with different lattice constants, and a simulated substrate layer with a thickness of 300 nm or more on the N buffer layers. The lattice constant of the initial growth substrate is set to a. g The lattice constant of the simulated substrate layer is set to a. p In the case of the simulated substrate layer relative to the initial growth substrate, the mismatch X p·g It is above 0.7%. N is a natural number greater than or equal to 3. The epitaxial growth substrate has three or more buffer layers containing mismatched dislocations on the initial growth substrate side of the buffer layer.

2. The substrate for epitaxial growth according to claim 1, wherein, The lattice constant in the vertical direction of the simulated substrate layer, calculated according to the reciprocal space mapping, is set as q. z Let the lattice constant in the horizontal direction be q. x Under the condition that the following equation (2) is satisfied: -0.0002≤q z -q x ≤0.0011 (2)。 3. The substrate for epitaxial growth according to claim 1, wherein, A grid-like pattern was observed when a top view of the surface of the simulated substrate layer was taken using a metal microscope.

4. The substrate for epitaxial growth according to claim 1, wherein, Let a be the lattice constant of the nth buffer layer, counting from the buffer layer located closest to the initial growth substrate. n Let the lattice constant of the (n+1)th buffer layer be a. n+1 Under the condition that the following equation (1) is satisfied: a n <a n+1 (1), In the above formula, n is 1 to N-1. When n is 1, the lattice constant a1 is greater than the aforementioned a g , The lattice constant a when n+1 is N N Less than the a p , Let the mismatch degree of each of the N buffer layers relative to the layer adjacent to it on the initial growth substrate side be the mismatch degree X. p·g The value obtained by dividing by N is as follows.

5. The substrate for epitaxial growth according to claim 1, wherein, The buffer layers are composed of one or more buffer layers, and the thickness of each buffer layer is 150 nm or more.

6. The substrate for epitaxial growth according to claim 4, wherein, At least one buffer layer consists of multiple buffer component layers. Compared to buffer layer B, which is located closest to the initial growth substrate within the buffer layer, buffer layer A, located closest to the simulated substrate layer within the buffer layer, is thicker. Here, the lattice constant of the buffer layer in equation (1) is the lattice constant of the buffer constituting layer A.

7. The substrate for epitaxial growth according to claim 6, wherein, The thickness of the buffer layer A is 100 nm or more, and the thickness of the buffer layer B is less than half the thickness of the buffer layer A.

8. The substrate for epitaxial growth according to claim 1, wherein, The initial growth substrate is an InP substrate, and the etch stop layer is an InGaAs layer.

9. The substrate for epitaxial growth according to claim 1, wherein, The initial growth substrate is an InP substrate, the buffer stack is a stack of multiple InAsP layers, and the buffer stack also has an InP window layer connected to the etch stop layer.

10. A method for manufacturing an optical semiconductor device, comprising: The process of forming a semiconductor stack including an active layer on a simulated substrate layer of an epitaxial growth substrate according to any one of claims 1 to 9; The process of bonding a support substrate to the semiconductor stack via a reflective layer; and, The process of removing the initial growth substrate of the epitaxial growth substrate.

11. The method for manufacturing an optical semiconductor element according to claim 10, wherein, The SORI value on the surface side of the semiconductor stack on the simulated substrate layer obtained by the process of forming the semiconductor stack is less than 30 μm.

12. An optical semiconductor device, comprising, in sequence: a support substrate, a reflective layer, a semiconductor laminate including an active layer, and a buffer laminate. The buffer stack comprises, in sequence: a simulated substrate layer with a thickness of 300 nm or more, N buffer layers, and a window layer, wherein the window layer is located on the light extraction side. The lattice constants of the simulated substrate layer and the window layer are respectively set to a. p and a t In the case of mismatch X between the simulated substrate layer and the window layer p·t It is above 0.7%. N is a natural number greater than or equal to 3. The optical semiconductor element has: three or more buffer layers containing mismatched dislocations on the window side of the buffer layer.

13. The optical semiconductor element according to claim 12, wherein, Let the lattice constant of the nth buffer layer, counting from the buffer layer closest to the window layer, be a. n Let the lattice constant of the (n+1)th buffer layer be a. n+1 Under the condition that the following equation (1) is satisfied: a n <a n+1 (1), In the above formula, n is 1 to N-1. When n is 1, the lattice constant a1 is greater than the aforementioned a t , The lattice constant a when n+1 is N N Less than the a p , Let the mismatch degree of each of the N buffer layers relative to the layer adjacent to it on the window layer side be the mismatch degree X. p·t The value obtained by dividing by N is as follows.

14. The optical semiconductor element according to claim 12, wherein, The refractive index gradually decreases from the simulated substrate layer toward the window layer.

15. The optical semiconductor element according to claim 12, wherein, The window layer is InP, the buffer stack is a stack of multiple InAsP layers, and the simulation substrate layer is an InAsP layer.

16. The optical semiconductor element according to claim 12, wherein, The light-emitting center wavelength of the active layer in the semiconductor stack is 2000~3000nm.

17. The optical semiconductor element according to claim 12, wherein, The active layer has a quantum well structure, when the lattice constant of the well layer is set to a. w hour, The mismatch X between the well layer and the simulated substrate layer w·p It is above 0.1% and less than 1.2%.

18. The optical semiconductor element according to claim 17, wherein, In the lattice constants of the semiconductor stack and the buffer stack, the lattice constant a of the well layer of the active layer is... w maximum.

19. The optical semiconductor element according to claim 12, wherein, The buffer layers are composed of one or more buffer layers, and the thickness of each buffer layer is 150 nm or more.

20. The optical semiconductor element according to claim 13, wherein, At least one buffer layer consists of multiple buffer component layers. Compared to buffer layer B, which is located closest to the initial growth substrate within the buffer layer, buffer layer A, located closest to the simulated substrate layer within the buffer layer, is thicker. Here, the lattice constant of the buffer layer in equation (1) is the lattice constant of the buffer constituting layer A.

21. The optical semiconductor element according to claim 17, wherein, When the lattice constant of the barrier layer of the active layer is set to a b Let the mismatch between the barrier layer and the simulated substrate layer be X. b·p In the case of mismatch X between the well layer and the simulated substrate layer, w·p and the mismatch X between the barrier layer and the simulated substrate layer b·p The calculated average thickness mismatch between the well layer and the barrier layer is in the range of -0.09% to 0.46%.

Images