Wafer-level device testing device
The wafer-level device testing equipment solves the problems of time and cost loss caused by post-packaging testing, and realizes reliable and accurate dynamic on-resistance measurement at the wafer level, ensuring the safety and compatibility of the testing instruments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BOE HUACAN OPTOELECTRONICS (GUANGDONG) CO LTD
- Filing Date
- 2025-12-23
- Publication Date
- 2026-05-08
AI Technical Summary
Existing technologies for testing the dynamic on-resistance of gallium nitride transistors after packaging suffer from losses in testing time and cost, and it is difficult to perform accurate measurements at the wafer level.
A wafer-level device testing device is provided, including a pin card, a power supply, a power supply protection module, a drive protection module, a load module, a current acquisition module, and a clamping module. These modules are connected to the device under test (DUT) to realize the measurement of dynamic on-resistance and protect the test circuit when the DUT breaks down or short-circuits.
It enables reliable and accurate dynamic on-resistance testing at the wafer level, avoiding the time and cost losses associated with post-packaging testing, expanding the compatibility of the testing platform, and ensuring the safety and repeatability of the testing instruments.
Smart Images
Figure CN121995110A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of testing technology, and in particular to a wafer-level device testing apparatus. Background Technology
[0002] Gallium nitride transistors are widely used in the field of power electronics due to their advantages of high power and low loss.
[0003] During the design process, the variation in dynamic on-resistance of gallium nitride (GaN) transistors is one of the more significant issues affecting their development. To accurately measure this variation under different stress conditions, many test platforms for dynamic on-resistance are designed for post-packaging testing.
[0004] However, post-packaging testing requires the prior packaging of gallium nitride transistors, resulting in losses in packaging time and cost during testing. Summary of the Invention
[0005] This disclosure provides a wafer-level device testing apparatus capable of testing wafer-level devices. The technical solution is as follows: On one hand, a wafer-level device testing apparatus is provided, the apparatus comprising: Pin connectors are used to connect to the device under test. Power supply, used to provide electrical signals; The power supply protection module is electrically connected between the power supply and the pin card. It is used to provide a drain drive signal to the device under test based on the electrical signal, and to stop providing the drain drive signal to the device under test when the device under test is broken down or short-circuited. A drive protection module is electrically connected between the power supply and the pin card, and is used to provide a gate drive signal to the device under test based on the electrical signal. The load module is electrically connected between the power supply protection module and the pin card, and is used to connect a load device. The current acquisition module is electrically connected between the pin and ground, and is used to acquire the leakage source current of the device under test; The clamping module, electrically connected to the pin card, is used to extract the clamping drain-source voltage of the device under test from the drain drive signal; An oscilloscope is electrically connected to the current acquisition module and the clamping module, respectively, and is used to measure the dynamic on-resistance of the device under test by measuring the drain-source current and the clamping drain-source voltage of the device under test.
[0006] Optionally, the device further includes a test circuit board and a power supply circuit board, the test circuit board and the power supply circuit board being electrically connected via ports; The test circuit board includes a pin connector port and an oscilloscope port. The pin connector is electrically connected to the test circuit board through the pin connector port, and the oscilloscope is electrically connected to the test circuit board through the oscilloscope port. The drive protection module, the load module, the current acquisition module, and the clamping module are located on the test circuit board; The power supply protection module is located on the power supply circuit board, and the power supply circuit board is electrically connected to the power source.
[0007] Optionally, the pin card port includes a drain power input pin, a drain detection pin, an empty pin, two gate signal control pins, a source detection pin, and a source power input pin; The drain power input pin and the source power input pin are located at two ends; The drain detection pin, the empty pin, the two gate signal control pins, and the source detection pin are located between the drain power input pin and the source power input pin; The drain detection pin, the empty pin, and the source detection pin are arranged in one row, and the two gate signal control pins are arranged in another row.
[0008] Optionally, the oscilloscope ports include a drain-source current port and a clamp drain-source voltage port; The device further includes an oscilloscope protection module electrically connected between the clamp drain-source voltage port and the source power input pin.
[0009] Optionally, the power supply protection module includes: a first isolated gate driver, a reset circuit, a PWM control loop, an enable circuit, and an LED indicator circuit; The first isolated gate driver is electrically connected between the power supply and the drain power input pin, and the reset circuit, the PWM control loop, the enable circuit and the LED indicator circuit are respectively electrically connected to the first isolated gate driver.
[0010] Optionally, the load module includes: Diode D1, the positive terminal of diode D1 is electrically connected to the drain power input pin, and the negative terminal of diode D1 is electrically connected to the power supply protection module; An inductor or resistor is connected in parallel with the diode D1.
[0011] Optionally, the clamping module includes: The MOSFET has its drain electrically connected to the drain power input pin and its source electrically connected to the clamp drain-source voltage port Vds_champ. Capacitor C12 is electrically connected between the drain and gate of the MOSFET; Resistor R13 is electrically connected between the drain and gate of the MOSFET; A second isolated gate driver is electrically connected between the power supply and the gate of the MOSFET.
[0012] Optionally, the device further includes: The first RC filter circuit is electrically connected between the clamp drain-source voltage port Vds_champ and the source power input pin.
[0013] Optionally, the device further includes: A protection diode D2 is provided, with its positive terminal electrically connected to the source power input pin and its negative terminal electrically connected to the clamp drain-source voltage port Vds_champ.
[0014] Optionally, the device further includes: The second RC filter circuit is electrically connected between the output terminal of the power supply protection module and ground.
[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: In the wafer-level device testing apparatus provided in this embodiment, the device under test (DUT) is connected to the wafer-level DUT via a pin connector to enable testing. After connection, a drain drive signal is provided by a power supply protection module, and a gate drive signal is provided by a drive protection module to drive the DUT. Simultaneously, a load device is connected via a load module to simulate the actual operating scenario of the DUT. In this case, the drain-source current of the DUT is acquired by a current acquisition module, the clamping drain-source voltage of the DUT is extracted by a clamping module, and the dynamic on-resistance is measured by an oscilloscope to complete the wafer-level DUT testing.
[0016] The power supply protection module stops supplying drain drive signals to the device under test (DUT) when it is broken down or short-circuited, protecting the entire test circuit. The drive protection module provides gate drive protection to prevent damage to the DUT when it is inserted into the pin clip. The clamping circuit enables the rapid response of the entire test device, ensuring the testing accuracy of high-frequency switching power transistors. Through these multi-level protections and rapid response, the safe use of the oscilloscope module is guaranteed, realizing a repeatable and highly reliable dynamic on-resistance testing platform. This expands the platform's compatibility with various instruments and equipment, allowing power devices to overcome the current collapse problem caused by dynamic on-circuit issues during R&D without being limited by test instruments. This enables the device to demonstrate its characteristics in real-world applications, achieve accurate evaluation, and continuously improve device performance. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the structure of a wafer-level device testing apparatus provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the module distribution of the wafer-level device testing apparatus provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the pin card port provided in an embodiment of this disclosure; Figure 4 This is a partial circuit diagram of the wafer-level device testing apparatus provided in an embodiment of this disclosure; Figure 5 This is a partial circuit diagram of the wafer-level device testing apparatus provided in an embodiment of this disclosure.
[0019] The attached figures are labeled as follows: 100: Pin card; 101: Power supply; 102: Power supply protection module; 103: Drive protection module; 104: Load module; 105: Current acquisition module; 106: Clamping module; 107: Oscilloscope; 108: Oscilloscope protection module; 109: First RC filter circuit; 110: Second RC filter circuit; 1: Drain power input pin; 2: Drain detection pin; 3: No pin; 4: Gate signal control pin; 5: Source detection pin; 6: Source power input pin; 10: Test circuit board; 11: Pin card port; 12: Oscilloscope port; 20: Power supply circuit board; 121: First isolated gate driver; 122: Reset circuit; 123: Pulse width modulation control loop; 124: Enable circuit; 125: LED indicator circuit; 141: Inductor or resistor; 161: Metal-oxide-semiconductor field-effect transistor; 162: Second isolated gate driver. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0021] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.
[0022] The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.
[0023] Similarly, words like "one" or "a" do not indicate a quantity limitation, but rather that at least one exists. Words like "include" or "contain" mean that the elements or objects preceding "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects.
[0024] Words like "connect" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms like "up," "down," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships; when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0025] Figure 1 This is a schematic diagram of a wafer-level device testing apparatus provided in an embodiment of this disclosure. See also... Figure 1 The device includes: a pin card 100, a power supply 101, a power supply protection module 102, a drive protection module 103, a load module 104, a current acquisition module 105, a clamping module 106, and an oscilloscope 107.
[0026] The pin connector 100 is used to connect to the device under test. The power supply 101 is used to provide electrical signals.
[0027] The power supply protection module 102 is electrically connected between the power supply 101 and the pin card 100. The power supply protection module 102 is used to provide a drain drive signal to the device under test based on the electrical signal, and to stop providing the drain drive signal to the device under test when the device under test is broken down or short-circuited.
[0028] The drive protection module 103 is electrically connected between the power supply 101 and the pin card 100. The drive protection module 103 is used to provide a gate drive signal to the device under test based on the electrical signal.
[0029] The load module 104 is electrically connected between the power supply protection module 102 and the pin card 100, and the load module 104 is used to connect to the load device.
[0030] The current acquisition module 105 is electrically connected between the pin 100 and ground. The current acquisition module 105 is used to acquire the drain-source current of the device under test.
[0031] The clamping module 106 is electrically connected to the pin card 100. The clamping module 106 is used to extract the clamping drain-source voltage of the device under test from the drain drive signal.
[0032] The oscilloscope 107 is electrically connected to the current acquisition module 105 and the clamping module 106 respectively. The oscilloscope 107 is used to measure the dynamic on-resistance of the device under test by using the drain-source current and the clamping drain-source voltage of the device under test.
[0033] In the wafer-level device testing apparatus provided in this embodiment, the device under test (DUT) is connected to the wafer-level DUT via a pin connector to enable testing. After connection, a drain drive signal is provided by a power supply protection module, and a gate drive signal is provided by a drive protection module to drive the DUT. Simultaneously, a load device is connected via a load module to simulate the actual operating scenario of the DUT. In this case, the drain-source current of the DUT is acquired by a current acquisition module, the clamping drain-source voltage of the DUT is extracted by a clamping module, and the dynamic on-resistance is measured by an oscilloscope to complete the wafer-level DUT testing.
[0034] The power supply protection module stops supplying drain drive signals to the device under test (DUT) when it is broken down or short-circuited, protecting the entire test circuit. The drive protection module provides gate drive protection to prevent damage to the DUT when it is inserted into the pin clip. The clamping circuit enables the rapid response of the entire test device, ensuring the testing accuracy of high-frequency switching power transistors. Through these multi-level protections and rapid response, the safe use of the oscilloscope module is guaranteed, realizing a repeatable and highly reliable dynamic on-resistance testing platform. This expands the platform's compatibility with various instruments and equipment, allowing power devices to overcome the current collapse problem caused by dynamic on-circuit issues during R&D without being limited by test instruments. This enables the device to demonstrate its characteristics in real-world applications, achieve accurate evaluation, and continuously improve device performance.
[0035] Among them, wafer-level devices refer to devices before they are packaged.
[0036] Figure 2 This is a schematic diagram of the module distribution of the wafer-level device testing apparatus provided in an embodiment of this disclosure. See also... Figure 2 The device also includes a test circuit board 10 and a power supply circuit board 20, which are electrically connected via ports.
[0037] The test circuit board 10 includes a pin card port 11 and an oscilloscope port 12. The pin card 100 is electrically connected to the test circuit board 10 through the pin card port 11, and the oscilloscope 107 is electrically connected to the test circuit board 10 through the oscilloscope port 12.
[0038] The drive protection module 103, the load module 104, the current acquisition module 105, and the clamping module 106 are located on the test circuit board 10.
[0039] The power supply protection module 102 is located on the power supply circuit board 20, and the power supply circuit board 20 is electrically connected to the power supply 101.
[0040] In this implementation, the above modules are distributed using a test circuit board 10 and a power supply circuit board 20, and the pin card 100 and oscilloscope 107 are connected by setting up ports, which facilitates the design and assembly of the test device.
[0041] In this embodiment of the disclosure, the test circuit board 10 and the power supply circuit board 20 can be printed circuit boards (PCBs). The above modules are integrated on the PCB via integrated circuits.
[0042] Figure 3 This is a schematic diagram of the pin card port provided in an embodiment of this disclosure. See also... Figure 3 The pin card port 11 includes a drain power input pin 1, a drain detection pin 2, an empty pin 3, two gate signal control pins 4, a source detection pin 5, and a source power input pin 6.
[0043] The drain power input pin and the source power input pin are located at opposite ends; the drain detection pin, the empty pin, the two gate signal control pins, and the source detection pin are located between the drain power input pin and the source power input pin; the drain detection pin, the empty pin, and the source detection pin are arranged in one row, and the two gate signal control pins are arranged in another row.
[0044] Pin 3 is not connected to any signal. Drain power input pin 1 is connected to the drain drive signal, the two gate signal control pins 4 are connected to the gate drive signal, and source power input pin 6 is grounded.
[0045] In this implementation, the above-mentioned pin arrangement and pin control effectively avoid interference between the drain power input pin and the source power input pin on the gate signal control pin and the source detection pin.
[0046] In this embodiment of the disclosure, the oscilloscope port 12 includes a drain-source current port Ids and a clamp drain-source voltage port Vds_champ.
[0047] The oscilloscope can acquire the drain-source current and clamp drain-source voltage through the two ports mentioned above, and then measure the dynamic resistance.
[0048] Additionally, the drain-source current port Ids and the clamp drain-source voltage port Vds_champ can be two Sub-Miniature Version A (SMA) connectors. Oscilloscope port 12 uses impedance control to reduce the oscilloscope impedance from 50Ω to 10Ω, increasing test accuracy.
[0049] In this embodiment of the disclosure, the pin card 100 has pins identical to the pins of the pin card port, and the same pins are connected accordingly. Furthermore, the pin card can be detachably electrically connected to the device under test (DUT, such as a gallium nitride transistor).
[0050] In this embodiment of the disclosure, the power module can be a programmable DC power supply, such as the IT6500 series wide-range high-power programmable DC power supply.
[0051] Figure 4 This is a partial circuit diagram of the wafer-level device testing apparatus provided in an embodiment of this disclosure. See also... Figure 4 The power supply protection module 102 includes: a first isolated gate driver 121, a reset circuit 122, a pulse width modulation (PWM) control loop 123, an enable circuit 124, and a light-emitting diode (LED) indicator circuit 125.
[0052] The first isolated gate driver 121 is electrically connected between the power supply 101 and the drain power input pin 1. The reset circuit 122, the PWM control loop 123, the enable circuit 124 and the LED indicator circuit 125 are respectively electrically connected to the first isolated gate driver 121.
[0053] The input of the first isolated gate driver 121 is connected to the power supply 101, and the output is connected to the drain power input pin 1, which in turn is connected to the pin card 100.
[0054] In this power supply protection module 102, the first isolated gate driver 121 provides a drive signal and implements overcurrent protection. The reset circuit 122 can perform a forced reset after a fault. The PWM control loop 123 can be used for active power-off. The enable circuit 124 can select whether to use the power supply protection module 102. The LED indicator circuit 125 is used to indicate the test device's status, for example, green for normal and red for abnormal.
[0055] The first isolated gate driver 121 can be an 1ED3321MC12N isolated gate driver. This gate driver includes multiple functional pins. The reset circuit 122, the PWM control loop 123, the enable circuit 124, and the LED indicator circuit 125 are respectively connected to a portion of the above-mentioned multiple functional pins, which will not be described in detail here.
[0056] In this embodiment of the disclosure, the drive protection module 103 is used not only to drive the device under test, but also to protect the device under test.
[0057] For example, the drive protection module 103 includes an SI8271DB-ISR type isolated gate driver, which implements drive and protection functions.
[0058] Figure 5 This is a partial circuit diagram of the wafer-level device testing apparatus provided in an embodiment of this disclosure. See also... Figure 5 The load module 104 includes a diode D1 and an inductor or resistor 141.
[0059] The positive terminal of diode D1 is electrically connected to the drain power input pin 1, and the negative terminal of diode D1 is electrically connected to the power supply protection module 102; the inductor or resistor 141 is connected in parallel with diode D1.
[0060] In this system, an inductor or resistor serves as the load device to simulate the actual application scenario of the device under test. The resistor / inductor is connected in parallel with the diode to allow the energy stored in the resistor / inductor to flow freely during the off-state.
[0061] See you again Figure 5 The current acquisition module 105 includes resistors R17 and R18.
[0062] Among them, resistor R17 is a 4-terminal resistor.
[0063] Furthermore, the positive current terminal of resistor R17 is electrically connected to the source power input pin 6, and the negative current terminal of resistor R17 is grounded. The positive voltage terminal of resistor R17 is electrically connected to the drain-source current port Ids, and the negative voltage terminal of resistor R17 is electrically connected to one end of resistor R18, while the other end of resistor R18 is grounded.
[0064] For example, the resistance value of resistor R18 can be 40~60Ω, such as 50Ω.
[0065] See you again Figure 5The clamping module 106 includes: a metal-oxide-semiconductor field-effect transistor (MOSFET) 161, a capacitor C12, a resistor R13, and a second isolated gate driver 162.
[0066] The drain of MOSFET 161 is electrically connected to the drain power input pin 1, and the source of MOSFET 161 is electrically connected to the clamp drain-source voltage port Vds_champ; capacitor C12 is electrically connected between the drain and gate of MOSFET 161; resistor R13 is electrically connected between the drain and gate of MOSFET 161; and second isolated gate driver 162 is electrically connected between the power supply 101 and the gate of MOSFET 161.
[0067] like Figure 5 As shown, the circuit also includes a monitoring port Vgs_Clamp and a monitoring port SOURCE for monitoring the circuit.
[0068] For example, the drain of MOSFET 161 is electrically connected to drain power input pin 1 through resistor R11.
[0069] For example, the resistance value of resistor R11 can be 0.8~1.2Ω, such as 1Ω.
[0070] During the test startup phase, the device under test is first turned on by the drive protection module 103, and then the MOSFET 161 is turned on by the second isolated gate driver 162.
[0071] At the end of the test, the device under test is first turned off by the drive protection module 103, and then the MOSFET 161 is turned off by the second isolated gate driver 162.
[0072] The above control method can prevent excessive current from passing through the clamping module, thereby achieving isolation between the two sides of the clamping module 106. Furthermore, the clamping module 106, through the combination of MOSFET 161, capacitor C12, resistor R13, and the second isolated gate driver 162, realizes the extraction of the clamping drain-source voltage.
[0073] For example, the capacitance C12 can be 80~120pF, such as 100pF.
[0074] For example, the resistance value of resistor R13 can be 8~12KΩ, such as 10KΩ.
[0075] For example, the second isolated gate driver 162 may be an SI8271DB-ISR type isolated gate driver.
[0076] In one implementation of this disclosure, the oscilloscope 107 can be a software module integrated into a computer device, which acquires the collected current and voltage signals, calculates the dynamic on-resistance, and outputs the waveform.
[0077] In another implementation of the present disclosure, the oscilloscope 107 can be any type of oscilloscope with a bandwidth of 350MHz or higher, thereby enabling the detection of the dynamic conductivity resistance of the transistor under test.
[0078] See you again Figure 5 The device may also include: an oscilloscope protection module 108.
[0079] The oscilloscope protection module 108 is electrically connected between the clamp drain-source voltage port Vds_champ and the source power input pin 6.
[0080] In this implementation, the oscilloscope's test channel is protected by setting an oscilloscope protection module 108.
[0081] like Figure 5 As shown, the oscilloscope protection module 108 includes resistors R12, R15, and R16. Capacitor R12 is electrically connected between the clamping module 106 and the clamping drain-source voltage port Vds_champ. Resistor R15 is electrically connected between the clamping drain-source voltage port Vds_champ and the source power input pin 6. Resistor R16 and resistor R15 are connected in parallel.
[0082] For example, the resistance value of resistor R12 can be 40~60Ω, such as 50Ω.
[0083] For example, the resistance value of resistors R15 to R16 can be 80 to 120Ω, such as 100Ω.
[0084] The resistors R15 and R16 are set for impedance matching and to protect the oscilloscope. When the device burns out, the voltage that the oscilloscope is subjected to is lower, thus protecting the oscilloscope channel.
[0085] See you again Figure 5 The device also includes a first RC filter circuit 109.
[0086] The first RC filter circuit 109 is electrically connected between the clamp drain-source voltage port Vds_champ and the source power input pin 6.
[0087] In this implementation, the clamping drain-source voltage signal output by the clamping module is filtered by the first RC filter circuit.
[0088] like Figure 5 As shown, the first RC filter circuit 109 includes capacitor C16, capacitor C17 and resistor R14. Capacitor C16 is electrically connected between the clamp drain-source voltage port Vds_champ and the source power input pin 6. The branch formed by capacitor C17 and resistor R14 connected in series is electrically connected between the clamp drain-source voltage port Vds_champ and the source power input pin 6.
[0089] For example, the capacitance C16 can be 2 to 2.4 nF, such as 2.2 nF.
[0090] For example, the capacitance of capacitor C17 can be 80~120nF, such as 100nF.
[0091] For example, the resistance of resistor 14 can be 80~120Ω, such as 100Ω.
[0092] See you again Figure 5 The device also includes a protection diode D2.
[0093] The positive terminal of the protection diode D2 is electrically connected to the source power input pin 6, and the negative terminal of the protection diode D2 is electrically connected to the clamp drain-source voltage port Vds_champ.
[0094] In this implementation, the clamping module is protected by setting a protection diode D2.
[0095] like Figure 5 As shown, the protection diode D2 is electrically connected between the clamp drain-source voltage port Vds_champ and the source power input pin 6.
[0096] For example, the protection diode D2 is a DFLS1200-7 type diode.
[0097] See you again Figure 5 The device also includes a second RC filter circuit 110.
[0098] The second RC filter circuit 110 is electrically connected between the output terminal of the power supply protection module 102 and ground.
[0099] In this implementation, the input voltage is stabilized and noise interference is removed by a second RC filter circuit.
[0100] like Figure 5As shown, the second RC filter circuit 110 includes capacitors C13, C14, and C15, resistors R9 and R10. Capacitor C13 is electrically connected between the output terminal of the power supply protection module 102 and ground. The branch formed by capacitor C14 and resistor R9 connected in series is electrically connected between the output terminal of the power supply protection module 102 and ground. The branch formed by capacitor C15 and resistor R10 connected in series is also electrically connected between the output terminal of the power supply protection module 102 and ground. That is, the second RC filter circuit 110 includes three parallel branches.
[0101] For example, the capacitance of capacitors C13 to C15 can be 80 to 120 nF, such as 100 nF.
[0102] For example, the resistance value of resistors R9 to R10 can be 80 to 120Ω, such as 100Ω.
[0103] The wafer-level device testing apparatus provided in this embodiment follows the following testing procedure: The first step is to connect the pin card to the device under test.
[0104] The second step is to set the number of pulses through the power supply protection module, such as 10 Pulse / continuous Pulse.
[0105] The third step is to set the clamping module to turn on after the device under test (DUT) is turned on, and turn off after the DUT is turned off.
[0106] The fourth step is to connect the load, such as a 400Ω resistor.
[0107] Fifth step, connect to a high-voltage power supply, such as a 400V power supply.
[0108] Step 6: Start the pulse test.
[0109] Step 7: Read the value of the dynamic on-resistance Rdson (Vds_clamp / Ids) on the oscilloscope.
[0110] Step 8: Power off. Switch to the next device under test and repeat the cycle.
[0111] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A wafer-level device testing apparatus, characterized in that, The device includes: Pin clip (100) is used to connect to the device under test; Power supply (101) is used to provide electrical signals; The power supply protection module (102) is electrically connected between the power supply (101) and the pin card (100) and is used to provide a drain drive signal to the device under test based on the electrical signal, and to stop providing the drain drive signal to the device under test when the device under test is broken down or short-circuited. The drive protection module (103) is electrically connected between the power supply (101) and the pin card (100) and is used to provide a gate drive signal to the device under test based on the electrical signal. The load module (104) is electrically connected between the power supply protection module (102) and the pin card (100) for connecting to the load device; The current acquisition module (105) is electrically connected between the pin clip (100) and ground, and is used to acquire the leakage source current of the device under test; The clamping module (106) is electrically connected to the pin card (100) and is used to extract the clamping drain-source voltage of the device under test from the drain drive signal; An oscilloscope (107) is electrically connected to the current acquisition module (105) and the clamping module (106) respectively, and is used to measure the dynamic on-resistance of the device under test by the drain-source current and the clamping drain-source voltage of the device under test.
2. The apparatus according to claim 1, characterized in that, The device further includes a test circuit board (10) and a power supply circuit board (20), the test circuit board (10) and the power supply circuit board (20) being electrically connected via ports; The test circuit board (10) includes a pin card port (11) and an oscilloscope port (12). The pin card (100) is electrically connected to the test circuit board (10) through the pin card port (11), and the oscilloscope (107) is electrically connected to the test circuit board (10) through the oscilloscope port (12). The drive protection module (103), the load module (104), the current acquisition module (105), and the clamping module (106) are located on the test circuit board (10); The power supply protection module (102) is located on the power supply circuit board (20), and the power supply circuit board (20) is electrically connected to the power supply (101).
3. The apparatus according to claim 2, characterized in that, The pin card port (11) includes a drain power input pin (1), a drain detection pin (2), an empty pin (3), two gate signal control pins (4), a source detection pin (5), and a source power input pin (6). The drain power input pin (1) and the source power input pin (6) are located at opposite ends; The drain detection pin (2), the empty pin (3), the two gate signal control pins (4) and the source detection pin (5) are located between the drain power input pin (1) and the source power input pin (6); The drain detection pin (2), the empty pin (3) and the source detection pin (5) are arranged in one row, and the two gate signal control pins (4) are arranged in another row.
4. The apparatus according to claim 3, characterized in that, The oscilloscope port (12) includes a drain-source current port Ids and a clamp drain-source voltage port Vds_champ; The device further includes an oscilloscope protection module (108) electrically connected between the clamp drain-source voltage port Vds_champ and the source power input pin (6).
5. The apparatus according to claim 3, characterized in that, The power supply protection module (102) includes: a first isolated gate driver (121), a reset circuit (122), a PWM control loop (123), an enable circuit (124), and an LED indicator circuit (125). The first isolated gate driver (121) is electrically connected between the power supply (101) and the drain power input pin (1), and the reset circuit (122), the PWM control loop (123), the enable circuit (124) and the LED indicator circuit (125) are respectively electrically connected to the first isolated gate driver (121).
6. The apparatus according to claim 3, characterized in that, The load module (104) includes: Diode D1, the positive terminal of diode D1 is electrically connected to the drain power input pin (1), and the negative terminal of diode D1 is electrically connected to the power supply protection module (102); An inductor or resistor (141) is connected in parallel with the diode D1.
7. The apparatus according to claim 3, characterized in that, The clamping module (106) includes: MOSFET (161), the drain of the MOSFET (161) is electrically connected to the drain power input pin (1), and the source of the MOSFET (161) is electrically connected to the clamp drain-source voltage port Vds_champ; Capacitor C12 is electrically connected between the drain and gate of the MOSFET (161); Resistor R13 is electrically connected between the drain and gate of the MOSFET (161); The second isolated gate driver (162) is electrically connected between the power supply (101) and the gate of the MOSFET (161).
8. The apparatus according to any one of claims 3 to 7, characterized in that, The device further includes: The first RC filter circuit (109) is electrically connected between the clamp drain-source voltage port Vds_champ and the source power input pin (6).
9. The apparatus according to any one of claims 3 to 7, characterized in that, The device further includes: The protection diode D2 is electrically connected to the source power input pin (6) and the negative terminal of the protection diode D2 is electrically connected to the clamp drain-source voltage port Vds_champ.
10. The apparatus according to any one of claims 1 to 7, characterized in that, The device further includes: The second RC filter circuit (110) is electrically connected between the output terminal of the power supply protection module (102) and ground.