Multi-channel signal and power analyzer

Abstract

The invention relates to a multi-channel signal and power analyzer. A signal and power analysis instrument includes: one or more high bandwidth input channels configured as one or more actual equivalent time (RET) input channels and / or one or more radio frequency (RF) channels; one or more input channels configured as one or more low bandwidth real time (RT) input channels; one or more analog-to-digital converters (ADCs) having conduits, a first set of conduits connected to the one or more high-bandwidth input channels to generate high-bandwidth data and a second set of conduits connected to the one or more low-bandwidth RT input channels to generate low-bandwidth RT data, a system clock connected to the high-bandwidth input channels and the low-bandwidth RT input channels, a memory connected to the system clock, the first set of pipes and the second set of pipes, and one or more processors storing the low bandwidth RT data and the high bandwidth data in the memory and aligning the high bandwidth data and the low bandwidth data.

Description

[0001] Cross-references to related applications This disclosure is a non-provisional application filed on November 8, 2024, entitled “MULTI-CHANNEL SIGNAL AND POWER ANALYZER”, and claims the benefit of that provisional application, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to test and measurement instruments, and more specifically, to multi-channel combined signal and power analysis instruments. Background Technology

[0003] With the development of generative artificial intelligence, data centers, electric vehicles (EVs), 5G / 6G wireless, and quantum computing, the demand for instruments with high channel counts and the ability to perform combined signal integrity (SI) and power integrity (PI) analysis is constantly increasing. High-speed wired data transmission enables generative AI and data centers to cope with ever-increasing data demands, requiring higher power to support data transmission and processing. Industry standards such as IEEE Ethernet 800G require high-analog bandwidth oscilloscopes to measure their signal integrity. Power supplies require oscilloscopes with much lower analog bandwidth to measure power integrity. Because there is a correlation between signal integrity (SI) and power integrity (PI), an instrument capable of capturing time-dependent signals for SI / PI analysis will allow users to gain a deeper understanding of their designs. Unmet needs exist in EVs, 5G / 6G wireless, and quantum computing, requiring an instrument to capture and analyze time-dependent time-domain signals, RF signals, and power signals.

[0004] The demand for such instruments stems from several factors. Advances in generative artificial intelligence have spurred significant developments in high-performance computing infrastructure, including GPU clusters for LLM training and large data centers providing data storage, processing, and transmission. These applications require higher power. The global adoption of electric vehicles has increased the demand for power analysis instruments. Modern vehicles are equipped with high-speed wired and wireless data communication systems to transmit video, radar, and other sensor data. The increasing number of qubits being built into quantum computing systems, with hundreds or thousands of qubits in quantum computers, necessitates spectrum analyzers with high channel counts. 5G and 6G wireless testing demands even higher channel counts from spectrum analyzers due to their use of massively multi-input multiple-output (MIMO) architectures.

[0005] Signal integrity (SI) analysis is required for high-speed time-domain signals such as 800G PAM4 Ethernet signals and high-bandwidth RF signals such as 5G and 6G wireless signals. Power supply and motors require power integrity (PI) analysis. The interaction between power supply and signal paths requires SI / PI analysis. SI / PI analysis is initially performed through simulation during the system design phase. When the actual system is produced, test instruments are used to verify the design and debug the system.

[0006] U.S. Patent No. 11,789,051, entitled "Real-equivalent-time oscilloscope" and published on October 17, 2023, describes a new class of oscilloscopes, namely the Real-Equivalent-Time (RET) oscilloscope, the contents of which are incorporated herein by reference in their entirety. RET oscilloscopes use only a single ADC with a low sampling rate per channel, thus significantly reducing complexity and cost compared to conventional real-time oscilloscopes, which typically have multiple interleaved ADCs to achieve higher sampling rates. U.S. Patent Application Publication No. 2024 / 0313795, filed February 29, 2024, entitled "Real-Equivalent-Time Oscilloscope and Wideband Real-Time Spectrum Analyzer," describes a new class of instruments, the contents of which are incorporated herein by reference in their entirety. This new class of instruments utilizes the RET oscilloscope architecture described in U.S. Patent No. 11,789,051 to enable the instrument to also function as a real-time spectrum analyzer. Embodiments of this disclosure utilize the techniques described in U.S. Patent No. 11,789,051 and U.S. Patent Application Publication No. 2024 / 0313795. Attached Figure Description

[0007] Figure 1 An example of a signal and power analysis instrument is shown.

[0008] Figure 2 A block diagram illustrating an embodiment of signal and power analysis is shown.

[0009] Figure 3 A block diagram illustrating an embodiment of the channel architecture for a signal and power analysis instrument is shown.

[0010] Figure 4 An example of a spectrum diagram of a signal caused by a power integrity problem is shown. Detailed Implementation

[0011] The embodiments described here relate to a new instrument referred to herein as a Signal and Power Analyzer (SPA). Generally, an SPA will have a higher channel count, and its system clock allows for synchronized signal capture across all channels. Each channel of the instrument can be configured as a high analog bandwidth equivalent time sampling oscilloscope channel, a high bandwidth real-time spectrum analyzer channel, or a lower analog bandwidth real-time oscilloscope channel. The unique architecture of the SPA enables high channel density, lower cost, and lower power consumption. A single SPA unit serves both the power market and the wired and wireless data communications markets.

[0012] SPA has many uses, but one particular application involves combined analysis of signal and power integrity at the same time. For example... Figure 1 As shown, the ability to perform signal integrity and power integrity analysis in a combined manner allows designers to understand the impact of power integrity issues on signals. High-speed time-domain signals 10, such as 800G PAM4 Ethernet signals, and high-bandwidth RF signals 10, such as 5G and 6G wireless signals, require signal integrity (SI) analysis 12. Power supplies and motors that generate power signals 14 require power integrity (PI) analysis 16. The interaction between power and signal paths requires SI / PI analysis 18. SI / PI analysis initially occurs during simulations during the system design phase. When the actual system is running, two different instruments are currently required, such as a higher-bandwidth real-time oscilloscope for signal capture and a lower-bandwidth real-time oscilloscope for power signals. Due to the use of two separate instruments, obtaining accurate time-related views on both instruments presents a challenge.

[0013] The embodiments described here involve more than just a combination of two separate instruments. They provide time alignment of the time-domain and frequency-domain signals, allowing designers to understand the effects of power and data signals on each other, thereby providing designers with the ability to build and troubleshoot more robust systems.

[0014] Figure 2 A diagram illustrating one embodiment of a SPA test and measurement instrument is shown. Instrument 20 includes one or more ports, such as 24, which can be any electrical or optical signaling medium. Ports such as 24 can include receivers, transmitters, and / or transceivers. Each port 24 includes a channel for the test and measurement instrument. The structure surrounded by 22 is repeated for each channel of the instrument.

[0015] The signal from the port is then sent to vertical offset 26, which adjusts the offset or baseline of the received signal. In some configurations or examples, vertical gain / offset 26 may also include vertical gain adjustment. Without vertical gain adjustment, vertical noise can be reduced, but dynamic range will also be reduced. To address this, in some examples, an external attenuator and / or amplifier can be used to attenuate and / or amplify the input signal under test. The signal is sent from vertical gain / offset 26 to sampler track-and-hold circuitry 28. Track-and-hold circuitry 28 samples each signal and holds each signal steady for a period of time sufficient for an analog-to-digital converter (ADC) such as 30 to acquire it.

[0016] In this embodiment, ADC 30 is one of a group of one or more ADCs. ADCs include ADC “pools,” and each ADC may have one or more “pipelines,” such as 31. This embodiment treats ADC pipelines as individual ADCs that can be connected to channels of various configurations typically controlled by processor 40. In an example of a currently available oscilloscope, a 4-channel real-time (RT) oscilloscope with a total of 100 GS / s (gigasamples / second) ADCs would get 100 / 4 = 25 GS / s per channel if the user turns on all four channels. If the user turns on only two channels, each channel would get 100 / 2 = 50 GS / s. In the instrumentation of this embodiment, there are wires and switches, such as switch array 32, that implement the various channels and ADC paths.

[0017] ADC 30 converts the analog data signal and / or power signal from track-and-hold circuit 28 into digital signal data and power data. The digitized signal from ADC converter 30 can then be stored in acquisition memory 34. ADC 30 can be a single high-resolution ADC, such as a 12-bit analog-to-digital converter with multiple channels. Different channels can be connected to multiple channels in a single ADC, such as 31, or multiple channels across different ADCs. These embodiments do not require any specific configuration of the ADC and channels.

[0018] One or more processors 40 may be configured to execute instructions from memory and may perform any methods and / or related steps indicated by such instructions, such as receiving acquired signals from acquisition memory 34 and reconstructing the measured signal without using hardware triggers, or acquiring samples at a high sampling rate.

[0019] The memory 34 or any other memory on the test and measurement instrument 20 can be implemented as a processor cache, random access memory (RAM), read-only memory (ROM), solid-state memory, one or more hard disk drives, or any other type of memory. The memory acts as a medium for storing data, computer program products, and other instructions.

[0020] User input 38 is coupled to one or more processors 40. User input 38 may include a keyboard, mouse, trackball, touchscreen, and / or any other controls that a user can use to interact with a GUI on display 36. Display 36 may be a digital screen, a cathode ray tube-based display, or any other monitor to display waveforms, measurements, and other data to the user. Although components of the test and measurement instrument are described as being integrated within test and measurement instrument 20, those skilled in the art will understand that any of these components may be external to test and measurement instrument 20 and may be coupled to test and measurement instrument 20 in any conventional manner, such as wired and / or wireless communication media and / or mechanisms. For example, in some examples, display 36 may be located remotely from test and measurement instrument 20.

[0021] The SPA implementation features configurable channels. These configurations come in four different types. The system can have one or more real-time (RT) channels. As two types of RT channels, each RT channel can include either a high sampling rate / high bandwidth channel or a low sampling rate / low bandwidth channel as two RT channel types. High-bandwidth RT channels require a large number of ADCs. Low-bandwidth RT channels require fewer ADCs, and the real-time equivalent time (RET) channel with high bandwidth and low sampling rate belongs to the third type. The fourth type of channel is a radio frequency (RF) channel with high bandwidth and low sampling rate. High-bandwidth RT channels typically digitize the entire waveform at once using one or more ADCs with a sufficiently high sampling rate to capture the signal in real time. RET channels have low sampling rates and high bandwidth. They typically sample the input signal at a sampling rate lower than the required Nyquist frequency in multiple iterations of a repetitive pattern, then perform software clock recovery and reconstruct the signal in an equivalent time sense. RF channels will typically require at least two pipes to digitize a high-bandwidth input signal at a low sampling rate.

[0022] An SPA is configured to have one or more high-bandwidth channels, including at least one or more RET channels and one or more RF channels, and low-bandwidth RT channels. An SPA may combine one or both of the RET and RF channels with one or more low-bandwidth RT channels. In another embodiment, the high-bandwidth channels include high-bandwidth RT channels. High-bandwidth channels may include RET and(one or more) RF channels,(one or more) RET and high-bandwidth RT channels,(one or more) RF and high-bandwidth RT channels, or combinations of RET, RF, and(one or more) high-bandwidth RT channels. Any configured high-bandwidth channel is combined with(one or more) low-bandwidth RT channels.

[0023] To facilitate understanding, consider this example. A sampler for a high-bandwidth RT channel is connected to a set of multiple ADCs or pipes. In one example, this could be assumed to be from one ADC or 16 pipes from multiple ADCs. These 16 pipes can be interleaved, providing a high combined ADC sampling rate for the high-bandwidth RT channel. A sampler for a RET channel is connected to a second set of pipes or ADCs, which may contain one or just a few ADC pipes, resulting in a combined ADC sampling rate significantly lower than that of the high-bandwidth RT channel. The RET channel can support sampling high analog bandwidth, just like the RT channel. The instrumentation in this example provides multiple channels that can be configured as RET channels, RF channels, low-bandwidth RT channels, and high-bandwidth RT channels. For signal and power analysis, the low-bandwidth RT channel can be connected to a power signal from the device under test (DUT) or the power supply supplying the DUT. The RET, RF, and high-bandwidth RT channels can be connected to one or more data signals from the DUT. The combination of the two inputs allows for combined power integrity / signal integrity analysis.

[0024] Figure 3 An embodiment of the overall architecture of a multi-channel SPA instrument according to embodiments of the present disclosure is shown. Because the lower ADC sampling rate supports RET / RF channels, they require fewer hardware components and consume less power. Therefore, a single SPA instrument can contain multiple channels. An SPA may have a higher channel count compared to a similarly sized RT oscilloscope or a similarly sized RT spectrum analyzer with the same analog bandwidth. The RET / RF channels are used for signal integrity (SI) analysis. Each channel (e.g., 50 and 52) can also be configured as a real-time (RT) channel, just like conventional real-time oscilloscope channels. The low-bandwidth RT channels can be used for power integrity (PI) analysis. Because system clock 54 drives all channels in the instrument, all channel acquisitions are synchronized. System clock information is stored together with the acquired channel data in acquisition memory 34. The time-correlated acquisition data with system clock 54 information enables accurate and consistent real-time combined SI / PI analysis.

[0025] As an example, the device under test (DUT) 56 can be connected to a first channel 50, which in this example is configured as a RET data input channel for signal integrity. This will allow the channel to operate at high analog bandwidth and capture data signals. ADC and / or ADC pipelines (such as...) Figure 2 The data signal (shown as a pipe) is then converted into signal data. One or more processors then reconstruct the complete data from the signal data and store it in memory. Meanwhile, power supply 58 is connected to the input channel configured as a low analog bandwidth RT channel to capture a power signal, which is then converted into power data to distinguish it from the signal data from the DUT. Power supply 58 can be located on the DUT or can include an external power supply. Each channel will have a set of ADCs or ADC pipes connected to it; the high bandwidth RT channel will have more ADCs than the RET and RF channels, and the low bandwidth RT channel may also have more. As an example, a high bandwidth RT channel requires 64 pipes, a RET channel requires 1 pipe, and an RF channel requires 2 pipes. The high bandwidth RT channel requires more pipes than the RET or RF channels.

[0026] Figure 4 An example of a scenario where a Spatial Optimizer (SPA) can provide numerous benefits to the design is shown. The spectrum plot shows the unexpected transient response of the oscillator that occurred before the 1.2µs time mark (horizontal axis). The spectrum data was captured by a high-bandwidth real-time oscilloscope. The designer spent some time before determining that the transient response was caused by a power supply problem. The designer had to use a second, lower-bandwidth real-time oscilloscope to debug the power supply. The SPA implementation described here allows for quick and confident identification of the problem. Power supply problems and oscillator transient responses can be captured in a time-dependent manner. Triggers in the time or frequency domain can be used to align signal and power data to help users quickly identify anomalies.

[0027] The embodiments described herein disclose a novel SPA instrument. The SPA provides higher channel counts and time-correlated acquisition in a single instrument, enabling real-time combined SI / PI analysis.

[0028] Various aspects of this disclosure can operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers including processors that operate according to programmed instructions. The terms controller or processor as used herein are intended to include microprocessors, microcomputers, application-specific integrated circuits (ASICs), and special-purpose hardware controllers. One or more aspects of this disclosure can be embodied in computer-usable data and computer-executable instructions, such as in one or more program modules executed by one or more computers (including monitoring modules) or other devices. Typically, program modules include routines, programs, objects, components, data structures, etc., which perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. Computer-executable instructions can be stored on non-transitory computer-readable media, such as hard disks, optical disks, removable storage media, solid-state storage, random access memory (RAM), etc. As those skilled in the art will understand, the functionality of a program module can be combined or distributed in various aspects as needed. Furthermore, this functionality can be wholly or partially embodied in firmware or hardware equivalents, such as integrated circuits, FPGAs, etc. Specific data structures can be used to more efficiently implement one or more aspects of this disclosure, and such data structures are contemplated within the scope of the computer-executable instructions and computer-usable data described herein.

[0029] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried or stored on one or more non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, a computer-readable medium means any medium accessible by a computing device. By way of example and not limitation, a computer-readable medium may include computer storage media and communication media.

[0030] Computer storage media refers to any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, optical disc read-only memory (CD-ROM), digital video disc (DVD) or other optical disc storage, magnetic tape cassettes, magnetic tape, disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable medium implemented in any technology. Computer storage media does not include the signal itself or the temporary form of signal transmission.

[0031] A communication medium is any medium that can be used to transmit computer-readable information. By way of example and not limitation, a communication medium may include coaxial cable, fiber optic cable, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0032] Example The following provides illustrative examples of the disclosed techniques. Embodiments of these techniques may include one or more of the examples below, as well as any combination thereof.

[0033] Example 1 is a signal and power analysis instrument comprising: one or more high-bandwidth input channels configured to be connected to at least one of one or more Real-Time Equivalent Time (RET) input channels or one or more radio frequency (RF) channels of a device under test (DUT); one or more input channels configured as one or more low-bandwidth real-time (RT) input channels; one or more analog-to-digital converters (ADCs), each ADC having one or more pipes, a first set of one or more pipes connected to one or more high-bandwidth input channels to generate high-bandwidth data, and a second set of one or more pipes connected to one or more low-bandwidth RT input channels to generate low-bandwidth data; a system clock connected to one or more high-bandwidth input channels and one or more low-bandwidth RT input channels; a memory connected to the system clock, the first set of one or more pipes connected to one or more high-bandwidth input channels, and the second set of one or more pipes connected to one or more low-bandwidth RT input channels; and one or more processors configured to execute code that causes the one or more processors to: store low-bandwidth data from the second set of pipes in memory; store high-bandwidth data from the first set of pipes in memory; and time-align the high-bandwidth data and low-bandwidth data using the system clock.

[0034] Example 2 is a signal and power analysis instrument of Example 1, wherein one or more high-bandwidth input channels include one or more RET input channels and one or more RF input channels, RET input channels only, or RF input channels only.

[0035] Example 3 is a signal and power analysis instrument of Example 1 or 2, wherein one or more high-bandwidth input channels further include one or more high-bandwidth RT input signal channels, and the instrument further includes a third set of pipes connected to one or more high-bandwidth RT input signal channels.

[0036] Example 4 is a signal and power analysis instrument of Example 3, wherein one or more high-bandwidth input channels include one or more RET input channels and one or more high-bandwidth RT input channels, one or more RF input channels and one or more high-bandwidth RT channels, or one or more RET input channels, one or more RF input channels and one or more high-bandwidth RT input channels.

[0037] Example 5 is a signal and power analysis instrument of Example 3, wherein one or more high-bandwidth input channels include one or more RET input channels, and the first set of pipes includes fewer pipes than the third set of pipes.

[0038] Example 6 is a signal and power analysis instrument of any of Examples 1 to 5, wherein one or more high-bandwidth input channels are configured to receive one or more signals from the DUT, and the high-bandwidth data includes signal data.

[0039] Example 7 is a signal and power analysis instrument similar to that of Example 6, wherein one or more low-bandwidth RT input channels are configured to be connected to a power supply that powers the DUT, and the low-bandwidth RT data includes power data.

[0040] Example 8 is a signal and power analysis instrument of Example 7, wherein the code that enables one or more processors to align high-bandwidth data and low-bandwidth data in time includes code that aligns power data and signal data by using a system clock.

[0041] Example 9 is a signal and power analysis instrument like that of Example 6, wherein the signal data includes at least one of RET data and RF data.

[0042] Example 10 is a signal and power analysis instrument like that of Example 6, wherein the signal data includes at least one of RET, RF, and high-bandwidth RT data.

[0043] Example 11 is a method for performing signal integrity and power integrity analysis, comprising: receiving one or more signals from one or more input channels configured as one or more low-bandwidth real-time (RT) input channels; receiving one or more signals from a device under test (DUT) from one or more high-bandwidth input channels configured as one or more real-time equivalent time (RET) input channels and radio frequency (RF) input channels; generating low-bandwidth RT data using a first set of one or more analog-to-digital converter (ADC) pipes connected to one or more low-bandwidth RT input channels; generating high-bandwidth data using a second set of one or more ADC pipes connected to one or more high-bandwidth input channels; storing the high-bandwidth data and low-bandwidth RT data in an acquisition memory; and aligning the low-bandwidth RT data and high-bandwidth data in time using a system clock.

[0044] Example 12 is a method of Example 11, wherein receiving a signal from one or more high-bandwidth input channels includes receiving a signal from one or more RET input channels and one or more RF input channels, receiving a signal from only one or more RET input channels, or receiving a signal from only one or more RF input channels.

[0045] Example 13 is a method of either Example 11 or 12, and further includes receiving one or more signals from one or more high-bandwidth RT input channels and using a third set of ADC pipes connected to one or more high-bandwidth RT input channels.

[0046] Example 14 is a method of Example 13, wherein receiving one or more signals from one or more high-bandwidth channels may include receiving one or more signals from one or more RET input channels and one or more high-bandwidth RT input channels, one or more RF input channels and one or more high-bandwidth RT channels, or one or more RET input channels, one or more RF input channels and one or more high-bandwidth RT input channels.

[0047] Example 15 is a method of Example 13, wherein one or more high-bandwidth input channels include one or more RET input channels, and the first group of pipes includes fewer pipes than the third group of pipes.

[0048] Example 16 is a method of Example 13, wherein receiving one or more signals from the DUT includes receiving one or more signals of at least one of RET, RF and high-bandwidth RT signals.

[0049] Example 17 is a method of any of Examples 11 to 16, wherein receiving one or more signals from the DUT from one or more high-bandwidth input channels includes receiving signal data.

[0050] Example 18 is a method of Example 17, wherein receiving one or more signals from one or more low-bandwidth RT input channels includes receiving one or more signals from a power supply that powers the DUT, and receiving one or more signals from one or more low-bandwidth RT channels includes receiving power data.

[0051] Example 19 is the method of Example 18, wherein aligning low-bandwidth RT data and high-bandwidth data in time includes aligning power data and signal data.

[0052] Example 20 is the method of Example 19, and also includes performing signal integrity and power integrity analysis on time-aligned power data and signal data.

[0053] All features disclosed in the specification, including the claims, abstract, and drawings, and all steps in any disclosed method or process, may be combined in any combination, except for combinations in which at least some of such features and / or steps are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in the specification (including the claims, abstract, and drawings) may be replaced by an alternative feature for the same, equivalent, or similar purpose.

[0054] Furthermore, this written description references specific features. It should be understood that the disclosure in this specification includes all possible combinations of these specific features. For example, where a specific feature is disclosed in the context of a particular aspect, that feature can also be used in the context of other aspects to the greatest extent possible.

[0055] Furthermore, when a method having two or more defined steps or operations is mentioned in this application, the defined steps or operations may be performed in any order or simultaneously, unless the context precludes those possibilities.

[0056] Although specific examples of the invention have been illustrated and described for illustrative purposes, it should be understood that various modifications can be made without departing from the spirit and scope of the invention. Therefore, the invention should not be limited except for the appended claims.

Claims

1. A signal and power analysis instrument, comprising: One or more high-bandwidth input channels are configured to be connected to at least one of one or more Real-Time Equivalent Time (RET) input channels or one or more radio frequency (RF) channels of the device under test (DUT). One or more input channels are configured as one or more low-bandwidth real-time (RT) input channels; One or more analog-to-digital converters (ADCs), each ADC having one or more pipes, a first set of one or more pipes connected to one or more high-bandwidth input channels to generate high-bandwidth data, and a second set of one or more pipes connected to one or more low-bandwidth RT input channels to generate low-bandwidth data; A system clock connected to one or more high-bandwidth input channels and one or more low-bandwidth RT input channels; The memory is connected to the system clock; a first group of one or more pipes is connected to one or more high-bandwidth input channels, and a second group of one or more pipes is connected to one or more low-bandwidth RT input channels. and One or more processors are configured to execute code that causes the one or more processors to: Low-bandwidth data from the second set of pipes is stored in memory; High-bandwidth data from the first set of pipes is stored in memory; and Use the system clock to time-align high-bandwidth data and low-bandwidth data.

2. The signal and power analyzer of claim 1, wherein the one or more high-bandwidth input channels include one or more RET input channels and one or more RF input channels, RET-only input channels, or RF-only input channels.

3. The signal and power analysis instrument of claim 1, wherein the one or more high-bandwidth input channels further include one or more high-bandwidth RT input signal channels, and the instrument further includes a third set of pipes connected to the one or more high-bandwidth RT input signal channels.

4. The signal and power analysis instrument according to claim 3, wherein, The one or more high-bandwidth input channels include one or more RET input channels and one or more high-bandwidth RT input channels, one or more RF input channels and one or more high-bandwidth RT channels, or one or more RET input channels, one or more RF input channels and one or more high-bandwidth RT input channels.

5. The signal and power analyzer of claim 3, wherein the one or more high-bandwidth input channels include one or more RET input channels, and the first set of pipes includes fewer pipes than the third set of pipes.

6. The signal and power analysis instrument according to claim 1, wherein, The one or more high-bandwidth input channels are configured to receive one or more signals from the DUT, and the high-bandwidth data includes signal data.

7. The signal and power analysis instrument of claim 6, wherein the one or more low-bandwidth RT input channels are configured to be connected to a power supply supplying the DUT, and the low-bandwidth data includes power data.

8. The signal and power analyzer according to claim 7, wherein, The code that enables the one or more processors to align high-bandwidth data and low-bandwidth data in time includes code that aligns power data and signal data by using a system clock.

9. The signal and power analyzer of claim 6, wherein the signal data includes at least one of RET data and RF data.

10. The signal and power analysis instrument of claim 6, wherein the signal data includes at least one of RET, RF, and high-bandwidth RT data.

11. A method for performing signal integrity and power integrity analysis, comprising: Receive one or more signals from one or more input channels configured as one or more low-bandwidth real-time (RT) input channels; Receive one or more signals from the device under test (DUT) from one or more high-bandwidth input channels configured as one or more of the real-time equivalent time (RET) input channel and radio frequency (RF) input channel; Low-bandwidth RT data is generated using a first set of one or more analog-to-digital converter (ADC) pipes connected to one or more low-bandwidth RT input channels; High-bandwidth data is generated by using a second set of one or more ADC pipes connected to one or more high-bandwidth input channels; High-bandwidth data and low-bandwidth RT data are stored in the acquisition memory; and Use the system clock to time-align low-bandwidth RT data and high-bandwidth data.

12. The method of claim 11, wherein receiving a signal from one or more high-bandwidth input channels includes receiving a signal from one or more RET input channels and one or more RF input channels, receiving a signal from only one or more RET input channels, or receiving a signal from only one or more RF input channels.

13. The method of claim 11, further comprising receiving one or more signals from one or more high-bandwidth RT input channels and using a third set of ADC pipes connected to one or more high-bandwidth RT input channels.

14. The method of claim 13, wherein receiving one or more signals from one or more high-bandwidth input channels can include receiving one or more of the following: receiving one or more signals from one or more RET input channels and one or more high-bandwidth RT input channels, one or more RF input channels and one or more high-bandwidth RT channels, or one or more RET input channels, one or more RF input channels and one or more high-bandwidth RT input channels.

15. The method of claim 13, wherein the one or more high-bandwidth input channels include one or more RET input channels, and the first set of pipes includes fewer pipes than the third set of pipes.

16. The method of claim 13, wherein receiving the one or more signals from the DUT comprises receiving one or more signals of at least one of RET, RF, and high-bandwidth RT signals.

17. The method of claim 11, wherein receiving one or more signals from the DUT from one or more high-bandwidth input channels includes receiving signal data.

18. The method of claim 17, wherein receiving one or more signals from the one or more low-bandwidth RT input channels includes receiving one or more signals from a power supply supplying the DUT, and receiving one or more signals from the one or more low-bandwidth RT channels includes receiving power data.

19. The method of claim 18, wherein aligning low-bandwidth RT data and high-bandwidth data in time includes aligning power data and signal data.

20. The method of claim 19, further comprising performing signal integrity and power integrity analysis on the time-aligned power data and signal data.

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