Method and system for testing clock chip

Abstract

The embodiment of the invention provides a method and system for testing a clock chip, and the method comprises the steps: controlling a power-on time sequence of multiple power supply domains, powering on a to-be-tested clock chip, recording a power-on surge current curve and a static power consumption spectrum of each power supply domain, and comprehensively determining the classification of the to-be-tested clock chip in combination with a digital interface, loading the initial configuration based on the classification; placing the to-be-tested clock chip in a high and low temperature box, adjusting the test temperature, calculating frequency precision errors at different temperatures, and dynamically optimizing a load capacitor based on the frequency precision errors to complete chip calibration; and testing the performance boundary, signal integrity and short-term reliability of the calibrated chip, and outputting a health score of the to-be-tested clock chip based on a test result.

Description

Technical Field

[0001] This invention relates to the field of clock chip technology, and in particular to a testing method and system for clock chips. Background Technology

[0002] Clock chips (such as crystal oscillators, phase-locked loops, clock generators / buffers, etc.) are the heart of electronic systems. Their core components include numerous data points. In mass production testing, each chip needs comprehensive testing to ensure it meets all specifications in the datasheet. Testing is conducted on expensive automated testing equipment, and the testing time directly determines the testing cost.

[0003] However, in the existing technology, the testing of clock chips usually adopts the traditional fixed sequence test, which performs the same time-consuming process on all chips, wasting a lot of time on inferior chips. Summary of the Invention

[0004] To address the problems existing in the prior art, embodiments of the present invention provide a testing method and system for clock chips.

[0005] This invention provides a method for testing a clock chip, the method comprising:

[0006] Control the power-on sequence of multiple power domains, power on the clock chip under test, record the power-on surge current curve and static power consumption spectrum of each power domain, and combine the digital interface to comprehensively determine the classification of the clock chip under test, and load the initial configuration based on this classification.

[0007] The clock chip under test is placed in a high and low temperature chamber, the test temperature is adjusted, the frequency accuracy error at different temperatures is calculated, and the load capacitance is dynamically optimized based on the frequency accuracy error to complete the chip calibration.

[0008] The test chip is evaluated for its performance limits, signal integrity, and short-term reliability after calibration, and a health score is output based on the test results.

[0009] In one embodiment, the method further includes:

[0010] In the chip calibration, the required indicators for reaching stability at each temperature point are tracked and recorded in real time, and the temperature point with the worst required indicators is marked as the worst temperature point; the required indicators include the number of iterations, the final absolute value of the residual error, or the observed maximum jitter value;

[0011] When performing performance boundary and signal integrity tests, the ambient temperature is set to the worst-case temperature point.

[0012] In one embodiment, the method further includes:

[0013] Based on the health pass rate of the health score, the performance pass threshold of the performance evaluation result is adjusted accordingly.

[0014] In one embodiment, the method further includes:

[0015] Adjust the temperature of the high and low temperature chamber, control the chip to output a reference frequency signal, measure the actual output frequency of the clock chip under test using a frequency meter, and calculate the percentage error of frequency accuracy at different temperature points based on the percentage error between the actual output frequency and the reference frequency signal.

[0016] In one embodiment, the method further includes:

[0017] When the error percentage is less than a preset threshold, the temperature point test is deemed to have passed, and the corresponding temperature and load capacitance values ​​are stored as one of the optimal configurations for the corresponding clock chip under test.

[0018] When the error percentage is greater than the preset threshold but does not reach the failure standard threshold, the dynamic load capacitance calibration algorithm is activated.

[0019] If the error percentage is greater than the failure standard threshold, the iteration is repeated until the maximum number of iterations is reached. If the error percentage is still greater than the failure standard threshold, the clock chip under test is determined to be unqualified in terms of frequency stability at this temperature point.

[0020] In one embodiment, the method further includes:

[0021] Based on the pre-stored capacitance-frequency sensitivity model, a new load capacitance value is calculated and set according to the error direction. If the error direction is positive frequency deviation, the load capacitance is increased; if the error direction is negative frequency deviation, the load capacitance is decreased.

[0022] This invention provides a testing system for a clock chip, the system comprising:

[0023] The baseline parameter module is used to control the power-on timing of multiple power domains, power on the clock chip under test, record the power-on surge current curve and static power consumption spectrum of each power domain, and combine the digital interface to comprehensively determine the classification of the clock chip under test, and load the initial configuration based on this classification.

[0024] The calibration module is used to place the clock chip under test in a high and low temperature chamber, adjust the test temperature, calculate the frequency accuracy error at different temperatures, and dynamically optimize the load capacitance based on the frequency accuracy error to complete the chip calibration.

[0025] The scoring module is used to test the performance boundaries, signal integrity, and short-term reliability of the chip after calibration, and outputs a health score of the clock chip under test based on the test results.

[0026] In one embodiment, the system further includes:

[0027] The temperature point module is used in the chip calibration to track and record the required indicators for stabilization at each temperature point in real time, and to mark the temperature point with the worst required indicators as the worst temperature point; the required indicators include the number of iterations, the final absolute value of the residual error, or the observed maximum jitter value;

[0028] The configuration module is used to set the ambient temperature to the worst-case temperature point when performing performance boundary and signal integrity tests.

[0029] This invention provides an electronic device, including a processor and a memory;

[0030] The processor is connected to the memory;

[0031] The memory is used to store executable program code;

[0032] The processor runs a program corresponding to the executable program code stored in the memory to perform the methods described in one or more embodiments.

[0033] This invention provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described clock chip testing method.

[0034] In view of the above, in one or more embodiments of this specification, the power-on sequence of multiple power domains is controlled to power on the clock chip under test, the power-on surge current curve and static power consumption spectrum of each power domain are recorded, and the classification of the clock chip under test is determined by combining the digital interface, and the initial configuration is loaded based on this classification; the clock chip under test is placed in a high and low temperature chamber, the test temperature is adjusted, the frequency accuracy error at different temperatures is calculated, and the load capacitance is dynamically optimized based on the frequency accuracy error to complete the chip calibration; the performance boundary, signal integrity and short-term reliability of the calibrated chip are tested, and a health score of the clock chip under test is output based on the test results. This enables intelligent screening and conditional calibration loops for performance evaluation, dynamic resource allocation based on chip quality, and significantly reduces the average test time. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a flowchart of a testing method for a clock chip provided in one embodiment of this specification.

[0037] Figure 2 This is a schematic diagram of the structure of a clock chip testing system provided in one embodiment of this specification.

[0038] Figure 3 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this specification. Detailed Implementation

[0039] The subject matter described herein will now be discussed with reference to exemplary embodiments. It should be understood that these embodiments are discussed merely to enable those skilled in the art to better understand and implement the subject matter described herein, and are not intended to limit the scope, applicability, or examples set forth in the claims. The function and arrangement of the elements discussed may be changed without departing from the scope of this specification. Various processes or components may be omitted, substituted, or added as needed in the various examples. For example, the described methods may be performed in a different order than described, and steps may be added, omitted, or combined. Furthermore, features described in some examples may be combined in other examples.

[0040] As used herein, the term "comprising" and its variations are open terms meaning "including but not limited to". The term "based on" means "at least partially based on". The terms "one embodiment" and "an embodiment" mean "at least one embodiment". The term "another embodiment" means "at least one other embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other definitions, whether explicit or implicit, may be included below. Unless explicitly indicated by the context, the definition of a term shall remain consistent throughout the specification.

[0041] like Figure 1 As shown, this embodiment of the invention provides a testing method for a clock chip, including:

[0042] Step S102: Control the power-on timing of multiple power domains, power on the clock chip under test, record the power-on surge current curve and static power consumption spectrum of each power domain, and combine the digital interface to comprehensively determine the classification of the clock chip under test, and load the initial configuration based on this classification.

[0043] Specifically, for the chip under test, a front-end screening is performed before testing. Front-end screening can include advanced power management, digital logic diagnostics, and communication bus verification. This involves connecting the power module to the ATE and applying power based on the chip's timing requirements (e.g., Core VDD powers on before I / O VDD). Simultaneously, the power-on surge current curve for each power domain is recorded at high speed. The peak value and waveform of the surge current curve are analyzed and compared with a good chip reference to detect potential defects in the ESD protection diodes and decoupling capacitors inside the power pins. The power-on timing is also verified. During power-on, after the chip enters different operating modes such as standby and shutdown, the ATE's high-resolution current measurement unit can be used to measure its static current with high precision to determine the static power consumption spectrum. The static power consumption spectrum is used to detect anomalies such as gate oxide short circuits and via bridging. Additionally, digital interface testing can be performed by connecting the ATE's digital pins to the chip's I2C / SPI interface. Boundary condition testing can include: communicating at rates exceeding the datasheet's limits to test interface robustness; sending error messages to verify whether the chip can correctly respond to NACK or ignore the instruction; and testing pull-up / pull-down resistor functionality. Register testing can be performed through bit flipping tests, reserved bit tests, and functional linkage tests.

[0044] Furthermore, all test data (such as power-on surge current curves, static power consumption, and register access stability) are correlated and analyzed to determine the chip's performance evaluation results (e.g., PLL lockout time, static power consumption level, interface stability score) and classification (e.g., Grade A - Excellent, Grade B - Standard, Grade C - Risk Observation, Failure). This classification allows for the loading of a customized initial configuration for the chip (e.g., initial values ​​for the load capacitor array), thereby optimizing the starting point of the calibration process in subsequent steps and improving overall testing efficiency.

[0045] Step S104: Place the clock chip under test in a high and low temperature chamber, adjust the test temperature, calculate the frequency accuracy error at different temperatures, and dynamically optimize the load capacitance based on the frequency accuracy error to complete the chip calibration.

[0046] Specifically, a test board containing multiple chips under test is placed in a high and low temperature test chamber. The test board is connected to a high-precision frequency meter / time interval analyzer and an ATE main controller outside the chamber via a switch matrix. The ATE controller reads the initial value of the temperature sensor built into each chip through the microcontroller on the test board. This initial value can be a uniform default intermediate value, but it is preferable to use the pre-configured value provided in step one according to the chip classification to improve calibration efficiency. The crystal load capacitance array is then reset to a default intermediate value. The high and low temperature test chamber is controlled to stabilize sequentially at multiple key temperature points (e.g., -40°C, -10°C, +25°C, +60°C, +85°C), and at each stable temperature point, the frequency accuracy error is calculated. This includes controlling the chip to output a reference frequency signal, measuring the actual output frequency using the frequency meter, and then performing calibration judgment based on the percentage error between the actual output frequency and the reference frequency.

[0047] The calibration judgment can include three results: 1. If the error percentage is less than a preset threshold, the test at that temperature point is considered passed. The corresponding temperature Ti and load capacitance value Cj are stored as one of the optimal configurations. Then, the test at the next temperature point is performed. 2. If the error percentage is greater than the preset threshold but does not reach the threshold for immediate failure, a dynamic load capacitance calibration algorithm can be activated. The microcontroller / ATE calculates and sets a new load capacitance value based on the direction of the error (positive bias indicates a high frequency, usually requiring an increase in load capacitance; negative bias indicates a low frequency, usually requiring a decrease in load capacitance) and a pre-stored capacitance-frequency sensitivity model. This loop can be set to a maximum number of iterations (e.g., 3 times) to achieve a balance between test time and accuracy. 3. If the error percentage is greater than the immediate failure threshold, and the error still exceeds the limit after the maximum number of iterations, or the initial error exceeds the immediate failure threshold, the chip is deemed to have unqualified frequency stability at this temperature point and is marked as a defective product.

[0048] In addition, during the calibration cycle, the number of iterations required to reach stability at each temperature point, the final absolute value of the residual error, or the observed maximum jitter value are tracked and recorded in real time. After completing tests at all temperature points, the system automatically marks the temperature point corresponding to the worst-case performance among these indicators as the worst-case temperature point for the chip. Test resources are controlled to quickly set the chip environment back to this worst-case temperature point, or, after completing frequency testing at this point, period jitter and period-to-period jitter measurements are immediately performed. This captures the worst-case jitter performance, ensuring that it still meets system timing requirements under extreme conditions and providing data support for subsequent steps.

[0049] Step S106: Test the performance boundaries, signal integrity, and short-term reliability of the chip after calibration, and output the health score of the clock chip under test based on the test results.

[0050] Specifically, performance boundary testing can be performed using the Shmoo test, scanning the core voltage and I / O voltage in small steps while simultaneously monitoring functionality and performance, accurately plotting the chip's voltage margin, and determining its stable operating voltage window. In addition, load capacity boundary testing should be conducted, verifying the chip's signal integrity (such as rise / fall time and overshoot) and jitter performance under drive overload conditions using a programmable capacitive load, and evaluating its actual drive capability margin. Signal integrity testing can include refined phase noise measurement: measurements are performed at multiple key frequency offset points (such as 10Hz, 100Hz, 1kHz, 1MHz), and near-carrier phase noise (reflecting PLL lock-in performance) and out-of-band phase noise (reflecting VCO noise floor) are analyzed to assess the contribution of different noise sources; system-level interference testing includes synchronous switching noise testing, configuring all output channels to switch synchronously, while monitoring power rail noise and crosstalk levels in static channels, quantifying channel isolation and power supply noise suppression capabilities. Short-term reliability testing can include: high-temperature dynamic aging: placing the chip at high temperatures for several hours continuously and periodically retesting key parameters to monitor for systematic parameter drift, thus screening for early life defects and process instability; rapid thermal stress testing: performing multiple rapid cycles between high and low temperatures to expose potential defects caused by mismatches in the thermal expansion coefficients of the materials within the chip package, such as solder joint cracks or interface delamination, using thermomechanical stress. Furthermore, integrity and system-level interference testing are not conducted at room temperature; instead, the chip environment is reset to the worst-case temperature point identified in the second step. This ensures that the final performance approval is based on the most stringent conditions. If the chip meets specifications at the worst-case temperature point, it will meet specifications at other temperatures.

[0051] Furthermore, a big data analysis platform is constructed to model the correlation between the baseline parameters (such as static power consumption) of step S102, the calibration process data (such as iteration count and worst-case performance) of step S106, and all test results of this step. The correlation patterns of the data are determined; for example, a predictive model is established between high initial static power consumption, calibration difficulties, and large aging drift in the later stages. Based on the model, a health score is determined for each chip, and chip grading is implemented (grading can include aerospace grade, industrial grade, consumer grade, etc.). The performance evaluation pass threshold in step S102 is adjusted based on the health pass rate feedback of the health score. Dynamically adjusting the performance in step S102 allows chips that meet the characteristics to be directly identified as defective products in advance.

[0052] This invention provides a method for testing clock chips. It controls the power-on sequence of multiple power domains, powers on the clock chip under test, records the power-on surge current curve and static power consumption spectrum of each power domain, and acquires the test results of the digital interface and registers. The method comprehensively determines the performance evaluation result and classification of the clock chip under test, and loads the initial configuration based on this classification. The method places the clock chip under test in a high-low temperature chamber, reads the initial chip temperature value, adjusts the test temperature, calculates the frequency accuracy error at different temperatures, and performs calibration judgment based on the frequency accuracy error. It dynamically optimizes the load capacitance to complete chip calibration. The method tests the performance boundaries, signal integrity, and short-term reliability of the calibrated chip, and outputs a health score for the clock chip under test based on the test results. This enables intelligent screening and conditional calibration loops for performance evaluation, dynamically allocates resources according to the chip's condition, and significantly reduces the average test time.

[0053] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a clock chip testing system provided in an embodiment of this application. Figure 2 As shown, the system includes:

[0054] The baseline parameter module S202 is used to control the power-on timing of multiple power domains, power on the clock chip under test, record the power-on surge current curve and static power consumption spectrum of each power domain, and combine the digital interface to comprehensively determine the classification of the clock chip under test, and load the initial configuration based on this classification.

[0055] The calibration module S204 is used to place the clock chip under test in a high and low temperature chamber, adjust the test temperature, calculate the frequency accuracy error at different temperatures, and dynamically optimize the load capacitance based on the frequency accuracy error to complete the chip calibration.

[0056] The scoring module S206 is used to test the performance boundaries, signal integrity, and short-term reliability of the chip after calibration, and outputs a health score of the clock chip under test based on the test results.

[0057] In another embodiment, a testing system for a clock chip further includes:

[0058] The temperature point module is used in the chip calibration to track and record the required indicators for stabilization at each temperature point in real time, and to mark the temperature point with the worst required indicators as the worst temperature point; the required indicators include the number of iterations, the final absolute value of the residual error, or the observed maximum jitter value;

[0059] The configuration module is used to set the ambient temperature to the worst-case temperature point when performing performance boundary and signal integrity tests.

[0060] Those skilled in the art will clearly understand that the technical solutions of the embodiments of this application can be implemented by means of software and / or hardware. In this specification, "unit" and "module" refer to software and / or hardware that can independently complete or cooperate with other components to complete a specific function, wherein the hardware may be, for example, a field-programmable gate array (FPGA), an integrated circuit (IC), etc.

[0061] Each processing unit and / or module in the embodiments of this application can be implemented by an analog circuit that implements the functions described in the embodiments of this application, or by software that executes the functions described in the embodiments of this application.

[0062] See Figure 3 It shows a schematic diagram of the structure of an electronic device according to an embodiment of this application, which can be used to implement... Figure 1 The method in the illustrated embodiment. (As shown) Figure 3 As shown, the electronic device 300 may include: at least one processor 301, at least one network interface 304, user interface 303, memory 305, and at least one communication bus 302.

[0063] The communication bus 302 is used to enable communication between these components.

[0064] The user interface 303 may include a display screen and a camera. Optionally, the user interface 303 may also include a standard wired interface and a wireless interface.

[0065] The network interface 304 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0066] The processor 301 may include one or more processing cores. The processor 301 connects to various parts within the electronic device 300 using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 305, and by calling data stored in the memory 305. Optionally, the processor 301 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 301 may integrate one or a combination of several of the following: a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and a modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display on the screen; and the modem handles wireless communication. It is understood that the modem may also not be integrated into the processor 301 and may be implemented as a separate chip.

[0067] The memory 305 may include random access memory (RAM) or read-only memory. Optionally, the memory 305 may include a non-transitory computer-readable storage medium. The memory 305 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 305 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 305 may also be at least one storage device located remotely from the aforementioned processor 301. Figure 3 As shown, the memory 305, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and program instructions.

[0068] exist Figure 3In the illustrated electronic device 300, the user interface 303 is mainly used to provide an input interface for the user and acquire user input data; while the processor 301 can be used to call the image-based interactive application stored in the memory 305 and specifically perform the following operations: control the power-on timing of multiple power domains, power on the clock chip under test, record the power-on surge current curve and static power consumption spectrum of each power domain, and comprehensively determine the classification of the clock chip under test in combination with the digital interface, and load the initial configuration based on this classification; place the clock chip under test in a high and low temperature chamber, adjust the test temperature, calculate the frequency accuracy error at different temperatures, and dynamically optimize the load capacitance based on the frequency accuracy error to complete the chip calibration; test the performance boundary, signal integrity and short-term reliability of the calibrated chip, and output the health score of the clock chip under test based on the test results.

[0069] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, as well as magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0070] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0071] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0072] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0073] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0074] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0075] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0076] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0077] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

Claims

1. A method for testing a clock chip, the method comprising: Control the power-on sequence of multiple power domains, power on the clock chip under test, record the power-on surge current curve and static power consumption spectrum of each power domain, and combine the digital interface to comprehensively determine the classification of the clock chip under test, and load the initial configuration based on this classification. The clock chip under test is placed in a high and low temperature chamber, the test temperature is adjusted, the frequency accuracy error at different temperatures is calculated, and the load capacitance is dynamically optimized based on the frequency accuracy error to complete the chip calibration. The test chip is evaluated for its performance limits, signal integrity, and short-term reliability after calibration, and a health score is output based on the test results.

2. The method according to claim 1, characterized in that, The method further includes: In the chip calibration, the required indicators for reaching stability at each temperature point are tracked and recorded in real time, and the temperature point with the worst required indicators is marked as the worst temperature point; the required indicators include the number of iterations, the final absolute value of the residual error, or the observed maximum jitter value; When performing performance boundary and signal integrity tests, the ambient temperature is set to the worst-case temperature point.

3. The method according to claim 3, characterized in that, The method further includes: Based on the health pass rate of the health score, the performance pass threshold of the performance evaluation result is adjusted accordingly.

4. The method according to claim 1, characterized in that, The adjustment of the test temperature and the calculation of the frequency accuracy error at different temperatures include: Adjust the temperature of the high and low temperature chamber, control the chip to output a reference frequency signal, measure the actual output frequency of the clock chip under test using a frequency meter, and calculate the percentage error of frequency accuracy at different temperature points based on the percentage error between the actual output frequency and the reference frequency signal.

5. The method according to claim 4, characterized in that, The method further includes: When the error percentage is less than a preset threshold, the temperature point test is deemed to have passed, and the corresponding temperature and load capacitance values ​​are stored as one of the optimal configurations for the corresponding clock chip under test. When the error percentage is greater than the preset threshold but does not reach the failure standard threshold, the dynamic load capacitance calibration algorithm is activated. If the error percentage is greater than the failure standard threshold, the iteration is repeated until the maximum number of iterations is reached. If the error percentage is still greater than the failure standard threshold, the clock chip under test is determined to be unqualified in terms of frequency stability at this temperature point.

6. The method according to claim 5, characterized in that, The startup dynamic load capacitance calibration algorithm includes: Based on the pre-stored capacitance-frequency sensitivity model, a new load capacitance value is calculated and set according to the error direction. If the error direction is positive frequency deviation, the load capacitance is increased; if the error direction is negative frequency deviation, the load capacitance is decreased.

7. A testing system for a clock chip, characterized in that, The system includes; The baseline parameter module is used to control the power-on timing of multiple power domains, power on the clock chip under test, record the power-on surge current curve and static power consumption spectrum of each power domain, and combine the digital interface to comprehensively determine the classification of the clock chip under test, and load the initial configuration based on this classification. The calibration module is used to place the clock chip under test in a high and low temperature chamber, adjust the test temperature, calculate the frequency accuracy error at different temperatures, and dynamically optimize the load capacitance based on the frequency accuracy error to complete the chip calibration. The scoring module is used to test the performance boundaries, signal integrity, and short-term reliability of the chip after calibration, and outputs a health score of the clock chip under test based on the test results.

8. The system according to claim 7, characterized in that, The system also includes: The temperature point module is used in the chip calibration to track and record the required indicators for stabilization at each temperature point in real time, and to mark the temperature point with the worst required indicators as the worst temperature point; the required indicators include the number of iterations, the final absolute value of the residual error, or the observed maximum jitter value; The configuration module is used to set the ambient temperature to the worst-case temperature point when performing performance boundary and signal integrity tests.

9. An electronic device, comprising a processor and a memory; The processor is connected to the memory; The memory is used to store executable program code; The processor runs a program corresponding to the executable program code stored in the memory to perform the method as described in any one of claims 1-6.

10. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described in any one of claims 1-6.

Images