Wide-loop broadband and high-frequency PSRR low-voltage linear voltage stabilizing circuit

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a wide-loop broadband and high-frequency PSRR low-voltage linear voltage stabilizing circuit which comprises an error amplifier, two modules with frequency compensation FVF structures and a resistor array. The module of the first frequency compensation FVF structure receives a specific value output by the error amplifier, outputs feedback voltage and is used for increasing the transient response speed of the circuit; and the module of the second frequency compensation FVF structure receives the specific value output by the error amplifier, and outputs the working voltage to the load for improving the load bearing capacity of the circuit. The LDO design of a frequency feedback voltage (FVF) structure is adopted, and the performance of the high-frequency PSRR module is improved by expanding the loop bandwidth and enhancing the high-frequency PSRR module. By adopting the FVF structure, the load bearing capacity of the LDO is remarkably enhanced, and by introducing the high-frequency PSRR lifting circuit, the LDO is endowed with strong anti-interference performance within a specific frequency range.

Description

Technical Field

[0001] In the field of integrated circuit design technology, this invention specifically relates to a low-voltage linear regulator circuit with wide loop bandwidth and high-frequency PSRR. Background Technology

[0002] Low-dropout linear regulators (LDOs) are widely used in various electronic devices as core components of power management units due to their simple structure, low cost, low noise, and low quiescent current. With the rapid development of portable devices, IoT nodes, and system-on-chips (SoCs), higher integration, smaller solution size, and better dynamic performance are required for LDOs. To reduce the number of external components, lower system costs, and reduce board area, "capacitor-free" LDOs have emerged and become a current research hotspot.

[0003] Traditional LDOs typically rely on a large external ceramic capacitor (usually in the range of 1μF to 10μF) at the output to compensate for loop stability and suppress output voltage fluctuations caused by load transients. However, the presence of this external capacitor contradicts the trend towards high integration and small size.

[0004] Therefore, various LDO architectures without external capacitors already exist in the current technology. These architectures typically achieve loop stability across the entire load range by employing on-chip compensation techniques, such as nested Miller compensation, voltage buffer compensation, or zero-pole tracking techniques based on feedback feedforward.

[0005] Although existing technologies have successfully made LDOs "capacitor-free," such LDOs, while pursuing high integration, typically suffer from the following inherent limitations that are interconnected:

[0006] The contradiction between load capacity and dynamic performance: Large-size power transistors designed to achieve large load currents have parasitic capacitances that severely limit loop bandwidth, resulting in slow load transient response and large output voltage fluctuations.

[0007] The contradiction between bandwidth and stability: The conservative compensation strategy adopted to ensure stability without external capacitors sacrifices system bandwidth and restricts the improvement of dynamic performance.

[0008] Inherent defects in high-frequency PSRR performance: Due to the lack of external capacitors for high-frequency bypass and the direct feedforward effect of power transistor parasitic capacitance, its PSRR performance in the high-frequency range above several hundred kHz is severely degraded, making it unable to meet the power supply requirements of high-precision analog / RF circuits that are sensitive to power supply noise.

[0009] Therefore, there is an urgent need in the field for an innovative LDO circuit architecture that can overcome the aforementioned limitations and achieve the triple goals of strong load driving capability, high loop bandwidth (fast transient response), and excellent high-frequency PSRR performance without requiring any external output capacitors. This is precisely the technical problem that this invention aims to solve. Summary of the Invention

[0010] The purpose of this invention is to overcome the limitations of traditional capacitorless low-dropout linear regulators (LDOs) in terms of load carrying capacity, bandwidth, and high-frequency power rejection ratio (PSRR) in the prior art. It adopts an LDO design with a frequency feedback voltage (FVF) structure and proposes a low-voltage linear regulator circuit with wide loop bandwidth and high-frequency PSRR, aiming to improve its performance by expanding the loop bandwidth and enhancing the high-frequency PSRR module.

[0011] To achieve the above-mentioned objectives, the present invention provides the following technical solution: A low-voltage linear regulator circuit with wide-loop bandwidth and high-frequency PSRR includes an error amplifier, two modules equipped with frequency-compensated FVF structures, and a resistor array. The error amplifier takes a reference voltage and a feedback voltage as inputs and outputs a specific value to maintain the stability of that specific value. The module equipped with the frequency compensation FVF structure includes a module with a first frequency compensation FVF structure and a module with a second frequency compensation FVF structure; the module with the first frequency compensation FVF structure and the module with the second frequency compensation FVF structure are connected in parallel between the power supply and ground. The module of the first frequency compensation FVF structure receives a specific value from the error amplifier and outputs a feedback voltage to improve the transient response speed of the circuit. The module of the second frequency compensation FVF structure receives a specific value from the error amplifier output and outputs a working voltage to the load to improve the load carrying capacity of the circuit. The resistor array is connected to the output terminal of the module of the first frequency compensation FVF structure and the feedback voltage input terminal of the error amplifier, which is used to realize precise adjustment of the output voltage.

[0012] Preferably, the module of the first frequency compensation FVF structure includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, and a resistor R1; The source of the first MOSFET is connected to the power supply, the drain of the first MOSFET is connected to the source of the second MOSFET, and the drain of the second MOSFET is grounded through resistor R1; the gate of the second MOSFET is connected to the output of the error amplifier, and the source of the second MOSFET is connected to the output feedback voltage after being connected to the resistor array. The gates of the third and fourth MOSFETs are respectively biased. The drain of the third MOSFET is connected to the gate of the first MOSFET, the source of the third MOSFET is connected to the drain of the fourth MOSFET, and the source of the fourth MOSFET is connected to the drain of the second MOSFET.

[0013] Preferably, the module of the second frequency compensation FVF structure includes: a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, and a resistor R2; The source of the fifth MOSFET is connected to the power supply, the drain of the fifth MOSFET is connected to the source of the sixth MOSFET, and the drain of the sixth MOSFET is grounded through resistor R2; the gate of the sixth MOSFET is connected to the output of the error amplifier, and the source of the sixth MOSFET outputs the operating voltage to the load. The gates of the seventh and eighth MOSFETs are respectively biased. The drain of the seventh MOSFET is connected to the gate of the sixth MOSFET, the source of the seventh MOSFET is connected to the drain of the eighth MOSFET, and the source of the eighth MOSFET is connected to the drain of the sixth MOSFET.

[0014] Preferably, the error amplifier is a folded cascode amplifier, comprising an input stage and an output stage; The input stage includes transistors NM1, NM2, and NM3; The output stage includes transistors PM1, PM2, PM3, PM4, NM4, NM5, NM6, and NM7; The source of transistor PM1 is connected to the power supply, and the drain of transistor PM1 is connected to the source of PM3; the drain of PM3 is connected to the drain of NM4, the source of NM4 is connected to the drain of NM6, and the source of NM6 is connected to ground. The source of transistor PM2 is connected to the power supply, and the drain of transistor PM2 is connected to the source of PM4; the drain of PM4 is connected to the drain of NM5, the source of NM5 is connected to the drain of NM7, and the source of NM7 is connected to ground. The gate of transistor PM1 is connected to the gate of transistor PM2; the gate of transistor PM3 is connected to the gate of transistor PM4; the gate of transistor NM4 is connected to the gate of transistor NM5; and the gate of transistor NM6 is connected to the gate of transistor NM7. The drain of transistor NM4 is connected to the gate of transistor NM6; The drains of transistor PM1 and transistor PM2 are also connected to the drains of transistors NM1 and NM2 in the input stage, respectively. The sources of transistors NM1 and NM2 are both connected to the drain of transistor NM3; the source of transistor NM3 is grounded. The gate input reference voltage of transistor NM1, and the gate input feedback voltage of transistor NM2.

[0015] Preferably, a capacitor is connected between the output and input terminals of the error amplifier to form a Miller compensation circuit.

[0016] Based on the same concept, a control method for a low-voltage linear regulator circuit with wide-loop bandwidth and high-frequency PSRR is also proposed. The circuit is constructed as described in any of the above-mentioned low-voltage linear regulator circuits, and the circuit is stabilized by connecting a zero-elimination resistor in series in the circuit.

[0017] Preferably, the formula for calculating the zero-elimination resistance is: ; Where Z1 is the zero-suppression resistance, Cc is the Miller capacitance, and gm3 is the equivalent transconductance of the second pole of the LDO topology.

[0018] Compared to existing technologies, the advantages of this invention are as follows: This invention adopts an LDO design with a frequency feedback voltage (FVF) structure, aiming to improve its performance by expanding the loop bandwidth and enhancing the high-frequency PSRR module. The FVF structure significantly enhances the LDO's load-carrying capacity, and the introduction of a high-frequency PSRR boost circuit endows the LDO with strong anti-interference performance within a specific frequency range. Attached Figure Description

[0019] Figure 1 This is a circuit block diagram of a low-voltage linear regulator circuit with wide loop bandwidth and high-frequency PSRR provided by the present invention; Figure 2 This is a low-dropout linear voltage regulator circuit diagram provided by the present invention; Figure 3 This is a circuit diagram of a folded common-source cascode amplifier provided by the present invention; Figure 4 This is the LDO topology diagram provided by the present invention; Figure 5 This is a small signal analysis diagram provided by the present invention. Detailed Implementation

[0020] The present invention will now be described in further detail with reference to specific embodiments. However, this should not be construed as limiting the scope of the present invention to the following embodiments; all technologies implemented based on the content of the present invention fall within the scope of the present invention.

[0021] Example 1 A low-voltage linear regulator circuit with wide-loop bandwidth and high-frequency PSRR is shown in the circuit diagram below. Figure 1 As shown, it includes an error amplifier, two modules equipped with frequency-compensated FVF structures, and a resistor array; The error amplifier takes a reference voltage and a feedback voltage as inputs and outputs a specific value to maintain the stability of that specific value. The module equipped with the frequency compensation FVF structure includes a module with a first frequency compensation FVF structure and a module with a second frequency compensation FVF structure; the module with the first frequency compensation FVF structure and the module with the second frequency compensation FVF structure are connected in parallel between the power supply and ground. The module of the first frequency compensation FVF structure receives a specific value from the error amplifier and outputs a feedback voltage to improve the transient response speed of the circuit. The module of the second frequency compensation FVF structure receives a specific value from the error amplifier output and outputs a working voltage to the load to improve the load carrying capacity of the circuit. The resistor array is connected to the output terminal of the module of the first frequency compensation FVF structure and the feedback voltage input terminal of the error amplifier, which is used to realize precise adjustment of the output voltage.

[0022] Preferably, the module of the first frequency compensation FVF structure includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, and a resistor; The source of the first MOSFET is connected to the power supply, and the drain of the first MOSFET is connected to the source of the second MOSFET. The drain of the second MOSFET is grounded through a resistor. The gate of the second MOSFET is connected to the output of the error amplifier, and the source of the second MOSFET is connected to a resistor array to output a feedback voltage. The resistor array is composed of a trimming structure, that is, multiple sets of MOSFETs and resistors are connected in parallel. The resistance value is adjusted by controlling the switching on and off of the MOSFETs. This is an existing technology.

[0023] The gates of the third and fourth MOSFETs are respectively biased. The drain of the third MOSFET is connected to the gate of the first MOSFET, the source of the third MOSFET is connected to the drain of the fourth MOSFET, and the source of the fourth MOSFET is connected to the drain of the second MOSFET.

[0024] The module of the second frequency compensation FVF structure includes: a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, and a resistor R2; The source of the fifth MOSFET is connected to the power supply, the drain of the fifth MOSFET is connected to the source of the sixth MOSFET, and the drain of the sixth MOSFET is grounded through resistor R2; the gate of the sixth MOSFET is connected to the output of the error amplifier, and the source of the sixth MOSFET outputs the operating voltage to the load. The gates of the seventh and eighth MOSFETs are respectively biased. The drain of the seventh MOSFET is connected to the gate of the sixth MOSFET, the source of the seventh MOSFET is connected to the drain of the eighth MOSFET, and the source of the eighth MOSFET is connected to the drain of the sixth MOSFET.

[0025] Preferably, the error amplifier is a folded cascode amplifier, comprising an input stage and an output stage; The input stage includes transistors NM1, NM2, and NM3; The output stage includes transistors PM1, PM2, PM3, PM4, NM4, NM5, NM6, and NM7; The source of transistor PM1 is connected to the power supply, and the drain of transistor PM1 is connected to the source of PM3; the drain of PM3 is connected to the drain of NM4, the source of NM4 is connected to the drain of NM6, and the source of NM6 is connected to ground. The source of transistor PM2 is connected to the power supply, and the drain of transistor PM2 is connected to the source of PM4; the drain of PM4 is connected to the drain of NM5, the source of NM5 is connected to the drain of NM7, and the source of NM7 is connected to ground. The gate of transistor PM1 is connected to the gate of transistor PM2; the gate of transistor PM3 is connected to the gate of transistor PM4; the gate of transistor NM4 is connected to the gate of transistor NM5; and the gate of transistor NM6 is connected to the gate of transistor NM7. The drain of transistor NM4 is connected to the gate of transistor NM6; The drains of transistor PM1 and transistor PM2 are also connected to the drains of transistors NM1 and NM2 in the input stage, respectively. The sources of transistors NM1 and NM2 are both connected to the drain of transistor NM3; the source of transistor NM3 is grounded. The gate input reference voltage of transistor NM1, and the gate input feedback voltage of transistor NM2.

[0026] Preferably, a capacitor is connected between the output and input terminals of the error amplifier to form a Miller compensation circuit.

[0027] Example 2 Please see Figure 2 The low dropout linear regulator (LDO) circuit designed in this invention consists of an error amplifier (EA), two modules equipped with frequency compensation (FVF) structures, and a resistor array.

[0028] Its working principle is as follows: Figure 2The circuit on the left side is the module of the first frequency compensation FVF structure. When the DC operating point is in a normal state, the voltage provided by the power supply and ground can work normally. Due to the presence of the negative feedback system, the voltage across the error amplifier will remain consistent, thus stabilizing the output vcopy voltage at a specific value.

[0029] This specific voltage value is processed by the FVF buffer and forms a complete loop at the output through the feedback resistor. Furthermore, the FVF structure in this circuit differs from the traditional structure. In the traditional structure, when the current is too large, the gate voltage of the load transistor becomes too high, causing the lower MOSFET to enter the linear region, and the circuit cannot function properly. To solve this problem, we added two additional transistors to the gate of the load transistor to ensure that the gate voltage is always two threshold voltages (Vov) higher than the drain (D terminal) of the lower transistor, thus ensuring that the DC operating point of each transistor remains normal. The LDO circuit proposed in this invention, by introducing a precisely controlled FVF structure, not only effectively suppresses the linear region problem in the traditional structure.

[0030] The transient response speed and stability of the circuit are significantly improved thanks to the introduction of the FVF structure. When encountering sudden changes in input voltage or load current, the circuit can quickly adjust the output voltage to adapt to these changes. This structure plays a crucial role in maintaining circuit stability, effectively reducing output voltage ripple and improving the power supply rejection ratio, thereby further enhancing the overall performance of the circuit. Furthermore, through the resistor array, this circuit achieves precise regulation of the output voltage to meet the needs of diverse application scenarios. In summary, the low-dropout linear regulator with an FVF structure proposed in this invention achieves a significant performance improvement and demonstrates broad application prospects.

[0031] Figure 2 The circuit on the right side is a module with a second frequency compensation FVF structure, primarily designed to enhance transient response. This section has a large bandwidth, aiming to improve response speed. When the output load enters a heavy load state, the current changes drastically, causing the output voltage Vout to drop rapidly. Since the Vout voltage is controlled by the circuit on the left, the gate voltage of the load transistor decreases accordingly to dissipate excess current. Conversely, when the load is light, the Vout voltage rises, and the gate voltage of the load transistor adjusts accordingly to the change in Vout, ensuring that the transistor can quickly correct the value of Vout.

[0032] This invention proposes an innovative three-loop design, an FVF structure, mainly composed of two parts. First, the stability enhancement section plays a role in stabilizing the voltage in the circuit, ensuring excellent circuit stability and avoiding problems caused by insufficient stability. Second, the section that improves transient response time and load carrying capacity utilizes the long-distance characteristic of the first pole of the FVF structure to significantly improve load carrying capacity without compromising stability. Despite the numerous loops, stability design is a key aspect of this design. The low-dropout linear regulator with an FVF structure exhibits excellent transient response capability in the face of rapid load changes. The small overshoot and undershoot amplitudes indicate that the fluctuation of the output voltage during load abrupt changes is effectively controlled, which is crucial for maintaining the stability and reliability of the circuit. In addition, the regulator can quickly recover to the normal output voltage level after load changes, demonstrating its excellent recovery characteristics and dynamic performance. Therefore, the low-dropout linear regulator with an FVF structure is an ideal choice for handling scenarios with rapid load changes due to its performance characteristics.

[0033] Given the need for high gain in circuit design to achieve high power supply rejection ratio and more accurate output values, this invention initially selected a two-stage operational amplifier structure consisting of a five-transistor operational amplifier and a common-source amplifier. However, this structure introduces a serious problem: the addition of the right-hand side structure transforms the circuit system into a four-stage structure. The original circuit already had three loops; the introduction of a four-stage system further increases the number of zeros and poles, significantly increasing the complexity of loop stability design. Furthermore, the increased number of capacitors and resistors leads to a significant increase in circuit layout area, resulting in higher costs. Since the first design failed to meet stability and other requirements, the second design adopted a folded common-source cascode amplifier as the operational amplifier, such as... Figure 3 As shown, this simplifies the circuit into a two-level system structure, effectively reducing the difficulty of stability design.

[0034] The application of a folded cascode amplifier significantly improves the circuit's power supply rejection ratio (PSRR). This ensures that the output voltage remains stable even under fluctuating power supply voltage. Simultaneously, the introduction of this structure does not lead to a significant increase in circuit power consumption, thus maintaining the high efficiency performance of the low-dropout linear regulator. After further optimization and adjustments, this error amplifier design has been successfully integrated into a practical circuit, achieving stable voltage output under rapidly changing load conditions.

[0035] like Figure 3 This is the topology diagram of the LDO. Figure 3 The stability compensation method used in this paper is to employ a Miller compensation circuit. Figure 3 The Miller capacitance is Cc, and the zero-shaving resistor is the same as the zero-adjustment resistor.

[0036] The Miller compensation circuit works by connecting a capacitor between the output of the error amplifier and the gate of the power transistor. This effectively pushes the dominant pole to lower frequencies and the secondary pole to higher frequencies, thus enhancing system stability. Miller compensation improves amplifier stability and bandwidth by introducing a compensation capacitor. It utilizes the Miller effect to treat a small capacitor as equivalent to a large capacitor at the input node, thereby achieving pole separation.

[0037] The introduction of this capacitor not only changes the location of the poles but also generates a zero in the left half-plane, which helps to offset the adverse effects of the output poles on system stability. Furthermore, to further improve stability, the size of the compensation capacitor and its matching with related resistors must be carefully adjusted to ensure that the phase margin meets design requirements.

[0038] By continuously optimizing the circuit and checking simulation results to verify whether the performance parameters meet the standards, it can be seen that the LDO has strong stability under various load conditions. The LDO topology diagram is shown below. Figure 4 As shown, in this structure, Ro1 and Ro2 represent the output resistances of the first two amplifier stages, Rout is the output stage resistance, Co1 and Co2 are the capacitors of the first two amplifier stages, and Cout is the output stage capacitor.

[0039] like Figure 5 This is a small-signal analysis diagram. By analyzing the small-signal model of the circuit, formulas can be derived using circuit theory.

[0040] (1-1) (1-2) (1-3) By combining equations 1-1, 1-2, and 1-3 above, we can derive the transfer function.

[0041] (1-4) in, (1-5) (1-6) (1-7) (1-8) (1-9) This will affect the stability of the system. The specific magnitude of the zero point can be calculated using Formula 1-1 above.

[0042] (1-10) Where Z1 is the zero-suppression resistance, Cc is the Miller capacitance, and gm3 is the equivalent transconductance of the second pole of the LDO topology.

[0043] Step 13: In the circuit design process, to address the adverse effects of right-plane zeros and transform them into left-half-plane zeros beneficial to circuit stability, an effective method is to connect a zero-suppression resistor in series in the capacitor circuit. By carefully adjusting the resistance value of this zero-adjustment resistor, circuit stability-related problems can be specifically addressed.

[0044] Step 14: Once the zero-adjustment resistor is added, the characteristics of the zero point will change, and its mathematical expression is shown in equation (1-11). When the value of the zero-adjustment resistor RZ is consistent with the value of 1 / gm³, theoretically, the zero point will be at infinity. At this point, the interference effect of the zero point on the phase margin is almost negligible. However, when the value of RZ exceeds 1 / gm³, the zero point will appear in the left half-plane region. This change in the zero point position has a positive promoting effect on increasing the phase margin, ultimately significantly enhancing the stability of the entire circuit system.

[0045] (1-11) This invention adopts an LDO design with a frequency feedback voltage (FVF) structure, aiming to improve its performance by expanding the loop bandwidth and enhancing the high-frequency PSRR module. The FVF structure significantly enhances the LDO's load-carrying capacity, and the introduction of a high-frequency PSRR boost circuit endows the LDO with strong anti-interference performance within a specific frequency range.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-voltage linear regulator circuit with wide-loop bandwidth and high-frequency PSRR, characterized in that, It includes an error amplifier, two modules equipped with frequency-compensated FVF structures, and a resistor array; The error amplifier takes a reference voltage and a feedback voltage as inputs and outputs a specific value to maintain the stability of that specific value. The module equipped with the frequency compensation FVF structure includes a module with a first frequency compensation FVF structure and a module with a second frequency compensation FVF structure; the module with the first frequency compensation FVF structure and the module with the second frequency compensation FVF structure are connected in parallel between the power supply and ground. The module of the first frequency compensation FVF structure receives a specific value from the error amplifier and outputs a feedback voltage to improve the transient response speed of the circuit. The module of the second frequency compensation FVF structure receives a specific value from the error amplifier output and outputs a working voltage to the load to improve the load carrying capacity of the circuit. The resistor array is connected to the output terminal of the module of the first frequency compensation FVF structure and the feedback voltage input terminal of the error amplifier, which is used to realize precise adjustment of the output voltage.

2. The low-voltage linear regulator circuit with wide loop bandwidth and high-frequency PSRR as described in claim 1, characterized in that, The module of the first frequency compensation FVF structure includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, and a resistor R1; The source of the first MOSFET is connected to the power supply, the drain of the first MOSFET is connected to the source of the second MOSFET, and the drain of the second MOSFET is grounded through resistor R1; the gate of the second MOSFET is connected to the output of the error amplifier, and the source of the second MOSFET is connected to the output feedback voltage after being connected to the resistor array. The gates of the third and fourth MOSFETs are respectively biased. The drain of the third MOSFET is connected to the gate of the first MOSFET, the source of the third MOSFET is connected to the drain of the fourth MOSFET, and the source of the fourth MOSFET is connected to the drain of the second MOSFET.

3. The low-voltage linear regulator circuit with wide loop bandwidth and high-frequency PSRR as described in claim 1, characterized in that, The module of the second frequency compensation FVF structure includes: a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, and a resistor R2; The source of the fifth MOSFET is connected to the power supply, the drain of the fifth MOSFET is connected to the source of the sixth MOSFET, and the drain of the sixth MOSFET is grounded through resistor R2; the gate of the sixth MOSFET is connected to the output of the error amplifier, and the source of the sixth MOSFET outputs the operating voltage to the load. The gates of the seventh and eighth MOSFETs are respectively biased. The drain of the seventh MOSFET is connected to the gate of the sixth MOSFET, the source of the seventh MOSFET is connected to the drain of the eighth MOSFET, and the source of the eighth MOSFET is connected to the drain of the sixth MOSFET.

4. The low-voltage linear regulator circuit with wide loop bandwidth and high-frequency PSRR as described in claim 1, characterized in that, The error amplifier is a folded common-source common-gate amplifier, including an input stage and an output stage; The input stage includes transistors NM1, NM2, and NM3; The output stage includes transistors PM1, PM2, PM3, PM4, NM4, NM5, NM6, and NM7; The source of transistor PM1 is connected to the power supply, and the drain of transistor PM1 is connected to the source of PM3; the drain of PM3 is connected to the drain of NM4, the source of NM4 is connected to the drain of NM6, and the source of NM6 is connected to ground. The source of transistor PM2 is connected to the power supply, and the drain of transistor PM2 is connected to the source of PM4; the drain of PM4 is connected to the drain of NM5, the source of NM5 is connected to the drain of NM7, and the source of NM7 is connected to ground. The gate of transistor PM1 is connected to the gate of transistor PM2; the gate of transistor PM3 is connected to the gate of transistor PM4; the gate of transistor NM4 is connected to the gate of transistor NM5; and the gate of transistor NM6 is connected to the gate of transistor NM7. The drain of transistor NM4 is connected to the gate of transistor NM6; The drains of transistor PM1 and transistor PM2 are also connected to the drains of transistors NM1 and NM2 in the input stage, respectively. The sources of transistors NM1 and NM2 are both connected to the drain of transistor NM3; the source of transistor NM3 is grounded. The gate input reference voltage of transistor NM1, and the gate input feedback voltage of transistor NM2.

5. A low-voltage linear regulator circuit with wide-loop bandwidth and high-frequency PSRR as described in any one of claims 1-4, characterized in that, A capacitor is connected between the output and input terminals of the error amplifier to form a Miller compensation circuit.

6. A control method for a low-voltage linear regulator circuit with wide-loop bandwidth and high-frequency PSRR, characterized in that, A low-voltage linear regulator circuit with wide loop bandwidth and high frequency PSRR as described in any one of claims 1-5 is constructed, and the circuit is stabilized by connecting a zero-elimination resistor in series in the circuit.

7. The control method for a low-voltage linear regulator circuit with wide-loop bandwidth and high-frequency PSRR as described in claim 6, characterized in that, The formula for calculating the zero-suppression resistor is: ； Where Z1 is the zero-suppression resistance, Cc is the Miller capacitance, and gm3 is the equivalent transconductance of the second pole of the LDO topology.

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