System and method for solving maximum clique problem

Abstract

The invention discloses a system and a method for solving a maximum clique problem. A system for solving a maximum clique problem includes an array light input source, a photonic chip, an array detector, and a comparator. The array light input source includes a plurality of light input sources configured to controllably input one or more light input sources of the plurality of light input sources. The photonic chip includes a splitter configured to equally divide an optical power of a corresponding optical input source into a predetermined number of light for a side associated with each optical input source. The array detector is configured to receive the equally divided light and to detect a sum of output powers for each element of a set of vertices of a cluster that needs to be solved. The comparator is configured to compare a sum of power detected for each element of the vertex set of the clique that needs to be solved to a threshold power. A result of the comparison is used to determine whether a set of vertices associated with a particular clique solution satisfies a clique condition.

Description

Technical Field

[0001] This invention relates in general to solving the maximum clique problem, and specifically to solving the maximum clique problem using photonic chips. Background Technology

[0002] The maximum clique problem is a classic problem in graph theory. Its goal is to find a subgraph in an undirected graph that contains the maximum number of vertices, where every adjacent vertex is connected by an edge. Solving the maximum clique problem has wide applications in social network analysis, market analysis, solution selection, bioinformatics, computer vision, and clustering problems in machine learning.

[0003] The maximum clique problem is an NP-hard problem, with its complexity increasing exponentially with the problem size. Current algorithms for solving the maximum clique problem include brute-force search and heuristic algorithms. Brute-force search requires exhaustively searching all possible cliques, which is time-consuming and highly inefficient on large scales. Heuristic algorithms, such as genetic algorithms and simulated annealing, can accelerate computation but do not guarantee finding the optimal solution.

[0004] Currently, solutions to the maximum clique problem primarily rely on algorithmic innovation, with the hardware used for solving the problem being digital electronic chips, including CPUs and GPUs. However, using digital electronic chips to solve the maximum clique problem suffers from limitations in computational speed due to the clock frequency of the processing unit, resulting in slow processing speed, high latency, and high power consumption. Faster computational solutions are needed in low-latency scenarios such as computer vision.

[0005] There is a need in this field for computational solutions to the maximum clique problem that offer faster processing speeds, lower latency, and lower power consumption. Summary of the Invention

[0006] This invention provides a computational solution for solving the maximum clique problem that is faster, has lower latency, and consumes less power.

[0007] One aspect of the present invention provides a system for solving a maximum clique problem, comprising: an array of optical input sources including a plurality of optical input sources configured to controllably input one or more of the plurality of optical input sources, wherein each optical input source is associated with an edge formed between vertices involved in the maximum clique problem, and whether light from each optical input source is input is determined based on whether the corresponding vertices are connected to form an edge; a photonic chip including a splitter configured to equally divide the optical power of the corresponding optical input source into a predetermined number of beams for each edge associated with the optical input source, the predetermined number being associated with the number of cliques to be solved, wherein the cliques to be solved comprise a set of vertices, the elements of the vertex set being based on the two vertices of the corresponding edge. The superset of points is determined; an array detector, coupled to the photonic chip, is configured to: receive equally divided light; and for each element of the vertex set of the clique to be solved, detect the sum of output power; and a comparator, coupled to the array detector, is configured to compare the sum of power detected for each element of the vertex set of the clique to be solved with a threshold power, wherein the threshold power is determined based on the optical power input from the array light input source, the number of cliques to be solved, and the number of vertices in the elements of the vertex set of the cliques to be solved, wherein the result of the comparison is used to determine whether the vertex set associated with a particular clique solution satisfies the clique formation condition to form a subclique, and the result of the maximoclique problem solution is determined based on the formed subcliques.

[0008] In the system described above, the number of vertices of the clique to be solved is greater than or equal to 2, and less than or equal to the total number of vertices involved in the maximal clique problem.

[0009] In any of the above-described systems, the array light input source includes an array light source and a corresponding array light switch; or the array light input source includes a controllable array light switch.

[0010] In any of the above systems, the array optical input source is integrated on the photonic chip; and / or the array detector is mounted on the output of the photonic chip.

[0011] In a system as described in any of the above, each edge of the clique to be solved is arranged in columns, and the array detector is configured to detect the power of the output light for each column and sum the detected output light power.

[0012] The system as described in any of the above embodiments, wherein the comparator includes a level comparator configured to compare the sum of power with a corresponding threshold power for each column.

[0013] The system as described in any of the above, wherein the array detector comprises a summation detector or a detector whose probe surface covers all optical input sources associated with the edge formed between every two vertices of the maximal clique problem.

[0014] The system as described in any of the above embodiments, wherein the photonic chip includes a silicon nitride waveguide and is fabricated using CMOS technology.

[0015] The system as described in any of the above, wherein the splitter includes at least one of a multimode interferometer, a Y-junction, and a directional coupler.

[0016] The system as described in any of the above, wherein the splitter includes at least one of the following: a one-input multiple-output splitter based on a multimode interferometer; a splitter based on a cascaded multimode interferometer; a splitter based on a cascaded directional coupler.

[0017] Another aspect of the present invention provides a system for solving the maximum clique problem, comprising: an array of optical input sources including a plurality of optical input sources configured to controllably input one or more of the plurality of optical input sources, wherein each optical input source is associated with an edge formed between vertices involved in the maximum clique problem, and whether light from each optical input source is input is determined based on whether the corresponding vertices are connected to form an edge; at least two photonic chips stacked on top of each other, each photonic chip including a splitter, the splitter of each photonic chip being configured to equally divide the optical power of the corresponding optical input source into a predetermined number of beams for each edge associated with each optical input source, the predetermined number being associated with the number of cliques to be solved, wherein the cliques to be solved comprise a set of vertices, the vertices being The elements of the set are determined based on the supersets of the two vertices of the corresponding edge; an array detector, coupled to the at least two photonic chips, is configured to: receive equally divided light and, for each element of the vertex set of the clique to be solved, detect the sum of output power; and a comparator, coupled to the array detector, is configured to compare the sum of power detected for each element of the vertex set of the clique to be solved with a threshold power, wherein the threshold power is determined based on the optical power input from the array light input source, the number of cliques to be solved, and the number of vertices of the cliques to be solved, wherein the result of the comparison is used to determine whether the vertex set associated with a specific clique solution can satisfy the clique formation condition to form a subclique, and the result of the maximal clique problem solution is determined based on the formed subcliques.

[0018] In the system described above, the photonic chip includes a silicon nitride waveguide and is fabricated using a CMOS process, and / or the comparator includes a level comparator configured to compare the sum of the power for each column with a corresponding threshold power.

[0019] Another aspect of the present invention provides a method for solving a maximum clique problem, comprising: configuring an array of optical input sources, including a plurality of optical input sources, to controllably input one or more of the plurality of optical input sources, wherein each optical input source is associated with an edge formed between vertices involved in the maximum clique problem, and whether light from each optical input source is input is determined based on whether the corresponding vertices are connected to form an edge; and using a splitter of a photonic chip, dividing the optical power of the corresponding optical input source into a predetermined number of beams for each edge associated with the optical input source, the predetermined number being associated with the number of cliques to be solved, wherein the cliques to be solved comprise a set of vertices, the set of vertices being... Elements are determined based on the supersets of the two vertices of the corresponding edge; equally divided light is received by an array detector; the array detector detects the sum of output power for each element of the vertex set of the clique to be solved; and a comparator compares the sum of the power detected for each element of the vertex set of the clique to be solved with a threshold power, wherein the threshold power is determined based on the optical power input from the array light input source, the number of cliques to be solved, and the number of vertices of the cliques to be solved, wherein the result of the comparison is used to determine whether the vertex set associated with a specific clique solution satisfies the clique formation condition to form a subclique, and the result of the maximal clique problem solution is determined based on the formed subcliques.

[0020] The method described above, wherein the number of vertices of the clique to be solved is greater than or equal to 2 and less than or equal to the total number of vertices involved in the maximal clique problem.

[0021] The method described in any of the above embodiments, wherein the light input source includes an array of light sources and corresponding array of optical switches, and configuring the array of light input sources including multiple light input sources to controllably input one or more of the multiple light input sources includes: configuring a corresponding optical switch in the array of optical switches to be turned on based on corresponding vertex connections to form edges; or wherein the light input source includes controllable array of optical switches, and configuring the array of light input sources including multiple light input sources to controllably input one or more of the multiple light input sources includes: configuring a corresponding optical switch in the controllable array of optical switches to input optical power based on corresponding vertex connections to form edges.

[0022] The method described in any of the above embodiments, wherein each edge of the clique to be solved is arranged in a column, and the sum of output power detected by the array detector for the vertex set of each clique to be solved includes: detecting the power of the output light for each column, and summing the detected output light power.

[0023] As described in any of the preceding methods, wherein comparing the sum of powers detected for each set of vertices of the clique to be solved with a threshold power by the comparator comprises: comparing the sum of powers with a corresponding threshold power for each column. As described in any of the preceding methods, wherein the photonic chip comprises a silicon nitride waveguide and is fabricated using a CMOS process, and / or the comparator comprises a level comparator configured to compare the sum of powers with a corresponding threshold power for each column.

[0024] The system and method for solving the maximum clique problem according to embodiments of the present invention have faster computation speed, lower latency, and lower power consumption. Attached Figure Description

[0025] Various embodiments of the present invention are described in conjunction with the accompanying drawings.

[0026] Figure 1 This is a block diagram illustrating a system for solving the maximal clique problem according to some embodiments of the present invention.

[0027] Figure 2 This is a diagram illustrating the maximum clique problem with 5 vertices.

[0028] Figure 3 This is a schematic diagram illustrating the optical path structure of a splitter for a photonic chip according to some embodiments of the present invention.

[0029] Figure 4 This is a schematic diagram illustrating the detection of the output of a photonic chip according to some embodiments of the present invention.

[0030] Figure 5 This is a schematic diagram illustrating various structures of a splitter for a photonic chip according to some embodiments of the present invention.

[0031] Figure 6 This is a block diagram illustrating a system for solving the maximal clique problem according to some embodiments of the present invention.

[0032] Figure 7 This is a schematic diagram illustrating the optical path structure of a stack of photonic chips and a corresponding splitter for each photonic chip according to some embodiments of the present invention.

[0033] Figure 8 This is a flowchart illustrating a method for solving the maximum clique problem according to some embodiments of the present invention. Detailed Implementation

[0034] According to one aspect of the present invention, a system for solving the maximal clique problem is provided.

[0035] Figure 1This is a block diagram illustrating a system 100 for solving the maximum clique problem according to some embodiments of the present invention.

[0036] System 100 includes an array optical input source 110, a photonic chip 120, an array detector 130, and a comparator 140.

[0037] The array of light input sources 110 may include multiple light input sources. The array of light input sources 110 can be configured to controllably input light from one or more of the multiple light input sources. Each light input source may be associated with an edge formed between the vertices involved in the maximum clique problem to be solved, and whether light from each light input source is input can be determined based on whether the corresponding vertices are connected to form an edge. As an example, if there is a connection between the corresponding two vertices to form an edge, then light from the light input source is input; otherwise, light from the light input source is not input. Thus, the edge formed between the vertices involved in the maximum clique problem can be mapped to the on / off state of each light input source.

[0038] The photonic chip 120 may include a splitter 125. The splitter 125 can be used to divide the optical power of the corresponding optical input source into a predetermined number of beams for each edge associated with the optical input source. This predetermined number is associated with the number of cliques to be solved. The cliques to be solved may include a set of vertices, which may be determined at least in part based on the superset of the two vertices of the corresponding edge. The following will combine... Figures 2-4 Describe the method for determining the aforementioned predetermined quantity and vertex set.

[0039] In some embodiments, the photonic chip 120 may include a gallium nitride waveguide and can be fabricated using a complementary metal-oxide-semiconductor (CMOS) process. Compared to other common methods of forming waveguides (e.g., using silicate glass and femtosecond laser direct writing for waveguide writing), the waveguide material used in this embodiment has low loss, and the waveguide formation method has a fast fabrication rate, more stable process, and is more suitable for large-scale processing.

[0040] Array detector 130 can be coupled to photonic chip 120. Array detector 130 can be configured to receive equally divided light. Array detector 130 can also be configured to detect the sum of output power for each element of the vertex set of the clique to be solved. As an example, the power or sum of power detected by array detector 130 can be output in the form of current or voltage. The back-mounted array detector 130 can directly sum the detected output power, providing faster information on the maximal clique compared to detection schemes using charge-coupled devices (CCDs) (which primarily aim to provide a clearer understanding of the clique formation of all cliques). The following will combine... Figures 2-4 Describes how to probe and determine the power sum for each element set of the vertex set of the clique that needs to be solved.

[0041] Comparator 140 may be coupled to array detector 130. Comparator 140 may be configured to compare the sum of the powers detected for each element of the vertex set of the clique to be solved with a threshold power. The threshold power may be determined based on the optical power input from array optical input source 110, the number of cliques to be solved, and the number of vertices in the elements of the vertex set of the cliques to be solved. The result of this comparison may be used to determine whether the vertex set associated with a particular clique solution satisfies the clique formation condition to form a subclique, and the result of the maximoclique problem solution is determined at least based on the formed subcliques. The subclique containing the largest number of vertices among the formed subcliques may be determined as the solved maximoclique.

[0042] Since the array detector 130 outputs the detected power in the form of current or voltage, the determined threshold power can be converted into a corresponding threshold current or threshold voltage value and compared with the current or voltage value output by the array detector 130. As an example, comparator 140 may include a level comparator. By setting a threshold current or threshold voltage and comparing the current or voltage value detected by the array detector 130 with the level comparator, it is possible to directly determine whether a clique has formed based on the comparison result. Compared to traditional methods that require post-processing in a digital backend for determination, this embodiment offers faster solution speed, simpler hardware structure, and lower power consumption.

[0043] Since the frequency of computation using the photonic chip 120 depends primarily on the rate of the accompanying optical switch, and current optical switches can reach speeds of tens of GHz, the photonic chip 120 can solve the maximum clique problem at ultra-high speed. Furthermore, by utilizing the propagation time of light within the photonic chip 120, the maximum clique problem can be solved, thereby significantly reducing computational latency. In summary, the system 100 according to an embodiment of the present invention, by using an architecture including the photonic chip 120 to compute the maximum clique problem, can greatly improve computational speed and reduce latency and power consumption.

[0044] As an example, for a maximum clique problem with 10 vertices, a conventional exhaustive search method would require trying 1024 combinations. Using an electronic computing scheme with a clock speed of GHz, this would take at least milliseconds. In contrast, using the computing scheme disclosed in the embodiments herein, which includes a photonic chip 120, and assuming the chip size is on the order of cm, results can be obtained with a sub-nanosecond latency, provided the chip size supports solving for 10 vertices.

[0045] In some embodiments, the number of vertices in the clique to be solved is greater than or equal to 2, and less than or equal to the total number of vertices involved in the maximal clique problem, which will be discussed in conjunction with the following. Figures 2-4 Further description.

[0046] In some embodiments, the array light input source 110 may include an array of light sources (e.g., an array of multiple light sources) and corresponding array light switches (e.g., an array of multiple light switches). Each light switch may be coupled to a corresponding light source, thereby controlling whether light emitted by the light source is input through the on / off state of the light switch. Accordingly, if there are connections between corresponding vertices to form an edge, the corresponding light switch may be configured to be on to input light from the corresponding light source.

[0047] In some embodiments, the array light input source 110 may include a controllable array light switch. The function of the controllable array light switch is equivalent to that of an array light source and an array light switch. Accordingly, if there are lines between corresponding vertices to form an edge, the controllable array light switch causes the corresponding light switch to open to input the corresponding light.

[0048] In some embodiments, the array light input source 110 may be external to the photonic chip 120, and the photonic chip 120 may be coupled to the array light input source 110 (e.g., Figure 1 (as shown in the figure). In some embodiments, the array light input source 110 may also be integrated on the photonic chip 120.

[0049] In some embodiments, the splitter 125 may include a multi-mode interferometer (MMI), a Y-junction, a directional coupler, or any combination thereof.

[0050] In some embodiments, the splitter 125 may include an MMI-based one-input multiple-output splitter, a cascaded MMI-based splitter, a cascaded directional coupler-based splitter, or any combination thereof. The following will be combined with... Figure 5 Describe the various possible forms of splitter 125.

[0051] In some embodiments, the array detector 130 may be mounted on the output of the photonic chip 120.

[0052] In some embodiments, each edge of the clique to be solved is arranged in columns. The array detector 130 can be configured to detect the power of the output light for each column and sum the detected output light power. This will be discussed in conjunction with the following. Figure 4 Further description.

[0053] In some embodiments, comparator 140 may be configured to compare the sum of the power values ​​with the corresponding threshold power for each column. This will be discussed in conjunction with the following. Figure 4Further description.

[0054] In some embodiments, array detector 130 may include a summation detector. In some embodiments, array detector 130 may include a detector whose detection surface covers all light input sources associated with the edge formed between every two vertices of the maximal clique problem.

[0055] Figure 2 This is a diagram illustrating the maximum clique problem with 5 vertices. Figure 2 In the graph theory problem with 5 vertices shown, solving its maximal clique requires finding the complete graph containing the most vertices.

[0056] Figure 3 This is a schematic diagram illustrating the optical path structure of a splitter for a photonic chip according to some embodiments of the present invention.

[0057] Figure 3 The diagram shows splitter 310, splitter 320 (and more possible optional splitters). Splitters 310 and 320 can be... Figure 1 The splitter 125 shown is not limited thereto.

[0058] Combination Figure 2 The solution shown involves a maximal clique problem with 5 vertices. Edges formed by the following vertex pairs can be considered: AB, AC, AD, AE, BC, BD, BE, CD, CE, DE. Correspondingly, there can be light input sources associated with each of these edges. Splitters 310 and 320 can be used to split the light input from the light input sources associated with the corresponding edges.

[0059] like Figure 3 As shown, splitter 310 can split the light input from the optical input source associated with edge AB (e.g., divide the input optical power equally). Splitter 320 can split the light input from the optical input source associated with edge AC (e.g., divide the input optical power equally), and so on.

[0060] Splitter 310 and splitter 320 can divide the input light into a predetermined number of beams according to power, wherein the predetermined number may be associated with the number of cliques to be solved. In some embodiments, the number of vertices in the clique to be solved is greater than or equal to 2 and less than or equal to the total number of vertices involved in the maximal clique problem. In some embodiments, to simplify the system, a problem with at least three vertices in the maximal clique to be solved may be considered. As an example, the clique to be solved may include a set of vertices, the elements of which may be determined based on the superset of the two vertices of the corresponding edge. As an example, for Figure 2The problem shown solves a maximum clique problem with 5 vertices. The supersets of the edges AB, AC, AD, AE, BC, BD, BE, CD, CE, DE formed by every pair of vertices are as follows:

[0061] AB :ABC,ABD,ABE,ABCD,ABCE,ABDE,ABCDE

[0062] AC :ABC,ACD,ACE,ABCD,ABCE,ACDE,ABCDE

[0063] AD : ABD, ACD, ADE, ABCD, ABDE, ACDE, ABCDE

[0064] AE :ABE, ACE, ADE, ABCE, ABDE, ACDE, ABCDE

[0065] BC : ABC, BCD, BCE, ABCD, ABCE, ABDE, ABCDE

[0066] BD :ABD, BCD, BDE, ABCD, ABDE, BCDE, ABCDE

[0067] BE :ABE, BCE, BDE, ABCE, ABDE, BCDE, ABCDE

[0068] CD :ACD, BCD, CDE, ABCD, ACDE, BCDE, ABCDE

[0069] CE : ACE, BCE, CDE, ABCE, ACDE, BCDE, ABCDE

[0070] DE : ADE, BDE, CDE, ABDE, ACDE, BCDE, ABCDE

[0071] It is evident that for each pair of vertices forming an edge, there exists a superset containing 7 elements. Accordingly, the optical power input to the optical source associated with each edge can be divided into 7 equal parts. Figure 3 The diagram shows that splitter 310 divides the optical power input from the optical input source associated with edge AB into 7 equal parts, and splitter 320 divides the optical power input from the optical input source associated with edge AC into 7 equal parts.

[0072] Generally, for a graph with N vertices, the maximum number of edges is N*(N-1) / 2. In this embodiment, to simplify the system, we consider solving for the maximum clique problem, which requires at least three vertices. Therefore, the search for the maximum clique problem can start from a vertex count of 3 (if three or more vertices do not meet the maximum clique condition, we can determine this by considering the light power input. If two vertices are connected by an edge, a clique containing those two vertices can be formed; if the light power input is 0, meaning two vertices are not connected by an edge, no clique is formed), and continue searching until the total number of vertices in the clique is reached.

[0073] Assume the power of each optical input source associated with each of the aforementioned edges is P, and splitters 310 and 320 divide the power of the light input from each optical input source into K equal parts (K = 7 in this example). For the number of vertices M contained in the clique to be solved, the corresponding threshold power can be determined as M*(M-1) / 2 / K*P. If the sum of the output power detected for each element of the vertex set to be solved is greater than or equal to the threshold, it can be determined that the vertices in that element satisfy the clique formation condition and can form a clique; otherwise, it can be determined that the vertices in that element do not satisfy the clique formation condition and cannot form a clique.

[0074] As an example, for the clique ABC that needs to be solved, the number of vertices is M=3 and K=7, then the threshold power = 3*(3-1) / 2 / 7*P = 3 / 7*P.

[0075] As an example, for the clique ABCD that needs to be solved, the number of vertices is M=4 and K=7, then the threshold power = 4*(4-1) / 2 / 7*P = 6 / 7*P.

[0076] As an example, for the clique ABCDE that needs to be solved, the number of vertices is M=5 and K=7, then the threshold power = 5*(5-1) / 2 / 7*P = 10 / 7*P.

[0077] This can be combined with the following text. Figure 4 The array is summed and compared in a manner described to determine whether the clique to be solved satisfies the clique condition (i.e., whether the corresponding vertex set can form a clique).

[0078] Figure 4 This is a schematic diagram illustrating the detection of the output of a photonic chip according to some embodiments of the present invention.

[0079] Figure 4 Column dimensions and Figure 2 The solution shown is a maximum clique problem with 5 vertices where any two vertices form an edge corresponding to each other. The row dimension is consistent with the above. Figure 3The description consists of the elements of the vertex set of the clique for the required solution obtained from each edge (where duplicate elements are considered to be merged). Positions marked "1" in the array indicate that the light from the light input source associated with the edge is to be detected after being split.

[0080] exist Figure 4 In the example shown, for each element ABC, ABD, ABE, ACD, ACE, ADE, BCD, BCE, BDE, CDE, ABCD, ABCE, ACDE, BCDE, ABCDE of the vertex set of the clique to be solved, the detected output power can be summed column-wise. For example... Figure 4 As shown, if normalization is performed using P / 7, then for elements ABC, ABD, ABE, ACD, ACE, ADE, BCD, BCE, BDE, and CDE containing 3 vertices, the sum of the detected output power is 3 (i.e., corresponding to 3 / 7*P), which achieves the result described above. Figure 3 The threshold for calculating 3 vertices is 3 / 7*P; therefore, this graph problem can form a clique containing 3 vertices. Similarly, for elements ABCD, ABCE, ABDE, ACDE, and BCDE containing 4 vertices, the sum of the detected output power is 6 (i.e., corresponding to 6 / 7*P), which achieves the combined effect described above. Figure 4 The threshold for calculating three vertices is 6 / 7*P; therefore, this graph problem can form a clique containing four vertices. Similarly, for an element ABCDE containing five vertices, the sum of the detected output powers is 10 (i.e., corresponding to 10 / 7*P), which achieves the combined effect described above. Figure 3 The threshold for calculating three vertices is 10 / 7*P. Therefore, this graph problem can form a clique containing five vertices. In summary, the maximal clique of this graph problem is the clique ABCDE containing five vertices A, B, C, D, and E.

[0081] In some embodiments, a summation detector can be used for, for example, Figure 4 The power of the output light detected in each column shown is summed. In some embodiments, a detector whose detection surface can cover the entire area of ​​each column may also be used.

[0082] In some embodiments, in order to compare the sum of the detected powers with a threshold power, the output photocurrent can be compared with a threshold photocurrent.

[0083] Figure 5 This is a schematic diagram illustrating various structures of an optical splitter for a photonic chip according to some embodiments of the present invention.

[0084] In some embodiments, an MMI arrangement 510 may be used, which is an MMI-based one-input multiple-output splitter. The splitter can divide a received beam of light into a predetermined number of beams of light according to their power.

[0085] In some embodiments, a Y-junction arrangement 530 may be used, which is a splitter based on a cascaded MMI and may include multiple stages of splitters. As an example, input light received at input 531 of the first stage can be split into two beams of equal power, output from output 532 and output 533 respectively. The light output from output 532 and output 533 can be further cascaded with their respective splitters (not shown) for further beam splitting.

[0086] In some embodiments, a directional coupler arrangement 550 can be used, which is a splitter based on cascaded directional coupling. To divide the power P of the received incident light into n equal parts, couplers 551 and 552 at the first stage can split the input beam at a splitting ratio of 1:n-1. Coupler 552 can also continue to be cascaded with subsequent couplers, such that the entire directional coupler arrangement 550 splits the light at each stage at splitting ratios of 1:n-1; n-2, ..., 1:2; 1:1, respectively. The splitting ratio of each coupler can be achieved by designing the length of the waveguide coupling region and the waveguide spacing.

[0087] Figure 6 This is a block diagram illustrating a system 600 for solving the maximal clique problem according to some embodiments of the present invention.

[0088] System 600 includes an array of optical input sources 610, at least two photonic chips (shown as photonic chips 620a, 620b, 620c, ... 620d), an array of detectors 630, and a comparator 640.

[0089] The array of light input sources 610 may include multiple light input sources. The array of light input sources 610 can be configured to controllably input light from one or more of the multiple light input sources. Each light input source may be associated with an edge formed between the vertices involved in the maximum clique problem to be solved, and whether light from each light input source is input can be determined based on whether the corresponding vertices are connected to form an edge. As an example, if there is a connection between the corresponding two vertices to form an edge, then light from the light input source is input; otherwise, light from the light input source is not input. Thus, the edge formed between the vertices involved in the maximum clique problem can be mapped to the on / off state of each light input source. Other aspects of the array of light input sources 610 are referenced above. Figure 1 The array optical input source 110 described is similar.

[0090] Photonic chips 620a, 620b, 620c, ..., 620d can be stacked on top of each other. Each photonic chip in the series 620a, 620b, 620c, ..., 620d may include a corresponding splitter (in... Figure 6 The diagram shows photonic chip 620a including a splitter 625a. The splitter in each of the photonic chips 620a, 620b, 620c, ..., 620d can be used to divide the optical power of the corresponding optical input source equally into a predetermined number of beams for each edge associated with that source. This predetermined number is related to the number of cliques to be solved. The cliques to be solved may include a set of vertices, which may be determined at least in part based on the superset of the two vertices of the corresponding edge. (The above is combined with...) Figures 2-4 The method for determining the predetermined quantity and vertex set described above. Other aspects of each photonic chip in photonic chips 620a, 620b, 620c, ..., 620d can be found in the above reference. Figure 1 The photonic chip 120 is described similarly. The splitters for each of the photonic chips 620a, 620b, 620c, ..., 620d can be combined with the above. Figure 1 The splitter 125 of the described photonic chip 120 is similar.

[0091] In some embodiments, each of the photonic chips 620a, 620b, 620c, ..., 620d may include a gallium nitride waveguide and can be fabricated using CMOS processes. Compared to other common methods of forming waveguides (e.g., using silicate glass and femtosecond laser direct writing for waveguide writing), the waveguide material used in these embodiments has low loss, and the waveguide formation method has a fast fabrication rate, more stable process, and is more suitable for large-scale processing.

[0092] Array detector 630 can be coupled to photonic chips 620a, 620b, 620c, ..., 620d. Array detector 630 can be configured to receive equally divided light. Array detector 630 can also be configured to detect the sum of output powers for each element of the vertex set of the clique to be solved. The back-mounted array detector 630 can directly sum the detected output powers, providing faster information on the maximal clique compared to detection schemes using CCDs (which primarily aim to understand the clique formation of all cliques). (The above is combined with...) Figures 2-4 This describes how the power sum is detected and determined for each element set of the vertex set of the clique to be solved. Other aspects of the array detector 630 can be combined with the above. Figure 1 The array detector 130 described is similar.

[0093] Comparator 640 may be coupled to array detector 630. Comparator 640 may be configured to compare the sum of the powers detected for each element of the vertex set of the clique to be solved with a threshold power. The threshold power may be determined at least in part based on the number of cliques to be solved and the number of vertices in the elements of the vertex set of the cliques to be solved. The result of this comparison may indicate whether the vertex set associated with each clique to be solved is clique-like, and the solution to the maximal clique problem is determined at least in part based on whether the vertex set associated with each clique to be solved is clique-like. As an example, comparator 640 may include a level comparator. Other aspects of comparator 640 may be combined with the above. Figure 1 The comparator 140 described is similar. By setting a threshold current or threshold voltage and comparing the current or voltage values ​​detected by the array detector 130 with those obtained by a level comparator, it is possible to directly determine whether a clique has formed. Compared to traditional methods that require post-processing in a digital backend, this embodiment offers faster solution speed, simpler hardware structure, and lower power consumption.

[0094] Since the frequency of computation using photonic chips 620a, 620b, 620c, ..., 620d depends primarily on the rate of the accompanying optical switches, and current optical switches can reach speeds of tens of GHz, the maximum clique problem can be solved at ultra-high speed using photonic chips 620a, 620b, 620c, ..., 620d. Furthermore, the maximum clique problem can be solved using photonic chips 620a, 620b, 620c, ..., 620d in a time equivalent to the propagation time of light within them, thereby significantly reducing computational latency. In summary, the system 600 according to an embodiment of the present invention, by using an architecture including photonic chips 620a, 620b, 620c, ..., 620d to compute the maximum clique problem, can greatly improve computational speed and reduce latency and power consumption.

[0095] Furthermore, in this embodiment, the summation of the output power of multiple optical signals detected by the array detector 630 can be easily achieved by stacking multiple photonic chips 620a, 620b, 620c, ..., 620d, thus avoiding the loss and crosstalk caused by waveguide crossing.

[0096] Figure 7 This is a schematic diagram illustrating the optical path structure of a photonic chip stack 700 and a corresponding splitter for each photonic chip according to some embodiments of the present invention. The photonic chip stack 700 can be a combination of the above. Figure 6 The photonic chip stack formed by the photonic chip 620a, photonic chip 620b, photonic chip 620c, photonic chip 620d... is described, but the scope of the present invention is not limited thereto.

[0097] The photonic chip stack 700 may include photonic chips 710, 720, ... Photonic chip 710 may include splitter 715, photonic chip 720 may include splitter 720, and so on. Splitters 715, 720, ... can respectively split the light input from the light input source associated with the corresponding edge (e.g., AB, AC, ...). The splitting process and principle can be combined with the above. Figure 3 The descriptions of splitter 310 and splitter 320 are similar.

[0098] The photonic chip stack 700 sets the splitters for beam splitting on stacked photonic chips, and then conveniently uses subsequent array detectors to sum the multiple beams, avoiding losses and crosstalk caused by waveguide crossings.

[0099] According to another aspect of the present invention, a method for solving the maximum clique problem is provided.

[0100] Figure 8 This is a flowchart illustrating a method 800 for solving a maximum clique problem according to some embodiments of the present invention.

[0101] Method 800 may include, at block 810, configuring an array of optical input sources comprising a plurality of optical input sources to controllably input one or more of the plurality of optical input sources. Each optical input source may be associated with an edge formed between vertices involved in the maximal clique problem. Whether light from each optical input source is input is determined based on whether the corresponding vertices are connected to form an edge. The step at block 810 may be related to the above. Figure 1 The described array optical input source 110 or combined Figure 6 The array light input source 610 described is used for execution, but the scope of the invention is not limited thereto.

[0102] In some embodiments, the light input source may include an array of light sources and corresponding array of optical switches. The step at block 810 may include configuring the corresponding optical switch in the array of optical switches to be turned on based on connecting corresponding vertices to form edges.

[0103] In some embodiments, the optical input source may include a controllable array of optical switches. The step at block 810 may include configuring a corresponding optical switch in the controllable array of optical switches to input optical power based on connecting corresponding vertices to form edges.

[0104] Method 800 may include, at block 820, using a splitter in the photonic chip, dividing the optical power of the corresponding optical input source equally into a predetermined number of beams for each edge associated with the optical input source. The predetermined number is related to the number of cliques to be solved. The cliques to be solved may include a set of vertices, the elements of which are determined based on the supers of the two vertices of the corresponding edge. The step at block 830 can be derived from the above. Figure 1The described photonic chip 120 splitter 125 or combination Figure 6 The corresponding splitters of the described photonic chips 620a, 620b, 620c, ..., 620d are implemented, but the scope of the invention is not limited thereto. (The above is in conjunction with...) Figures 2-4 Describe the method for determining the aforementioned predetermined quantity and vertex set.

[0105] Method 800 may include: at block 830, receiving equally divided light by an array detector.

[0106] Method 800 may include: at block 840, the sum of output power is detected by an array detector for each element of the vertex set of the clique to be solved.

[0107] The steps at boxes 830 and 840 can be combined with the above. Figure 1 The array detector 130 or combined with Figure 6 The array detector 630 described herein performs the function, but the scope of the invention is not limited thereto. (The above is in conjunction with...) Figures 2-4 Describes how to probe and determine the power sum for each element set of the vertex set of the clique that needs to be solved.

[0108] In some embodiments, each edge of the clique to be solved is arranged in columns. The step at block 840 may include: probing the power of the output light for each column and summing the probing power of the output light.

[0109] Method 800 may include, at block 850, a comparator comparing the sum of powers detected for each element of the vertex set of the clique to be solved with a threshold power. The threshold power is determined based on the optical power input from the array light input source, the number of cliques to be solved, and the number of vertices in the cliques to be solved. The result of this comparison can be used to determine whether the vertex set associated with a particular clique solution satisfies the clique formation condition to form a subclique, and the result of the maximoclique problem solution is determined based on the formed subcliques. The subclique containing the largest number of vertices among the formed subcliques can be determined as the solved maximoclique. The step at block 850 can be derived from the above. Figure 1 The comparator 140 or combination described Figure 6 The comparator 640 described is performed, but the scope of the invention is not limited thereto.

[0110] In some embodiments, each edge of the clique to be solved is arranged in columns. The step at block 850 may include: comparing the sum of the power with the corresponding threshold power for each column.

[0111] In some embodiments, the photonic chip may include a gallium nitride waveguide and can be fabricated using CMOS processes. Compared to other common methods of forming waveguides (e.g., using silicate glass and femtosecond laser direct writing for waveguide writing), the waveguide material used in this embodiment has low loss, and the waveguide formation method has a fast fabrication rate, more stable process, and is more suitable for large-scale processing.

[0112] In some embodiments, the comparator may include a level comparator configured to compare the sum of the power values ​​for each column with a corresponding threshold power. By setting a threshold current or threshold voltage and comparing the current or voltage values ​​detected by the array detectors with the level comparator, it is possible to directly determine whether a clique has formed based on the comparison result. Compared to traditional methods that require post-processing in the digital backend for determination, this embodiment offers faster solution speed, simpler hardware structure, and lower power consumption.

[0113] Since the frequency of computation using photonic chips depends primarily on the rate of the accompanying optical switches, and current optical switches can reach speeds of tens of GHz, photonic chips enable ultra-high-speed solutions to the maximum clique problem. Furthermore, the maximum clique problem can be solved using the same propagation time of light within the photonic chip, thereby significantly reducing computational latency. In summary, the method 800 according to an embodiment of the present invention, by using an architecture including photonic chips to compute the maximum clique problem, can greatly improve computational speed and reduce latency and power consumption.

[0114] Various embodiments of the invention have been described with reference to the accompanying drawings. These embodiments are illustrative and not restrictive.

Claims

1. A system for solving the maximal clique problem, comprising: An array of light input sources includes multiple light input sources configured to controllably input light into one or more of the multiple light input sources, wherein each light input source is associated with an edge formed between vertices involved in a maximum clique problem, and whether light from each light input source is input is determined based on whether the corresponding vertices are connected to form an edge; A photonic chip, the photonic chip including a splitter configured to divide the optical power of the corresponding optical input source into a predetermined number of beams for each edge associated with an optical input source, the predetermined number being associated with the number of cliques to be solved, wherein the cliques to be solved include a set of vertices, the elements of which are determined based on the superset of the two vertices of the corresponding edge. An array detector, coupled to the photonic chip, is configured to: Receive equally divided light; and For each element of the vertex set of the clique to be solved, the sum of output power is detected; and a comparator, coupled to the array detector, is configured to compare the sum of power detected for each element of the vertex set of the clique to be solved with a threshold power, wherein the threshold power is determined based on the optical power input from the array optical input source, the number of cliques to be solved, and the number of vertices in the elements of the vertex set of the cliques to be solved, wherein the result of the comparison is used to determine whether the vertex set associated with a particular clique solution satisfies the clique formation condition to form a subclique, and the result of the maximoclique problem solution is determined based on the formed subcliques.

2. The system as claimed in claim 1, wherein, The clique to be solved has a number of vertices greater than or equal to 2, and less than or equal to the total number of vertices involved in the maximal clique problem.

3. The system as described in claim 1, wherein, The array optical input source includes an array light source and a corresponding array optical switch; or The array optical input source includes a controllable array optical switch.

4. The system as claimed in claim 1, wherein, The array optical input source is integrated on the photonic chip; and / or The array detector is attached to the output end of the photonic chip.

5. The system as claimed in claim 1, wherein, Each edge of the clique to be solved is arranged in a column, and The array detector is configured to detect the power of the output light for each column and sum the power of the detected output light.

6. The system of claim 5, wherein, The comparator includes a level comparator configured to compare the sum of power with the corresponding threshold power for each column.

7. The system as claimed in claim 1, wherein, The array detector includes a summation detector or a detector whose surface covers all light input sources associated with the edge formed between every two vertices of the maximal clique problem.

8. The system of claim 1, wherein, The photonic chip includes a silicon nitride waveguide and is fabricated using CMOS technology.

9. The system as claimed in claim 1, wherein, The splitter includes at least one of a multimode interferometer, a Y-junction, and a directional coupler.

10. The system of claim 1, wherein, The splitter includes at least one of the following: One-input multiple-output splitter based on multimode interferometer; A splitter based on a cascaded multimode interferometer; Splitter based on cascaded directional couplers.

11. A system for solving the maximal clique problem, comprising: An array of light input sources includes multiple light input sources configured to controllably input light into one or more of the multiple light input sources, wherein each light input source is associated with an edge formed between vertices involved in a maximum clique problem, and whether light from each light input source is input is determined based on whether the corresponding vertices are connected to form an edge; At least two photonic chips are stacked on top of each other. Each photonic chip includes a splitter, and the splitter of each photonic chip is configured to divide the optical power of the corresponding optical input source into a predetermined number of beams for each edge associated with an optical input source. The predetermined number is associated with the number of cliques to be solved, wherein the cliques to be solved include a set of vertices, the elements of which are determined based on the superset of the two vertices of the corresponding edge. An array detector, coupled to the at least two photonic chips, is configured to: Receive equally divided light, and for each element of the vertex set of the clique to be solved, probe the sum of the output powers; and A comparator, coupled to the array detector, is configured to compare the sum of the powers detected for each element of the vertex set of the clique to be solved with a threshold power, wherein the threshold power is determined based on the optical power input from the array optical input source, the number of cliques to be solved, and the number of vertices of the cliques to be solved, wherein the result of the comparison is used to determine whether the vertex set associated with a particular clique solution can satisfy the clique formation condition to form a subclique, and the result of the maximoclique problem solution is determined based on the subcliques formed.

12. The system of claim 11, wherein, The photonic chip includes a silicon nitride waveguide and is fabricated using CMOS technology, and / or The comparator includes a level comparator configured to compare the sum of power with the corresponding threshold power for each column.

13. A method for solving the maximum clique problem, comprising: An array of optical input sources comprising multiple optical input sources is configured to controllably input one or more of the multiple optical input sources, wherein each optical input source is associated with an edge formed between vertices involved in the maximal clique problem, and whether light from each optical input source is input is determined based on whether the corresponding vertices are connected to form an edge. The optical power of the corresponding optical input source is divided into a predetermined number of beams by the splitter of the photonic chip for each edge associated with the optical input source. The predetermined number is associated with the number of cliques to be solved. The cliques to be solved include a set of vertices, and the elements of the vertex set are determined based on the superset of the two vertices of the corresponding edge. The equally divided light is received by an array detector; The sum of the output powers detected by the array detectors for each element of the vertex set of the clique to be solved; and The comparator compares the sum of the powers detected for each element of the vertex set of the clique to be solved with a threshold power, wherein the threshold power is determined based on the optical power input from the array optical input source, the number of cliques to be solved, and the number of vertices of the cliques to be solved. The result of the comparison is used to determine whether the vertex set associated with a specific clique solution satisfies the clique formation condition to form a subclique, and the result of the maximal clique problem solution is determined based on the subcliques formed.

14. The method of claim 13, wherein, The clique to be solved has a number of vertices greater than or equal to 2, and less than or equal to the total number of vertices involved in the maximal clique problem.

15. The method as described in claim 13, in, The optical input source includes an array of light sources and corresponding array of optical switches, and Configuring an array of optical input sources, comprising multiple optical input sources, to controllably input one or more of the multiple optical input sources includes: The corresponding optical switches in the array of optical switches are configured to be turned on by connecting corresponding vertices to form edges; or in, The optical input source includes a controllable array of optical switches, and Configuring an array of optical input sources, comprising multiple optical input sources, to controllably input one or more of the multiple optical input sources includes: The corresponding optical switches in the controllable array optical switches are configured to input optical power by connecting the corresponding vertices to form edges.

16. The method of claim 13, wherein, Each edge of the clique to be solved is arranged in a column, and The sum of the output powers detected by the array detectors for each set of vertices of the clique to be solved includes: The power of the output light for each column is detected, and the power of the detected output light is summed.

17. The method of claim 16, wherein, The comparator compares the sum of the powers probed for each set of vertices of the clique to be solved with the threshold power, including: For each column, the sum of the power is compared with the corresponding threshold power.

18. The method of claim 15, wherein, The photonic chip includes a silicon nitride waveguide and is fabricated using CMOS technology, and / or The comparator includes a level comparator configured to compare the sum of power with the corresponding threshold power for each column.

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