Memory system

Abstract

Embodiments of the invention relate to a memory system. A computer system according to an embodiment transmits, to a storage device, a write request specifying a first logical address for identifying first data to be written and a length of the first data. The computer system receives, from the storage device, a first physical address indicating both a first block selected by the storage device as a write target block for the first data from among blocks other than a defective block, and a first physical storage location within the first block to which the first data has been written, and the first logical address. The computer system maps the first physical address to the first logical address in a first table that manages a mapping between each logical address and each physical address of the storage device.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on August 6, 2018, with application number 201810887535.3 and title "Control Method for Computer System and Storage Device".

[0003] [Related Applications]

[0004] This application claims priority to Japanese Patent Application No. 2017-209344 (filed on October 30, 2017). This application incorporates the entire contents of that basic application by reference. Technical Field

[0005] The embodiments of the present invention relate to a computer system and a control method for a storage device. Background Technology

[0006] In recent years, storage devices with non-volatile memory have become increasingly common. One type of such storage device is the solid-state drive (SSD) based on NAND (Not And) flash memory technology. Storage devices used in computer systems such as servers in data centers require high I / O (Input / Output) performance. Therefore, new interfaces between the host side and the storage device side have recently been proposed.

[0007] However, if the number of faulty blocks in non-volatile memory increases, the following situation arises: on the storage device side, the amount of replacement information required to replace faulty blocks with other blocks increases, leading to increased read latency due to this replacement process. This can sometimes degrade the overall I / O performance of the system. Summary of the Invention

[0008] The embodiments of the present invention provide a computer system and control method that can improve I / O performance.

[0009] According to an embodiment, a computer system controlling a storage device comprising multiple nonvolatile memory dies, each containing multiple blocks, and a controller includes: a memory; and a processor configured to be electrically connected to the memory and to execute a computer program stored in the memory. The processor sends a write request to the storage device specifying a first logical address for identifying first data to be written and the length of the first data. The processor receives from the storage device a first physical address and a first logical address, the first physical address representing both a first block selected by the storage device from blocks excluding bad blocks as the target block for writing the first data, and a first physical storage location within the first block where the first data has been written. The processor maps the first physical address to the first logical address in a first table that manages the mapping between logical addresses and physical addresses of the storage device. Attached Figure Description

[0010] Figure 1 It is a block diagram showing the relationship between the host and the memory system (flash storage device).

[0011] Figure 2 This diagram illustrates the functional division between the flash storage device and the host computer.

[0012] Figure 3 This is a block diagram illustrating an example of the configuration of a flash storage device.

[0013] Figure 4 This is a diagram showing the instructions used by the In-Drive-GC API.

[0014] Figure 5 This is a diagram representing the instructions used by the superblock API.

[0015] Figure 6 This is a block diagram illustrating the relationship between the flash I / O control circuitry of the flash storage device and multiple NAND flash memory chips.

[0016] Figure 7 It is a diagram representing a superblock (parallel unit) constructed from a collection of multiple blocks.

[0017] Figure 8 It is a diagram used to illustrate the relationship between the block address of a superblock and the block addresses of the multiple blocks that make up the superblock.

[0018] Figure 9 This diagram illustrates the process of replacing each faulty block belonging to a non-volatile memory chip with other blocks of the same non-volatile memory chip.

[0019] Figure 10 It is a diagram used to illustrate the action of selecting the target block to write from non-bad blocks in the superblock without replacing bad blocks.

[0020] Figure 11 This is a diagram used to illustrate the write commands applied to flash storage devices.

[0021] Figure 12 It is used to explain the Figure 11 A diagram showing the response to the write command.

[0022] Figure 13 This is a diagram used to illustrate the Trim command applied to flash storage devices.

[0023] Figure 14 It is a diagram representing the action of writing data to a superblock that has bad blocks.

[0024] Figure 15 It means Figure 12 The diagram shows an example of the physical address contained in the response.

[0025] Figure 16 It is a diagram showing the relationship between the block address of the superblock and the block addresses of the blocks contained in the superblock.

[0026] Figure 17 It is a diagram used to illustrate the process of writing logical address-data pairs into pages within a block.

[0027] Figure 18 It is a diagram used to illustrate the action of writing data into the user data area of ​​a page within a block and writing the logical address of that data into the redundant area of ​​that page.

[0028] Figure 19 This diagram illustrates the process of writing multiple data units and a vanishing correction code calculated based on these data units into a superblock containing defective blocks.

[0029] Figure 20 This is a block diagram illustrating the relationship between the flash memory conversion unit within the host and the write operation control unit within the flash storage device.

[0030] Figure 21 It is a block diagram used to illustrate the write and read operations performed by the host and flash storage device.

[0031] Figure 22 It is a sequence diagram representing the sequence of write operations performed by the host and flash storage device.

[0032] Figure 23 It is a diagram that represents the data update action of writing new data to data that has already been written.

[0033] Figure 24It is a diagram used to illustrate the action of updating the block management table managed by the flash storage device.

[0034] Figure 25 It is a diagram used to illustrate the actions of updating the lookup table (logical physical address translation table) managed by the host.

[0035] Figure 26 It is a diagram used to illustrate the action of updating the block management table based on a notification from the host that represents the physical address corresponding to the data to be invalidated.

[0036] Figure 27 This is a diagram used to illustrate the read instructions applied to a flash storage device.

[0037] Figure 28 This is a diagram used to illustrate the reading operation performed by a flash storage device.

[0038] Figure 29 It is a sequence diagram representing the sequence of read processes performed by the host and flash storage device.

[0039] Figure 30 This is a diagram used to illustrate the garbage collection (GC) control instructions applied to flash storage devices.

[0040] Figure 31 This is a diagram used to illustrate the forced garbage collection (GC) instructions applied to flash storage devices.

[0041] Figure 32 This is a diagram used to illustrate the address update notification sent from the flash storage device to the host.

[0042] Figure 33 It is a sequence diagram showing the order of garbage collection (GC) actions performed by flash storage devices.

[0043] Figure 34 This is a diagram used to illustrate an example of the data copying action performed for garbage collection (GC).

[0044] Figure 35 It is used to explain based on Figure 34 The graph shows the result of the data replication action updating the contents of the host's lookup table.

[0045] Figure 36 This diagram illustrates the relationship between responses to write commands and GC callback processing (address update notifications).

[0046] Figure 37 It is a flowchart showing the sequence of lookup table update processes performed by the host.

[0047] Figure 38 This is a diagram illustrating an example of the structure of a block management table used to manage lookup counts.

[0048] Figure 39 It is a diagram used to illustrate the repetitive instructions applied to flash storage devices.

[0049] Figure 40 This is a sequence diagram representing the lookup count increment / decrement process performed by the host and flash storage device.

[0050] Figure 41 This is a flowchart showing the sequence of superblock allocation processes performed by the flash storage device.

[0051] Figure 42 It is a diagram used to illustrate the address translation operation of accessing the target block by logically arranging all non-bad blocks within the superblock sequentially from the beginning of the superblock.

[0052] Figure 43 This is a diagram used to illustrate an example of a bad information management table and address translation for address translation operations.

[0053] Figure 44 This is a block diagram illustrating the relationship between the flash memory conversion unit within the host and the defective block conversion unit within the flash storage device.

[0054] Figure 45 This is a block diagram illustrating an example of the structure of a host (computer system).

[0055] Figure 46 This is a diagram illustrating an example of the configuration of a host computer with a built-in flash storage device.

[0056] Figure 47 It is a flowchart showing the sequence of write operations performed by the host.

[0057] Figure 48 This is a flowchart showing the sequence of read operations performed by the host.

[0058] Figure 49 It is a flowchart showing the sequence of lookup count increment / decrement processing performed by the host. Detailed Implementation

[0059] Hereinafter, the embodiments will be described with reference to the accompanying drawings.

[0060] First, refer to Figure 1 This section explains the relationship between the host computer and the memory system.

[0061] This memory system is a semiconductor storage device configured to write data to and read data from non-volatile memory. This memory system is implemented as a flash storage device 3 based on NAND flash memory technology.

[0062] The host (host device) 2 is configured to control multiple flash storage devices 3. The host 2 is implemented by a computer system configured to use a flash array consisting of multiple flash storage devices 3 as storage. This computer system may also be a server.

[0063] Furthermore, the flash storage device 3 can also be used as one of multiple storage devices disposed within a storage array. The storage array can also be connected to a computer system such as a server via cable or network, and the storage array includes a controller that controls multiple storage devices (e.g., multiple flash storage devices 3) within the storage array. When the flash storage device 3 is used in a storage array, the controller of the storage array can also function as the host of the flash storage device 3.

[0064] The following example illustrates a computer system, such as a server, functioning as host 2.

[0065] The host (server) 2 and multiple flash storage devices 3 are interconnected (internal interconnection) via interface 50. This interface 50 for internal interconnection is not limited to this; it may use PCI Express (Peripheral Component Interconnect Express) (PCIe) (registered trademark), NVM Express (Non-Volatile Memory Express) (NVMe) (registered trademark), Ethernet (registered trademark), NVMe over Fabrics (NVMeOF), etc.

[0066] As a typical example of a server functioning as host 2, servers within a data center can be cited.

[0067] In an instance where host 2 is implemented as a server within a data center, host 2 can also be connected to multiple end-user terminals (clients) 61 via network 51. Host 2 can provide various services to these end-user terminals 61.

[0068] The services that host (server) 2 can provide include, for example: (1) providing a platform as a service (PaaS) to each client (each end user terminal 61) to operate the system; (2) providing infrastructure as a service (IaaS) to each client (each end user terminal 61) to provide infrastructure such as virtual servers, etc.

[0069] Multiple virtual machines can also run on the physical server that functions as host (server) 2. These virtual machines running on host (server) 2 can each function as a virtual server that provides various services to corresponding clients (end-user terminals 61).

[0070] The host (server) 2 includes storage management functions for managing multiple flash storage devices 3 that constitute the flash array, and front-end functions for providing various services including storage access to each end user terminal 61.

[0071] In existing SSDs, the block / page hierarchy of NAND flash memory is hidden by the Flash Translation Layer (FTL) within the SSD. That is, the existing SSD's FTL has the following functions: (1) managing the mapping between logical addresses and physical addresses of NAND flash memory using a lookup table that functions as a logical-to-physical address translation table; (2) hiding page-based read / write operations and block-based delete operations; and (3) performing garbage collection (GC) on the NAND flash memory. The mapping between logical addresses and physical addresses of NAND flash memory is not visible to the host. The block / page structure of the NAND flash memory is also not visible to the host.

[0072] On the other hand, in the host, an address translation (application-level address translation) is sometimes performed. This address translation uses an application-level address translation table to manage the mapping between logical addresses used by the application layer and logical addresses used by the SSD. Additionally, in the host, there are also cases where, in order to eliminate fragmentation in the logical address space used by the SSD, a garbage collection (GC) is performed to change the data configuration in that logical address space.

[0073] However, in a redundant configuration where both the host and SSD have address translation tables (the SSD has a lookup table that functions as a logical-to-physical address translation table, and the host has an application-level address translation table), storing these address translation tables consumes a significant amount of memory resources. Furthermore, the dual address translation involving both host-side and SSD-side address translation also contributes to the overall degraded I / O performance of the system.

[0074] Furthermore, application-level garbage collection (GC) on the host side becomes a factor that increases the amount of data written to the SSD by several times (e.g., twice) the actual amount of user data. While this increase in data write volume does not increase SSD write amplification, it reduces the overall storage performance of the system and shortens the lifespan of the SSD.

[0075] Therefore, in this embodiment, the FTL function is distributed between the host 2 and the flash storage device 3. The host 2 manages the lookup table, which functions as a logical-physical address translation table, but the blocks and pages to be written can be determined by the flash storage device 3, not the host 2. Furthermore, GC can also be performed by the flash storage device 3, not the host 2. Hereinafter, the FTL function transferred to the host 2 will be referred to as the global FTL.

[0076] In addition, the flash storage device 3 manages multiple parallel units (multiple superblocks) that each comprise multiple blocks (multiple physical blocks) to improve write / read speeds. The flash storage device 3 can perform write and read operations on multiple blocks within a parallel unit in parallel.

[0077] However, because NAND flash memory chips contain several defective blocks, there are situations where defective blocks within a parallel unit are replaced with other blocks to ensure parallelism. However, if the number of defective blocks in each NAND flash memory chip increases, the amount of information required for replacement management may increase.

[0078] Taking a parallel unit containing 64 blocks as an example, in the instance where the block addresses of each block are generated from the block address representing the parallel unit according to mathematical rules, if the 15th block out of 64 blocks is replaced with block address 2049, at least 6 bits are needed to represent the 15th block, and 12 bits are needed to represent 2049. When the number of blocks to be replaced is large, the amount of information required is proportional to it. If the number of blocks to be replaced is set to a maximum of 16, then 18 bits × 16 = 294 bits of information are needed for each parallel unit.

[0079] Furthermore, during data reading, substitution information must be used to perform address translation, converting the address representing a bad block to the address representing the target block. Therefore, if the number of bad blocks increases, the time required for this address translation process increases along with the increase in substitution information, thus increasing read latency.

[0080] Therefore, in the write operation for writing data from host 2, flash storage device 3 avoids bad blocks within the parallel unit of the write target and selects a write target block from the non-bad blocks within that parallel unit, and determines the write target position within that write target block. Data from host 2 is written to this write target position. Furthermore, flash storage device 3 notifies host 2 of the physical addresses representing both the write target block and the write position within that write target block. Thus, host 2 can identify the block where data has actually been written and the write target position within that block. Therefore, when it is necessary to read the data, a read request specifying that physical address can be sent to flash storage device 3. Flash storage device 3 can read data from the write target position within the selected block based on the physical address specified in the read request. Therefore, in flash storage device 3, address translation processing is unnecessary, reducing read latency.

[0081] The global FTL of host 2 may also have functions such as performing storage services, managing lookup tables (LUTs), software and hardware control functions, functions for achieving high availability, and deduplication functions to prevent multiple duplicate data with the same content from being stored in the storage.

[0082] On the other hand, the flash storage device 3 can perform low-level abstraction (LLA). LLA is an abstraction function for NAND flash memory. LLA includes functions such as auxiliary data configuration. These auxiliary data configuration functions include determining the write target location (block address, location within that block) of user data, notifying the upper-level layer (host 2) of the physical address indicating the write target location where user data has been written, determining the source block and target block for garbage collection, and notifying the upper-level layer (host 2) of the copy target location for valid data. Furthermore, LLA also has QoS control functions for performing resource management of the flash storage device 3 for each domain (QoS (Quality of Service) domain).

[0083] The QoS control function includes the ability to determine the access unit (data granularity) for each QoS domain. The access unit represents the minimum data size (data granularity) that host 2 can write / read. Flash storage device 3 supports single or multiple access units (data granularities). When flash storage device 3 supports multiple access units, host 2 can indicate the access unit (data granularity) to be used for each QoS domain to flash storage device 3.

[0084] In addition, the QoS control functions include features to prevent performance interference between QoS domains as much as possible. This feature is designed to maintain a substantially stable latency.

[0085] To achieve this, the flash storage device 3 can also logically divide the NAND flash memory into multiple regions (multiple QoS domains). One region (one QoS domain) contains more than one parallel unit (superblock). Each parallel unit (superblock) belongs to only one region (QoS domain).

[0086] Figure 2 This represents the overall hierarchical structure of the system, which includes the flash storage device 3 and the host 2.

[0087] On host (server) 2, virtual machine service 401 is executed to provide multiple virtual machines to multiple end users. In each virtual machine on virtual machine service 401, the corresponding operating system and user application 402 used by the end user are executed.

[0088] Additionally, in host (server) 2, multiple I / O services 403 corresponding to multiple user applications 402 are executed. These I / O services 403 may also include block I / O services based on LBA (logical block address), key-value storage services, etc. Each I / O service 403 includes a lookup table (LUT) that manages the mapping between each logical address and each physical address of the flash storage device 3. Here, a logical address refers to an identifier (tag) that identifies the data of the accessed object. This logical address can be a logical block address (LBA) specifying a location in the logical address space, a key in a key-value store, or a file identifier such as a filename.

[0089] In LBA-based block I / O services, a LUT that manages the mapping between each logical address (LBA) and each physical address of the flash storage device 3 can also be used.

[0090] In key-value storage services, a LUT can also be used to manage the mapping between each logical address (a tag such as a key) and the physical addresses of the flash storage device 3 that store the data corresponding to these logical addresses (i.e., tags such as keys). This LUT can also manage the correspondence between tags, the physical address storing the data identified by the tag, and the data length of that data.

[0091] Each end user can choose the addressing method to use (LBA, key-value store key, file identifier, etc.).

[0092] The LUTs do not translate the logical addresses from user application 402 into logical addresses for flash storage device 3, but rather translate the logical addresses from user application 402 into physical addresses for flash storage device 3. In other words, each LUT is a table obtained by integrating (merging) the table that translates logical addresses for flash storage device 3 into physical addresses with the application-level address translation table.

[0093] In host (server) 2, there is an I / O service 403 for each of the QoS domains. The I / O service 403 belonging to a certain QoS domain manages the mapping between the logical addresses used by user applications 402 within the corresponding QoS domain and the physical addresses of the areas allocated to the corresponding QoS domain.

[0094] The transmission of instructions from host (server) 2 to flash storage device 3 and the return of responses from flash storage device 3 to host (server) 2 are performed via I / O queues 500 present in both host (server) 2 and flash storage device 3. These I / O queues 500 can also be classified into multiple queue groups corresponding to multiple QoS domains.

[0095] The flash storage device 3 includes multiple write buffers (WB) 601 corresponding to multiple QoS domains, multiple garbage collection (GC) functions 602 corresponding to multiple QoS domains, and NAND flash memory (NAND flash array) 603.

[0096] Figure 3 This shows an example of the configuration of the flash storage device 3.

[0097] The flash storage device 3 includes a controller 4 and non-volatile memory (NAND flash memory) 5. The flash storage device 3 may also include random access memory, such as DRAM (Dynamic Random Access Memory) 6.

[0098] The NAND flash memory 5 includes a memory cell array comprising multiple memory cells arranged in a matrix. The NAND flash memory 5 can be a two-dimensional NAND flash memory or a three-dimensional NAND flash memory.

[0099] The NAND flash memory 5's cell array contains multiple blocks BLK0 to BLKm-1. Each block BLK0 to BLKm-1 consists of multiple pages (here, pages P0 to Pn-1). Blocks BLK0 to BLKm-1 function as deletion units. A block is sometimes referred to as a "delete block," "physical block," or "physical delete block." Pages P0 to Pn-1 each contain multiple memory cells connected to the same word line. Pages P0 to Pn-1 are the units for data write and data read operations.

[0100] The controller 4 is electrically connected to the NAND flash memory 5, which is a non-volatile memory, via a flash I / O control circuit 13 such as Toggle and Open NAND Flash Interface (ONFI). The controller 4 is a memory controller (control circuit) configured to control the NAND flash memory 5.

[0101] The NAND flash memory 5 contains multiple NAND flash memory chips. The controller 4 manages these multiple parallel units (parallel cells). Each parallel unit is implemented as a superblock, a group of blocks (multiple physical blocks) belonging to different NAND flash memory chips. The controller 4 can execute write and read operations on the multiple blocks contained in each parallel unit (superblock) in parallel. Each parallel unit (superblock) has its own unique superblock address (first block address). Each block within a non-volatile memory chip has its own unique block address (second block address). The block address of each block to be included in each parallel unit (superblock) is determined from the superblock of each parallel unit based on mathematical rules.

[0102] The controller 4 includes a host interface 11, a CPU (Central Processing Unit) 12, a flash I / O control circuit 13, and a DRAM interface 14. These components, including the CPU 12, the flash I / O control circuit 13, and the DRAM interface 14, are interconnected via a bus 10.

[0103] The host interface 11 is a host interface circuit configured to perform communication with the host 2. The host interface 11 can be, for example, a PCIe controller (NVMe controller). The host interface 11 receives various requests (instructions) from the host 2. These requests (instructions) include write requests (write instructions), read requests (read instructions), and various other requests (instructions).

[0104] CPU 12 is a processor configured with a host interface 11, a flash I / O control circuit 13, and a DRAM interface 14. In response to power-on of the flash storage device 3, CPU 12 loads a control program (firmware) from NAND flash memory 5 or a ROM (Read-Only Memory) not shown into DRAM 6, and then executes the firmware to perform various processes. Alternatively, the firmware can also be loaded into SRAM (Static Random-Access Memory) not shown within the controller 4. CPU 12 can perform instruction processing, etc., to process various instructions from the host 2. The operation of CPU 12 is controlled by the firmware executed by CPU 12. Furthermore, some or all of the instruction processing can also be performed by dedicated hardware within the controller 4.

[0105] CPU 12 can function as a write action control unit 21, a read action control unit 22, and a GC action control unit 23. Within these write action control units 21, read action control units 22, and GC action control units 23, there are components for implementing... Figure 2 The system configuration shown is an application programming interface (API).

[0106] The write action control unit 21 receives a write request (write instruction) from the host 2, specifying a logical address (tag) for identifying the data (user data) to be written. Upon receiving the write instruction, the write action control unit 21 first consults the defect information management table 33 and selects a block as the write target block from the non-defective blocks (non-defective blocks) contained in the parallel unit (superblock) of the write target. The defect information management table 33 stores defect information, which stores at least 1 bit of information indicating whether each block contained in each parallel unit (superblock) is usable or unusable. The defect information corresponding to each superblock may also be a bitmap containing the same number of bits as the number of blocks contained in each superblock. By consulting the defect information (defect information management table 33) corresponding to the parallel unit (superblock) of the write target, the write action control unit 21 can identify whether each block in the parallel unit of the write target is a defective block or a non-defective block.

[0107] Furthermore, the defective information is not limited to the bitmap; for example, information representing the number of deletions (programming / erasing cycles) for each block can also be used instead. In this case, the controller 4 can also determine blocks with a deletion count exceeding a certain threshold as defective blocks.

[0108] Bad blocks are unusable blocks and are also checked as "bad blocks". Bad blocks (bad blocks) represented by bad information may include bad blocks (primary bad blocks) generated during the manufacturing process of NAND flash memory, bad blocks (grown bad blocks) generated after the start of use of flash storage device 3, or both of these primary and secondary bad blocks.

[0109] The write action control unit 21 determines the write target location (page and position within that page) within the selected write target block. Next, the write action control unit 21 writes the data (write data) from the host 2 to the write target location of the write target block. In this case, the write action control unit 21 can not only write the data from the host 2 to the write target block, but also write both the data and its logical address (tag) to the write target block.

[0110] Then, the write action control unit 21 returns the specified logical address (tag) and the physical address representing the write target block and the write target location to the host 2.

[0111] In this case, the physical address can also be represented by the chip identifier, the physical block address (the second block address), and the offset. The chip identifier is an identifier inherent to each non-volatile memory chip. The chip identifier included in the physical address represents the chip identifier of the non-volatile memory chip to which the target block belongs. The physical block address is the block address (block number) used to identify the individual blocks within each non-volatile memory chip. The block address included in the physical address represents the block address of the target block. The offset is the intra-block offset. The offset included in the physical address represents the offset (offset value) from the beginning of the target block to the target location. This offset can also be represented by the page address of the page to which the target location belongs, and the intra-page offset corresponding to the target location.

[0112] Alternatively, the physical address can be represented by the superblock address (block 1 address) and an offset. The superblock address is the block address inherent to each superblock. The superblock address contained in this physical address represents the superblock address of the superblock to be written. The offset represents the offset (offset value) from the beginning of the superblock to the target location. This offset can also be represented by the chip identifier of the non-volatile memory chip to which the target block belongs, the page address of the page to which the target location belongs, and the offset within the page corresponding to the target location.

[0113] The physical address is also looked up as the "flash address".

[0114] Furthermore, the write command can specify not only the logical address (tag) but also the superblock address. Upon receiving a write command specifying a superblock address, the write action control unit 21 selects the superblock with the superblock address specified by the write command from among multiple superblocks as the parallel unit for writing (the write target superblock).

[0115] When the read action control unit 22 receives a read request (read instruction) from the host 2 with a specified physical address (indicating the block to be read and the location of the read object within that block), it reads data from the location of the read object within the block to be read based on that physical address.

[0116] When performing garbage collection on the NAND flash memory 5, the GC action control unit 23 selects copy source blocks (GC source blocks) and copy destination blocks (GC destination blocks) from multiple blocks within the NAND flash memory 5 for the purpose of garbage collection. Each of these GC source blocks and GC destination blocks can be a superblock or a physical block.

[0117] The GC action control unit 23 typically selects multiple source blocks (GC source blocks) and one or more target blocks (GC destination blocks). The conditions (GC strategy) used to select the source blocks (GC source blocks) can also be specified by the host 2. For example, a GC strategy that prioritizes the block with the least amount of valid data can be used as the source block (GC source block), or other GC strategies can be used. In this way, the selection of source blocks (GC source blocks) and target blocks (GC destination blocks) is not performed by the host 2, but by the controller 4 (GC action control unit 23) of the flash storage device 3. The controller 4 can also use block management tables to manage the amount of valid data in each block.

[0118] The management of valid / invalid data can also be performed using block management table 32. This block management table 32 can exist, for example, for each superblock. In the block management table 32 corresponding to a superblock, bitmap flags representing the valid / invalid data of each block within that superblock are stored. Here, valid data refers to data that has been looked up by the LUT (that is, data associated with the latest logical address) and is likely to be read by host 2 later. Invalid data refers to data that is no longer likely to be read by host 2. For example, data associated with a logical address is valid data, and data not associated with any logical address is invalid data.

[0119] The GC action control unit 23 determines the location (replication target location) within the replication target block (GC destination block) where the valid data stored in the replication source block (GC source block) should be written, and copies the valid data to that determined location (replication target location) in the replication target block (GC destination block). In this case, the GC action control unit 23 may also copy both the valid data and its logical address to the replication target block (GC destination block). The GC action control unit 23 may also specify the valid data in the GC source block by consulting the block management table 32 corresponding to the replication source block (GC source block). Alternatively, in other embodiments, the host 2 may specify the GC source block and the GC destination block. These GC source blocks and GC destination blocks may be superblocks or physical blocks.

[0120] Furthermore, the GC action control unit 23 notifies the host 2 of the logical address (tag) of the copied valid data, the physical address representing the old physical storage location of the copied valid data, and the physical address representing the new physical storage location of the copied valid data.

[0121] In this embodiment, as described above, the write action control unit 21 can write both the data (write data) from the host 2 and the logical address (tag) from the host 2 to the write target block. Therefore, the GC action control unit 23 can easily obtain the logical addresses of each data in the copy source block (GC source block), and thus can easily notify the host 2 of the logical addresses of the copied valid data.

[0122] The flash I / O control circuit 13 is a memory control circuit configured to control the NAND flash memory 5 under the control of the CPU 12. The DRAM interface 14 is a DRAM control circuit configured to control the DRAM 6 under the control of the CPU 12. A portion of the storage area of ​​the DRAM 6 is used to store the read buffer (RB) 30, write buffer (WB) 31, block management table 32, and defect information management table 33. In addition, these read buffers (RB) 30, write buffers (WB) 31, block management table 32, and defect information management table 33 may also be stored in an SRAM (not shown) within the controller 4.

[0123] Next, the API used as the software interface between the flash storage device 3 and the host 2 will be described. In this embodiment, the API is broadly divided into two types: the In-Drive-GC API and the Superblock API.

[0124] The In-Drive-GC-API contains a set of instructions that assume garbage collection (GC) is performed independently by the flash storage device 3. These instructions may include write instructions (Write without Physical Address), read instructions (Read with Physical Address), trim instructions, duplicate instructions, address update notification (DeviceInitiated), forced garbage collection instructions, and garbage collection control instructions as basic instructions.

[0125] A write instruction (without physical address) specifies the logical address (tag) that identifies the user data to be written, but does not specify the physical address of the target data.

[0126] A read instruction (Read with Physical Address) is a read instruction that specifies the physical address of the physical storage location (physical block, or the location of the read object within the physical block) of the object being read.

[0127] The Trim instruction specifies the physical address of data that should be invalidated and instructs the storage device 3 to invalidate the data corresponding to that physical address. Furthermore, when the host 2 supports a deduplication function to prevent multiple duplicate data entries with identical content from being stored in the storage, the Trim instruction instructs the storage device 3 to decrease the lookup count representing the number of logical addresses accessing certain data. The Duplicate instruction instructs the storage device 3 to increase the lookup count representing the number of logical addresses accessing certain data.

[0128] The Address Update Notification (Device Initiated) is used to notify the host 2 of the logical address of the copied data (valid data), the old physical storage location of the valid data, and the new physical storage location of the valid data after the flash storage device 3 performs a data copying operation for GC.

[0129] The Forced Garbage-Collection command is used to force the flash storage device 3 to perform a garbage collection (GC).

[0130] Garbage Collection Control (GC) instructions are used to instruct the flash storage device 3 on conditions for initiating GC, etc.

[0131] Figure 4 Examples of parameters and return values ​​for the instructions used in the In-Drive-GC-API.

[0132] exist Figure 4 In this context, the content following the "Host:" label is the parameter specified by the corresponding instruction, while the content following the "Device:" label is the parameter (return value) included in the response to that instruction.

[0133] Write commands (without physical address) can also include a user address, length, data, and QoS domain identifier. The user address is a logical address (label) used to identify the data to be written. User addresses may include, for example, LBAs, keys for key-value stores, file identifiers, etc.

[0134] The response to a write command may also include a status (success / failure), user address, flash memory address (physical address), length, and remaining writable data (distance-to-block-boundary). The remaining writable data (distance-to-block-boundary) is an optional return value, representing the amount of data remaining that can be written to the superblock where data has already been written. The remaining writable data (distance-to-block-boundary) may also be represented as a multiple of the data granularity. Data sometimes spans the writing of two non-bad blocks before and after a bad block. Therefore, the response to a write command may also include multiple sets, each containing the user address, flash memory address (physical address), and length.

[0135] A read instruction (Read with Physical Address) may also include the flash memory address and length. A read instruction (Read with Physical Address) may also include multiple sets, each containing the flash memory address and length. The response to a read instruction may also include status, user address, length, and data. The response to a read instruction may also include multiple sets, each containing the user address and length.

[0136] Disabling the Trim / Duplicate command can also include increments or decrements in the flash memory address, length, and reference count. Disabling the Trim / Duplicate command can also include multiple sets, each containing increments or decrements in the flash memory address, length, and reference count.

[0137] The Address Update Notification (Device Initiated) may also include the user address, old flash memory address, new flash memory address, lookup count, and length as output parameters notified by the flash storage device 3 to the host 2. For example, after the flash storage device 3 copies data from the old physical storage location to the new physical storage location, it sends an Address Update Notification (Device Initiated) to the host 2. This Address Update Notification (Device Initiated) may also include the user address of the data, the old flash memory address representing the old physical storage location of the data, the new flash memory address representing the new physical storage location of the data, the lookup count representing the number of logical addresses that have looked up the data, and the length of the data. The Address Update Notification (Device Initiated) may also include multiple sets, each containing the user address, old flash memory address, new flash memory address, lookup count, and length.

[0138] The Forced Garbage-Collection directive may also include a QoS domain identifier and the source superblock address (optional).

[0139] Garbage Collection Control (GC) instructions can also include the maximum number of data, QoS domain identifiers, and GC methods (policies).

[0140] The Superblock API includes a set of instructions that specify a logical address (tag) and a superblock on host 2, and the flash storage device determines the write target block and the write target location within that superblock. These instructions include write instructions (Write without Page Address), read instructions (Read with Physical Address), superblock release instructions (Release Super Block to Unused Super Block Pool), superblock allocation instructions (Allocate Super Block and Open Write Buffer with Block Healing), superblock close instructions (Close Super Block and Write Buffer), superblock information instructions, non-copy data setting instructions (Set Data not to be Copied), and data copy instructions (Data Copy without Page Address).

[0141] Write instructions (without page address) specify a logical address (tag) and a superblock address. Read instructions are the same as those used in the In-Drive-GC-API. ReleaseSuperBlock to UnusedSuperBlock Pool instructions release allocated superblocks. AllocateSuperBlock and Open Write Buffer with Block Healing instructions request the allocation of a superblock. AllocateSuperBlock and Open Write Buffer with Block Healing instructions can also include a parameter specifying the number of blocks that can be accessed concurrently. SuperBlock Information instructions retrieve information related to a specific superblock. Set Data not to be Copied instructions specify data within a superblock that should not be copied. Data Copy instructions (without page address) copy data for GC purposes. Examples of parameters and return values ​​for these instructions are shown in... Figure 5 In. Figure 5 In this context, the content following the "Host:" label represents the parameters specified by the corresponding instruction, while the content following the "Device:" label represents the parameters (return value) included in the response to the instruction.

[0142] Figure 6 This indicates the relationship between the flash I / O control circuit 13 and multiple NAND flash memory chips.

[0143] like Figure 6 As shown, the NAND flash memory 5 comprises multiple NAND flash memory chips. Each NAND flash memory chip is a non-volatile memory chip including a memory cell array containing multiple blocks (physical blocks) BLKs and peripheral circuitry controlling the memory cell array. Each NAND flash memory chip can operate independently. Therefore, the NAND flash memory chip functions as the smallest parallel operating unit. NAND flash memory chips are also referred to as "NAND flash memory chips" or "non-volatile memory chips." Figure 6The example illustrates the following scenario: A flash I / O control circuit 13 is connected to 16 channels Ch0, Ch1, ... Ch15, and each of these channels Ch0, Ch1, ... Ch15 is connected to the same number (e.g., one chip per channel) of NAND flash memory chips. Each channel contains a communication line (memory bus) for communicating with the corresponding NAND flash memory chip.

[0144] Controller 4 controls NAND flash memory chips #0 to #15 via channels Ch0, Ch1, ... Ch15. Controller 4 can drive channels Ch0, Ch1, ... Ch15 simultaneously.

[0145] exist Figure 6 In this configuration example, up to 16 NAND flash memory chips can operate in parallel.

[0146] In this embodiment, the controller 4 manages multiple parallel units (superblocks), each comprising multiple blocks (BLKs). The superblock is not limited to this; it may also contain a total of 16 blocks (BLKs) selected sequentially from NAND flash memory chips #0 to #15 connected to different channels. Furthermore, each of the NAND flash memory chips #0 to #15 may have a multi-plane configuration. For example, if each of the NAND flash memory chips #0 to #15 has a multi-plane configuration containing two planes, a superblock may contain a total of 32 blocks (BLKs) selected sequentially from the 32 planes corresponding to the NAND flash memory chips #0 to #15.

[0147] exist Figure 7 The example illustrates a superblock SB comprising 16 block BLKs selected sequentially from NAND flash memory chips #0 to #14. During the write operation to the superblock SB, data is written in the following order: page P0 of block BLK belonging to NAND flash memory chip #0, page P0 of block BLK belonging to NAND flash memory chip #1, ..., page P0 of block BLK belonging to NAND flash memory chip #15, page P1 of block BLK belonging to NAND flash memory chip #0, page P1 of block BLK belonging to NAND flash memory chip #2, ..., page P1 of block BLK belonging to NAND flash memory chip #15, ...

[0148] Figure 8 This indicates the relationship between the block address of the superblock SB (superblock address) and the block addresses of the multiple blocks (physical blocks) that make up the superblock SB.

[0149] The block address of each block (physical block) that should be included in the superblock SB is determined from the block address (superblock address) of the superblock SB based on a certain mathematical rule.

[0150] For example, the value obtained by performing specific arithmetic operations on the superblock address of the superblock SB can be used to determine the block addresses that should be included in the superblock SB. Alternatively, the value obtained by performing specific bit flips or specific bit shifts on multiple bits representing the superblock address of the superblock SB can be used to determine the block addresses that should be included in the superblock SB.

[0151] exist Figure 8 To simplify the illustration, the case in which the superblock SB is composed of blocks having the same block address as the superblock SB is illustrated.

[0152] In other words, the superblock SB0 with superblock address 0 is composed of block BLK0 with block address 0 contained in NAND flash memory chip #0 (chip #0), block BLK0 with block address 0 contained in NAND flash memory chip #1 (chip #1), block BLK0 with block address 0 contained in NAND flash memory chip #2 (chip #2), ..., block BLK0 with block address 0 contained in NAND flash memory chip #15 (chip #15).

[0153] Similarly, the superblock SB1000 with superblock address 1000 is composed of block BLK1000 with block address 1000 contained in NAND flash memory chip #0 (chip #0), block BLK1000 with block address 1000 contained in NAND flash memory chip #1 (chip #1), block BLK1000 with block address 1000 contained in NAND flash memory chip #2 (chip #2), ..., block BLK1000 with block address 1000 contained in NAND flash memory chip #15 (chip #15).

[0154] There are cases where each chip contains several defective blocks. Typically, the number of defective blocks varies for each chip.

[0155] exist Figure 9 The diagram illustrates the process of replacing defective blocks contained in each chip with other blocks belonging to the same chip.

[0156] exist Figure 9 In the example, consider the following scenario: each chip contains 2048 blocks (BLK), chip #0 contains 100 defective blocks, chip #1 contains no defective blocks, chip #2 contains 20 defective blocks, and chip #15 contains 30 defective blocks.

[0157] In chip #0, for example, faulty block BLK1 is replaced by non-faulty block BLK1948 of chip #0, and faulty block BLK5 is replaced by non-faulty block BLK1949 of chip #0. In this way, only 1948 (=2048-100) blocks from the beginning of chip #0 become usable, and the remaining blocks BLK1948~BLK2047 of chip #0 are unusable.

[0158] Therefore, even if chip #1 does not contain any bad blocks, blocks BLK1948 to BLK2047 of chip #1 cannot be used to construct a superblock. Thus, the number of superblocks SB that can be constructed is limited to the number of non-bad blocks within chip #0, which has the most bad blocks.

[0159] Figure 10 This indicates the action of selecting a target block from non-bad blocks within a superblock SB without replacing the bad blocks.

[0160] exist Figure 10 To simplify the illustration, the following example is shown: A superblock (here, superblock SB5) is composed of 8 blocks, namely block BLK5 in chip #0, block BLK5 in chip #1, block BLK5 in chip #2, block BLK5 in chip #3, block BLK5 in chip #4, block BLK5 in chip #5, block BLK5 in chip #6, and block BLK5 in chip #7.

[0161] In this embodiment, a defect information management table 33 corresponding to each superblock is set up. In the defect information management table 33 used by superblock SB5, defect information (bitmap) is stored, which contains 1 bit of information indicating whether each block is usable or unusable. In the defect information (bitmap), "0" represents a non-defective block and "1" represents a defective block.

[0162] exist Figure 10 In the example, we envision that block BLK5 in chip #1, block BLK5 in chip #4, and block BLK5 in chip #5 are all defective blocks.

[0163] Controller 4 does not perform the processes of replacing block BLK5 in chip #1 with other blocks in chip #1, replacing block BLK5 in chip #4 with other blocks in chip #4, or replacing block BLK5 in chip #5 with other blocks in chip #5. Instead, controller 4 consults the defective information management table 33 used by super block SB5 and selects a block as the write target block from the non-defective blocks included in super block SB5 (here, block BLK5 in chip #0, block BLK5 in chip #2, block BLK5 in chip #3, block BLK5 in chip #6, and block BLK5 in chip #7). Controller 4 determines the write target location within the write target block and writes the write data from host 2 to the write target location within the write target block. Furthermore, controller 4 notifies host 2 of the physical addresses representing both the write target block and the write target location.

[0164] Therefore, host 2 can identify the block where data has actually been written (the target block) and the target location within that block. Thus, when the data must be read, a read request (read instruction) specifying the physical address of the notification can be sent to flash storage device 3. Specifically, host 2 first sends a write request (write instruction) containing the logical address (tag) identifying the data to be written to flash storage device 3. Host 2 receives from flash storage device 3 the physical address of the block selected as the target block from blocks other than bad blocks, the target location within that block (physical storage location), and the logical address (tag) of the data. Furthermore, host 2 updates the lookup table (LUT) on host 2, which manages the mapping between logical addresses (tags) and physical addresses on flash storage device 3, mapping the received physical address to the logical address (tag) identifying the data. When the data must be read, host 2 consults the lookup table (LUT) on host 2 to obtain the physical address mapped to the logical address (tag) of the data, and sends a read request (read instruction) specifying the obtained physical address to flash storage device 3.

[0165] In this embodiment, without replacing faulty blocks within the superblock to be written to with other blocks within the chip to which the faulty block belongs, data writing and reading operations for the superblock can be performed normally. Therefore, even if the number of faulty blocks increases, there is no need to manage a large amount of replacement information. Furthermore, address translation processing for replacement is not required, thus reducing read latency. Moreover, the number of superblocks can be essentially the same as the number of blocks belonging to each chip, so even if the number of faulty blocks increases, almost all non-faulty blocks can be utilized.

[0166] Figure 11This indicates a write command applied to flash storage device 3 (Write without Physical Address).

[0167] This write command is a command to request data to be written to the flash storage device 3. As mentioned above, this write command may also include a command ID (Identifier), QoS domain ID, user address, length, etc.

[0168] The instruction ID is the ID (instruction code) that indicates that the instruction is a write instruction. The write instruction contains the instruction ID used for writing.

[0169] A QoS domain ID is an identifier that uniquely identifies the QoS domain to which data should be written. A write command sent from host 2 based on a write request from an end user may also contain a QoS domain ID specifying the QoS domain corresponding to that end user. Namespace IDs can also be used as QoS domain IDs.

[0170] A user address is a logical address (label) that identifies data. For example, LBA, keys, and file identifiers are equivalent to user addresses.

[0171] The length indicates the length of the data to be written. The length can be specified by the number of LBAs, or its size can be specified in bytes.

[0172] Figure 12 Indicates to Figure 11 The response to the write command.

[0173] The response includes the user address, flash memory address, length, and remaining writable data (distance-to-block-boundary).

[0174] The user address is Figure 11 The write instruction contains the user address.

[0175] Flash address representation based on Figure 11 The write command writes the physical address of the physical storage location of the data within the NAND flash memory 5.

[0176] In this embodiment, the physical address is specified, for example, by a combination of a chip identifier, a block address, and an offset (offset within the block), or a combination of a superblock address and an offset (offset within the superblock).

[0177] The length indicates the length of the data written. The length can be specified by the number of LBAs, or its size can be specified in bytes.

[0178] The remaining writable data (distance-to-block-boundary) represents the amount of data that can be further written to a superblock that has already been written to.

[0179] Figure 13 This indicates the Trim command applied to flash storage device 3.

[0180] The Trim instruction includes the instruction ID, flash address, length, and the amount of reference-count-to-subtract reduction.

[0181] The instruction ID is the ID (instruction code) that indicates that the instruction is a Trim instruction. The Trim instruction contains the instruction ID used by the Trim instruction.

[0182] A flash memory address indicates the initial physical storage location where data that should be invalidated (data that should reduce the lookup count) is stored. In this embodiment, the flash memory address is specified by a combination of a chip identifier, a block address, and an offset (offset within the block), or a combination of a superblock address and an offset (offset within the superblock).

[0183] The length indicates the length of the data that should be invalidated (the data that should reduce the lookup count). This length (data length) can also be specified in bytes.

[0184] Controller 4 uses block management table 32 to manage the valid / invalid flags (bitmap flags) representing the data contained in each of the multiple superblocks. When a Trim instruction containing a flash memory address indicating the physical storage location storing data that should be invalidated is received from host 2, controller 4 updates block management table 32, changing the flag (bitmap flag) corresponding to the data at the physical storage location corresponding to the flash memory address contained in the Trim instruction to a value indicating invalidity.

[0185] In instances that support deduplication, the lookup counts for the data contained in each of the multiple superblocks are managed in block management table 32. The amount by which the lookup count is reduced indicates the amount by which the lookup count should be decreased.

[0186] Next, refer to Figure 14 This section explains the action of writing data to a superblock containing bad blocks.

[0187] To simplify the illustration, imagine that a superblock SB0 is composed of four blocks BLK0 (chip #0), BLK0 (chip #1), BLK0 (chip #2), and BLK0 (chip #3), where BLK0 (chip #2) is a faulty block.

[0188] Controller 4 writes data in the following order, avoiding bad blocks: page 0 of block BLK0 (chip #0), page 0 of block BLK0 (chip #1), page 0 of block BLK0 (chip #3), page 1 of block BLK0 (chip #0), page 1 of block BLK0 (chip #1), page 1 of block BLK0 (chip #3), ...

[0189] With a page size of 16 KB and a data granularity of 4 KB, the initial 16 KB of data (D1–D4) is written to page 0 of block BLK0 (chip #0). The subsequent 16 KB of data (D5–D8) is written to page 0 of block BLK0 (chip #1). The write to BLK0 (chip #2) is skipped, and the subsequent 16 KB of data (D9–D12) is written to page 0 of block BLK0 (chip #3).

[0190] Figure 15 express Figure 12 An example of the physical address contained in the response.

[0191] Physical address such as Figure 15 The upper part of the diagram consists of the chip identifier of the chip to which the selected block belongs, the block address corresponding to the selected block, and the offset from the beginning of the selected block to the write target location. The offset from the beginning of the selected block to the write target location includes the page address and the offset within the page.

[0192] Or, such as Figure 15 As shown in the lower part, the physical address consists of the block address (superblock address) corresponding to the superblock to which the target block belongs, and the offset from the beginning of the superblock to the target location. The offset from the beginning of the superblock to the target location includes the chip identifier, page address, and offset within the page.

[0193] Figure 16 This indicates the relationship between the superblock address (block 1 address) of the superblock and the block addresses (block 2 addresses) of each block contained in the superblock.

[0194] To simplify the explanation, let's assume that superblocks SB0, SB1, and SB2 are each composed of 4 blocks.

[0195] Superblock SB0 contains blocks 80, 81, 82, and 83. These blocks 80, 81, 82, and 83 each contain a block address (block 2 address) determined from the superblock address (block 1 address) of superblock SB0 based on mathematical rules. If block 81 is a bad block, host 2 writes data to the write target block selected from blocks 80, 82, and 83. Therefore, the block 2 address of bad block 81 (the chip identifier of the chip to which bad block 81 belongs) is not sent back to host 2.

[0196] Superblock SB1 contains blocks 84, 85, 86, and 87. These blocks 84, 85, 86, and 87 each contain a block address (second block address) determined from the superblock address (first block address) of superblock SB1 based on mathematical rules. If blocks 86 and 87 are faulty blocks, host 2 writes data to the write target blocks selected from blocks 84 and 85. Therefore, the second block address of faulty block 86 (the chip identifier of the chip to which faulty block 86 belongs) and the second block address of faulty block 87 (the chip identifier of the chip to which faulty block 87 belongs) are not sent back to host 2.

[0197] Superblock SB2 contains blocks 88, 89, 90, and 91. These blocks 88, 89, 90, and 91 each contain a block address (block 2 address) determined mathematically from the superblock address (block 1 address) of superblock SB2. If block 88 is a bad block, host 2 writes data to the write target block selected from blocks 89, 90, and 91. Therefore, the block 2 address of bad block 88 (the chip identifier of the chip to which bad block 88 belongs) is not sent back to host 2.

[0198] Figure 17 , Figure 18 This indicates the action of writing a logical address and data pair into a page within a block.

[0199] Within each block, each page may also contain a user data area for storing user data and a redundant area for storing management data. The page size is 16 KB + α.

[0200] Controller 4 writes 4 KB of user data and its corresponding logical address (e.g., LBA) to the write target block BLK. In this case, such as... Figure 17 As shown, four datasets, each containing LBA and 4 KB of user data respectively, can be written to the same page. Intra-block offsets can also represent set boundaries.

[0201] Or, such as Figure 18 As shown, four 4 KB user data entries can also be written to the user data area within the page, and the four LBAs corresponding to the four 4 KB user data entries can be written to the redundant area within the page.

[0202] use Figure 19 The process of writing multiple data units and the disappearance correction code calculated based on these data units into a superblock containing bad blocks is explained.

[0203] To implement RAID (Redundant Arrays of Independent Disks) mechanisms using multiple blocks within a superblock, controller 4, as... Figure 19 As shown, multiple pages belonging to multiple blocks contained in a superblock and having the same page address are written with multiple data sections and one or more disappearance correction codes calculated based on these multiple data sections. These multiple pages belonging to multiple blocks and having the same page address are then looked up as superpages.

[0204] exist Figure 19 The upper part shows the writing of data and disappearance correction codes to the super page in super block SB0. The super page includes page 0 of BLK0 (chip #0), page 0 of BLK0 (chip #1), page 0 of BLK0 (chip #2), page 0 of BLK0 (chip #3), page 0 of BLK0 (chip #4), page 0 of BLK0 (chip #5), page 0 of BLK0 (chip #6), and page 0 of BLK0 (chip #7).

[0205] Data is written to page 0 of BLK0 (chip #0), BLK0 (chip #2), BLK0 (chip #3), and BLK0 (chip #4), which are non-bad blocks.

[0206] Vanishing correction codes include, for example, Reed-Solomon codes and parity. The vanishing correction code is written to pages within non-bad blocks. Furthermore, the vanishing correction code is calculated assuming that each page within a bad block stores a predefined value (e.g., a string of all "0"s or a string of all "1"s).

[0207] exist Figure 19 The example shown above illustrates the case where two vanishing correction codes are written to a superpage of superblock SB0. The two vanishing correction codes are written to pages within the last two non-bad blocks. Figure 19 In the example shown above, the last block, BLK0 (chip #7), is a non-defective block, the second block from the end, BLK0 (chip #6), is a defective block, and the third block from the end, BLK0 (chip #5), is a non-defective block. Therefore, the two disappearance correction codes are written to page 0 of BLK0 (chip #5) and page 0 of BLK0 (chip #7).

[0208] In the encoding process, the controller 4 calculates two disappearance correction codes based on the data written to the data section of BLK0 (chip #0), the pre-defined value assumed to be written to BLK0 (chip #0) which is a bad block, the data section written to BLK0 (chip #2), the data section written to BLK0 (chip #3), the data section written to BLK0 (chip #4), and the pre-defined value assumed to be written to BLK0 (chip #6).

[0209] Therefore, regardless of the bad / non-bad block pattern within the superblock, the vanishing correction code can be easily calculated using the same operations used for encoding.

[0210] In addition, controller 4 performs decoding processing using disappearance correction codes, assuming that the pages in each bad block store predefined values.

[0211] exist Figure 19 In the example shown below, the last block constituting superblock SB1, namely BLK1 (chip #7), is a bad block. The second block from the end, namely BLK1 (chip #6), is a bad block. The third block from the end, namely BLK1 (chip #5), is a non-bad block. Therefore, the two disappearance correction codes are written to page 0 of BLK1 (chip #5) and page 0 of BLK1 (chip #6).

[0212] Next, using Figure 20 The relationship between the flash memory conversion unit 2A in the host 2 and the write operation control unit 21 in the flash storage device 3 will be explained.

[0213] On the host side, the flash memory conversion unit 2A sends a write command containing a tag (e.g., LBA) identifying the data to the flash storage device 3 when data is being written. Furthermore, when using a superblock API, the flash memory conversion unit 2A sends a write command (without page address) specifying the tag (e.g., LBA) identifying the data and the block address of the parallel unit to the flash storage device 3. Since the parallel unit is implemented through a superblock, the block address of the parallel unit is the superblock address of that superblock.

[0214] The flash storage device 3 includes a write operation control unit 21, a flash I / O control circuit 13, a defect information management table 33, and a NAND flash memory chip. Furthermore, the flash storage device 3 manages and stores defect information, including at least 1 bit of information indicating whether a superblock is usable or unusable, using the defect information management table 33.

[0215] When a write request is received from the host 2 side containing a tag (e.g., LBA) that serves as information for identifying the data to be written, the write action control unit 21 consults the bad information management table 33, selects a block as the write target block from the non-bad blocks contained in a super block, and determines the write target location (write target page, offset within that page) within the selected block where the data to be written should be.

[0216] Furthermore, when a write instruction is received from host 2 for a block address (superblock address) specifying a parallel unit, write action control unit 21 selects a write target block from non-bad blocks contained in the superblock having the specified block address (superblock address) and determines the write target location (write target page, offset within the page) within the selected block where the data to be written.

[0217] Furthermore, the write action control unit 21 sends a write instruction to the flash I / O control circuit 13, specifying the chip identifier (chip ID) of the chip to which the target block belongs, the block address (raw block) of the target block, the target page (raw page) to be written, and the offset within the target page to be written.

[0218] In addition, the write action control unit 21 notifies the host 2 of the flash memory address (chip ID, original block, original page, offset) and tag (e.g., LBA) indicating the target block and the target location to be written.

[0219] Upon receiving a write instruction, the flash I / O control circuit 13 writes data to the write target location based on the write instruction.

[0220] On the host 2 side, if the flash memory conversion unit 2A receives a flash memory address (chip ID, original block, original page, offset) and a tag (e.g., LBA) from the flash storage device 3, it updates the LUT managed in the host 2. At this time, a correspondence is established between the flash memory address (chip ID, original block, original page, offset) and the tag (e.g., LBA).

[0221] The flash memory conversion unit 2A sends a read request for a specified flash memory address (chip ID, original block, original page, offset) to the flash storage device 3 when a read request is made.

[0222] On the flash storage device 3 side, upon receiving a read request from the host 2 for a specified flash memory address (chip ID, original block, original page, offset), the flash I / O control circuit 13 reads data based on the flash memory address. The block to be read is identified based on the chip ID and the original block. The page to be read is identified based on the original page. The position of the read object within the page to be read is identified based on the offset.

[0223] Next, using Figure 21 The write and read operations performed by the host 2 and the flash storage device 3 are explained.

[0224] <Write Action>

[0225] (1) Receiving write commands

[0226] In the flash storage device 3, write commands including LBAs and data received from the host 2 are temporarily stored in the write buffer 31 within the flash storage device 3.

[0227] (2) Access to harmful information

[0228] The write action control unit 21 checks the bad information managed by the bad information management table 33, selects a block as the write target block from the non-bad blocks contained in the super block of the write object, and determines the write target position within the write target block.

[0229] (3) Write Instruction

[0230] When the write action control unit 21 determines the target block to be written to and the target location within the target block, it sends a write instruction specifying the flash memory address (raw address) of both the target block and the target block to the flash I / O control circuit 13 via the write buffer 31. Here, the raw address includes the chip ID, the original block, the original page, and the offset. Upon receiving the raw address, the flash I / O control circuit 13 writes the write data to the target location within the selected target block based on the raw address.

[0231] (4) Notification to the write target of the host

[0232] The write action control unit 21 notifies the host 2 of the original address and LBA. The host 2 can then update the LUT and map the original address to the LBA.

[0233] <Reading Action>

[0234] (11) LBA notification

[0235] If the read parser 2B receives a read instruction containing an LBA, it notifies the flash memory converter 2A of the LBA.

[0236] (12) Obtaining the original address

[0237] If the flash memory conversion unit 2A receives an LBA from the read parser 2B, it consults the LUT to obtain the original address corresponding to the received LBA, and returns the obtained original address to the read parser 2B. Thus, the read parser 2B can obtain the original address, thereby converting a read instruction containing an LBA into a read instruction containing the original address.

[0238] (13) Reading Instruction

[0239] The read parser 2B sends a read instruction containing the original address to the flash storage device 3. In the flash storage device 3, the flash I / O control circuit 13, upon receiving the read instruction containing the original address, reads the data based on the original address and sends the read data to the read buffer 30. The read data is temporarily stored in the read buffer 30.

[0240] (14) Reading data sent to the host

[0241] The read data temporarily stored in the read buffer 30 is sent to the host 2.

[0242] Figure 22 The sequence diagram represents the order in which write operations are processed by host 2 and flash storage device 3.

[0243] Host 2 sends a write instruction (Write without Physical Address) containing the QoS domain ID, user address (logical address), write data, and length to flash storage device 3. When controller 4 of flash storage device 3 receives the write instruction, controller 4 selects a block from the non-bad blocks contained in a superblock (the superblock to be written) as the write target block and determines the write target location within the selected block (step S11). In step S11, the superblock to be written can also be a superblock belonging to the QoS domain specified by the QoS domain ID. If multiple superblocks belong to the QoS domain, one of these multiple superblocks is selected as the superblock to be written.

[0244] The controller 4 writes the write data received from the host 2 to the write target location (step S12). In step S12, the controller 4 writes both the user address (e.g., LBA) and the write data to the write target location of the write target block.

[0245] Controller 4 updates block management table 32, changing the bitmap flag corresponding to the written data (that is, the bitmap flag corresponding to the physical address of the physical storage location where the data was written) from 0 to 1 (step S13). For example, imagine... Figure 23The diagram illustrates the scenario where 16 KB of update data with a starting LBA of LBAx is written to the physical storage location corresponding to offsets +0 to +3 on page 1 of block BLK11. In this case, as... Figure 24 As shown, in the block management table used by block BLK11, the bitmap flags corresponding to offsets +0 to +3 in page 1 are changed from 0 to 1 respectively.

[0246] Controller 4 returns a response to the write command to host 2 (step S14). The response includes the user address, physical address (flash memory address), and length. For example, if... Figure 23 As shown, 16 KB of update data with a starting LBA of LBAx has been written to the physical storage location corresponding to offsets +0 to +3 in page 1 of block BLK11. Then, an acknowledgment containing LBAx, the flash memory address (the chip identifier of the chip to which block BLK11 belongs, the block address of block BLK11, the page address (=1), the offset within the page (=+0)), and the length (=4) is sent from controller 4 to host 2. The flash memory address is expressed as a combination of the block address, page address, and offset within the page; however, in the following description, the chip identifier within the flash memory address is omitted for simplicity.

[0247] When host 2 receives the response, host 2 updates the LUT managed by host 2, mapping the flash memory address (physical address) to the user address corresponding to the written data (step S21). Figure 25 As shown, the LUT contains multiple entries corresponding to multiple user addresses (logical addresses). The entry corresponding to a specific user address (e.g., a specific LBA) stores the physical address of the location (physical storage location) within the NAND flash memory 5 that stores the data corresponding to that LBA. If... Figure 23 As shown, 16 KB of update data with a starting LBA of LBAx has been written to the physical storage location corresponding to offsets +0 to +3 in page 1 of block BLK11. Then, as... Figure 25 As shown, the LUT update stores BLK11, page 1, and offset +0 in the entry corresponding to LBAx, BLK11, page 1, and offset +1 in the entry corresponding to LBAx+1, BLK11, page 1, and offset +2 in the entry corresponding to LBAx+2, and BLK11, page 1, and offset +3 in the entry corresponding to LBAx+3.

[0248] Then, host 2 sends a Trim command to flash storage device 3 to invalidate previous data that has become useless due to the writing of the updated data. Figure 23 As shown, if the previous data was stored in the positions corresponding to offsets +0, +1, +2, and +3 on page 0 of block BLK0, then... Figure 26As shown, a Trim instruction specifying the flash memory address (block address (=BLK0), page address (=page 0), page offset (=+0)), and length (=4) is sent from host 2 to flash storage device 3. The controller 4 of flash storage device 3 updates the block management table 32 according to the Trim instruction (step S15). In step S15, as... Figure 26 As shown, in the block management table used by block BLK0, the bitmap flags corresponding to offsets +0 to +3 of page 0 are changed from 1 to 0 respectively.

[0249] Figure 27 This indicates a read instruction (Read with Physical Address) applied to flash storage device 3.

[0250] A read command is an instruction to request data from flash storage device 3. This read command includes an instruction ID, flash memory address, length, and a transfer destination pointer.

[0251] The instruction ID is the ID (instruction code) that indicates that the instruction is a read instruction. The read instruction contains the instruction ID used for reading.

[0252] The flash address indicates the flash memory address (physical address) of the initial physical storage location from which the data should be read. The length indicates the length of the data to be read.

[0253] The destination pointer indicates the location of the data to be read in the host 2 memory.

[0254] A single read instruction can specify multiple groups of flash memory addresses (physical addresses) and lengths.

[0255] Here, the read instruction can also contain two or more groups of flash memory addresses and lengths. Consider the following scenario where there are two or more groups of flash memory addresses and lengths: because there are bad blocks in the superblock where data was written, the data is written to two blocks separated by the bad block.

[0256] Figure 28 This indicates a read operation.

[0257] Here, we envision a scenario where host 2 receives a read instruction specifying a block address (=BLK2), page address (=page 1), page offset (=+1), and length (=3). The controller 4 of the flash storage device 3 reads data d1 to d3 from BLK2 based on the block address (=BLK2), page address (=page 1), page offset (=+1), and length (=3). In this case, controller 4 reads data equivalent to one page size from page 1 of BLK2 and extracts data d1 to d3 from this read data. Then, controller 4 transfers data d1 to d3 to the host memory specified by the transfer destination pointer.

[0258] Figure 29 The sequence diagram shows the order of read processes performed by host 2 and flash storage device 3.

[0259] Host 2 consults the LUT managed by Host 2 and converts the user address (logical address) contained in the read request from the user application into a flash memory address. Then, Host 2 sends a read command specifying the flash memory address and length to flash storage device 3.

[0260] When the controller 4 of the flash storage device 3 receives a read command from the host 2, the controller 4 determines the block to be read, the page to be read, and the location within the page to be read based on the flash memory address specified by the read command (step S31). The controller 4 reads the data specified by the flash memory address and length from the NAND flash memory 5 (step S32) and sends the read data to the host 2.

[0261] Figure 30 This indicates the garbage collection (GC) control command applied to the flash storage device 3.

[0262] GC control instructions may also include instruction ID, policy (GC method), QoS domain ID, maximum number of data, etc.

[0263] The instruction ID is the ID (instruction code) that indicates that the instruction is a GC control instruction. The GC control instructions contain the instruction ID used by the GC control instructions.

[0264] The strategy (GC method) is a parameter that specifies the conditions (GC strategy) used to select GC candidate blocks (GC source blocks). The controller 4 of the flash storage device 3 supports multiple GC strategies.

[0265] The GC strategies supported by controller 4 can also include a strategy (greedy) that prioritizes blocks with less effective data as GC candidate blocks (GC source blocks).

[0266] In addition, the GC strategy supported by controller 4 may also include the following strategy: prioritize the selection of blocks containing data with a lower update frequency (cold data) as GC candidate blocks (GC source blocks) from blocks containing data with a higher update frequency (hot data).

[0267] Furthermore, GC strategies can also specify GC start conditions. GC start conditions can, for example, represent the number of remaining free blocks.

[0268] Controller 4 can also use the active block list to manage superblock groups containing valid data. When performing GC, it selects one or more GC candidate superblocks (GC source blocks) from the superblock group managed by the active block list based on the GC strategy specified by the GC control instructions.

[0269] The QoS domain ID is a parameter that specifies the QoS domain to which GC should be implemented. Controller 4 selects one or more GC candidate superblocks (GC source blocks) from the superblock group belonging to the QoS domain specified by the QoS domain ID, that is, from the list of active blocks corresponding to that QoS domain.

[0270] The maximum number of data items represents the upper limit of the amount of data copied during garbage collection (GC). In other words, GC operations cannot be performed beyond the maximum number of data items.

[0271] Controller 4 can also start GC if the number of remaining free blocks corresponding to the QoS domain falls below the threshold specified by the policy.

[0272] Figure 31 This indicates a Forced Garbage-Collection (GC) command applied to flash storage device 3.

[0273] Forced GC commands can also include command IDs, QoS domain IDs, superblock addresses, etc. When a forced GC command is received, the controller immediately performs GC.

[0274] Figure 32 This indicates an address update notification (Device Initiated) sent from flash storage device 3 to host 2.

[0275] Address update notifications are used to inform host 2 of the storage location of data in flash storage device 3 that has changed due to a garbage collection (GC) operation. They may also include user address, old flash memory address, new flash memory address, lookup count, length, etc.

[0276] The user address is the address that identifies the copied data.

[0277] The old flash memory address refers to the physical address of the old physical storage location where the copied data is stored (old physical address).

[0278] The new flash memory address represents the physical address of the new physical storage location where the copied data is stored (the new physical address).

[0279] The lookup count represents the number of user addresses that have looked up the copied data.

[0280] The length indicates the length of the data being copied.

[0281] Figure 33 The sequence diagram represents the order of GC actions performed via flash storage device 3.

[0282] The controller 4 of the flash storage device 3 selects one or more GC source blocks (GC source superblocks) from the superblock group belonging to the QoS domain specified by the host 2, where valid and invalid data coexist (step S41). Next, the controller 4 selects one or more free blocks (free superblocks) from the free block group (free superblock group) belonging to the QoS domain, and assigns the selected free blocks as GC destination blocks (GC destination superblocks) (step S42).

[0283] Controller 4 copies all valid data from the GC source block (GC source superblock) to the GC destination block (GC destination superblock) (step S43). In step S43, controller 4 not only copies the valid data from the GC source block (GC source superblock), but also copies both the valid data and the corresponding user address (logical address) from the GC source block (GC source superblock) to the GC destination block (GC destination superblock). Thus, the data-user address (logical address) pair can be stored within the GC destination block (GC destination superblock).

[0284] Then, for each valid piece of data copied, controller 4 uses address update notification to notify host 2 of the user address (logical address), old flash memory address, new flash memory address, and length (step S44).

[0285] When host 2 receives the address update notification, host 2 updates the LUT managed by host 2 and maps the new flash memory address to the user address (logical address) corresponding to each of the copied valid data (step S51).

[0286] Figure 34 This represents an example of a data copying action performed for garbage collection (GC).

[0287] exist Figure 34Consider the following scenario: Copy the valid data (LBA=10) stored at the offset +0 position of page 1 of the GC source block (here, block BLK50) to the offset +0 position of page 0 of the GC destination block (here, block BLK100), and copy the valid data (LBA=20) stored at the offset +2 position of page 2 of the GC source block (here, block BLK50) to the offset +1 position of page 0 of the GC destination block (here, block BLK100). In this case, controller 4 will notify host 2 of {LBA10, old flash address (BLK50, page 1, offset (=+0)), new flash address (LBA100, page 0, offset (=+0)), length (=1)} and {LBA20, old flash address (BLK50, page 2, offset (=+2)), new flash address (LBA100, page 0, offset (=+1)), length (=1)} (address update notification).

[0288] Figure 35 Indicates based on Figure 34 The result of the data replication action is to update the contents of the LUT on host 2.

[0289] In this LUT, the flash memory address (block address, page address, and offset (offset within page)) corresponding to LBA10 is updated from BLK50, page 1, offset (=+0) to BLK100, page 0, offset (=+0). Similarly, the flash memory address (block address, page address, and offset (offset within page)) corresponding to LBA20 is updated from BLK50, page 2, offset (=+2) to BLK100, page 0, offset (=+1).

[0290] After the LUT is updated, host 2 can also send a Trim command specifying BLK50, page 1, and offset (=+0) to flash storage device 3, invalidating the data stored at the position corresponding to offset (=+0) on page 1 of BLK50. Furthermore, host 2 can also send a Trim command specifying BLK50, page 2, and offset (=+2) to flash storage device 3, invalidating the data stored at the position corresponding to offset (=+2) on page 2 of BLK50.

[0291] Figure 36 This indicates the relationship between the response to the write command and the GC callback processing (address update notification).

[0292] There is a scenario where the controller 4 receives a write instruction from the host 2 specifying a user address while copying valid data corresponding to a certain user address (logical address).

[0293] exist Figure 36 Consider the following scenario: Figure 34During the execution of the data copying action (the data copying action corresponding to LBA10), a write command for the specified LBA10 is received from host 2.

[0294] Controller 4 writes the write data received from host 2 to the write target block (here, to the position corresponding to offset +0 of page 0 of BLK3). Then, controller 4 returns {LBA10, BLK3, page 0, offset (= +0)} to host 2 as a response to the write command.

[0295] Host 2 updates the LUT, changing the block address, page address, and offset (offset within the page) corresponding to LBA10 from BLK50, page 1, offset (+0) to BLK3, page 0, offset (+0).

[0296] If the new flash address of LBA10 is subsequently notified from controller 4 to host 2, the block address, page address, and offset (BLK3, page 0, offset (+0)) of the location storing the latest data corresponding to LBA10 may be incorrectly changed to the new flash address corresponding to LBA10 (here, BLK100, page 0, offset (=+0)).

[0297] In this embodiment, the controller 4 can notify the host 2 of both the LBA10, the new flash address (BLK100, page 0, offset (=+0)), and length = 1, as well as the old flash address (BLK50, page 1, offset (=+0)) (address update notification). The host 2 does not update the LUT if the old flash address (BLK50, page 1, offset (=+0)) is inconsistent with the block address, page address, and offset currently mapped to LBA10 via the LUT. This prevents the block address, page address, and offset (BLK3, page 0, offset (+0)) representing the location storing the latest data corresponding to LBA10 from being incorrectly changed to the new flash address corresponding to LBA10 (here, BLK100, page 0, offset (=+0)).

[0298] Figure 37 The flowchart shows the sequence of LUT update processes performed by host 2.

[0299] If host 2 receives an address update notification (yes in step S101), it compares the old flash memory address with the current physical address on the LUT (step S102). If the old flash memory address matches the current physical address (yes in step S103), host 2 updates the current physical address corresponding to the user address to the new flash memory address (step S104). Next, host 2 sends a Trim command to the flash storage device to invalidate the data stored at the location corresponding to the old flash memory address (step S105).

[0300] On the other hand, if the old flash memory address is inconsistent with the current physical address (NO in step S106), then host 2 maintains the current physical address corresponding to the user address (step S106). This prevents the block address, page address, and offset indicating the location where the latest data is stored, as notified by the address update notification, from being incorrectly changed to the new flash memory address.

[0301] exist Figure 38 The example shows the block management table used by block BLK1.

[0302] The block management table used by block BLK1 contains multiple entries corresponding to the page address and the offset within the page of block BLK1.

[0303] For example, the lookup count for the 4 KB of data stored at the location corresponding to page 0, offset +0 of storage block BLK1 in the entry corresponding to page 0, offset +0. Similarly, the lookup count for the 4 KB of data stored at the location corresponding to page 0, offset +1 of storage block BLK1 in the entry corresponding to page 0, offset +1.

[0304] Data with a count of 1 or higher is considered valid data, while data with a count of 0 is considered invalid data.

[0305] The flash storage device 3 increments / decrements the lookup count based on the repeat command / Ttim command received from the host 2.

[0306] Figure 39 This indicates a repeating instruction applied to the flash storage device 3 for the purpose of checking the count management.

[0307] A repeat instruction is an instruction that requests the flash storage device 3 to increment the lookup count of data stored at a certain physical address (block address, page address, offset within page).

[0308] The repeat instruction may also include instruction ID, flash memory address, length, etc.

[0309] The instruction ID is the ID (instruction code) that indicates that the instruction is a repeating instruction. Repeating instructions contain the instruction ID used for repeating instructions.

[0310] A flash memory address indicates the initial physical storage location where the data that should cause the lookup count to increment is stored.

[0311] The length indicates the length of the data that should increase the lookup count.

[0312] When the controller 4 receives a repeat instruction from the host 2 containing the block address, page address, and page offset of the physical storage location where the lookup count should be increased, the controller 4 updates the block management table 32 to increase the lookup count corresponding to the data of the physical storage location containing the block number, page number, and page offset in the repeat instruction.

[0313] Figure 40 The sequence diagram represents the increment / decrement processing of the lookup count.

[0314] When the controller 4 of the flash storage device 3 receives a repeat instruction from the host 2, the controller 4 increments the lookup count corresponding to the flash memory address (block address, page address, offset (page offset)) specified by the repeat instruction, that is, the lookup count corresponding to the data stored at the physical storage location within the NAND flash memory 5 specified by the block address, page address, and offset, by, for example, by 1 (step S61). In this case, the controller 4 updates the block management table 32 corresponding to the block with the block address specified by the repeat instruction. Through the update of the block management table 32, the lookup count stored in the entry of the block management table 32 corresponding to the physical storage location specified by the repeat instruction is increased by, for example, by 1. When the length specified by the repeat instruction is 2 or more, not only the lookup count corresponding to the page address and offset specified by the repeat instruction, but also the lookup count corresponding to several page addresses and offsets following that page address and offset are also increased by, for example, by 1.

[0315] When the controller 4 of the flash storage device 3 receives a Trim command from the host 2, the controller 4 decreases the lookup count corresponding to the flash memory address (block address, page address, offset (page offset)) specified by the Trim command, that is, the lookup count corresponding to the data stored at the physical storage location within the NAND flash memory 5 specified by the block address, page address, and offset, by, for example, by 1 (step S62). In this case, the controller 4 updates the block management table 32 corresponding to the block with the block address specified by the Trim command. Through the update of the block management table 32, the lookup count stored in the entry of the block management table 32 corresponding to the page address and offset specified by the Trim command is decreased by, for example, by 1. When the length specified by the Trim command is 2 or more, not only the lookup count corresponding to the page address and offset specified by the Trim command, but also the lookup count corresponding to several page addresses and offsets following that offset are also decreased by, for example, by 1.

[0316] During GC, controller 4 consults the block management table corresponding to the GC source block, determining whether the data within the GC source block is valid or invalid, using data units of 4 KB in size. Controller 4 classifies data with a lookup count of 0 as invalid data and data with a lookup count of 1 or higher as valid data. Furthermore, controller 4 copies the valid data (data with a lookup count of 1 or higher) and its corresponding logical address from the GC source block (GC source superblock) to the GC destination block (GC destination superblock).

[0317] More specifically, when performing garbage collection on the NAND flash memory 5, controller 4 selects the GC source block (GC source superblock) and GC destination block (GC destination superblock) for garbage collection. Controller 4 copies the first data (valid data) with a lookup count of 1 or higher stored in the GC source block (GC source superblock) and the logical address of the first data to the GC destination block (GC destination superblock). Furthermore, controller 4 notifies host 2 of the user address (logical address) of the first data, the physical address of the target physical storage location (new physical storage location) of the first data, and the physical address of the source physical storage location (old physical storage location) of the first data.

[0318] Figure 41 The flowchart shows the sequence of superblock allocation processes performed by the flash storage device 3.

[0319] If a superblock allocation request (parallel unit allocation request) is received from host 2 (yes in step S71), controller 4 selects a superblock that contains more than the number of non-bad blocks specified by the allocation request (step S72).

[0320] Next, controller 4 assigns the selected superblock to host 2 (step S73).

[0321] Next, if a write request is received from host 2 (yes in step S74), controller 4 writes the write data to a non-bad block within the allocated superblock (step S75). Then, controller 4 returns an acknowledgment to the host (step S76).

[0322] Next, using Figure 42 This section describes the address translation operation that involves logically arranging all non-bad blocks within a superblock sequentially from the beginning of the superblock to access the address of the target block.

[0323] exist Figure 42The diagram illustrates the following: Superblock SB5 is composed of BLK5(chip #0), BLK5(chip #1), BLK5(chip #2), BLK5(chip #3), BLK5(chip #4), BLK5(chip #5), BLK5(chip #6), and BLK5(chip #7), among which BLK5(chip #2) and BLK5(chip #5) are faulty blocks. Furthermore, BLK5(chip #0), BLK5(chip #1), BLK5(chip #2), BLK5(chip #3), BLK5(chip #4), BLK5(chip #5), BLK5(chip #6), and BLK5(chip #7) are assigned external block numbers (block addresses) of 0, 1, 2, 3, 4, 5, 6, and 7, respectively.

[0324] Address translation is performed by treating the six non-bad blocks (BLK5(chip #0), BLK5(chip #1), BLK5(chip #3), BLK5(chip #4), BLK5(chip #6), BLK5(chip #7)) within the superblock SB5 as blocks numbered 0 to 6.

[0325] During address translation, the block numbers of BLK5 (chip #0), BLK5 (chip #1), BLK5 (chip #2), BLK5 (chip #3), and BLK5 (chip #4) are translated in the order 1→1, 2→3, 3→4, 4→6, and 5→7, respectively. This address translation ensures that block numbers within a continuous offset address range starting from the beginning of superblock SB5 do not contain faulty blocks. Therefore, through this address translation, all non-faulty blocks within superblock SB5 are logically and continuously arranged from the beginning of superblock SB5. Thus, superblock SB5 can be viewed as a small superblock (consisting of only 6 non-faulty blocks) that does not contain faulty blocks. Consequently, even long data can have its physical storage location expressed by a combination of a physical address representing the starting physical storage location of the data and a length.

[0326] Next, using Figure 43 The following section explains the bad information management table 33 used for address translation operations and provides an example of address translation. Furthermore, in... Figure 43 In this context, block numbers are represented in hexadecimal.

[0327] Table 33 of the Defective Information Management section represents the cumulative number of defective blocks discovered, starting from the beginning (block numbers in ascending order). Figure 43In the diagram, blocks numbered 4 and 9 of the Defective Information Management Table 33 are defective blocks. In this case, within the Defective Information Management Table 33, "0" is stored in the positions corresponding to block number 0, block number 1, block number 2, and block number 3; "1" is stored in the positions corresponding to block number 4, block number 5, block number 6, block number 7, and block number 8; and "1" is stored in the positions corresponding to block number 9, block number A, block number B, block number C, and block number D. In other words, the block corresponding to the block number where the stored value changes is a defective block.

[0328] Furthermore, impossible values ​​are stored in the positions corresponding to block numbers E and F in the adverse information management table 33. If the number of bits for the adverse information in each block is 2 bits, then "3" is stored in the positions corresponding to block numbers E and F.

[0329] Additionally, during address translation, the block number of the accessed object is converted to the sum of that block number and the cumulative number of bad blocks. For example, for block numbers 0-3, since the cumulative number of bad blocks is "0", the block number remains unchanged.

[0330] On the other hand, for example, if the block number of the accessed object is 4, this block number is incremented by 1 to become block number "5". Therefore, if the block number of the written object is 4, the data is actually written to block number "5". Controller 4 notifies host 2 of block number 4 as the physical address of the target block for data writing. Upon receiving a read request specifying block number 4 as the physical address of the read object block, controller 4 reads data from block number "5" since block number 4 is converted to block number "5".

[0331] Similarly, if the block number of the accessed object is 5, then the block number is incremented by 1 to become block number "6". Therefore, if the block number of the written object is 5, the data is actually written to block number "6". Controller 4 notifies host 2 of block number 5 as the physical address of the target block to be written. Upon receiving a read request specifying block number 5 as the physical address of the block to be read, since block number 5 is converted to block number "6", controller 4 reads data from block number "6".

[0332] Figure 44 This indicates the relationship between the flash memory conversion unit 2A in the host 2 and the bad block conversion unit 24 in the flash storage device 3.

[0333] On the host side, the flash memory conversion unit 2A sends a write command containing a tag (e.g., LBA) identifying the data to the flash storage device 3 when data is being written. Furthermore, when using a superblock API, the flash memory conversion unit 2A sends a write command (without page address) specifying the tag (e.g., LBA) identifying the data and the block address of the parallel unit to the flash storage device 3. Since the parallel unit is implemented through a superblock, the block address of the parallel unit is the superblock address of that superblock.

[0334] The flash storage device 3 includes a defective block conversion unit 24, a flash I / O control circuit 13, a defective information management table 33, and a NAND flash memory chip. Furthermore, within the flash storage device 3, the defective information management table 33 manages and stores at least 2 bits of information indicating whether each superblock is usable or unusable, representing defective information.

[0335] When a write request containing a tag (e.g., LBA) for identifying data to be written is received from host 2, the bad block conversion unit 24 checks the bad information and performs address conversion to convert the address of the access target block in a logical manner by continuously and logically configuring all non-bad blocks contained in the superblock of the write target from the beginning of the superblock of the write target. As a result, a non-bad block in the superblock of the write target is selected as the write target block, and the write target location (write target page, offset within the page) in the selected block is determined.

[0336] Furthermore, when a write instruction is received from host 2 with a specified block address (superblock address) for a parallel unit, the bad block conversion unit 24 checks the bad information and selects the superblock with the specified block address (superblock address) as the superblock to be written.

[0337] Furthermore, the defective block conversion unit 24 sends a write instruction to the flash I / O control circuit 13, specifying the chip identifier (chip ID) of the chip to which the target block belongs, the block address (original block) of the target block, the target page (original page) to be written, and the offset within the target page to be written.

[0338] Additionally, the bad block translation unit 24 notifies the host 2 of the physical addresses of both the access target block before address translation and the write target location, as well as the tag (e.g., LBA). This physical address can also be represented by the parallel unit representing the superblock to be written to and the offset within that superblock. The parallel unit representing the superblock to be written to is the superblock address of the superblock to be written to.

[0339] Upon receiving a write instruction, the flash I / O control circuit 13 writes data to the write target location based on the write instruction.

[0340] On the host 2 side, if the flash conversion unit 2A receives a physical address (parallel unit, offset) and a tag (e.g., LBA), it updates the LUT managed in the host 2 and maps the received physical address to the received tag (e.g., LBA).

[0341] The flash memory conversion unit 2A sends a read request with a specified physical address (parallel unit, offset) to the flash storage device 3 when a read request is made.

[0342] On the flash storage device 3 side, upon receiving a read request from the host 2 for a specified physical address (parallel unit, offset), the faulty block translation unit 24 performs the address translation, converting the physical address (parallel unit, offset) into a chip identifier (chip ID), block address (original block), page address (original page), and offset within the page. Furthermore, the faulty block translation unit 24 sends a write instruction specifying the chip identifier (chip ID), block address (original block), page address (original page), and offset within the page to the flash I / O control circuit 13. The flash I / O control circuit 13 reads data based on the chip identifier (chip ID), block address (original block), page address (original page), and offset within the page.

[0343] Figure 45 This represents an example of the configuration of host 2 (computer system).

[0344] The host 2 (computer system) includes a processor (CPU) 101, a main memory 102, a BIOS (Basic Input / Output System) ROM 103, a network controller 105, a peripheral interface controller 106, a controller 107, and an embedded controller (EC) 108, etc.

[0345] Processor 101 is a CPU configured to control the operation of various components of the computer system. Processor 101 executes various programs loaded from any of the multiple flash storage devices 3 into main memory 102. Main memory 102 includes random access memory such as DRAM. The programs executed by processor 101 include application software layer 41, operating system (OS) 42, file system 43, drive 44, etc. Here, file system 43 includes flash storage manager 45. Alternatively, flash storage manager 45 may be included in drive 44, rather than in file system 43.

[0346] In addition, the processor 101 also executes the Basic Input / Output System (BIOS) stored in the BIOS-ROM 103, which is a non-volatile memory. The BIOS is a system program used for hardware control.

[0347] The network controller 105 is a communication device such as a wired LAN (Local Area Network) controller or a wireless LAN controller. The peripheral interface controller 106 is configured to perform communication with peripheral devices such as USB (Universal Serial Bus) devices.

[0348] The controller 107 is configured to perform communication with devices that are respectively connected to multiple connectors 107A. Multiple flash storage devices 3 can also be respectively connected to multiple connectors 107A. The controller 107 is an SAS (Serial Attached SCSI) expander, PCIe switch, PCIe expander, or RAID controller, etc.

[0349] The EC108 functions as a system controller for power management of a computer system. The EC108 connects and disconnects the computer system's power supply based on user input to the power switch. The EC108 is implemented as a processing circuit such as a single-chip microcontroller.

[0350] The flash memory manager 45 is a program module that functions as the flash memory conversion unit 2A. The flash memory manager 45 has a LUT that manages the mapping between each user address (logical address) and each physical address of the flash memory device 3. When using LBAs as user addresses (logical addresses), the flash memory manager 45 can also be located within the drive 44.

[0351] The flash storage manager 45 sends a write instruction to the flash storage device 3, specifying the user address (logical address) used to identify the data to be written (write data) and the length of the write data. The flash storage manager 45 receives from the flash storage device 3 the physical address of the write target block selected by the flash storage device 3 from blocks other than bad blocks, and the write target location within the write target block, as well as the user address (logical address), and updates the LUT to map the physical address to the user address (logical address). Specifically, the received physical address represents both the write target block selected by the flash storage device 3 from blocks other than bad blocks included in a parallel unit of the write object as the write target block for writing data, and the physical storage location within the write target block where the write data has been written.

[0352] Additionally, the flash storage manager 45 consults the LUT to obtain the physical address of the user address (logical address) corresponding to the data mapped to the read object, and sends a read instruction specifying that physical address to the flash storage device 3.

[0353] Figure 46 This section describes a configuration example of a host (computer system) 2 with a built-in flash storage device 3.

[0354] The computer system has a thin, box-shaped housing 201 that can be housed in a rack. Multiple flash storage devices 3 can also be arranged within the housing 201. In this case, each flash storage device 3 can be removably inserted into a slot provided on the front surface 201A of the housing 201.

[0355] The system board (mother board) 202 is disposed within the housing 201. Various electronic components, including a CPU 101, a memory 102, a network controller 105, and a controller 107, are mounted on the system board (mother board) 202. These electronic components function as the host computer 2.

[0356] Figure 47 The flowchart shows the sequence of write operations performed by host (computer system) 2.

[0357] The processor 101 of host 2 executes the following sequence by executing computer programs (such as flash storage manager 45) stored in main memory 102.

[0358] In other words, the processor 101 determines whether a write command needs to be sent (step S201). If a write command needs to be sent (yes in step S201), the processor 101 sends a write command specifying the user address, flash memory address, and length to the flash storage device 3 (step S202).

[0359] Then, if the processor 101 receives a confirmation from the flash storage device 3 that the write operation is complete (including the user address, flash memory address, and length) (yes in step S203), it updates the LUT (step S204). Then, the processor 101 sends a Trim instruction specifying the physical address corresponding to the old data to the flash storage device 3, instructing the flash storage device 3 to invalidate the old data (or to reduce the lookup count representing the number of logical addresses that look up the old data) (step S205).

[0360] Figure 48 The flowchart shows the sequence of read operations performed by host 2.

[0361] The processor 101 determines whether a read command needs to be sent (step S301). If a read command needs to be sent (yes in step S301), the processor 101 sends a read command specifying the flash memory address and length to the flash storage device 3 (step S302).

[0362] Then, the processor 101 determines whether the read data has been received (step S303). If the read data has been received (yes in step S303), the operation is completed.

[0363] Figure 49 The flowchart shows the sequence of lookup count increment / decrement processing performed by host 2.

[0364] The processor 101 determines whether it is necessary to send a repeat instruction to increase the lookup count of old data (step S401). If it is necessary to send a repeat instruction (yes in step S401), the repeat instruction is sent to the flash storage device 3 (step S402).

[0365] Additionally, the processor 101 determines whether it is necessary to send a Trim instruction to reduce the number of lookups for old data (step S403). If it is necessary to send a Trim instruction (yes in step S403), the Trim instruction is sent to the flash storage device 3 (step S404).

[0366] As explained above, according to this embodiment, the host (computer system) 2 sends a write request specifying a logical address for identifying the data to be written to the storage device 3, and receives a physical address and the logical address from the storage device 3. The physical address represents both the write target block selected by the storage device 3 from blocks other than defective blocks as the write target block for writing data, and the physical storage location within the write target block where the data has been written. Furthermore, the host (computer system) 2 updates the LUT, mapping the received physical address to the received logical address. Therefore, the host (computer system) 2 can utilize the LUT to manage the physical address directly representing the physical storage location other than the defective block, so the host (computer system) 2 can send a read request specifying the physical address directly representing the physical storage location to the storage device 3 as needed. As a result, on the storage device 3 side, without replacing the defective block with other blocks within the chip to which the defective block belongs, data writing and reading operations for blocks other than the defective block can be performed normally. Therefore, even if the number of defective blocks increases, there is no need to manage a large amount of replacement information. In addition, address translation processing for replacement processing is not required, thus reducing read latency. Therefore, it can improve the overall I / O performance of the system.

[0367] Furthermore, in this embodiment, NAND flash memory is exemplified as a non-volatile memory. However, the functionality of this embodiment can also be applied to various other non-volatile memories such as MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory).

[0368] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0369] [Explanation of Symbols]

[0370] 2 hosts

[0371] 3 flash storage devices

[0372] 4 controllers

[0373] 5NAND flash memory

[0374] 21. Write to the motion control unit

[0375] 22 Reading Motion Control Unit

[0376] 23GC Motion Control Unit.

Claims

1. A memory system connectable to a host computer, comprising: A non-volatile memory comprising multiple blocks, each block being a unit for data deletion operations; and The controller is electrically connected to the non-volatile memory and is configured as follows: Manage multiple block groups, each block group comprising at least one of the multiple blocks; and The system responds as follows to a write instruction received from the host, the write instruction requesting the writing of first data and specifying an identifier associated with the write destination block group to which the first data should be written: Based on the specified identifier, select the block group corresponding to the specified identifier from the plurality of block groups. Selecting a first block from at least one of the plurality of blocks included in the selected block group, and Write the first data into the first position of the first block.

2. The memory system according to claim 1, wherein The controller is also configured to notify the host of a first logical address associated with the first data.

3. The memory system according to claim 1, wherein The write instruction also specifies a first logical address associated with the first data, but does not specify an identifier for the first block.

4. The memory system according to claim 1, wherein The controller is also configured to notify the host of the first location by using at least the identifier of the first block.

5. The memory system according to claim 4, wherein The controller is configured to notify the host of the first location by using the offset address in the first block and the identifier of the first block.

6. The memory system according to claim 5, wherein Each of the plurality of blocks comprises a plurality of pages, and each of the plurality of pages is a unit of write operation; and The controller is configured to specify the offset address by using a multiple of granularity, the size of which is different from the size of each of the plurality of pages.

7. The memory system according to claim 1, wherein Each of the plurality of blocks belongs to only one block group among the plurality of block groups.

8. The memory system according to claim 1, wherein The controller is further configured as follows: Copy the second data from the first block to the second block of the plurality of blocks; and The host is notified of at least a second logical address associated with the second data.

9. The memory system according to claim 8, wherein The controller is also configured to notify the host of the identifier of the second block.

10. The memory system of claim 8, wherein The second block is included in the block group that includes the first block.

11. The memory system according to claim 8, wherein The second block is contained in a different block group than the block group that includes the first block.

12. A memory system connectable to a host computer, comprising: A non-volatile memory comprising multiple blocks, each block being a unit for data deletion operations; and The controller is electrically connected to the non-volatile memory and is configured as follows: In response to a write instruction received from the host requesting the writing of first data, the system specifies the logical address corresponding to the first data, but does not specify an identifier for the block where the first data should be written. The system then writes the first data to the first storage location in the non-volatile memory, and notifies the host of the first storage location using the identifier of the block where the first data has been written and the offset address within that block. In response to a read instruction received from the host requesting to read the first data and specifying the identifier of the block in which the first data has been written and the offset address within the block in which the first data has been written, the first data is read from the first storage location in the non-volatile memory.

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