Model computing power optimization method and device, electronic equipment, chip and medium

Abstract

The invention discloses a model computing power optimization method and device, electronic equipment, a chip and a medium, relates to the technical field of graph neural networks, and aims to solve the problems of single computing power evaluation dimension, inaccurate analysis and untimely early warning. The method comprises the following steps: acquiring multi-source data, wherein the multi-source data comprises performance index data and equipment connection data; based on the multi-source data, determining a data processing coefficient corresponding to the performance index data and an equipment connection coefficient corresponding to the equipment connection data; based on the data processing coefficient and the equipment connection coefficient, determining a computing power optimization rationality index; if the computing power optimization rationality index is greater than a preset index value, outputting a normal signal; otherwise, outputting an early warning signal.

Description

Technical Field

[0001] This application relates to the field of graph neural network technology, and in particular to a model computing power optimization method and apparatus, electronic device, chip and medium thereof. Background Technology

[0002] With the development of IoT technology, large-scale models based on graph neural networks are widely used in the IoT field, but the high demand for computing power has become a bottleneck. Existing computing power optimization methods include steps such as data acquisition and preprocessing, graph structure construction, computing resource allocation and scheduling, performance evaluation and tuning. However, these methods suffer from incomplete data acquisition, with missing data from some regions or devices, affecting the accuracy of model training and prediction. Furthermore, when faced with high-dimensional, large-scale, and noisy data, the analysis methods are inefficient and produce inaccurate results, reducing model reliability and practicality, and impacting effective system management and optimization. Summary of the Invention

[0003] The purpose of this application is to provide a model computing power optimization method and its device, electronic equipment, chip and medium to solve the problems of single computing power evaluation dimension, inaccurate analysis and untimely early warning in the current technology.

[0004] To achieve the above objectives, this application provides the following technical solution: A method for optimizing model computing power includes: Acquire multi-source data, including performance index data and device connection data; Based on the multi-source data, determine the data processing coefficients corresponding to the performance index data and the device connection coefficients corresponding to the device connection data; Based on the data processing coefficient and the device connection coefficient, a computing power optimization rationality index is determined; If the computing power optimization rationality index is greater than the preset index value, a normal signal is output; Otherwise, issue a warning signal.

[0005] Compared with existing technologies, the model computing power optimization method provided in this application collects multi-source data, including performance index data and device connection data, to obtain performance index data reflecting the health of the data processing chain and device connection data reflecting the stability of the network access chain. This multi-faceted data collection provides solid and rich data support for subsequent optimization strategies. By analyzing and calculating the acquired data, the data processing coefficients corresponding to the performance index data and the device connection coefficients corresponding to the device connection data can be determined to accurately identify key factors that may affect computing power. Finally, by systematically evaluating the data processing results, the feasibility and effectiveness of the optimization strategy are improved. With the help of real-time monitoring and dynamic tracking technology, once a computing power bottleneck or performance anomaly is detected, an intelligent adjustment mechanism is immediately activated, enabling operation and maintenance personnel to quickly grasp the real-time status and potential problems of large model computing power, and promptly adjust and optimize resource allocation schemes or system configurations. This provides a solid guarantee for achieving efficient and stable large model computing power support and scientific and reasonable technical deployment, and powerfully promotes the efficient operation and widespread application of large models in complex tasks.

[0006] This application also provides a model computing power optimization device, including: The acquisition module is used to acquire multi-source data, including performance index data and device connection data. The determination module is used to determine the data processing coefficient corresponding to the performance index data and the device connection coefficient corresponding to the device connection data based on the multi-source data. The determining module is also used to determine the computing power optimization rationality index based on the data processing coefficient and the device connection coefficient; If the computing power optimization rationality index is greater than the preset index value, the processing module is used to output a normal signal; Otherwise, the processing module is also used to output a warning signal.

[0007] Compared with the prior art, the beneficial effects of the model computing power optimization device provided in this application are the same as those of the model computing power optimization device method described in the above technical solutions, and will not be repeated here.

[0008] This application also provides an electronic device, including a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the method described in the embodiments of this application.

[0009] Compared with the prior art, the beneficial effects of the electronic device provided in this application are the same as those of the model computing power optimization device method described in the above technical solutions, and will not be repeated here.

[0010] This application also provides a computer storage medium storing instructions that, when executed, implement the methods described in the embodiments of this application.

[0011] Compared with the prior art, the beneficial effects of the computer storage medium provided in this application are the same as those of the model computing power optimization device method described in the above technical solutions, and will not be repeated here.

[0012] This application also provides a chip including a processor and a communication interface coupled to the processor, the processor being used to run computer programs or instructions to implement the methods described in the embodiments of this application.

[0013] Compared with the prior art, the beneficial effects of the chip provided in this application are the same as those of the model computing power optimization device method described in the above technical solution, and will not be repeated here. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A flowchart of the model computing power optimization method provided in the embodiments of this application is shown; Figure 2 This paper shows a schematic diagram of the structure of a model computing power optimization device provided in an embodiment of this application; Figure 3 A schematic block diagram of a chip according to an embodiment of this application is shown; Figure 4 A structural block diagram of an exemplary electronic device that can be used to implement embodiments of this application is shown. Detailed Implementation

[0015] To facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are only used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0016] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0017] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0018] With the development of IoT technology, large-scale models based on graph neural networks are increasingly being used in the IoT field, such as traffic flow prediction in smart cities, equipment fault diagnosis in industrial IoT, and energy management in smart homes. However, the enormous computing power required by these models to process IoT data has become a key factor limiting their efficient application. Against this backdrop, effective computing power optimization methods are crucial for improving the performance and practicality of large-scale graph neural network-based models in IoT scenarios.

[0019] Existing methods for optimizing the computational power of large-scale models based on graph neural networks mainly include the following core steps: data acquisition and preprocessing, graph structure construction, computational resource allocation and scheduling, and performance evaluation and tuning. In the IoT data acquisition and preprocessing step, diverse data such as temperature, humidity, pressure, and device operating status are collected through sensors deployed on various IoT nodes. This data is continuously generated from different geographical locations and device types, and undergoes preliminary cleaning, noise reduction, and normalization to remove outliers and unify the data format, providing the foundational data for subsequent graph structure construction. The graph structure construction step, based on the inherent relationships of IoT data, uses devices and sensors as nodes, and their physical connections and data interaction relationships as edges, constructing a graph model that reflects the topology of the IoT system. During this process, the attributes of nodes and edges are determined according to the characteristics of the data and application requirements to better represent the complex relationships in the IoT system, providing a suitable structural foundation for the application of graph neural networks. The computational resource allocation and scheduling step, based on the structure and computational requirements of the graph neural network model and combined with existing hardware resources such as cloud servers and edge computing devices, rationally divides and allocates computational tasks to meet the dual requirements of real-time performance and accuracy for IoT systems. The performance evaluation and optimization step assesses the performance of the trained model in real-world IoT application scenarios using a series of evaluation metrics, such as accuracy, recall, and mean squared error. Based on the evaluation results, the model's structure, parameters, and computational resource allocation strategies are adjusted and optimized to continuously improve the model's performance and computational efficiency, enabling it to better adapt to the dynamic changes and complex needs of the IoT environment.

[0020] However, this method still has some shortcomings. From the perspective of data acquisition, there is a problem of incomplete data collection. Due to the wide distribution and complex environment of IoT devices, data collection may be missing in some areas or devices due to signal interference, equipment failure, etc., which cannot fully reflect the overall picture of the IoT system and cannot meet the real-time data requirements of large-scale graph neural network-based models, thus affecting the training effect and prediction accuracy of the model. From the perspective of data analysis, facing the characteristics of high dimensionality, large scale and strong noise, existing analysis methods have the defects of low processing efficiency and inaccurate analysis results, thereby reducing the reliability and practicality of the model and affecting the effective management and optimization of the system.

[0021] Therefore, there is an urgent need for a large-scale model computational optimization method based on graph neural networks to address the problems of insufficient data collection and inaccurate analysis results in existing methods. This would improve the comprehensiveness of data collection and the accuracy of analysis results, enhance the training effect and prediction accuracy of the model, and thus enable the efficient application of large-scale models based on graph neural networks in the Internet of Things (IoT) field, promoting the development of IoT technology towards a more intelligent and efficient direction.

[0022] To overcome the above problems, this application provides a method for optimizing model computing power. Figure 1 A flowchart of the model computing power optimization method provided in an embodiment of this application is shown. For example... Figure 1 As shown, the method includes: Step 110: Obtain multi-source data, which includes performance indicator data and device connection data. Performance indicator data includes one or more of data processing latency data and data processing accuracy data; device connection data includes one or more of device access characteristic data and device connection stability data.

[0023] In one example, the aforementioned data processing latency data includes one or more of edge node processing latency, cloud processing latency, and end-to-end processing latency, while the data processing accuracy data includes one or more of data error rate, data integrity verification failure rate, and abnormal data filtering ratio.

[0024] The aforementioned edge node processing latency is used to reduce the processing burden on the cloud and improve system real-time performance. Graph neural networks optimize edge models accordingly, moving some simple but real-time-critical tasks to the edge for processing, such as initial data screening and simple feature extraction. This reduces the amount of data transmitted to the cloud, allowing the cloud to focus on complex model training and analysis, thus improving overall efficiency. For example, in smart factories, edge nodes quickly process sensor data, transmitting only key anomaly data to the cloud for in-depth analysis, preventing cloud computing power from being consumed by massive amounts of raw data, making computing power allocation more rational and meeting low-latency requirements. The data collection method involves embedding high-precision timestamp acquisition code at the start of data processing (e.g., the code position where data reception is completed and processing logic begins) and at the end (the code position where processing results are prepared for transmission) in the edge device code. After processing each batch of data, the difference between the two values ​​is calculated to obtain the processing latency. After continuously recording a certain number of batches, the average latency and standard deviation are statistically analyzed to accurately assess the edge node processing latency characteristics. The data is stored in the edge device's local log file for subsequent analysis.

[0025] The aforementioned cloud processing latency is used to adjust model complexity. For example, if a complex model leads to high latency, model quantization and pruning techniques are used to simplify the model structure and reduce computational load; or, under high load, the elastic scaling capabilities of cloud computing are utilized to increase computing resources and improve processing speed. Simultaneously, tasks are prioritized based on data importance and urgency, ensuring computing power for critical tasks is guaranteed to maintain overall service quality and user experience, balancing the return on investment in computing power. Data collection is performed as follows: within the cloud server log system, a start timestamp is recorded when a data processing task is scheduled for execution (the task start time can be obtained from the task scheduling queue), and an end timestamp is recorded when the task is completed (at the point where the processing result is returned or the code marking task completion is entered). The difference between these two timestamps represents the cloud processing latency for a single task. Through the accumulation of data from a large number of tasks (such as all processing tasks within a week), the average latency, maximum and minimum latency, and latency distribution are analyzed to comprehensively understand cloud processing latency performance and provide data for optimization. This data is stored in a dedicated log database on the cloud server.

[0026] The aforementioned end-to-end latency reflects the response speed of IoT applications and directly impacts user experience. Graph neural networks need to comprehensively consider edge and cloud computing power and transmission at each stage, optimizing model architecture and data transmission protocols. For example, an edge-cloud collaborative inference model can be adopted, where the edge performs partial feature extraction and then transmits the data to the cloud for further processing, reducing overall transmission and processing time; optimizing network protocols (such as using a low-latency MQTT variant) reduces transmission overhead; and by monitoring end-to-end latency in real time, dynamically adjusting the edge and cloud computing power allocation ratio and data processing strategies ensures the system maintains low-latency and efficient operation under different conditions, improving application availability and competitiveness. The data collection method involves combining edge and cloud timestamp recording mechanisms. The start time is recorded at the moment of data acquisition at the IoT device (the device driver layer obtains the data acquisition trigger time), and the end time is recorded when the processing result is generated and prepared for transmission at the cloud or final processing node. The difference between the two timestamps is calculated to obtain the end-to-end processing latency. Simultaneously, the Network Time Protocol (NTP) is used to ensure time synchronization among nodes, improving timestamp accuracy. Long-term collection and analysis of end-to-end latency data from a large amount of data processing processes helps understand system performance trends and facilitates targeted optimization and improvement.

[0027] High bit error rates negatively impact data quality, reducing the accuracy of graph neural network training and inference. Therefore, additional computing power is needed for error correction, such as using complex error correction coding, but this increases computational overhead. Thus, computing power allocation can be dynamically adjusted based on the bit error rate. Simple verification is used when the bit error rate is low, while complex error correction is enabled when it is high, or severely erroneous data is downweighted to avoid excessive impact of erroneous data on the model. This optimizes computing power utilization while ensuring data accuracy, guaranteeing stable and reliable system operation. The data collection method is as follows: At the data receiving end, a hardware or software bit error detection module is used to count the number of erroneous symbols in the received data and compare it with the total number of transmitted symbols (the total number of symbols can be calculated from the data transmission protocol header or the number of transmitted bytes) to obtain the data bit error rate. Multiple measurements and calculations are performed at different times (e.g., different hours within a day) to analyze the trend of bit error rate changes, and the data is recorded in the bit error statistics log file at the receiving end.

[0028] The aforementioned data integrity verification failure rate can improve accuracy. Specifically, a high data integrity verification failure rate indicates problems with data transmission and processing, which may lead to graph neural networks being trained and inferred based on incomplete data, affecting accuracy and reliability. In this case, computing power needs to be allocated to repair the data (such as restoring from backup data sources or interpolating based on data correlations), or data needs to be re-collected, both of which require additional computing power. Simultaneously, optimizing the transmission and processing protocol based on the data integrity verification failure rate, such as adding redundant verification information or adjusting the transmission window size, reduces the probability of data loss and errors, and rationally allocates computing power to ensure data integrity and system performance stability. The data collection method is as follows: At the data receiving end, based on the data integrity verification algorithm used (such as hash function verification, message authentication code, etc.), the integrity of each data packet is checked, the number of data packets that failed verification is recorded, and this number is compared with the total number of received packets to obtain the integrity verification failure rate. Through long-term (e.g., one month) continuous monitoring and recording, the pattern of failure rate changes is analyzed, and the data is stored in a dedicated integrity verification log database at the receiving end for subsequent analysis and improvement measure formulation.

[0029] While reasonable anomaly filtering can improve the training efficiency and accuracy of graph neural networks (Graph Neural Networks), excessively high filtering ratios may result in the loss of useful information. Therefore, by monitoring the anomaly filtering ratio, Graph Neural Networks can dynamically adjust the anomaly detection threshold and computational power allocation. If the anomaly ratio is high, computational power is increased to improve the accuracy of the anomaly detection algorithm, ensuring effective identification of truly anomalous data. Simultaneously, the filtered data undergoes a secondary evaluation to avoid misjudgments. This maximizes the retention of useful information while improving data quality, optimizing the allocation of computational power between anomaly handling and normal data processing, and enhancing overall processing effectiveness. The data collection method is as follows: During the data preprocessing stage, the amount of data identified as anomalous by the anomaly detection algorithm and filtered is statistically analyzed (the number of filtered data can be recorded in the filtering operation code). This is compared with the total amount of original data entering the preprocessing stage to determine the anomaly filtering ratio. The changes in this ratio are analyzed periodically (e.g., weekly), taking into account the data source and processing task characteristics, to determine whether the anomaly situation is reasonable. The data is recorded in the data preprocessing statistics log file for subsequent backtracking and optimization of the anomaly handling strategy.

[0030] In another example, the device access characteristic data mentioned above includes one or more of the following: heterogeneous network access ratio, average device authentication time, and low-power device wake-up cycle; and the device connection stability data includes one or more of the following: connection interruption frequency, average reconnection time, and signal strength standard deviation.

[0031] Because devices using different communication protocols differ in data transmission rates, latency, and packet sizes, graph neural networks (Graph Neural Networks) need to allocate computing resources rationally based on the heterogeneous network access ratio when processing data from devices using multiple protocols. For example, when there are many high-speed, large-data-packet 5G devices, more cores should be allocated for fast data parsing and feature extraction; while when there are a high proportion of low-speed, small-data-packet Bluetooth devices, fewer computing resources can be allocated for initial processing, while more computing power can be reserved for data processing stages that have a greater impact on the overall model accuracy. This avoids wasting computing power on inefficient data channels, thereby optimizing the overall computing power utilization efficiency and improving the model training and inference speed. The data collection method involves using the protocol identification module in the IoT network management system to count the number of device connections for each access protocol within a certain period (e.g., one day), and then calculating the proportion of each protocol's devices to the total number of connected devices to obtain the heterogeneous network access ratio. Specifically, the network management system records and counts the protocol identification information in the connection request sent by the device when a connection is established, storing this data in a database for subsequent ratio calculations.

[0032] Long authentication times can delay the entry of device data into the system, affecting the timeliness and consistency of the data. During this delay, graph neural networks can dynamically adjust data preprocessing tasks based on the average authentication time of the devices mentioned above. For example, for devices with long authentication times, lightweight data verification and simple feature extraction tasks can be started in advance. While waiting for authentication to complete, idle computing resources can be utilized. Once authentication is successful, the preprocessed results can be quickly integrated into the subsequent model processing flow, reducing overall processing time waste, ensuring continuous and efficient use of computing power, and avoiding idleness due to waiting. The data collection method is as follows: extract the authentication start time and end timestamp of each device from the log files of the IoT authentication server, calculate the difference between the two to obtain the authentication time of a single device, and then calculate the average authentication time of all devices over a certain period (such as one week) to obtain the average device authentication time. The authentication server's log system records detailed authentication process information for each device, including start time, end time, and authentication result. By writing a dedicated log parsing script, the required timestamp information can be extracted for subsequent time calculation and statistical analysis.

[0033] The wake-up cycle of the aforementioned low-power devices determines their data upload time pattern. Graph neural networks can use this cycle to transfer computing resources originally allocated to the device during its sleep period to data processing on other active devices, achieving flexible allocation of computing power and improving overall utilization. When the low-power device wakes up, sufficient computing power is quickly reallocated to process newly collected data, ensuring timely data processing and avoiding idle computing power during device sleep, thus optimizing the computing power time allocation strategy and improving overall system performance. The data collection method involves monitoring the power management module of the low-power device, recording the time points of each sleep and wake-up state, and statistically analyzing the wake-up cycle within a certain time range (e.g., one month). Many low-power device power management chips or modules provide corresponding status monitoring interfaces. Monitoring devices (such as microcontrollers or dedicated monitoring circuits) connected to these interfaces can be used to obtain the device's sleep and wake-up signals and record the corresponding time information. Alternatively, relevant sleep and wake-up time information can be extracted from the low-power device's operating system logs for analysis and calculation to determine the wake-up cycle. The operating system records relevant logs when the device state changes; by analyzing the timestamps and status identifiers in these log files, the device's wake-up cycle can be determined.

[0034] Frequent connection interruptions can lead to incomplete data transmission, impacting the training data quality and inference accuracy of graph neural networks (Graph Neural Networks). Therefore, by acquiring the connection interruption frequency, when the frequency is high, the Graph Neural Network needs to allocate additional computing power for data recovery and verification. This can be achieved by employing more complex error detection and correction algorithms, data interpolation algorithms, etc., to supplement missing data or correct erroneous data, ensuring that model training and inference are not excessively interfered with. Simultaneously, to balance overall computing power consumption, it may be necessary to appropriately reduce the computing power allocation for data processing tasks with lower real-time requirements, prioritizing the processing of critical data and system stability. The data collection method involves using a connection status monitoring tool on an IoT network monitoring platform to track the connection status of each device in real time. Each time a device connection changes from normal to interrupted, an interruption event is recorded. The connection interruption frequency is obtained by counting the number of interruption events occurring daily. Connection status monitoring tools typically determine device connection status based on network protocol heartbeat mechanisms or periodic connection detection requests. When no response signal is received from the device within a certain period, a connection interruption is determined, and the interruption event is recorded in a database for subsequent frequency statistics.

[0035] Since a shorter average reconnection time means that devices can quickly resume data transmission, graph neural networks can optimize data caching and processing strategies based on the aforementioned average reconnection time parameter. During device reconnection, computing power is rationally allocated for preprocessing cached data, such as preliminary classification and feature extraction. This allows for rapid fusion of the processed cached data with newly received data after successful reconnection, accelerating the overall data processing flow, reducing processing delays caused by reconnection, improving system response speed and data processing efficiency, and ensuring effective utilization of computing power during device reconnection. The data collection method involves recording the timestamps of each device connection interruption and reconnection, calculating the time difference between the two to obtain the single reconnection time, and then averaging the reconnection times of all devices over a certain period (e.g., a quarter) to obtain the average reconnection time. This timestamp data can be obtained from the network management system's log files or connection status monitoring database. The network management system records corresponding time information when device connection status changes; by filtering and calculating this data, the average reconnection time can be obtained.

[0036] The aforementioned signal strength standard deviation reflects the stability of the signal received by the device. A larger standard deviation indicates severe signal fluctuations, which can easily lead to data transmission errors and packet loss. When processing data from such devices, graph neural networks require more computing power to implement more robust data verification and error correction mechanisms, such as using Cyclic Redundancy Check (CRC) and Forward Error Correction (FEC) technologies to ensure data accuracy and integrity. Simultaneously, to avoid wasting computing power due to excessive error correction, the precision requirements for data processing can be appropriately reduced for device data in areas with extremely unstable signals. For example, feature dimensions can be reduced or a simplified model structure can be used to balance computing power consumption and data processing effectiveness, ensuring stable operation of the system under different signal conditions. The acquisition method involves using professional signal strength detection tools deployed in the environment where IoT devices are located to periodically (e.g., every 5 minutes) sample and measure the signal strength of each device for a period of time (e.g., two weeks). Then, the standard deviation of these sampled values ​​is calculated using statistical analysis software to obtain the signal strength standard deviation. Signal strength detection tools typically employ wireless signal receiving chips or modules, capable of monitoring the wireless signal strength around the device in real time and transmitting the measurement results to a data acquisition center via wired or wireless communication. At the data acquisition center, the received signal strength data is stored in a database for subsequent statistical analysis and standard deviation calculation.

[0037] Step 120: Based on multi-source data, determine the data processing coefficients corresponding to performance index data and the device connection coefficients corresponding to device connection data. By performing data analysis and processing on multi-source data, obtain the data processing coefficients used to assess the health of data processing and the device connection coefficients used to assess the device connection status. This transforms the multi-dimensional and multi-dimensional raw data into quantitative coefficients with clear physical meaning and capable of mathematical synthesis, thereby enabling intelligent evaluation based on these quantitative coefficients.

[0038] In one example, the aforementioned data processing coefficients include a latency pressure coefficient and a data quality coefficient. Specifically, the latency pressure coefficient can be obtained by importing data processing latency data into a data processing latency data calculation model, thus comprehensively quantifying the cumulative pressure the system experiences due to processing latency. The latency pressure coefficient is positively correlated with edge node processing latency and cloud processing latency, and negatively correlated with end-to-end processing latency, amplifying the negative impact of high-latency areas and making the system more sensitive to latency deterioration, thereby enabling early warning. The expression for the data processing latency data calculation model is as follows:

[0039] In the formula, α represents the delay pressure coefficient, Ed represents the edge node processing delay of the data acquisition, Cd represents the cloud processing delay of the data acquisition, and Ee represents the end-to-end processing delay of the data acquisition.

[0040] By importing data processing accuracy data into the data processing accuracy data calculation model, a data quality coefficient can be obtained to quantify the risks posed by low-quality data to the model and the urgency of data governance. The data quality coefficient is positively correlated with the data error rate and data integrity verification failure rate, and negatively correlated with the proportion of outlier data filtering. This amplifies the harm of high error rates and high failure rates, while rationally scheduling normal filtering operations helps to prioritize computing power for resolving data source quality issues. The expression for the data processing accuracy data calculation model is as follows:

[0041] In the formula, β represents the data quality coefficient, Er represents the bit error rate of the collected data, Fr represents the failure rate of the collected data integrity verification, and Fp represents the filtering ratio of the collected abnormal data.

[0042] In another example, the aforementioned device connectivity coefficient includes an access energy efficiency coefficient and a connectivity risk coefficient. Specifically, the access energy efficiency coefficient can be obtained by importing device access characteristic data into a device access characteristic data calculation model to assess the contribution of the overall efficiency of device access to the network to the smoothness of computing power supply. The access energy efficiency coefficient is positively correlated with the proportion of heterogeneous network access, and negatively correlated with the average device authentication time and the wake-up cycle of low-power devices, thus comprehensively reflecting the throughput efficiency of the access process. A high access energy efficiency coefficient means that data can reach the computing unit more smoothly and promptly, and the computing power has less idle time waiting for data. The expression of the device access characteristic data calculation model is as follows:

[0043] In the formula, γ represents the access energy efficiency coefficient, Hp represents the proportion of heterogeneous network access collected, Ca represents the average device authentication time collected, and Cu represents the wake-up cycle of low-power devices collected.

[0044] The device connection stability data collected during the data acquisition process is imported into the device connection stability data calculation model to obtain a connection risk coefficient, quantifying the risk of data flow interruption due to connection instability. The connection risk coefficient is positively correlated with the connection interruption frequency and the standard deviation of signal strength, and negatively correlated with the average reconnection time. Through model calculations incorporating trigonometric functions, the dynamic relationship between interruption and reconnection can be determined: frequent but rapid reconnections pose different risks than infrequent but lengthy interruptions. This coefficient helps the system identify connection problems most likely to disrupt data continuity and thus waste computing power. The expression for the device connection stability data calculation model is as follows: , In the formula, The connection risk coefficient is represented by Cf, the connection interruption frequency is represented by Rt, the average reconnection time is represented by Sd, and the standard deviation of the signal strength is represented by Sd.

[0045] Step 130: Determine the computing power optimization rationality index based on the data processing coefficient and device connectivity coefficient. This guides the system to focus on optimizing the performance of data processing itself and the quality of input data, rather than just network connectivity. For example, even if the network connection is very stable (good access energy efficiency coefficient and connection risk coefficient values), if the latency pressure coefficient value spikes, the computing power optimization rationality index will rapidly decrease, issuing a strong warning.

[0046] Step 140: Determine whether the computing power optimization rationality index is greater than the preset index value. If yes, proceed to step 150; otherwise, proceed to step 160.

[0047] Step 150: Output Normal Signal. When the system outputs a normal signal, it indicates that the computing power configuration and operating status of the entire chain from data acquisition, transmission, processing to model calculation are within a reasonable or acceptable range. When the system outputs a normal signal, the operation and maintenance interface displays green; at this time, no manual intervention is required.

[0048] Step 160: Output Warning Signal. When the system outputs a warning signal, it indicates that the system's computing power configuration is unreasonable in at least one or more dimensions, posing a performance bottleneck or risk of degradation. The system immediately outputs a warning signal (such as a yellow or orange alarm) and can also simultaneously highlight it on the monitoring screen. The warning signal can include a computing power optimization rationality index value and information on the coefficient with the greatest contribution (for example, the prompt message: Current main problem: Data processing latency pressure coefficient is abnormally high), providing maintenance personnel with a precise entry point for troubleshooting.

[0049] In one example, let OR be the rationality index for computing power optimization, and let OR be the preset index. def When OR def When OR ≤ 0, it means the preset index is not greater than the computational power optimization rationality index, and a normal signal is issued. This signal indicates that the computational power optimization of the large model of the graph neural network is relatively reasonable; when OR ≤ 0, it means the computational power optimization of the large model of the graph neural network is relatively reasonable. def When OR is greater than the computational power optimization rationality index, a warning signal is issued. This signal indicates that the computational power optimization of the large model of the graph neural network is unreasonable and needs to be adjusted by technical personnel.

[0050] As can be seen from the above, the model computing power optimization method provided in this application collects multi-source data, including performance index data and device connection data, to obtain performance index data reflecting the health of the data processing chain and device connection data reflecting the stability of the network access chain. This multi-faceted data collection provides solid and rich data support for subsequent optimization strategies. By analyzing and calculating the acquired data, the data processing coefficients corresponding to the performance index data and the device connection coefficients corresponding to the device connection data can be determined to accurately identify key factors that may affect computing power. Finally, by systematically evaluating the data processing results, the feasibility and effectiveness of the optimization strategy are improved. With the help of real-time monitoring and dynamic tracking technology, once a computing power bottleneck or performance anomaly is detected, an intelligent adjustment mechanism is immediately activated, enabling operation and maintenance personnel to quickly grasp the real-time status and potential problems of large model computing power, and promptly adjust and optimize resource allocation schemes or system configurations. This provides a solid guarantee for achieving efficient and stable large model computing power support and scientific and reasonable technical deployment, and powerfully promotes the efficient operation and widespread application of large models in complex tasks.

[0051] In some embodiments, determining the computing power optimization rationality index based on the data processing coefficient and the device connection coefficient further includes: determining the computing power optimization rationality index based on the latency pressure coefficient, the data quality coefficient, the access energy efficiency coefficient, and the connection risk coefficient. The computing power optimization rationality index is positively correlated with the product of the latency pressure coefficient, the data quality coefficient, the access energy efficiency coefficient, and the connection risk coefficient, and negatively correlated with the square of the sum of the latency pressure coefficient and the data quality coefficient.

[0052] In one example, latency pressure coefficient, data quality coefficient, access energy efficiency coefficient, and connection risk coefficient can be imported into the large-scale computing power optimization data calculation model of a graph neural network to obtain a computing power optimization rationality index. This achieves nonlinearity and fusion of multi-dimensional information, avoiding biased evaluation. The expression for the large-scale computing power optimization data calculation model of the graph neural network is as follows:

[0053] In the formula, OR represents the computing power optimization rationality index, α represents the calculated latency pressure coefficient, β represents the calculated data quality coefficient, and γ represents the calculated access energy efficiency coefficient. This represents the calculated connectivity risk coefficient. The squared term in the denominator amplifies the OR exponent, ensuring it is sensitive to changes in α and β. For example, in intelligent transportation systems, when cloud GPU resource contention causes the prediction model latency (α) to increase from 2 seconds to 3 seconds, even with a very stable network connection (γ and β), the risk factor may be significantly reduced. (Good), the OR index will also decrease significantly as the denominator (α+β)² increases, thus issuing a timely warning signal. When the OR index alarms, the system can analyze the contribution of each coefficient to the index change, that is, by comparing the change in (α+β)² with (γ×)². The change in the value of α and β can immediately determine whether the main cause of the performance degradation stems from the data processing chain (α, β) or the device connection chain (γ, β). Furthermore, by comparing the changes in α and β themselves, it's possible to pinpoint whether the issue is latency or data quality. For example, if the primary cause of performance degradation is determined to be the data processing chain, prompts can be used to guide operations personnel to prioritize checking computing resources rather than network links, thereby improving efficiency.

[0054] In some embodiments, the above method further includes: updating multi-source data in response to an early warning signal; determining a target computing power optimization rationality index based on the updated multi-source data; if the target computing power optimization rationality index is greater than or equal to a preset index value, stopping the output of the early warning signal and outputting a normal signal; otherwise, generating an optimization log. It is understood that the preset index value involved in the embodiments of this application can be designed according to actual conditions and is not limited here. When the computing power optimization rationality index is received, the system will re-collect, analyze, and comprehensively analyze the performance index data and device connection data to obtain an updated computing power optimization rationality index, i.e., the target computing power optimization rationality index, and compare it with the preset index value again. If the target computing power optimization rationality index is greater than the preset index value, the early warning signal is interrupted and corrected to a normal signal; when the judgment result is still less than or equal to the preset index value, the system can strengthen further monitoring of data processing delay data, data processing accuracy data, device access characteristics, and device connection stability, and generate logs for further optimization by technical personnel.

[0055] The aforementioned reassessment mechanism allows the system to automatically ignore numerous anomalies caused by momentary network interruptions or brief spikes in computing tasks. For example, in an intelligent transportation system, a large vehicle temporarily blocking the signal of a roadside sensor might cause a data interruption for a few seconds, triggering an initial warning. However, during the reassessment 30 seconds later, the signal has recovered, the data flow is normal, and the system automatically clears the alarm. This avoids maintenance personnel frequently dealing with transient issues that don't require intervention, allowing them to focus more on handling real, persistent faults, greatly improving the efficiency of human resource utilization and the focus of maintenance work. Furthermore, for real faults, this reassessment mechanism serves as an early confirmation and preliminary diagnosis mechanism, ensuring that persistent anomalies are reconfirmed within tens of seconds, allowing maintenance personnel to address the fault earlier. Simultaneously, the generated logs can be reports containing multi-dimensional data comparisons and coefficient analyses. For example, the logs might show that the data error rate returned to normal after the reassessment, but cloud processing latency remained high, and the latency pressure coefficient was the main negative contributor. This directly guides operations and maintenance personnel to skip network quality checks and directly identify problems with cloud computing resources or model performance, reducing the average fault location time by more than 50%.

[0056] The above mainly describes the solutions provided in the embodiments of this application from the perspective of interaction between various network elements. It is understood that each network element, such as a base station and a UE, includes corresponding hardware structures and / or software modules to perform the above functions. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0057] This application embodiment can divide the base station, UE, etc. into functional modules according to the above method example. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0058] When dividing each function into modules according to its corresponding function. Figure 2 A schematic diagram of a model computing power optimization device provided in an embodiment of this application is shown. Figure 2As shown, the model computing power optimization device 200 includes: The acquisition module 210 is used to acquire multi-source data, which includes performance index data and device connection data. The determination module 220 is used to determine the data processing coefficients corresponding to the performance index data and the device connection coefficients corresponding to the device connection data based on multi-source data. The determination module 220 is also used to determine the computing power optimization rationality index based on the data processing coefficient and the device connection coefficient; Processing module 230: If the computing power optimization rationality index is greater than the preset index value, the processing module is used to output a normal signal; Otherwise, the processing module 230 is also used to output a warning signal.

[0059] In some embodiments, the above performance metrics data include one or more of data processing latency data and data processing accuracy data; Data processing latency data includes one or more of edge node processing latency, cloud processing latency, and end-to-end processing latency. Data processing accuracy data includes one or more of data error rate, data integrity verification failure rate, and abnormal data filtering ratio.

[0060] In some embodiments, the device connection data includes one or more of device access characteristic data and device connection stability data; Device access characteristic data includes one or more of the following: heterogeneous network access ratio, average device authentication time, and low-power device wake-up cycle. Device connection stability data includes one or more of the following: connection interruption frequency, average reconnection time, and signal strength standard deviation.

[0061] In some embodiments, the above-mentioned data processing coefficients include latency pressure coefficients and data quality coefficients, and the device connectivity coefficients include access energy efficiency coefficients and connectivity risk coefficients.

[0062] In some embodiments, the aforementioned latency stress coefficient is positively correlated with edge node processing latency and cloud processing latency, and negatively correlated with end-to-end processing latency.

[0063] In some embodiments, the data quality coefficient is positively correlated with the data error rate and the data integrity verification failure rate, and negatively correlated with the abnormal data filtering ratio.

[0064] In some embodiments, the access energy efficiency coefficient is positively correlated with the proportion of heterogeneous network access, and negatively correlated with the average device authentication time and the wake-up cycle of low-power devices.

[0065] In some embodiments, the connection risk coefficient is positively correlated with the connection interruption frequency and the standard deviation of signal strength, and negatively correlated with the average reconnection time.

[0066] In some embodiments, the determining module 220 is further configured to determine the computing power optimization rationality index based on the latency pressure coefficient, data quality coefficient, access energy efficiency coefficient, and connection risk coefficient. The computing power optimization rationality index is positively correlated with the product of latency pressure coefficient, data quality coefficient, access energy efficiency coefficient and connection risk coefficient, and negatively correlated with the square of the sum of latency pressure coefficient and data quality coefficient.

[0067] In some embodiments, the above-described model computing power optimization device 200 further includes an update module 240, which updates multi-source data in response to an early warning signal; The determination module 220 is also used to determine the target computing power optimization rationality index based on the updated multi-source data; The processing module 230 is also used to stop outputting the warning signal and output a normal signal if the target computing power optimization rationality index is greater than the preset index value; otherwise, it generates an optimization log.

[0068] Figure 3 A schematic block diagram of a chip according to an embodiment of this application is shown. Figure 3 As shown, the chip 300 includes one or more processors 301 and a communication interface 302. The communication interface 302 can support the server in performing the data transmission and reception steps in the above-described image processing method, and the processor 301 can support the server in performing the data processing steps in the above-described image processing method.

[0069] Optional, such as Figure 3 As shown, the chip 300 also includes a memory 303, which may include read-only memory and random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include non-volatile random access memory (NVRAM).

[0070] In some implementations, such as Figure 3As shown, processor 301 executes corresponding operations by calling operation instructions stored in memory (which may be stored in the operating system). Processor 301 controls the processing operations of any terminal device; processor can also be called a central processing unit (CPU). Memory 303 may include read-only memory and random access memory, and provides instructions and data to processor 301. A portion of memory 303 may also include NVRAM. For example, in applications, memory, communication interfaces, and other components are coupled together via a bus system, which may include, in addition to a data bus, a power bus, a control bus, and a status signal bus, etc. However, for clarity, in... Figure 3 The general designated all buses as Bus System 304.

[0071] The methods disclosed in the embodiments of this disclosure can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above methods can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0072] Exemplary embodiments of this disclosure also provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor. The memory stores a computer program executable by the at least one processor, which, when executed by the at least one processor, causes the electronic device to perform a method according to an embodiment of this disclosure.

[0073] Exemplary embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform a method according to embodiments of this disclosure.

[0074] Exemplary embodiments of this disclosure also provide a computer program product, including a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform a method according to an embodiment of this disclosure.

[0075] refer to Figure 4 The present invention describes a structural block diagram of an electronic device 400 that can serve as a server or client of the present disclosure, which is an example of a hardware device that can be applied to various aspects of the present disclosure. Electronic device 400 is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic device 400 can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0076] like Figure 4 As shown, the electronic device 400 includes a computing unit 401, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 402 or a computer program loaded from a storage unit 408 into a random access memory (RAM) 403. The RAM 403 may also store various programs and data required for the operation of the electronic device 400. The computing unit 401, ROM 402, and RAM 403 are interconnected via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0077] Multiple components in electronic device 400 are connected to I / O interface 405, including: input unit 406, output unit 407, storage unit 408, and communication unit 409. Input unit 406 can be any type of device capable of inputting information to electronic device 400. Input unit 406 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of electronic device. Output unit 407 can be any type of device capable of presenting information and may include, but is not limited to, a display, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 408 may include, but is not limited to, disks and optical discs. Communication unit 409 allows electronic device 400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth™ devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0078] The computing unit 401 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above. For example, in some embodiments, the methods of the embodiments of this disclosure can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 408. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 400 via ROM 402 and / or communication unit 409. In some embodiments, the computing unit 401 can be configured to perform the methods of the embodiments of this disclosure by any other suitable means (e.g., by means of firmware).

[0079] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0080] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0081] As used in this disclosure, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and / or apparatus (e.g., disk, optical disk, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including machine-readable media that receive machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0082] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0083] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0084] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other.

[0085] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions of the embodiments of this disclosure are performed, in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, a computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0086] Although this disclosure has been described in conjunction with specific features and embodiments, it will be apparent that various modifications and combinations can be made therein without departing from the spirit and scope of this disclosure. Accordingly, this specification and drawings are merely exemplary illustrations of the disclosure as defined by the appended claims and are to be considered as covering any and all modifications, variations, combinations, or equivalents within the scope of this disclosure. It is obvious that those skilled in the art can make various alterations and modifications to this disclosure without departing from its spirit and scope. Thus, this disclosure is also intended to include any such modifications and modifications that fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A method for optimizing model computing power, characterized in that, include: Acquire multi-source data, including performance index data and device connection data; Based on the multi-source data, determine the data processing coefficients corresponding to the performance index data and the device connection coefficients corresponding to the device connection data; Based on the data processing coefficient and the device connection coefficient, a computing power optimization rationality index is determined; If the computing power optimization rationality index is greater than the preset index value, a normal signal is output. Otherwise, issue a warning signal.

2. The method according to claim 1, characterized in that, The performance metrics data include one or more of data processing latency data and data processing accuracy data; The data processing latency data includes one or more of edge node processing latency, cloud processing latency, and end-to-end processing latency, and the data processing accuracy data includes one or more of data error rate, data integrity verification failure rate, and abnormal data filtering ratio.

3. The method according to claim 2, characterized in that, The device connection data includes one or more of the following: device access characteristic data and device connection stability data; The device access characteristic data includes one or more of the following: heterogeneous network access ratio, average device authentication time, and low-power device wake-up cycle. The device connection stability data includes one or more of the following: connection interruption frequency, average reconnection time, and signal strength standard deviation.

4. The method according to claim 3, characterized in that, The data processing coefficients include latency pressure coefficients and data quality coefficients, and the device connectivity coefficients include access energy efficiency coefficients and connectivity risk coefficients.

5. The method according to claim 4, characterized in that, The latency pressure coefficient is positively correlated with the edge node processing latency and the cloud processing latency, and negatively correlated with the end-to-end processing latency.

6. The method according to claim 4, characterized in that, The data quality coefficient is positively correlated with the data error rate and the data integrity verification failure rate, and negatively correlated with the abnormal data filtering ratio.

7. The method according to claim 4, characterized in that, The access energy efficiency coefficient is positively correlated with the heterogeneous network access ratio, and negatively correlated with the average device authentication time and the low-power device wake-up cycle.

8. The method according to claim 4, characterized in that, The connection risk coefficient is positively correlated with the connection interruption frequency and the signal strength standard deviation, and negatively correlated with the average reconnection time.

9. The method according to claim 4, characterized in that, The determination of the computing power optimization rationality index based on the data processing coefficient and the device connection coefficient includes: Based on the latency pressure coefficient, the data quality coefficient, the access energy efficiency coefficient, and the connection risk coefficient, the computing power optimization rationality index is determined; The computing power optimization rationality index is positively correlated with the product of the latency pressure coefficient, the data quality coefficient, the access energy efficiency coefficient, and the connection risk coefficient, and negatively correlated with the square of the sum of the latency pressure coefficient and the data quality coefficient.

10. The method according to claim 1, characterized in that, The method further includes: In response to the warning signal, update the multi-source data; Based on the updated multi-source data, a target computing power optimization rationality index is determined. If the target computing power optimization rationality index is greater than the preset index value, then stop outputting the warning signal and output a normal signal. Otherwise, generate an optimization log.

11. A model computing power optimization device, characterized in that, include: The acquisition module is used to acquire multi-source data, including performance index data and device connection data. The determination module is used to determine the data processing coefficient corresponding to the performance index data and the device connection coefficient corresponding to the device connection data based on the multi-source data. The determining module is also used to determine the computing power optimization rationality index based on the data processing coefficient and the device connection coefficient; If the computing power optimization rationality index is greater than the preset index value, the processing module is used to output a normal signal; Otherwise, the processing module is also used to output a warning signal.

12. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a computer program that, when executed by the processor, implements the method as described in any one of claims 1-10.

13. A computer storage medium, characterized in that, The computer storage medium stores instructions that, when executed, implement the method of any one of claims 1-10.

14. A chip, characterized in that, It includes a processor and a communication interface coupled to the processor, the processor being configured to run computer programs or instructions to implement the method as described in any one of claims 1-10.

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