Performance test method and device, computer equipment, storage medium and program product

Abstract

The invention relates to a performance test method and device, computer equipment, a storage medium and a program product. The method comprises the following steps: in response to a selection operation on an accelerator card display area in a test interface, determining an accelerator card to be tested from a plurality of accelerator cards on a server; and in response to a trigger operation on the test control in the test interface, performing a performance test on the to-be-tested accelerator card to obtain a test report of the to-be-tested accelerator card. According to the embodiment of the invention, after the user selects the to-be-tested accelerator card, the user only needs to trigger the test control in the test interface, the performance of the to-be-tested accelerator card can be tested, the user does not need to manually carry out a large amount of test operations, and the test efficiency of the to-be-tested accelerator card can be improved.

Description

Technical Field

[0001] This application relates to the field of server testing technology, and in particular to a performance testing method, apparatus, computer equipment, storage medium, and program product. Background Technology

[0002] With the continuous development of modern data centers and high-performance computing, an increasing number of servers are equipped with GPUs (Graphics Processing Units). GPUs accelerate computer computation, reducing the workload of the central processing unit (CPU). Therefore, the performance of GPUs has a significant impact on the processing performance of computer devices. Consequently, testing the performance of GPUs is crucial for evaluating server performance.

[0003] However, current performance testing methods for accelerator cards suffer from low testing efficiency. Summary of the Invention

[0004] Therefore, it is necessary to provide a performance testing method, apparatus, computer equipment, storage medium, and program product that can improve the efficiency of performance testing for accelerator cards in response to the above-mentioned technical problems.

[0005] Firstly, this application provides a performance testing method, including:

[0006] In response to the selection operation of the acceleration card display area in the test interface, the acceleration card to be tested is determined from multiple acceleration cards on the server;

[0007] In response to the triggering operation of the test control in the test interface, the performance test of the accelerator card under test is performed, and a test report of the accelerator card under test is obtained.

[0008] In the aforementioned performance testing method, in response to the selection operation of the accelerator card display area in the test interface, the accelerator card to be tested is determined from multiple accelerator cards on the server. Then, in response to the triggering operation of the test control in the test interface, the performance test of the accelerator card to be tested is performed, and a test report of the accelerator card to be tested is obtained. In this embodiment of the application, after the user selects the accelerator card to be tested, the user only needs to trigger the test control in the test interface to perform the performance test on the accelerator card to be tested, without the need for the user to perform a large number of manual test operations, thus improving the testing efficiency for the accelerator card to be tested.

[0009] In one embodiment, the step of performing a performance test on the accelerator card under test in response to a trigger operation on a test control in the test interface, and obtaining a test report of the accelerator card under test, includes:

[0010] In response to the triggering operation of the test controls in the test interface, the test item interface is switched to display; the test item interface includes multiple test items corresponding to the accelerator card under test;

[0011] In response to the triggering operation of the target test item in the plurality of test projects, the performance test of the accelerator card under test is performed according to the test plan corresponding to the target test item, and a test report of the accelerator card under test is obtained.

[0012] In this embodiment, the test item interface can be switched in response to the triggering operation of the test controls in the test interface. The test item interface includes multiple test items corresponding to the accelerator card under test. Thus, the user can select at least one target test item from the multiple test items displayed in the test item interface. Therefore, by simply triggering the test controls in the test interface and selecting at least one target test item, the computer device can efficiently and accurately perform performance testing on the accelerator card under test according to the test plan corresponding to the target test item.

[0013] In one embodiment, the target test item is a stress test item, and the step of performing performance testing on the accelerator card under test according to the test plan corresponding to the target test item to obtain a test report of the accelerator card under test includes:

[0014] The processor of the accelerator card under test is controlled to run under high load, and the temperature change of the processor is detected within a preset time period;

[0015] The performance of the accelerator card under test is tested based on the temperature changes, and a test report of the accelerator card under test is obtained.

[0016] In this embodiment, the processor of the accelerator card under test can be automatically controlled to run under high load, the temperature change of the processor can be detected within a preset time period, and the performance test of the accelerator card under test can be automatically performed based on the temperature change. Therefore, without manual operation by the user, stress testing of the accelerator card under test can be carried out efficiently and accurately.

[0017] In one embodiment, the target test item is a bandwidth test item, and the performance test of the accelerator card under test according to the test plan corresponding to the target test item, to obtain a test report of the accelerator card under test, includes:

[0018] The data transmission rate of the accelerator card under test is detected during task execution, and a performance test is performed on the accelerator card under test based on the data transmission rate to obtain a test report of the accelerator card under test.

[0019] In this embodiment, the data transmission rate of the accelerator card under test during task execution can be automatically detected, and the performance of the accelerator card under test can be automatically tested based on the data transmission rate. Therefore, without manual operation by the user, various bandwidth tests can be performed on the accelerator card under test efficiently and accurately.

[0020] In one embodiment, the target test item is a balanced computing power test item. The step of performing performance testing on the accelerator card under test according to the test plan corresponding to the target test item, and obtaining a test report for the accelerator card under test, includes:

[0021] The first computing power value of the accelerator card under test when executing each task under balanced load is detected, and the performance of the accelerator card under test is tested based on the first computing power value to obtain a test report of the accelerator card under test.

[0022] In this embodiment, the first computing power value of the accelerator card under test when performing each task under balanced load can be automatically detected, and the performance test of the accelerator card under test can be automatically performed based on the first computing power value. Therefore, without manual operation by the user, balanced computing power test of the accelerator card under test can be achieved efficiently and accurately.

[0023] In one embodiment, the target test item is a peak computing power test item, and the step of performing performance testing on the accelerator card under test according to the test plan corresponding to the target test item to obtain a test report of the accelerator card under test includes:

[0024] The second computing power value of the accelerator card under test is detected when it executes each task under peak load, and the performance of the accelerator card under test is tested based on the second computing power value to obtain a test report of the accelerator card under test.

[0025] In this embodiment, the second computing power value of the accelerator card under test when performing various tasks under peak load can be automatically detected, and the performance test of the accelerator card under test can be automatically performed based on the second computing power value. Therefore, without manual operation by the user, the peak computing power test of the accelerator card under test can be carried out efficiently and accurately.

[0026] In one embodiment, the target test item is a model performance test item. The step of performing performance testing on the accelerator card under test according to the test plan corresponding to the target test item, and obtaining a test report for the accelerator card under test, includes:

[0027] The model test rate of the accelerator card under test is detected during the model test process. Based on the model test rate, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0028] In this embodiment, the model testing rate of the accelerator card under test can be automatically detected during the model testing process, and the performance test of the accelerator card under test can be automatically performed based on the model testing rate. Therefore, without manual operation by the user, the model application inference performance test and model application training performance test of the accelerator card under test can be carried out efficiently and accurately.

[0029] Secondly, this application also provides a performance testing apparatus, comprising:

[0030] The determination module is used to determine the accelerator card to be tested from multiple accelerator cards on the server in response to the selection operation of the accelerator card display area in the test interface.

[0031] The performance testing module is used to perform performance testing on the accelerator card under test in response to the trigger operation of the test control in the test interface, and obtain a test report of the accelerator card under test.

[0032] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the embodiments of the first aspect described above.

[0033] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the steps of the method in any of the embodiments of the first aspect described above.

[0034] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps of the method in any of the embodiments of the first aspect described above.

[0035] The aforementioned performance testing method, apparatus, computer equipment, storage medium, and program product, in response to a selection operation of the accelerator card display area in the test interface, determine the accelerator card to be tested from multiple accelerator cards on the server, and then, in response to a trigger operation of the test control in the test interface, perform performance testing on the accelerator card to be tested, obtaining a test report for the accelerator card to be tested. In this embodiment, after the user selects the accelerator card to be tested, the user only needs to trigger the test control in the test interface to perform performance testing on the accelerator card to be tested, eliminating the need for the user to perform numerous manual testing operations, thus improving the testing efficiency for the accelerator card to be tested. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a diagram illustrating the application environment of a performance testing method in one embodiment;

[0038] Figure 2 This is a flowchart illustrating a performance testing method in one embodiment;

[0039] Figure 3 This is a flowchart illustrating the performance testing steps in one embodiment;

[0040] Figure 4 This is a schematic diagram of the test item interface before the target test item is triggered in one embodiment;

[0041] Figure 5 This is a flowchart illustrating the performance testing method in another embodiment;

[0042] Figure 6 This is a schematic diagram of the test item interface after the target test item is triggered in one embodiment;

[0043] Figure 7 This is a schematic diagram of a test report in one embodiment;

[0044] Figure 8 This is a structural block diagram of a performance testing device in one embodiment. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0047] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0048] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0049] With the continuous development of modern data centers and high-performance computing, an increasing number of servers are equipped with GPUs (Graphics Processing Units). Due to their excellent parallel processing capabilities, GPUs are widely used in deep learning, graphics rendering, data analysis, and other fields. GPUs accelerate computer computation to reduce the workload of the central processing unit (CPU). Therefore, the performance of GPUs has a significant impact on the processing performance of computer devices. Consequently, performance testing of GPUs is necessary to ensure their effectiveness and stability in various application scenarios. Therefore, testing the performance of GPUs is crucial for server performance.

[0050] However, current performance testing methods for accelerator cards lack automation and require a large number of manual testing operations, resulting in a long testing process. Therefore, current performance testing methods for accelerator cards suffer from low testing efficiency.

[0051] Having described the background technology of the performance testing method provided in the embodiments of this application, the implementation environment involved in the performance testing method provided in the embodiments of this application will be briefly described below. The performance testing method provided in the embodiments of this application can be applied to, for example... Figure 1The computer device shown can be a terminal or a server. It includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a performance testing method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0052] Those skilled in the art will understand that Figure 1 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. A specific terminal may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0053] In one embodiment, such as Figure 2 As shown, a performance testing method is provided, which is applied to... Figure 1 Taking a computer device as an example, the explanation includes the following steps:

[0054] S201, in response to the selection operation of the acceleration card display area in the test interface, determines the acceleration card to be tested from multiple acceleration cards on the server.

[0055] The test interface refers to the interface on the computer device used to perform performance testing on at least one accelerator card under test. The test interface includes an accelerator card display area with multiple accelerator card options, each corresponding to a different accelerator card. The accelerator card under test is the at least one accelerator card that needs to be tested. The accelerator card is located on the server; that is, it is a card connected to the computer device, for example, it can be plugged into the computer device. For example, the accelerator card can include, but is not limited to, any of the following: GPU (Graphics Processing Unit), DCU (Deep Computing Unit), etc. The selection operation refers to the user's action of selecting the accelerator card under test from the multiple accelerator card options in the accelerator card display area. The selection operation can include, but is not limited to, clicking, checking, etc.

[0056] In this embodiment, after opening the test interface, the user can select from multiple accelerator card options in the accelerator card display area to choose at least one accelerator card to be tested. The computer device can then respond to the user's selection in the accelerator card display area and determine at least one accelerator card to be tested from the multiple accelerator cards on the server. Optionally, the user can select only one accelerator card to be tested, thus requiring only that one card to undergo performance testing; or, the user can select multiple accelerator cards to be tested at once, allowing for parallel performance testing of multiple cards. Of course, this embodiment does not limit the number of accelerator cards to be tested.

[0057] S202, in response to the trigger operation of the test control in the test interface, performs performance testing on the accelerator card under test and obtains the test report of the accelerator card under test.

[0058] Among them, the test control refers to the startup control for performance testing, and the test report refers to the performance test results of the accelerator card under test.

[0059] In this embodiment, after selecting the accelerator card to be tested, the user can trigger the test controls in the test interface. For example, the user can click the button corresponding to the test control, and the computer device can respond to the trigger operation of the test control in the test interface to perform performance testing on the accelerator card to be tested and obtain a test report of the accelerator card to be tested. The performance testing methods in this embodiment include the following two: First performance testing method: The computer device can respond to the trigger operation of the test controls in the test interface to directly perform default multiple performance tests on the accelerator card to be tested and obtain a test report of the accelerator card to be tested. The default multiple performance tests may include, but are not limited to, at least one of stress testing, bandwidth testing, balanced computing power testing, peak computing power testing, and model performance testing. Second performance testing method: The computer device can respond to the trigger operation of the test controls in the test interface to switch from the test interface to the test item interface. The user can then select multiple test items on the test item interface to select a target test item. The computer device can then perform the performance test corresponding to the target test item on the accelerator card to be tested and obtain a test report of the accelerator card to be tested. Of course, this application does not limit the specific implementation method of performance testing.

[0060] In the aforementioned performance testing method, in response to the selection operation of the accelerator card display area in the test interface, the accelerator card to be tested is determined from multiple accelerator cards on the server. Then, in response to the triggering operation of the test control in the test interface, the performance test of the accelerator card to be tested is performed, and a test report of the accelerator card to be tested is obtained. In this embodiment of the application, after the user selects the accelerator card to be tested, the user only needs to trigger the test control in the test interface to perform the performance test on the accelerator card to be tested, without the need for the user to perform a large number of manual test operations, thus improving the testing efficiency for the accelerator card to be tested.

[0061] In one embodiment, a performance testing implementation method is provided, namely, "in response to the triggering operation of the test control in the test interface, a performance test is performed on the accelerator card under test, and a test report of the accelerator card under test is obtained," as described in S202 above. Figure 3 As shown, it includes:

[0062] S301, in response to the trigger operation of the test control in the test interface, switches the display of the test item interface; the test item interface includes multiple test items corresponding to the accelerator card under test.

[0063] The test item interface includes multiple test items corresponding to the accelerator card under test. For example, such as... Figure 4 As shown, Figure 4This is a schematic diagram of the test item interface before triggering the target test item in one embodiment. The multiple test items may include, but are not limited to, at least one of the following: computing core stress test item, PCIE bandwidth test item, XHMI bandwidth test item, HBM bandwidth test item, balanced computing power test item, peak computing power test item, AI (Artificial Intelligence) model application inference performance test item, and AI model application training performance test item.

[0064] In this embodiment, after the user triggers the test controls in the test interface, the computer device can automatically switch the display interface from the test interface to the test item interface, and directly display multiple test items corresponding to the accelerator card under test in the test item interface. It should be noted that each accelerator card under test corresponds to multiple test items, that is, performance tests corresponding to each test item can be performed on at least one accelerator card under test.

[0065] S302, in response to the triggering operation of the target test item in multiple test projects, performs performance testing on the accelerator card under test according to the test plan corresponding to the target test item, and obtains the test report of the accelerator card under test.

[0066] The target test item can be at least one of multiple test items, and the test plan refers to the performance test process corresponding to the target test item.

[0067] In this embodiment, the user can select multiple test items in the test item interface to choose at least one target test item. The computer device can then respond to the user's triggering operation on the target test item among the multiple test items, determining the target test item and its corresponding test plan. Optionally, after determining the test plan corresponding to the target test item, the computer device can directly perform performance testing on the accelerator card under test according to the test plan, obtaining a test report for the accelerator card under test; or, in conjunction with... Figure 4 As shown, after determining the test plan corresponding to the target test item, the user can click the "Execute Test" button. The computer device can then respond to the user's triggering of the "Execute Test" button, performing the performance test corresponding to the target test item on the accelerator card under test according to the test plan, and obtaining a test report for the accelerator card under test. Of course, this application embodiment does not limit the specific implementation method for performing the performance test corresponding to the target test item.

[0068] In this embodiment, the test item interface can be switched in response to the triggering operation of the test controls in the test interface. The test item interface includes multiple test items corresponding to the accelerator card under test. Thus, the user can select at least one target test item from the multiple test items displayed in the test item interface. Therefore, by simply triggering the test controls in the test interface and selecting at least one target test item, the computer device can efficiently and accurately perform performance testing on the accelerator card under test according to the test plan corresponding to the target test item.

[0069] In one embodiment, the target test item is a stress test item. Based on this, a performance testing implementation method is provided, namely, the "performance test of the accelerator card under test according to the test plan corresponding to the target test item, and obtain the test report of the accelerator card under test" in S302 above includes:

[0070] The processor of the accelerator card under test is controlled to run under high load, and the temperature change of the processor is detected within a preset time period.

[0071] The performance of the accelerator card under test is tested based on temperature changes, and a test report of the accelerator card under test is obtained.

[0072] Among them, the aforementioned target test items may include stress test items, which refer to the core stress test items for the processor of the accelerator card under test. Core stress test is used to evaluate the stability and performance of the processor of the accelerator card under test under extreme working conditions. The core stress test simulates the high load of the processor in the accelerator card under test to detect whether the processor of the accelerator card under test can maintain performance without degradation during long-term operation.

[0073] In this embodiment, the computer device can obtain the number of computing cores of the corresponding model of the accelerator card under test, determine the optimal workload of each computing core when performing matrix multiplication, and then set the initial size of the matrix based on the optimal workload of each computing core when performing matrix multiplication, so as to ensure that the dimension of the matrix is ​​divisible by the number of computing cores, allowing each computing core to distribute the workload evenly. For example, if the accelerator card under test includes 256 computing cores, the initial size of the matrix can be set to 1024*1024. Then, the computer device can gradually increase the initial size of the matrix in multiples of 2 until the initial size of the matrix reaches the limit threshold of the video memory or computing cores. Thus, by running two random matrix multiplications of the above-mentioned size over a continuous preset time period, the computer device can control the processor of the accelerator card under test to operate under high load during the preset time period and detect the temperature change of the processor during the preset time period. Based on the relationship between the temperature change and the test time, a test report of the accelerator card under test can be obtained. The test report of the accelerator card under test may include, but is not limited to, graphs.

[0074] In this embodiment, the processor of the accelerator card under test can be automatically controlled to run under high load, the temperature change of the processor can be detected within a preset time period, and the performance test of the accelerator card under test can be automatically performed based on the temperature change. Therefore, without manual operation by the user, stress testing of the accelerator card under test can be carried out efficiently and accurately.

[0075] In one embodiment, the target test item is a bandwidth test item. Based on this, a performance test implementation method is provided, namely, the "performance test of the accelerator card under test according to the test plan corresponding to the target test item, and obtain the test report of the accelerator card under test" in S302 above includes:

[0076] The data transfer rate of the accelerator card under test is detected during task execution. Based on the data transfer rate, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0077] Among them, the aforementioned target test items may include bandwidth test items, which refer to the items used to test the bandwidth of the accelerator card under test. For example, bandwidth tests may include, but are not limited to, PCIe bandwidth tests, XHMI bandwidth tests, HBM bandwidth tests, etc.

[0078] In this embodiment, the computer device can detect the data transfer rate of the accelerator card under test during task execution, and perform bandwidth performance testing on the accelerator card under test based on the data transfer rate to obtain a test report for the accelerator card under test. For example, PCIE (Peripheral Component Interconnect Express) bandwidth testing is used to measure the data transfer rate between the accelerator card under test and the host system. PCIE bandwidth testing can be applied to evaluate the performance of the host system in data-intensive tasks. The specific method of PCIE bandwidth testing is as follows: First, allocate 20GB of data on the host device (memory) and determine the PCIE copy baseline speed. For example, the copy baseline speed for PCIE 3.0 can be 13GB / s, and the copy baseline speed for PCIE 4.0 can be 26GB / s. Second, copy the data between the host and the accelerator card under test five times. Then, calculate the time for copying from the host to the accelerator card under test and the time for copying from the accelerator card under test to the host, and determine the corresponding copy speed of the accelerator card under test based on the copy times from the host to the accelerator card under test and the copy times from the accelerator card under test to the host. Next, based on the copy speed of the accelerator card under test, it is determined whether the accelerator card meets the corresponding PCIe standard, and a test report for the accelerator card under test is obtained. This test report may include a conclusion on whether the performance test passed or failed.

[0079] For example, XHMI (Extended Host Management Interface) bandwidth testing is used to evaluate the efficiency of the accelerator card under test (ADC) in management tasks and data exchange. XHMI bandwidth testing ensures that the ADC can communicate effectively in complex systems. The specific method for XHMI bandwidth testing is similar to that for PCIe bandwidth testing and will not be repeated here. It should be noted that XHMI is a bridge card interconnecting the ADC; if the server does not use XHMI, then XHMI bandwidth testing is not necessary.

[0080] For example, the HBM (High Bandwidth Memory) bandwidth test is used to evaluate the memory transfer rate inside the accelerator card under test. The HBM bandwidth test is mainly used to test the efficiency in processing large amounts of data and high-speed computing tasks. The specific method of the HBM bandwidth test is as follows: First, allocate 256MB of space on the accelerator card under test, and perform a simple assignment (write) operation and record the time. Second, perform a simple retrieval (read) operation on the previously assigned data and record the time. Then, repeat the operation a preset number of times, and average the recorded times to ensure accuracy. Finally, compare the recorded times with a preset time threshold to determine whether the accelerator card under test passes the HBM bandwidth test, and obtain the test report for the accelerator card under test.

[0081] In this embodiment, the data transmission rate of the accelerator card under test during task execution can be automatically detected, and the performance of the accelerator card under test can be automatically tested based on the data transmission rate. Therefore, without manual operation by the user, various bandwidth tests can be performed on the accelerator card under test efficiently and accurately.

[0082] In one embodiment, the target test item is a balanced computing power test item. Based on this, a performance testing implementation method is provided, namely, the "performance test of the accelerator card under test according to the test plan corresponding to the target test item, and obtain the test report of the accelerator card under test" in S302 above includes:

[0083] The test accelerator card under test is tested for its first computing power value when performing various tasks under balanced load. Based on the first computing power value, the test accelerator card under test is tested, and a test report of the test accelerator card is obtained.

[0084] Among them, the above-mentioned target test items may include the balanced computing power test item, which refers to the item for testing the balanced computing power of the accelerator card under test. The balanced computing power test is used to evaluate the performance of the accelerator card under test when executing standard computing tasks FP64, FP32, FP16, and INT8. The performance of the accelerator card under test under normal usage conditions can be obtained through the balanced computing power test.

[0085] In this embodiment, since FP64, FP32, FP16, and INT8 are represented by float, double, _half, and char types respectively in CUDA C language, the addition of two variables of the same type can be used as a single calculation task for each precision. Based on this, the computer device can sequentially execute the multiplication of two random matrices of size 12000*12000 under each precision condition, and calculate the calculation time (in seconds) for each precision. Since the multiplication of the above-mentioned random matrices involves 3.456 trillion operations, dividing 3.456 by the number of seconds takes can calculate the balanced computing power value TOPS (under INT8) or TFLOPS (under FP64, FP32, and FP16). In this way, the first computing power value of the accelerator card under test when performing each task under balanced load can be detected. Thus, the computer device can compare the first computing power value with the preset balanced computing power threshold to determine whether the balanced computing power test of the accelerator card under test has passed, and obtain the test report of the accelerator card under test.

[0086] In this embodiment, the first computing power value of the accelerator card under test when performing each task under balanced load can be automatically detected, and the performance test of the accelerator card under test can be automatically performed based on the first computing power value. Therefore, without manual operation by the user, balanced computing power test of the accelerator card under test can be achieved efficiently and accurately.

[0087] In one embodiment, the target test item is a peak computing power test item. Based on this, a performance testing implementation method is provided, namely, the "performance test of the accelerator card under test according to the test plan corresponding to the target test item, and obtain the test report of the accelerator card under test" in S302 above includes:

[0088] The second computing power value of the accelerator card under test is detected when it executes various tasks under peak load. Based on the second computing power value, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0089] Among them, the aforementioned target test items may include peak computing power test items, which refer to the items that perform peak computing power tests on the accelerator card under test. Peak computing power tests are used to determine the performance limits of the accelerator card under test in actual situations for FP64, FP32, FP16, and INT8. Through peak computing power tests, the performance of the accelerator card under test in application scenarios with extreme requirements can be evaluated.

[0090] In this embodiment, the computer device can fix the accelerator card under test to its maximum power consumption. Under maximum power consumption and at various precision levels, it sequentially performs the multiplication of two random matrices of size 12000*12000, and calculates the computation time (in seconds) for each precision level. Since the multiplication of the aforementioned random matrices involves 3.456 trillion operations, dividing 3.456 by the time taken in seconds yields the balanced computing power value TOPS (trillions of integer operations per second under INT8) or TFLOPS (trillions of floating-point operations per second under FP64, FP32, and FP16). This allows the detection of the second computing power value of the accelerator card under test when performing various tasks under peak load. The computer device can then compare the second computing power value with a preset balanced computing power threshold to determine whether the peak computing power test of the accelerator card under test has passed, and obtain a test report for the accelerator card under test.

[0091] In this embodiment, the second computing power value of the accelerator card under test when performing various tasks under peak load can be automatically detected, and the performance test of the accelerator card under test can be automatically performed based on the second computing power value. Therefore, without manual operation by the user, the peak computing power test of the accelerator card under test can be carried out efficiently and accurately.

[0092] In one embodiment, the target test item is a model performance test item. Based on this, a performance testing implementation method is provided, namely, the "performance test of the accelerator card under test according to the test plan corresponding to the target test item, and obtain the test report of the accelerator card under test" in S302 above includes:

[0093] The model test rate of the accelerator card under test is detected during the model test process. Based on the model test rate, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0094] Among them, the aforementioned target test items may include model performance test items, which refer to the items for testing the model performance of the accelerator card under test. Model performance testing may include, but is not limited to, at least one of the following: application inference performance test for artificial intelligence model, application training performance test for artificial intelligence model, etc.

[0095] In this embodiment of the application, for example, the application inference performance test of the artificial intelligence model is used to determine the performance of the accelerator card under test in AI inference. This embodiment selects two mainstream neural network models each from Computer Vision (CV) and Large Language Model (LLM) for testing, and the testing environment for each model is pre-packaged in the testing tool. Based on this, the computer device can detect the first model test rate of the accelerator card under test during the application inference performance test of the artificial intelligence model, and determine whether the application inference performance test of the accelerator card under test passes based on the first model test rate, thus obtaining a test report for the accelerator card under test.

[0096] For example, the application training performance test of the artificial intelligence model is used to determine the performance of the accelerator card under test in AI training. In this embodiment, two mainstream neural network models are selected for testing in computer vision and large language models, respectively, and the testing environment for each model is pre-packaged in the testing tool. Based on this, the computer device can detect the second model test rate of the accelerator card under test in the application training performance test of the artificial intelligence model, and determine whether the application training performance test of the accelerator card under test passes based on the second model test rate, thus obtaining a test report for the accelerator card under test.

[0097] In this embodiment, the model testing rate of the accelerator card under test can be automatically detected during the model testing process, and the performance test of the accelerator card under test can be automatically performed based on the model testing rate. Therefore, without manual operation by the user, the model application inference performance test and model application training performance test of the accelerator card under test can be carried out efficiently and accurately.

[0098] In summary, based on all the above embodiments, this application also provides a complete performance testing method, such as... Figure 5 As shown, the method includes:

[0099] S501, in response to the selection operation of the accelerator card display area in the test interface, determines the accelerator card to be tested from multiple accelerator cards on the server;

[0100] S502, in response to the trigger operation of the test control in the test interface, switches the display of the test item interface; the test item interface includes multiple test items corresponding to the accelerator card under test;

[0101] S503, in response to the triggering operation of the target test item in multiple test projects, performs performance testing on the accelerator card under test according to the test plan corresponding to the target test item, and obtains the test report of the accelerator card under test.

[0102] The target test items include stress tests, bandwidth tests, balanced computing power tests, peak computing power tests, and model performance tests. The test schemes for each target test item have been described in the above embodiments and will not be repeated here. It should be noted that the embodiments of this application do not limit the order in which the target test items are tested.

[0103] For example, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the test item interface after the target test item is triggered in one embodiment. Figure 6 The performance test results can be displayed in the rectangle in the lower left corner. Additionally, users can also... Figure 6 Editing is performed within the rectangle in the lower left corner. For example, as shown... Figure 7 As shown, Figure 7 This is a schematic diagram of a test report in one embodiment.

[0104] In the aforementioned performance testing method, in response to the selection operation of the accelerator card display area in the test interface, the accelerator card to be tested is determined from multiple accelerator cards on a heterogeneous server. Then, in response to the triggering operation of the test control in the test interface, performance testing is performed on the accelerator card to be tested, and a test report of the accelerator card to be tested is obtained. In this embodiment, after the user selects the accelerator card to be tested, the user only needs to trigger the test control in the test interface to perform performance testing on the accelerator card to be tested, without the need for the user to perform a large number of manual testing operations. Therefore, it can improve the testing efficiency for the accelerator card to be tested, and can automatically execute performance tests under various configurations and environments, and generate detailed performance reports. In addition, the performance testing tool in this embodiment not only includes basic performance testing of the accelerator card to be tested, but can also be extended to the simulation of more practical application scenarios, such as scientific computing and big data processing. In this way, users can more comprehensively and accurately evaluate the performance of the accelerator card to be tested under different workloads, thereby providing more accurate data support for server configuration and optimization.

[0105] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0106] Based on the same inventive concept, this application also provides a performance testing apparatus for implementing the performance testing method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more performance testing apparatus embodiments provided below can be found in the limitations of the performance testing method described above, and will not be repeated here.

[0107] In one exemplary embodiment, such as Figure 8 As shown, a performance testing apparatus is provided, including: a determination module 31 and a performance testing module 32, wherein:

[0108] The determination module 31 is used to determine the accelerator card to be tested from multiple accelerator cards on the server in response to the selection operation of the accelerator card display area in the test interface.

[0109] The performance testing module 32 is used to perform performance testing on the accelerator card under test in response to the trigger operation of the test control in the test interface, and obtain the test report of the accelerator card under test.

[0110] In one embodiment, the performance testing module 32 includes:

[0111] The switching unit is used to switch the display of the test item interface in response to the trigger operation of the test control in the test interface; the test item interface includes multiple test items corresponding to the accelerator card under test;

[0112] The performance testing unit is used to respond to the triggering operation of the target test item in multiple test projects, perform performance testing on the accelerator card under test according to the test plan corresponding to the target test item, and obtain the test report of the accelerator card under test.

[0113] In one embodiment, the target test item is a stress test item, and the performance test unit includes:

[0114] The temperature change detection subunit is used to control the processor of the accelerator card under test to run under high load and detect the temperature change of the processor within a preset time period.

[0115] The first performance testing subunit is used to perform performance tests on the accelerator card under test based on temperature changes and to obtain a test report for the accelerator card under test.

[0116] In one embodiment, the target test item is a bandwidth test item, and the performance test unit includes:

[0117] The second performance testing subunit is used to detect the data transmission rate of the accelerator card under test during task execution, and to perform performance tests on the accelerator card under test based on the data transmission rate, thereby obtaining a test report for the accelerator card under test.

[0118] In one embodiment, the target test item is a balanced computing power test item, and the performance test unit includes:

[0119] The third performance testing subunit is used to detect the first computing power value of the accelerator card under test when executing each task under balanced load, and to perform performance testing on the accelerator card under test based on the first computing power value, and obtain the test report of the accelerator card under test.

[0120] In one embodiment, the target test item is the peak computing power test item, and the performance test unit includes:

[0121] The fourth performance testing subunit is used to detect the second computing power value of the accelerator card under test when performing various tasks under peak load, and to perform performance testing on the accelerator card under test based on the second computing power value, and obtain the test report of the accelerator card under test.

[0122] In one embodiment, the target test item is a model performance test item, and the performance test unit includes:

[0123] The fifth performance testing subunit is used to detect the model test rate of the accelerator card under test during the model testing process, and to perform performance testing on the accelerator card under test based on the model test rate to obtain a test report of the accelerator card under test.

[0124] Each module in the aforementioned performance testing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0125] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 1As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a performance testing method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0126] Those skilled in the art will understand that Figure 1 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0127] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0128] In response to the selection operation of the acceleration card display area in the test interface, the acceleration card to be tested is determined from multiple acceleration cards on the server;

[0129] In response to the triggering operation of the test controls in the test interface, the performance test of the accelerator card under test is performed, and the test report of the accelerator card under test is obtained.

[0130] In one embodiment, in response to a trigger operation of a test control in the test interface, a performance test is performed on the accelerator card under test to obtain a test report of the accelerator card under test. When the processor executes the computer program, the following steps are also implemented:

[0131] In response to the triggering operation of the test controls in the test interface, the test item interface is switched to display; the test item interface includes multiple test items corresponding to the accelerator card under test;

[0132] In response to the triggering operation of the target test item in multiple test projects, the performance test of the accelerator card under test is carried out according to the test plan corresponding to the target test item, and the test report of the accelerator card under test is obtained.

[0133] In one embodiment, the target test item is a stress test item. Performance testing is performed on the accelerator card under test according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card. When the processor executes the computer program, the following steps are also implemented:

[0134] The processor of the accelerator card under test is controlled to run under high load, and the temperature change of the processor is detected within a preset time period.

[0135] The performance of the accelerator card under test is tested based on temperature changes, and a test report of the accelerator card under test is obtained.

[0136] In one embodiment, the target test item is a bandwidth test item. Performance testing is performed on the accelerator card under test according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test. When the processor executes the computer program, it also performs the following steps:

[0137] The data transfer rate of the accelerator card under test is detected during task execution. Based on the data transfer rate, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0138] In one embodiment, the target test item is a balanced computing power test item. Performance testing is performed on the accelerator card under test according to the test plan corresponding to the target test item, and a test report for the accelerator card under test is obtained. When the processor executes the computer program, the following steps are also implemented:

[0139] The test accelerator card under test is tested for its first computing power value when performing various tasks under balanced load. Based on the first computing power value, the test accelerator card under test is tested, and a test report of the test accelerator card is obtained.

[0140] In one embodiment, the target test item is the peak computing power test item. Performance testing is performed on the accelerator card under test according to the test plan corresponding to the target test item, and a test report for the accelerator card under test is obtained. When the processor executes the computer program, the following steps are also implemented:

[0141] The second computing power value of the accelerator card under test is detected when it executes various tasks under peak load. Based on the second computing power value, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0142] In one embodiment, the target test item is a model performance test item. The performance of the accelerator card under test is performed according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test. When the processor executes the computer program, the following steps are also implemented:

[0143] The model test rate of the accelerator card under test is detected during the model test process. Based on the model test rate, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0144] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0145] In response to the selection operation of the acceleration card display area in the test interface, the acceleration card to be tested is determined from multiple acceleration cards on the server;

[0146] In response to the triggering operation of the test controls in the test interface, the performance test of the accelerator card under test is performed, and the test report of the accelerator card under test is obtained.

[0147] In one embodiment, in response to a trigger operation on a test control in the test interface, a performance test is performed on the accelerator card under test to obtain a test report of the accelerator card under test. When the computer program is executed by the processor, the following steps are also implemented:

[0148] In response to the triggering operation of the test controls in the test interface, the test item interface is switched to display; the test item interface includes multiple test items corresponding to the accelerator card under test;

[0149] In response to the triggering operation of the target test item in multiple test projects, the performance test of the accelerator card under test is carried out according to the test plan corresponding to the target test item, and the test report of the accelerator card under test is obtained.

[0150] In one embodiment, the target test item is a stress test item. Performance testing is performed on the accelerator card under test according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card. When the computer program is executed by the processor, the following steps are also implemented:

[0151] The processor of the accelerator card under test is controlled to run under high load, and the temperature change of the processor is detected within a preset time period.

[0152] The performance of the accelerator card under test is tested based on temperature changes, and a test report of the accelerator card under test is obtained.

[0153] In one embodiment, the target test item is a bandwidth test item. Performance testing of the accelerator card under test is performed according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test. When the computer program is executed by the processor, the following steps are also implemented:

[0154] The data transfer rate of the accelerator card under test is detected during task execution. Based on the data transfer rate, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0155] In one embodiment, the target test item is a balanced computing power test item. Performance testing of the accelerator card under test is performed according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test. When the computer program is executed by the processor, the following steps are also implemented:

[0156] The test accelerator card under test is tested for its first computing power value when performing various tasks under balanced load. Based on the first computing power value, the test accelerator card under test is tested, and a test report of the test accelerator card is obtained.

[0157] In one embodiment, the target test item is the peak computing power test item. The performance of the accelerator card under test is performed according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test. When the computer program is executed by the processor, the following steps are also implemented:

[0158] The second computing power value of the accelerator card under test is detected when it executes various tasks under peak load. Based on the second computing power value, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0159] In one embodiment, the target test item is a model performance test item. The performance of the accelerator card under test is performed according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test. When the computer program is executed by the processor, the following steps are also implemented:

[0160] The model test rate of the accelerator card under test is detected during the model test process. Based on the model test rate, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0161] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0162] In response to the selection operation of the acceleration card display area in the test interface, the acceleration card to be tested is determined from multiple acceleration cards on the server;

[0163] In response to the triggering operation of the test controls in the test interface, the performance test of the accelerator card under test is performed, and the test report of the accelerator card under test is obtained.

[0164] In one embodiment, in response to a trigger operation on a test control in the test interface, a performance test is performed on the accelerator card under test to obtain a test report of the accelerator card under test. When the computer program is executed by the processor, the following steps are also implemented:

[0165] In response to the triggering operation of the test controls in the test interface, the test item interface is switched to display; the test item interface includes multiple test items corresponding to the accelerator card under test;

[0166] In response to the triggering operation of the target test item in multiple test projects, the performance test of the accelerator card under test is carried out according to the test plan corresponding to the target test item, and the test report of the accelerator card under test is obtained.

[0167] In one embodiment, the target test item is a stress test item. Performance testing is performed on the accelerator card under test according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card. When the computer program is executed by the processor, the following steps are also implemented:

[0168] The processor of the accelerator card under test is controlled to run under high load, and the temperature change of the processor is detected within a preset time period.

[0169] The performance of the accelerator card under test is tested based on temperature changes, and a test report of the accelerator card under test is obtained.

[0170] In one embodiment, the target test item is a bandwidth test item. Performance testing of the accelerator card under test is performed according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test. When the computer program is executed by the processor, the following steps are also implemented:

[0171] The data transfer rate of the accelerator card under test is detected during task execution. Based on the data transfer rate, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0172] In one embodiment, the target test item is a balanced computing power test item. Performance testing of the accelerator card under test is performed according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test. When the computer program is executed by the processor, the following steps are also implemented:

[0173] The test accelerator card under test is tested for its first computing power value when performing various tasks under balanced load. Based on the first computing power value, the test accelerator card under test is tested, and a test report of the test accelerator card is obtained.

[0174] In one embodiment, the target test item is the peak computing power test item. The performance of the accelerator card under test is performed according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test. When the computer program is executed by the processor, the following steps are also implemented:

[0175] The second computing power value of the accelerator card under test is detected when it executes various tasks under peak load. Based on the second computing power value, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0176] In one embodiment, the target test item is a model performance test item. The performance of the accelerator card under test is performed according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test. When the computer program is executed by the processor, the following steps are also implemented:

[0177] The model test rate of the accelerator card under test is detected during the model test process. Based on the model test rate, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

[0178] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0179] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0180] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0181] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A performance testing method, characterized in that, The method includes: In response to the selection operation of the acceleration card display area in the test interface, the acceleration card to be tested is determined from multiple acceleration cards on the server; In response to the triggering operation of the test control in the test interface, the performance test of the accelerator card under test is performed, and a test report of the accelerator card under test is obtained.

2. The method according to claim 1, characterized in that, The system responds to a trigger operation on a test control in the test interface, performs a performance test on the accelerator card under test, and obtains a test report for the accelerator card under test, including: In response to the triggering operation of the test controls in the test interface, the test item interface is switched to display; the test item interface includes multiple test items corresponding to the accelerator card under test; In response to the triggering operation of the target test item in the plurality of test projects, the performance test of the accelerator card under test is performed according to the test plan corresponding to the target test item, and a test report of the accelerator card under test is obtained.

3. The method according to claim 2, characterized in that, The target test item is a stress test item. The performance test of the accelerator card under test is performed according to the test plan corresponding to the target test item, and a test report of the accelerator card under test is obtained, including: The processor of the accelerator card under test is controlled to run under high load, and the temperature change of the processor is detected within a preset time period; The performance of the accelerator card under test is tested based on the temperature changes, and a test report of the accelerator card under test is obtained.

4. The method according to claim 2, characterized in that, The target test item is a bandwidth test item. The performance test of the accelerator card under test is performed according to the test plan corresponding to the target test item, resulting in a test report for the accelerator card under test, including: The data transmission rate of the accelerator card under test is detected during task execution, and a performance test is performed on the accelerator card under test based on the data transmission rate to obtain a test report of the accelerator card under test.

5. The method according to claim 2, characterized in that, The target test item is a balanced computing power test item. The performance test of the accelerator card under test is conducted according to the test plan corresponding to the target test item, and a test report of the accelerator card under test is obtained, including: The first computing power value of the accelerator card under test when executing each task under balanced load is detected, and the performance of the accelerator card under test is tested based on the first computing power value to obtain a test report of the accelerator card under test.

6. The method according to claim 2, characterized in that, The target test item is the peak computing power test item. The performance test of the accelerator card under test is conducted according to the test plan corresponding to the target test item, and a test report of the accelerator card under test is obtained, including: The second computing power value of the accelerator card under test is detected when it executes each task under peak load, and the performance of the accelerator card under test is tested based on the second computing power value to obtain a test report of the accelerator card under test.

7. The method according to claim 2, characterized in that, The target test item is a model performance test item. The performance test of the accelerator card under test is performed according to the test plan corresponding to the target test item, and a test report of the accelerator card under test is obtained, including: The model test rate of the accelerator card under test is detected during the model test process. Based on the model test rate, the performance of the accelerator card under test is tested, and a test report of the accelerator card under test is obtained.

8. A performance testing device, characterized in that, The device includes: The determination module is used to determine the accelerator card to be tested from multiple accelerator cards on the server in response to the selection operation of the accelerator card display area in the test interface. The performance testing module is used to perform performance testing on the accelerator card under test in response to the trigger operation of the test control in the test interface, and obtain a test report of the accelerator card under test.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

11. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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